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authorLinus Torvalds <torvalds@linux-foundation.org>2011-10-28 15:02:27 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-10-28 15:02:27 -0400
commit1fdb24e969110fafea36d3b393bea438f702c87f (patch)
tree47a1dfef8a259e7922285315f8a02d31b4efe2f1 /arch
parentf362f98e7c445643d27c610bb7a86b79727b592e (diff)
parent531a6a941745e1e045dd2a6bd09e1dc01247a5f3 (diff)
Merge branch 'devel-stable' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm
* 'devel-stable' of http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-2.6-arm: (178 commits) ARM: 7139/1: fix compilation with CONFIG_ARM_ATAG_DTB_COMPAT and large TEXT_OFFSET ARM: gic, local timers: use the request_percpu_irq() interface ARM: gic: consolidate PPI handling ARM: switch from NO_MACH_MEMORY_H to NEED_MACH_MEMORY_H ARM: mach-s5p64x0: remove mach/memory.h ARM: mach-s3c64xx: remove mach/memory.h ARM: plat-mxc: remove mach/memory.h ARM: mach-prima2: remove mach/memory.h ARM: mach-zynq: remove mach/memory.h ARM: mach-bcmring: remove mach/memory.h ARM: mach-davinci: remove mach/memory.h ARM: mach-pxa: remove mach/memory.h ARM: mach-ixp4xx: remove mach/memory.h ARM: mach-h720x: remove mach/memory.h ARM: mach-vt8500: remove mach/memory.h ARM: mach-s5pc100: remove mach/memory.h ARM: mach-tegra: remove mach/memory.h ARM: plat-tcc: remove mach/memory.h ARM: mach-mmp: remove mach/memory.h ARM: mach-cns3xxx: remove mach/memory.h ... Fix up mostly pretty trivial conflicts in: - arch/arm/Kconfig - arch/arm/include/asm/localtimer.h - arch/arm/kernel/Makefile - arch/arm/mach-shmobile/board-ap4evb.c - arch/arm/mach-u300/core.c - arch/arm/mm/dma-mapping.c - arch/arm/mm/proc-v7.S - arch/arm/plat-omap/Kconfig largely due to some CONFIG option renaming (ie CONFIG_PM_SLEEP -> CONFIG_ARM_CPU_SUSPEND for the arm-specific suspend code etc) and addition of NEED_MACH_MEMORY_H next to HAVE_IDE.
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig63
-rw-r--r--arch/arm/Kconfig.debug6
-rw-r--r--arch/arm/boot/compressed/.gitignore9
-rw-r--r--arch/arm/boot/compressed/Makefile32
-rw-r--r--arch/arm/boot/compressed/atags_to_fdt.c97
-rw-r--r--arch/arm/boot/compressed/head.S122
-rw-r--r--arch/arm/boot/compressed/libfdt_env.h15
-rw-r--r--arch/arm/boot/compressed/misc.c42
-rw-r--r--arch/arm/boot/compressed/string.c127
-rw-r--r--arch/arm/boot/compressed/vmlinux.lds.in4
-rw-r--r--arch/arm/common/gic.c231
-rw-r--r--arch/arm/include/asm/dma-mapping.h7
-rw-r--r--arch/arm/include/asm/entry-macro-multi.S7
-rw-r--r--arch/arm/include/asm/hardirq.h3
-rw-r--r--arch/arm/include/asm/hardware/entry-macro-gic.S19
-rw-r--r--arch/arm/include/asm/hardware/gic.h9
-rw-r--r--arch/arm/include/asm/hw_breakpoint.h2
-rw-r--r--arch/arm/include/asm/localtimer.h22
-rw-r--r--arch/arm/include/asm/mach/arch.h2
-rw-r--r--arch/arm/include/asm/mach/map.h1
-rw-r--r--arch/arm/include/asm/memory.h18
-rw-r--r--arch/arm/include/asm/pgtable.h3
-rw-r--r--arch/arm/include/asm/pmu.h93
-rw-r--r--arch/arm/include/asm/proc-fns.h8
-rw-r--r--arch/arm/include/asm/smp.h5
-rw-r--r--arch/arm/include/asm/smp_twd.h2
-rw-r--r--arch/arm/include/asm/suspend.h17
-rw-r--r--arch/arm/kernel/Makefile9
-rw-r--r--arch/arm/kernel/debug.S4
-rw-r--r--arch/arm/kernel/head.S4
-rw-r--r--arch/arm/kernel/hw_breakpoint.c275
-rw-r--r--arch/arm/kernel/irq.c3
-rw-r--r--arch/arm/kernel/kprobes-arm.c4
-rw-r--r--arch/arm/kernel/kprobes-test-arm.c1323
-rw-r--r--arch/arm/kernel/kprobes-test-thumb.c1187
-rw-r--r--arch/arm/kernel/kprobes-test.c1748
-rw-r--r--arch/arm/kernel/kprobes-test.h392
-rw-r--r--arch/arm/kernel/kprobes-thumb.c7
-rw-r--r--arch/arm/kernel/kprobes.h8
-rw-r--r--arch/arm/kernel/perf_event.c475
-rw-r--r--arch/arm/kernel/perf_event_v6.c87
-rw-r--r--arch/arm/kernel/perf_event_v7.c395
-rw-r--r--arch/arm/kernel/perf_event_xscale.c90
-rw-r--r--arch/arm/kernel/pmu.c182
-rw-r--r--arch/arm/kernel/setup.c21
-rw-r--r--arch/arm/kernel/sleep.S85
-rw-r--r--arch/arm/kernel/smp.c38
-rw-r--r--arch/arm/kernel/smp_twd.c47
-rw-r--r--arch/arm/kernel/suspend.c72
-rw-r--r--arch/arm/mach-at91/at91sam9g45.c2
-rw-r--r--arch/arm/mach-at91/include/mach/at91sam9g45.h2
-rw-r--r--arch/arm/mach-at91/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-bcmring/include/mach/hardware.h3
-rw-r--r--arch/arm/mach-bcmring/include/mach/memory.h33
-rw-r--r--arch/arm/mach-bcmring/mm.c3
-rw-r--r--arch/arm/mach-clps711x/autcpu12.c2
-rw-r--r--arch/arm/mach-clps711x/cdb89712.c2
-rw-r--r--arch/arm/mach-clps711x/ceiva.c2
-rw-r--r--arch/arm/mach-clps711x/clep7312.c2
-rw-r--r--arch/arm/mach-clps711x/edb7211-arch.c2
-rw-r--r--arch/arm/mach-clps711x/fortunet.c1
-rw-r--r--arch/arm/mach-clps711x/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-clps711x/p720t.c2
-rw-r--r--arch/arm/mach-cns3xxx/cns3420vb.c2
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-cns3xxx/include/mach/memory.h26
-rw-r--r--arch/arm/mach-davinci/board-da830-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-da850-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm355-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm355-leopard.c2
-rw-r--r--arch/arm/mach-davinci/board-dm365-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c2
-rw-r--r--arch/arm/mach-davinci/board-dm646x-evm.c4
-rw-r--r--arch/arm/mach-davinci/board-mityomapl138.c2
-rw-r--r--arch/arm/mach-davinci/board-neuros-osd2.c2
-rw-r--r--arch/arm/mach-davinci/board-omapl138-hawk.c2
-rw-r--r--arch/arm/mach-davinci/board-sffsdr.c2
-rw-r--r--arch/arm/mach-davinci/board-tnetv107x-evm.c2
-rw-r--r--arch/arm/mach-davinci/common.c3
-rw-r--r--arch/arm/mach-davinci/cpuidle.c2
-rw-r--r--arch/arm/mach-davinci/include/mach/ddr2.h4
-rw-r--r--arch/arm/mach-davinci/include/mach/debug-macro.S52
-rw-r--r--arch/arm/mach-davinci/include/mach/memory.h44
-rw-r--r--arch/arm/mach-davinci/include/mach/serial.h3
-rw-r--r--arch/arm/mach-davinci/include/mach/uncompress.h7
-rw-r--r--arch/arm/mach-davinci/sleep.S2
-rw-r--r--arch/arm/mach-dove/cm-a510.c2
-rw-r--r--arch/arm/mach-dove/dove-db-setup.c2
-rw-r--r--arch/arm/mach-dove/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-dove/include/mach/memory.h10
-rw-r--r--arch/arm/mach-ebsa110/core.c2
-rw-r--r--arch/arm/mach-ebsa110/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-ep93xx/adssphere.c2
-rw-r--r--arch/arm/mach-ep93xx/edb93xx.c16
-rw-r--r--arch/arm/mach-ep93xx/gesbc9312.c2
-rw-r--r--arch/arm/mach-ep93xx/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-ep93xx/micro9.c8
-rw-r--r--arch/arm/mach-ep93xx/simone.c4
-rw-r--r--arch/arm/mach-ep93xx/snappercl15.c2
-rw-r--r--arch/arm/mach-ep93xx/ts72xx.c2
-rw-r--r--arch/arm/mach-exynos4/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-exynos4/include/mach/entry-macro.S7
-rw-r--r--arch/arm/mach-exynos4/mach-armlex4210.c2
-rw-r--r--arch/arm/mach-exynos4/mach-nuri.c2
-rw-r--r--arch/arm/mach-exynos4/mach-smdkc210.c2
-rw-r--r--arch/arm/mach-exynos4/mach-smdkv310.c2
-rw-r--r--arch/arm/mach-exynos4/mach-universal_c210.c2
-rw-r--r--arch/arm/mach-exynos4/mct.c7
-rw-r--r--arch/arm/mach-footbridge/cats-hw.c2
-rw-r--r--arch/arm/mach-footbridge/ebsa285.c2
-rw-r--r--arch/arm/mach-footbridge/include/mach/debug-macro.S4
-rw-r--r--arch/arm/mach-footbridge/netwinder-hw.c2
-rw-r--r--arch/arm/mach-footbridge/personal.c2
-rw-r--r--arch/arm/mach-gemini/board-nas4220b.c2
-rw-r--r--arch/arm/mach-gemini/board-rut1xx.c2
-rw-r--r--arch/arm/mach-gemini/board-wbd111.c2
-rw-r--r--arch/arm/mach-gemini/board-wbd222.c2
-rw-r--r--arch/arm/mach-gemini/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-gemini/include/mach/memory.h19
-rw-r--r--arch/arm/mach-h720x/h7201-eval.c2
-rw-r--r--arch/arm/mach-h720x/h7202-eval.c2
-rw-r--r--arch/arm/mach-h720x/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-h720x/include/mach/memory.h11
-rw-r--r--arch/arm/mach-imx/mach-armadillo5x0.c2
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c2
-rw-r--r--arch/arm/mach-imx/mach-cpuimx35.c2
-rw-r--r--arch/arm/mach-imx/mach-eukrea_cpuimx25.c2
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c2
-rw-r--r--arch/arm/mach-imx/mach-imx27ipcam.c2
-rw-r--r--arch/arm/mach-imx/mach-imx27lite.c2
-rw-r--r--arch/arm/mach-imx/mach-kzm_arm11_01.c2
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c4
-rw-r--r--arch/arm/mach-imx/mach-mx21ads.c2
-rw-r--r--arch/arm/mach-imx/mach-mx25_3ds.c2
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c2
-rw-r--r--arch/arm/mach-imx/mach-mx27ads.c2
-rw-r--r--arch/arm/mach-imx/mach-mx31_3ds.c2
-rw-r--r--arch/arm/mach-imx/mach-mx31ads.c2
-rw-r--r--arch/arm/mach-imx/mach-mx31lilly.c2
-rw-r--r--arch/arm/mach-imx/mach-mx31lite.c2
-rw-r--r--arch/arm/mach-imx/mach-mx31moboard.c2
-rw-r--r--arch/arm/mach-imx/mach-mx35_3ds.c2
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c2
-rw-r--r--arch/arm/mach-imx/mach-pca100.c2
-rw-r--r--arch/arm/mach-imx/mach-pcm037.c2
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c2
-rw-r--r--arch/arm/mach-imx/mach-pcm043.c2
-rw-r--r--arch/arm/mach-imx/mach-qong.c2
-rw-r--r--arch/arm/mach-imx/mach-scb9328.c2
-rw-r--r--arch/arm/mach-integrator/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-integrator/integrator_ap.c2
-rw-r--r--arch/arm/mach-integrator/integrator_cp.c2
-rw-r--r--arch/arm/mach-iop13xx/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-iop13xx/iq81340mc.c2
-rw-r--r--arch/arm/mach-iop13xx/iq81340sc.c2
-rw-r--r--arch/arm/mach-iop32x/em7210.c2
-rw-r--r--arch/arm/mach-iop32x/glantank.c2
-rw-r--r--arch/arm/mach-iop32x/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-iop32x/include/mach/memory.h13
-rw-r--r--arch/arm/mach-iop32x/iq31244.c4
-rw-r--r--arch/arm/mach-iop32x/iq80321.c2
-rw-r--r--arch/arm/mach-iop32x/n2100.c2
-rw-r--r--arch/arm/mach-iop33x/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-iop33x/include/mach/memory.h13
-rw-r--r--arch/arm/mach-iop33x/iq80331.c2
-rw-r--r--arch/arm/mach-iop33x/iq80332.c2
-rw-r--r--arch/arm/mach-ixp2000/enp2611.c2
-rw-r--r--arch/arm/mach-ixp2000/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-ixp2000/ixdp2400.c2
-rw-r--r--arch/arm/mach-ixp2000/ixdp2800.c2
-rw-r--r--arch/arm/mach-ixp2000/ixdp2x01.c6
-rw-r--r--arch/arm/mach-ixp23xx/espresso.c2
-rw-r--r--arch/arm/mach-ixp23xx/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-ixp23xx/ixdp2351.c2
-rw-r--r--arch/arm/mach-ixp23xx/roadrunner.c2
-rw-r--r--arch/arm/mach-ixp4xx/avila-setup.c4
-rw-r--r--arch/arm/mach-ixp4xx/coyote-setup.c4
-rw-r--r--arch/arm/mach-ixp4xx/dsmg600-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/fsg-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/gateway7001-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/goramo_mlr.c2
-rw-r--r--arch/arm/mach-ixp4xx/gtwx5715-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-ixp4xx/include/mach/memory.h17
-rw-r--r--arch/arm/mach-ixp4xx/ixdp425-setup.c8
-rw-r--r--arch/arm/mach-ixp4xx/nas100d-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/nslu2-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/vulcan-setup.c2
-rw-r--r--arch/arm/mach-ixp4xx/wg302v2-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/d2net_v2-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/db88f6281-bp-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/dockstar-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/guruplug-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-kirkwood/include/mach/memory.h10
-rw-r--r--arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/netspace_v2-setup.c6
-rw-r--r--arch/arm/mach-kirkwood/netxbig_v2-setup.c4
-rw-r--r--arch/arm/mach-kirkwood/openrd-setup.c6
-rw-r--r--arch/arm/mach-kirkwood/rd88f6192-nas-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/rd88f6281-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/sheevaplug-setup.c4
-rw-r--r--arch/arm/mach-kirkwood/t5325-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/ts219-setup.c2
-rw-r--r--arch/arm/mach-kirkwood/ts41x-setup.c2
-rw-r--r--arch/arm/mach-ks8695/board-acs5k.c2
-rw-r--r--arch/arm/mach-ks8695/board-dsm320.c2
-rw-r--r--arch/arm/mach-ks8695/board-micrel.c2
-rw-r--r--arch/arm/mach-ks8695/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-l7200/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/memory.h27
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c2
-rw-r--r--arch/arm/mach-mmp/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-mmp/include/mach/memory.h14
-rw-r--r--arch/arm/mach-msm/board-halibut.c2
-rw-r--r--arch/arm/mach-msm/board-mahimahi.c2
-rw-r--r--arch/arm/mach-msm/board-msm7x27.c8
-rw-r--r--arch/arm/mach-msm/board-msm7x30.c6
-rw-r--r--arch/arm/mach-msm/board-msm8x60.c11
-rw-r--r--arch/arm/mach-msm/board-qsd8x50.c4
-rw-r--r--arch/arm/mach-msm/board-sapphire.c2
-rw-r--r--arch/arm/mach-msm/board-trout.c2
-rw-r--r--arch/arm/mach-msm/include/mach/debug-macro.S4
-rw-r--r--arch/arm/mach-msm/include/mach/entry-macro-qgic.S73
-rw-r--r--arch/arm/mach-msm/include/mach/memory.h35
-rw-r--r--arch/arm/mach-msm/timer.c69
-rw-r--r--arch/arm/mach-mv78xx0/buffalo-wxl-setup.c2
-rw-r--r--arch/arm/mach-mv78xx0/db78x00-bp-setup.c2
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-mv78xx0/include/mach/memory.h10
-rw-r--r--arch/arm/mach-mv78xx0/rd78x00-masa-setup.c2
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c2
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51sd.c2
-rw-r--r--arch/arm/mach-mx5/board-mx51_3ds.c2
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c2
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikamx.c2
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikasb.c2
-rw-r--r--arch/arm/mach-mxs/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-mxs/include/mach/memory.h24
-rw-r--r--arch/arm/mach-netx/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-netx/include/mach/memory.h26
-rw-r--r--arch/arm/mach-netx/nxdb500.c2
-rw-r--r--arch/arm/mach-netx/nxdkn.c2
-rw-r--r--arch/arm/mach-netx/nxeb500hmi.c2
-rw-r--r--arch/arm/mach-nomadik/board-nhk8815.c2
-rw-r--r--arch/arm/mach-nomadik/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-nomadik/include/mach/memory.h28
-rw-r--r--arch/arm/mach-nuc93x/include/mach/memory.h21
-rw-r--r--arch/arm/mach-nuc93x/mach-nuc932evb.c1
-rw-r--r--arch/arm/mach-omap1/board-ams-delta.c2
-rw-r--r--arch/arm/mach-omap1/board-fsample.c2
-rw-r--r--arch/arm/mach-omap1/board-generic.c2
-rw-r--r--arch/arm/mach-omap1/board-h2.c2
-rw-r--r--arch/arm/mach-omap1/board-h3.c2
-rw-r--r--arch/arm/mach-omap1/board-htcherald.c2
-rw-r--r--arch/arm/mach-omap1/board-innovator.c2
-rw-r--r--arch/arm/mach-omap1/board-nokia770.c2
-rw-r--r--arch/arm/mach-omap1/board-osk.c2
-rw-r--r--arch/arm/mach-omap1/board-palmte.c2
-rw-r--r--arch/arm/mach-omap1/board-palmtt.c2
-rw-r--r--arch/arm/mach-omap1/board-palmz71.c2
-rw-r--r--arch/arm/mach-omap1/board-perseus2.c2
-rw-r--r--arch/arm/mach-omap1/board-sx1.c2
-rw-r--r--arch/arm/mach-omap1/board-voiceblue.c2
-rw-r--r--arch/arm/mach-omap1/include/mach/debug-macro.S48
-rw-r--r--arch/arm/mach-omap1/include/mach/memory.h53
-rw-r--r--arch/arm/mach-omap1/io.c1
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-rw-r--r--arch/arm/mach-shark/core.c2
-rw-r--r--arch/arm/mach-shark/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-shmobile/board-ag5evm.c3
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-rw-r--r--arch/arm/mach-shmobile/entry-intc.S3
-rw-r--r--arch/arm/mach-shmobile/include/mach/entry-macro.S3
-rw-r--r--arch/arm/mach-shmobile/include/mach/memory.h3
-rw-r--r--arch/arm/mach-spear3xx/include/mach/memory.h19
-rw-r--r--arch/arm/mach-spear3xx/spear300_evb.c2
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-rw-r--r--arch/arm/mach-spear6xx/spear600_evb.c2
-rw-r--r--arch/arm/mach-tcc8k/board-tcc8000-sdk.c2
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-rw-r--r--arch/arm/mach-tegra/board-paz00.c2
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-rw-r--r--arch/arm/mach-tegra/include/mach/debug-macro.S2
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-rw-r--r--arch/arm/mach-u300/core.c3
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-rw-r--r--arch/arm/mach-u300/include/mach/memory.h13
-rw-r--r--arch/arm/mach-u300/u300.c2
-rw-r--r--arch/arm/mach-ux500/board-mop500.c6
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-rw-r--r--arch/arm/mach-versatile/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-versatile/include/mach/memory.h28
-rw-r--r--arch/arm/mach-versatile/versatile_ab.c2
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-rw-r--r--arch/arm/mach-vexpress/include/mach/debug-macro.S2
-rw-r--r--arch/arm/mach-vexpress/include/mach/memory.h25
-rw-r--r--arch/arm/mach-vexpress/v2m.c2
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-rw-r--r--arch/arm/mach-vt8500/include/mach/memory.h28
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-rw-r--r--arch/arm/mach-w90x900/mach-nuc910evb.c1
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-rw-r--r--arch/arm/mm/proc-v6.S44
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-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h58
-rw-r--r--arch/arm/plat-omap/Kconfig1
-rw-r--r--arch/arm/plat-omap/include/plat/io.h2
-rw-r--r--arch/arm/plat-omap/include/plat/memory.h102
-rw-r--r--arch/arm/plat-omap/include/plat/serial.h6
-rw-r--r--arch/arm/plat-omap/include/plat/uncompress.h8
-rw-r--r--arch/arm/plat-omap/io.c8
-rw-r--r--arch/arm/plat-spear/include/plat/debug-macro.S2
-rw-r--r--arch/arm/plat-spear/include/plat/memory.h20
-rw-r--r--arch/arm/plat-tcc/include/mach/debug-macro.S2
-rw-r--r--arch/arm/plat-tcc/include/mach/memory.h18
-rw-r--r--arch/arm/vfp/vfpmodule.c31
519 files changed, 7219 insertions, 2881 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index e91cec43f2c0..5ca86e7ab66d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -29,6 +29,7 @@ config ARM
29 select HAVE_GENERIC_HARDIRQS 29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ 30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW 31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
32 help 33 help
33 The ARM series is a line of low-power-consumption RISC chip designs 34 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and 35 licensed by ARM Ltd and targeted at embedded applications and
@@ -211,6 +212,19 @@ config ARM_PATCH_PHYS_VIRT
211 this feature (eg, building a kernel for a single machine) and 212 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size. 213 you need to shrink the kernel to the minimal size.
213 214
215config NEED_MACH_MEMORY_H
216 bool
217 help
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
221
222config PHYS_OFFSET
223 hex "Physical address of main memory"
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 help
226 Please provide the physical address corresponding to the
227 location of main memory in your system.
214 228
215config GENERIC_BUG 229config GENERIC_BUG
216 def_bool y 230 def_bool y
@@ -247,6 +261,7 @@ config ARCH_INTEGRATOR
247 select GENERIC_CLOCKEVENTS 261 select GENERIC_CLOCKEVENTS
248 select PLAT_VERSATILE 262 select PLAT_VERSATILE
249 select PLAT_VERSATILE_FPGA_IRQ 263 select PLAT_VERSATILE_FPGA_IRQ
264 select NEED_MACH_MEMORY_H
250 help 265 help
251 Support for ARM's Integrator platform. 266 Support for ARM's Integrator platform.
252 267
@@ -262,6 +277,7 @@ config ARCH_REALVIEW
262 select PLAT_VERSATILE_CLCD 277 select PLAT_VERSATILE_CLCD
263 select ARM_TIMER_SP804 278 select ARM_TIMER_SP804
264 select GPIO_PL061 if GPIOLIB 279 select GPIO_PL061 if GPIOLIB
280 select NEED_MACH_MEMORY_H
265 help 281 help
266 This enables support for ARM Ltd RealView boards. 282 This enables support for ARM Ltd RealView boards.
267 283
@@ -322,6 +338,7 @@ config ARCH_CLPS711X
322 bool "Cirrus Logic CLPS711x/EP721x-based" 338 bool "Cirrus Logic CLPS711x/EP721x-based"
323 select CPU_ARM720T 339 select CPU_ARM720T
324 select ARCH_USES_GETTIMEOFFSET 340 select ARCH_USES_GETTIMEOFFSET
341 select NEED_MACH_MEMORY_H
325 help 342 help
326 Support for Cirrus Logic 711x/721x based boards. 343 Support for Cirrus Logic 711x/721x based boards.
327 344
@@ -361,6 +378,7 @@ config ARCH_EBSA110
361 select ISA 378 select ISA
362 select NO_IOPORT 379 select NO_IOPORT
363 select ARCH_USES_GETTIMEOFFSET 380 select ARCH_USES_GETTIMEOFFSET
381 select NEED_MACH_MEMORY_H
364 help 382 help
365 This is an evaluation board for the StrongARM processor available 383 This is an evaluation board for the StrongARM processor available
366 from Digital. It has limited hardware on-board, including an 384 from Digital. It has limited hardware on-board, including an
@@ -376,6 +394,7 @@ config ARCH_EP93XX
376 select ARCH_REQUIRE_GPIOLIB 394 select ARCH_REQUIRE_GPIOLIB
377 select ARCH_HAS_HOLES_MEMORYMODEL 395 select ARCH_HAS_HOLES_MEMORYMODEL
378 select ARCH_USES_GETTIMEOFFSET 396 select ARCH_USES_GETTIMEOFFSET
397 select NEED_MEMORY_H
379 help 398 help
380 This enables support for the Cirrus EP93xx series of CPUs. 399 This enables support for the Cirrus EP93xx series of CPUs.
381 400
@@ -385,6 +404,7 @@ config ARCH_FOOTBRIDGE
385 select FOOTBRIDGE 404 select FOOTBRIDGE
386 select GENERIC_CLOCKEVENTS 405 select GENERIC_CLOCKEVENTS
387 select HAVE_IDE 406 select HAVE_IDE
407 select NEED_MACH_MEMORY_H
388 help 408 help
389 Support for systems based on the DC21285 companion chip 409 Support for systems based on the DC21285 companion chip
390 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder. 410 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
@@ -434,6 +454,7 @@ config ARCH_IOP13XX
434 select PCI 454 select PCI
435 select ARCH_SUPPORTS_MSI 455 select ARCH_SUPPORTS_MSI
436 select VMSPLIT_1G 456 select VMSPLIT_1G
457 select NEED_MACH_MEMORY_H
437 help 458 help
438 Support for Intel's IOP13XX (XScale) family of processors. 459 Support for Intel's IOP13XX (XScale) family of processors.
439 460
@@ -464,6 +485,7 @@ config ARCH_IXP23XX
464 select CPU_XSC3 485 select CPU_XSC3
465 select PCI 486 select PCI
466 select ARCH_USES_GETTIMEOFFSET 487 select ARCH_USES_GETTIMEOFFSET
488 select NEED_MACH_MEMORY_H
467 help 489 help
468 Support for Intel's IXP23xx (XScale) family of processors. 490 Support for Intel's IXP23xx (XScale) family of processors.
469 491
@@ -473,6 +495,7 @@ config ARCH_IXP2000
473 select CPU_XSCALE 495 select CPU_XSCALE
474 select PCI 496 select PCI
475 select ARCH_USES_GETTIMEOFFSET 497 select ARCH_USES_GETTIMEOFFSET
498 select NEED_MACH_MEMORY_H
476 help 499 help
477 Support for Intel's IXP2400/2800 (XScale) family of processors. 500 Support for Intel's IXP2400/2800 (XScale) family of processors.
478 501
@@ -565,6 +588,7 @@ config ARCH_KS8695
565 select CPU_ARM922T 588 select CPU_ARM922T
566 select ARCH_REQUIRE_GPIOLIB 589 select ARCH_REQUIRE_GPIOLIB
567 select ARCH_USES_GETTIMEOFFSET 590 select ARCH_USES_GETTIMEOFFSET
591 select NEED_MACH_MEMORY_H
568 help 592 help
569 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based 593 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
570 System-on-Chip devices. 594 System-on-Chip devices.
@@ -657,6 +681,7 @@ config ARCH_SHMOBILE
657 select SPARSE_IRQ 681 select SPARSE_IRQ
658 select MULTI_IRQ_HANDLER 682 select MULTI_IRQ_HANDLER
659 select PM_GENERIC_DOMAINS if PM 683 select PM_GENERIC_DOMAINS if PM
684 select NEED_MACH_MEMORY_H
660 help 685 help
661 Support for Renesas's SH-Mobile and R-Mobile ARM platforms. 686 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
662 687
@@ -672,6 +697,7 @@ config ARCH_RPC
672 select ARCH_SPARSEMEM_ENABLE 697 select ARCH_SPARSEMEM_ENABLE
673 select ARCH_USES_GETTIMEOFFSET 698 select ARCH_USES_GETTIMEOFFSET
674 select HAVE_IDE 699 select HAVE_IDE
700 select NEED_MACH_MEMORY_H
675 help 701 help
676 On the Acorn Risc-PC, Linux can support the internal IDE disk and 702 On the Acorn Risc-PC, Linux can support the internal IDE disk and
677 CD-ROM interface, serial and parallel port, and the floppy drive. 703 CD-ROM interface, serial and parallel port, and the floppy drive.
@@ -691,6 +717,7 @@ config ARCH_SA1100
691 select TICK_ONESHOT 717 select TICK_ONESHOT
692 select ARCH_REQUIRE_GPIOLIB 718 select ARCH_REQUIRE_GPIOLIB
693 select HAVE_IDE 719 select HAVE_IDE
720 select NEED_MACH_MEMORY_H
694 help 721 help
695 Support for StrongARM 11x0 based boards. 722 Support for StrongARM 11x0 based boards.
696 723
@@ -782,6 +809,7 @@ config ARCH_S5PV210
782 select HAVE_S3C2410_I2C if I2C 809 select HAVE_S3C2410_I2C if I2C
783 select HAVE_S3C_RTC if RTC_CLASS 810 select HAVE_S3C_RTC if RTC_CLASS
784 select HAVE_S3C2410_WATCHDOG if WATCHDOG 811 select HAVE_S3C2410_WATCHDOG if WATCHDOG
812 select NEED_MACH_MEMORY_H
785 help 813 help
786 Samsung S5PV210/S5PC110 series based systems 814 Samsung S5PV210/S5PC110 series based systems
787 815
@@ -798,6 +826,7 @@ config ARCH_EXYNOS4
798 select HAVE_S3C_RTC if RTC_CLASS 826 select HAVE_S3C_RTC if RTC_CLASS
799 select HAVE_S3C2410_I2C if I2C 827 select HAVE_S3C2410_I2C if I2C
800 select HAVE_S3C2410_WATCHDOG if WATCHDOG 828 select HAVE_S3C2410_WATCHDOG if WATCHDOG
829 select NEED_MACH_MEMORY_H
801 help 830 help
802 Samsung EXYNOS4 series based systems 831 Samsung EXYNOS4 series based systems
803 832
@@ -809,6 +838,7 @@ config ARCH_SHARK
809 select ZONE_DMA 838 select ZONE_DMA
810 select PCI 839 select PCI
811 select ARCH_USES_GETTIMEOFFSET 840 select ARCH_USES_GETTIMEOFFSET
841 select NEED_MACH_MEMORY_H
812 help 842 help
813 Support for the StrongARM based Digital DNARD machine, also known 843 Support for the StrongARM based Digital DNARD machine, also known
814 as "Shark" (<http://www.shark-linux.de/shark.html>). 844 as "Shark" (<http://www.shark-linux.de/shark.html>).
@@ -837,6 +867,7 @@ config ARCH_U300
837 select HAVE_MACH_CLKDEV 867 select HAVE_MACH_CLKDEV
838 select GENERIC_GPIO 868 select GENERIC_GPIO
839 select ARCH_REQUIRE_GPIOLIB 869 select ARCH_REQUIRE_GPIOLIB
870 select NEED_MACH_MEMORY_H
840 help 871 help
841 Support for ST-Ericsson U300 series mobile platforms. 872 Support for ST-Ericsson U300 series mobile platforms.
842 873
@@ -1835,6 +1866,38 @@ config ZBOOT_ROM_SH_MOBILE_SDHI
1835 1866
1836endchoice 1867endchoice
1837 1868
1869config ARM_APPENDED_DTB
1870 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1871 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1872 help
1873 With this option, the boot code will look for a device tree binary
1874 (DTB) appended to zImage
1875 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1876
1877 This is meant as a backward compatibility convenience for those
1878 systems with a bootloader that can't be upgraded to accommodate
1879 the documented boot protocol using a device tree.
1880
1881 Beware that there is very little in terms of protection against
1882 this option being confused by leftover garbage in memory that might
1883 look like a DTB header after a reboot if no actual DTB is appended
1884 to zImage. Do not leave this option active in a production kernel
1885 if you don't intend to always append a DTB. Proper passing of the
1886 location into r2 of a bootloader provided DTB is always preferable
1887 to this option.
1888
1889config ARM_ATAG_DTB_COMPAT
1890 bool "Supplement the appended DTB with traditional ATAG information"
1891 depends on ARM_APPENDED_DTB
1892 help
1893 Some old bootloaders can't be updated to a DTB capable one, yet
1894 they provide ATAGs with memory configuration, the ramdisk address,
1895 the kernel cmdline string, etc. Such information is dynamically
1896 provided by the bootloader and can't always be stored in a static
1897 DTB. To allow a device tree enabled kernel to be used with such
1898 bootloaders, this option allows zImage to extract the information
1899 from the ATAG list and store it at run time into the appended DTB.
1900
1838config CMDLINE 1901config CMDLINE
1839 string "Default kernel command string" 1902 string "Default kernel command string"
1840 default "" 1903 default ""
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index df3eb3ccd769..f283938c2fc7 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -158,4 +158,10 @@ config DEBUG_S3C_UART
158 The uncompressor code port configuration is now handled 158 The uncompressor code port configuration is now handled
159 by CONFIG_S3C_LOWLEVEL_UART_PORT. 159 by CONFIG_S3C_LOWLEVEL_UART_PORT.
160 160
161config ARM_KPROBES_TEST
162 tristate "Kprobes test module"
163 depends on KPROBES && MODULES
164 help
165 Perform tests of kprobes API and instruction set simulation.
166
161endmenu 167endmenu
diff --git a/arch/arm/boot/compressed/.gitignore b/arch/arm/boot/compressed/.gitignore
index c6028967d336..e0936a148516 100644
--- a/arch/arm/boot/compressed/.gitignore
+++ b/arch/arm/boot/compressed/.gitignore
@@ -5,3 +5,12 @@ piggy.lzo
5piggy.lzma 5piggy.lzma
6vmlinux 6vmlinux
7vmlinux.lds 7vmlinux.lds
8
9# borrowed libfdt files
10fdt.c
11fdt.h
12fdt_ro.c
13fdt_rw.c
14fdt_wip.c
15libfdt.h
16libfdt_internal.h
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index a6b30b35ca65..21f56ff32797 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -26,6 +26,10 @@ HEAD = head.o
26OBJS += misc.o decompress.o 26OBJS += misc.o decompress.o
27FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c 27FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c
28 28
29# string library code (-Os is enforced to keep it much smaller)
30OBJS += string.o
31CFLAGS_string.o := -Os
32
29# 33#
30# Architecture dependencies 34# Architecture dependencies
31# 35#
@@ -89,21 +93,41 @@ suffix_$(CONFIG_KERNEL_GZIP) = gzip
89suffix_$(CONFIG_KERNEL_LZO) = lzo 93suffix_$(CONFIG_KERNEL_LZO) = lzo
90suffix_$(CONFIG_KERNEL_LZMA) = lzma 94suffix_$(CONFIG_KERNEL_LZMA) = lzma
91 95
96# Borrowed libfdt files for the ATAG compatibility mode
97
98libfdt := fdt_rw.c fdt_ro.c fdt_wip.c fdt.c
99libfdt_hdrs := fdt.h libfdt.h libfdt_internal.h
100
101libfdt_objs := $(addsuffix .o, $(basename $(libfdt)))
102
103$(addprefix $(obj)/,$(libfdt) $(libfdt_hdrs)): $(obj)/%: $(srctree)/scripts/dtc/libfdt/%
104 $(call cmd,shipped)
105
106$(addprefix $(obj)/,$(libfdt_objs) atags_to_fdt.o): \
107 $(addprefix $(obj)/,$(libfdt_hdrs))
108
109ifeq ($(CONFIG_ARM_ATAG_DTB_COMPAT),y)
110OBJS += $(libfdt_objs) atags_to_fdt.o
111endif
112
92targets := vmlinux vmlinux.lds \ 113targets := vmlinux vmlinux.lds \
93 piggy.$(suffix_y) piggy.$(suffix_y).o \ 114 piggy.$(suffix_y) piggy.$(suffix_y).o \
94 font.o font.c head.o misc.o $(OBJS) 115 lib1funcs.o lib1funcs.S font.o font.c head.o misc.o $(OBJS)
95 116
96# Make sure files are removed during clean 117# Make sure files are removed during clean
97extra-y += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S 118extra-y += piggy.gzip piggy.lzo piggy.lzma lib1funcs.S $(libfdt) $(libfdt_hdrs)
98 119
99ifeq ($(CONFIG_FUNCTION_TRACER),y) 120ifeq ($(CONFIG_FUNCTION_TRACER),y)
100ORIG_CFLAGS := $(KBUILD_CFLAGS) 121ORIG_CFLAGS := $(KBUILD_CFLAGS)
101KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS)) 122KBUILD_CFLAGS = $(subst -pg, , $(ORIG_CFLAGS))
102endif 123endif
103 124
104ccflags-y := -fpic -fno-builtin 125ccflags-y := -fpic -fno-builtin -I$(obj)
105asflags-y := -Wa,-march=all 126asflags-y := -Wa,-march=all
106 127
128# Supply kernel BSS size to the decompressor via a linker symbol.
129KBSS_SZ = $(shell size $(obj)/../../../../vmlinux | awk 'END{print $$3}')
130LDFLAGS_vmlinux = --defsym _kernel_bss_size=$(KBSS_SZ)
107# Supply ZRELADDR to the decompressor via a linker symbol. 131# Supply ZRELADDR to the decompressor via a linker symbol.
108ifneq ($(CONFIG_AUTO_ZRELADDR),y) 132ifneq ($(CONFIG_AUTO_ZRELADDR),y)
109LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR) 133LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR)
@@ -123,7 +147,7 @@ LDFLAGS_vmlinux += -T
123# For __aeabi_uidivmod 147# For __aeabi_uidivmod
124lib1funcs = $(obj)/lib1funcs.o 148lib1funcs = $(obj)/lib1funcs.o
125 149
126$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE 150$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S
127 $(call cmd,shipped) 151 $(call cmd,shipped)
128 152
129# We need to prevent any GOTOFF relocs being used with references 153# We need to prevent any GOTOFF relocs being used with references
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c b/arch/arm/boot/compressed/atags_to_fdt.c
new file mode 100644
index 000000000000..6ce11c481178
--- /dev/null
+++ b/arch/arm/boot/compressed/atags_to_fdt.c
@@ -0,0 +1,97 @@
1#include <asm/setup.h>
2#include <libfdt.h>
3
4static int node_offset(void *fdt, const char *node_path)
5{
6 int offset = fdt_path_offset(fdt, node_path);
7 if (offset == -FDT_ERR_NOTFOUND)
8 offset = fdt_add_subnode(fdt, 0, node_path);
9 return offset;
10}
11
12static int setprop(void *fdt, const char *node_path, const char *property,
13 uint32_t *val_array, int size)
14{
15 int offset = node_offset(fdt, node_path);
16 if (offset < 0)
17 return offset;
18 return fdt_setprop(fdt, offset, property, val_array, size);
19}
20
21static int setprop_string(void *fdt, const char *node_path,
22 const char *property, const char *string)
23{
24 int offset = node_offset(fdt, node_path);
25 if (offset < 0)
26 return offset;
27 return fdt_setprop_string(fdt, offset, property, string);
28}
29
30static int setprop_cell(void *fdt, const char *node_path,
31 const char *property, uint32_t val)
32{
33 int offset = node_offset(fdt, node_path);
34 if (offset < 0)
35 return offset;
36 return fdt_setprop_cell(fdt, offset, property, val);
37}
38
39/*
40 * Convert and fold provided ATAGs into the provided FDT.
41 *
42 * REturn values:
43 * = 0 -> pretend success
44 * = 1 -> bad ATAG (may retry with another possible ATAG pointer)
45 * < 0 -> error from libfdt
46 */
47int atags_to_fdt(void *atag_list, void *fdt, int total_space)
48{
49 struct tag *atag = atag_list;
50 uint32_t mem_reg_property[2 * NR_BANKS];
51 int memcount = 0;
52 int ret;
53
54 /* make sure we've got an aligned pointer */
55 if ((u32)atag_list & 0x3)
56 return 1;
57
58 /* if we get a DTB here we're done already */
59 if (*(u32 *)atag_list == fdt32_to_cpu(FDT_MAGIC))
60 return 0;
61
62 /* validate the ATAG */
63 if (atag->hdr.tag != ATAG_CORE ||
64 (atag->hdr.size != tag_size(tag_core) &&
65 atag->hdr.size != 2))
66 return 1;
67
68 /* let's give it all the room it could need */
69 ret = fdt_open_into(fdt, fdt, total_space);
70 if (ret < 0)
71 return ret;
72
73 for_each_tag(atag, atag_list) {
74 if (atag->hdr.tag == ATAG_CMDLINE) {
75 setprop_string(fdt, "/chosen", "bootargs",
76 atag->u.cmdline.cmdline);
77 } else if (atag->hdr.tag == ATAG_MEM) {
78 if (memcount >= sizeof(mem_reg_property)/4)
79 continue;
80 mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.start);
81 mem_reg_property[memcount++] = cpu_to_fdt32(atag->u.mem.size);
82 } else if (atag->hdr.tag == ATAG_INITRD2) {
83 uint32_t initrd_start, initrd_size;
84 initrd_start = atag->u.initrd.start;
85 initrd_size = atag->u.initrd.size;
86 setprop_cell(fdt, "/chosen", "linux,initrd-start",
87 initrd_start);
88 setprop_cell(fdt, "/chosen", "linux,initrd-end",
89 initrd_start + initrd_size);
90 }
91 }
92
93 if (memcount)
94 setprop(fdt, "/memory", "reg", mem_reg_property, 4*memcount);
95
96 return fdt_pack(fdt);
97}
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index e95a5989602a..c2effc917254 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -216,6 +216,104 @@ restart: adr r0, LC0
216 mov r10, r6 216 mov r10, r6
217#endif 217#endif
218 218
219 mov r5, #0 @ init dtb size to 0
220#ifdef CONFIG_ARM_APPENDED_DTB
221/*
222 * r0 = delta
223 * r2 = BSS start
224 * r3 = BSS end
225 * r4 = final kernel address
226 * r5 = appended dtb size (still unknown)
227 * r6 = _edata
228 * r7 = architecture ID
229 * r8 = atags/device tree pointer
230 * r9 = size of decompressed image
231 * r10 = end of this image, including bss/stack/malloc space if non XIP
232 * r11 = GOT start
233 * r12 = GOT end
234 * sp = stack pointer
235 *
236 * if there are device trees (dtb) appended to zImage, advance r10 so that the
237 * dtb data will get relocated along with the kernel if necessary.
238 */
239
240 ldr lr, [r6, #0]
241#ifndef __ARMEB__
242 ldr r1, =0xedfe0dd0 @ sig is 0xd00dfeed big endian
243#else
244 ldr r1, =0xd00dfeed
245#endif
246 cmp lr, r1
247 bne dtb_check_done @ not found
248
249#ifdef CONFIG_ARM_ATAG_DTB_COMPAT
250 /*
251 * OK... Let's do some funky business here.
252 * If we do have a DTB appended to zImage, and we do have
253 * an ATAG list around, we want the later to be translated
254 * and folded into the former here. To be on the safe side,
255 * let's temporarily move the stack away into the malloc
256 * area. No GOT fixup has occurred yet, but none of the
257 * code we're about to call uses any global variable.
258 */
259 add sp, sp, #0x10000
260 stmfd sp!, {r0-r3, ip, lr}
261 mov r0, r8
262 mov r1, r6
263 sub r2, sp, r6
264 bl atags_to_fdt
265
266 /*
267 * If returned value is 1, there is no ATAG at the location
268 * pointed by r8. Try the typical 0x100 offset from start
269 * of RAM and hope for the best.
270 */
271 cmp r0, #1
272 sub r0, r4, #TEXT_OFFSET
273 add r0, r0, #0x100
274 mov r1, r6
275 sub r2, sp, r6
276 blne atags_to_fdt
277
278 ldmfd sp!, {r0-r3, ip, lr}
279 sub sp, sp, #0x10000
280#endif
281
282 mov r8, r6 @ use the appended device tree
283
284 /*
285 * Make sure that the DTB doesn't end up in the final
286 * kernel's .bss area. To do so, we adjust the decompressed
287 * kernel size to compensate if that .bss size is larger
288 * than the relocated code.
289 */
290 ldr r5, =_kernel_bss_size
291 adr r1, wont_overwrite
292 sub r1, r6, r1
293 subs r1, r5, r1
294 addhi r9, r9, r1
295
296 /* Get the dtb's size */
297 ldr r5, [r6, #4]
298#ifndef __ARMEB__
299 /* convert r5 (dtb size) to little endian */
300 eor r1, r5, r5, ror #16
301 bic r1, r1, #0x00ff0000
302 mov r5, r5, ror #8
303 eor r5, r5, r1, lsr #8
304#endif
305
306 /* preserve 64-bit alignment */
307 add r5, r5, #7
308 bic r5, r5, #7
309
310 /* relocate some pointers past the appended dtb */
311 add r6, r6, r5
312 add r10, r10, r5
313 add sp, sp, r5
314dtb_check_done:
315#endif
316
219/* 317/*
220 * Check to see if we will overwrite ourselves. 318 * Check to see if we will overwrite ourselves.
221 * r4 = final kernel address 319 * r4 = final kernel address
@@ -223,15 +321,14 @@ restart: adr r0, LC0
223 * r10 = end of this image, including bss/stack/malloc space if non XIP 321 * r10 = end of this image, including bss/stack/malloc space if non XIP
224 * We basically want: 322 * We basically want:
225 * r4 - 16k page directory >= r10 -> OK 323 * r4 - 16k page directory >= r10 -> OK
226 * r4 + image length <= current position (pc) -> OK 324 * r4 + image length <= address of wont_overwrite -> OK
227 */ 325 */
228 add r10, r10, #16384 326 add r10, r10, #16384
229 cmp r4, r10 327 cmp r4, r10
230 bhs wont_overwrite 328 bhs wont_overwrite
231 add r10, r4, r9 329 add r10, r4, r9
232 ARM( cmp r10, pc ) 330 adr r9, wont_overwrite
233 THUMB( mov lr, pc ) 331 cmp r10, r9
234 THUMB( cmp r10, lr )
235 bls wont_overwrite 332 bls wont_overwrite
236 333
237/* 334/*
@@ -285,14 +382,16 @@ wont_overwrite:
285 * r2 = BSS start 382 * r2 = BSS start
286 * r3 = BSS end 383 * r3 = BSS end
287 * r4 = kernel execution address 384 * r4 = kernel execution address
385 * r5 = appended dtb size (0 if not present)
288 * r7 = architecture ID 386 * r7 = architecture ID
289 * r8 = atags pointer 387 * r8 = atags pointer
290 * r11 = GOT start 388 * r11 = GOT start
291 * r12 = GOT end 389 * r12 = GOT end
292 * sp = stack pointer 390 * sp = stack pointer
293 */ 391 */
294 teq r0, #0 392 orrs r1, r0, r5
295 beq not_relocated 393 beq not_relocated
394
296 add r11, r11, r0 395 add r11, r11, r0
297 add r12, r12, r0 396 add r12, r12, r0
298 397
@@ -307,12 +406,21 @@ wont_overwrite:
307 406
308 /* 407 /*
309 * Relocate all entries in the GOT table. 408 * Relocate all entries in the GOT table.
409 * Bump bss entries to _edata + dtb size
310 */ 410 */
3111: ldr r1, [r11, #0] @ relocate entries in the GOT 4111: ldr r1, [r11, #0] @ relocate entries in the GOT
312 add r1, r1, r0 @ table. This fixes up the 412 add r1, r1, r0 @ This fixes up C references
313 str r1, [r11], #4 @ C references. 413 cmp r1, r2 @ if entry >= bss_start &&
414 cmphs r3, r1 @ bss_end > entry
415 addhi r1, r1, r5 @ entry += dtb size
416 str r1, [r11], #4 @ next entry
314 cmp r11, r12 417 cmp r11, r12
315 blo 1b 418 blo 1b
419
420 /* bump our bss pointers too */
421 add r2, r2, r5
422 add r3, r3, r5
423
316#else 424#else
317 425
318 /* 426 /*
diff --git a/arch/arm/boot/compressed/libfdt_env.h b/arch/arm/boot/compressed/libfdt_env.h
new file mode 100644
index 000000000000..1f4e71876b00
--- /dev/null
+++ b/arch/arm/boot/compressed/libfdt_env.h
@@ -0,0 +1,15 @@
1#ifndef _ARM_LIBFDT_ENV_H
2#define _ARM_LIBFDT_ENV_H
3
4#include <linux/types.h>
5#include <linux/string.h>
6#include <asm/byteorder.h>
7
8#define fdt16_to_cpu(x) be16_to_cpu(x)
9#define cpu_to_fdt16(x) cpu_to_be16(x)
10#define fdt32_to_cpu(x) be32_to_cpu(x)
11#define cpu_to_fdt32(x) cpu_to_be32(x)
12#define fdt64_to_cpu(x) be64_to_cpu(x)
13#define cpu_to_fdt64(x) cpu_to_be64(x)
14
15#endif
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 832d37236c59..8e2a8fca5ed2 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -18,14 +18,9 @@
18 18
19unsigned int __machine_arch_type; 19unsigned int __machine_arch_type;
20 20
21#define _LINUX_STRING_H_
22
23#include <linux/compiler.h> /* for inline */ 21#include <linux/compiler.h> /* for inline */
24#include <linux/types.h> /* for size_t */ 22#include <linux/types.h>
25#include <linux/stddef.h> /* for NULL */
26#include <linux/linkage.h> 23#include <linux/linkage.h>
27#include <asm/string.h>
28
29 24
30static void putstr(const char *ptr); 25static void putstr(const char *ptr);
31extern void error(char *x); 26extern void error(char *x);
@@ -101,41 +96,6 @@ static void putstr(const char *ptr)
101 flush(); 96 flush();
102} 97}
103 98
104
105void *memcpy(void *__dest, __const void *__src, size_t __n)
106{
107 int i = 0;
108 unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
109
110 for (i = __n >> 3; i > 0; i--) {
111 *d++ = *s++;
112 *d++ = *s++;
113 *d++ = *s++;
114 *d++ = *s++;
115 *d++ = *s++;
116 *d++ = *s++;
117 *d++ = *s++;
118 *d++ = *s++;
119 }
120
121 if (__n & 1 << 2) {
122 *d++ = *s++;
123 *d++ = *s++;
124 *d++ = *s++;
125 *d++ = *s++;
126 }
127
128 if (__n & 1 << 1) {
129 *d++ = *s++;
130 *d++ = *s++;
131 }
132
133 if (__n & 1)
134 *d++ = *s++;
135
136 return __dest;
137}
138
139/* 99/*
140 * gzip declarations 100 * gzip declarations
141 */ 101 */
diff --git a/arch/arm/boot/compressed/string.c b/arch/arm/boot/compressed/string.c
new file mode 100644
index 000000000000..36e53ef9200f
--- /dev/null
+++ b/arch/arm/boot/compressed/string.c
@@ -0,0 +1,127 @@
1/*
2 * arch/arm/boot/compressed/string.c
3 *
4 * Small subset of simple string routines
5 */
6
7#include <linux/string.h>
8
9void *memcpy(void *__dest, __const void *__src, size_t __n)
10{
11 int i = 0;
12 unsigned char *d = (unsigned char *)__dest, *s = (unsigned char *)__src;
13
14 for (i = __n >> 3; i > 0; i--) {
15 *d++ = *s++;
16 *d++ = *s++;
17 *d++ = *s++;
18 *d++ = *s++;
19 *d++ = *s++;
20 *d++ = *s++;
21 *d++ = *s++;
22 *d++ = *s++;
23 }
24
25 if (__n & 1 << 2) {
26 *d++ = *s++;
27 *d++ = *s++;
28 *d++ = *s++;
29 *d++ = *s++;
30 }
31
32 if (__n & 1 << 1) {
33 *d++ = *s++;
34 *d++ = *s++;
35 }
36
37 if (__n & 1)
38 *d++ = *s++;
39
40 return __dest;
41}
42
43void *memmove(void *__dest, __const void *__src, size_t count)
44{
45 unsigned char *d = __dest;
46 const unsigned char *s = __src;
47
48 if (__dest == __src)
49 return __dest;
50
51 if (__dest < __src)
52 return memcpy(__dest, __src, count);
53
54 while (count--)
55 d[count] = s[count];
56 return __dest;
57}
58
59size_t strlen(const char *s)
60{
61 const char *sc = s;
62
63 while (*sc != '\0')
64 sc++;
65 return sc - s;
66}
67
68int memcmp(const void *cs, const void *ct, size_t count)
69{
70 const unsigned char *su1 = cs, *su2 = ct, *end = su1 + count;
71 int res = 0;
72
73 while (su1 < end) {
74 res = *su1++ - *su2++;
75 if (res)
76 break;
77 }
78 return res;
79}
80
81int strcmp(const char *cs, const char *ct)
82{
83 unsigned char c1, c2;
84 int res = 0;
85
86 do {
87 c1 = *cs++;
88 c2 = *ct++;
89 res = c1 - c2;
90 if (res)
91 break;
92 } while (c1);
93 return res;
94}
95
96void *memchr(const void *s, int c, size_t count)
97{
98 const unsigned char *p = s;
99
100 while (count--)
101 if ((unsigned char)c == *p++)
102 return (void *)(p - 1);
103 return NULL;
104}
105
106char *strchr(const char *s, int c)
107{
108 while (*s != (char)c)
109 if (*s++ == '\0')
110 return NULL;
111 return (char *)s;
112}
113
114#undef memset
115
116void *memset(void *s, int c, size_t count)
117{
118 char *xs = s;
119 while (count--)
120 *xs++ = c;
121 return s;
122}
123
124void __memzero(void *s, size_t count)
125{
126 memset(s, 0, count);
127}
diff --git a/arch/arm/boot/compressed/vmlinux.lds.in b/arch/arm/boot/compressed/vmlinux.lds.in
index 4e728834a1b9..4919f2ac8b89 100644
--- a/arch/arm/boot/compressed/vmlinux.lds.in
+++ b/arch/arm/boot/compressed/vmlinux.lds.in
@@ -51,6 +51,10 @@ SECTIONS
51 _got_start = .; 51 _got_start = .;
52 .got : { *(.got) } 52 .got : { *(.got) }
53 _got_end = .; 53 _got_end = .;
54
55 /* ensure the zImage file size is always a multiple of 64 bits */
56 /* (without a dummy byte, ld just ignores the empty section) */
57 .pad : { BYTE(0); . = ALIGN(8); }
54 _edata = .; 58 _edata = .;
55 59
56 . = BSS_START; 60 . = BSS_START;
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index bdbb3f74f0fe..a8fc6b237592 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -26,8 +26,12 @@
26#include <linux/kernel.h> 26#include <linux/kernel.h>
27#include <linux/list.h> 27#include <linux/list.h>
28#include <linux/smp.h> 28#include <linux/smp.h>
29#include <linux/cpu_pm.h>
29#include <linux/cpumask.h> 30#include <linux/cpumask.h>
30#include <linux/io.h> 31#include <linux/io.h>
32#include <linux/interrupt.h>
33#include <linux/percpu.h>
34#include <linux/slab.h>
31 35
32#include <asm/irq.h> 36#include <asm/irq.h>
33#include <asm/mach/irq.h> 37#include <asm/mach/irq.h>
@@ -262,6 +266,7 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
262 u32 cpumask; 266 u32 cpumask;
263 void __iomem *base = gic->dist_base; 267 void __iomem *base = gic->dist_base;
264 u32 cpu = 0; 268 u32 cpu = 0;
269 u32 nrppis = 0, ppi_base = 0;
265 270
266#ifdef CONFIG_SMP 271#ifdef CONFIG_SMP
267 cpu = cpu_logical_map(smp_processor_id()); 272 cpu = cpu_logical_map(smp_processor_id());
@@ -282,6 +287,25 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
282 if (gic_irqs > 1020) 287 if (gic_irqs > 1020)
283 gic_irqs = 1020; 288 gic_irqs = 1020;
284 289
290 gic->gic_irqs = gic_irqs;
291
292 /*
293 * Nobody would be insane enough to use PPIs on a secondary
294 * GIC, right?
295 */
296 if (gic == &gic_data[0]) {
297 nrppis = (32 - irq_start) & 31;
298
299 /* The GIC only supports up to 16 PPIs. */
300 if (nrppis > 16)
301 BUG();
302
303 ppi_base = gic->irq_offset + 32 - nrppis;
304 }
305
306 pr_info("Configuring GIC with %d sources (%d PPIs)\n",
307 gic_irqs, (gic == &gic_data[0]) ? nrppis : 0);
308
285 /* 309 /*
286 * Set all global interrupts to be level triggered, active low. 310 * Set all global interrupts to be level triggered, active low.
287 */ 311 */
@@ -317,7 +341,17 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
317 /* 341 /*
318 * Setup the Linux IRQ subsystem. 342 * Setup the Linux IRQ subsystem.
319 */ 343 */
320 for (i = irq_start; i < irq_limit; i++) { 344 for (i = 0; i < nrppis; i++) {
345 int ppi = i + ppi_base;
346
347 irq_set_percpu_devid(ppi);
348 irq_set_chip_and_handler(ppi, &gic_chip,
349 handle_percpu_devid_irq);
350 irq_set_chip_data(ppi, gic);
351 set_irq_flags(ppi, IRQF_VALID | IRQF_NOAUTOEN);
352 }
353
354 for (i = irq_start + nrppis; i < irq_limit; i++) {
321 irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq); 355 irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
322 irq_set_chip_data(i, gic); 356 irq_set_chip_data(i, gic);
323 set_irq_flags(i, IRQF_VALID | IRQF_PROBE); 357 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
@@ -349,6 +383,189 @@ static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
349 writel_relaxed(1, base + GIC_CPU_CTRL); 383 writel_relaxed(1, base + GIC_CPU_CTRL);
350} 384}
351 385
386#ifdef CONFIG_CPU_PM
387/*
388 * Saves the GIC distributor registers during suspend or idle. Must be called
389 * with interrupts disabled but before powering down the GIC. After calling
390 * this function, no interrupts will be delivered by the GIC, and another
391 * platform-specific wakeup source must be enabled.
392 */
393static void gic_dist_save(unsigned int gic_nr)
394{
395 unsigned int gic_irqs;
396 void __iomem *dist_base;
397 int i;
398
399 if (gic_nr >= MAX_GIC_NR)
400 BUG();
401
402 gic_irqs = gic_data[gic_nr].gic_irqs;
403 dist_base = gic_data[gic_nr].dist_base;
404
405 if (!dist_base)
406 return;
407
408 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
409 gic_data[gic_nr].saved_spi_conf[i] =
410 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
411
412 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
413 gic_data[gic_nr].saved_spi_target[i] =
414 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
415
416 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
417 gic_data[gic_nr].saved_spi_enable[i] =
418 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
419}
420
421/*
422 * Restores the GIC distributor registers during resume or when coming out of
423 * idle. Must be called before enabling interrupts. If a level interrupt
424 * that occured while the GIC was suspended is still present, it will be
425 * handled normally, but any edge interrupts that occured will not be seen by
426 * the GIC and need to be handled by the platform-specific wakeup source.
427 */
428static void gic_dist_restore(unsigned int gic_nr)
429{
430 unsigned int gic_irqs;
431 unsigned int i;
432 void __iomem *dist_base;
433
434 if (gic_nr >= MAX_GIC_NR)
435 BUG();
436
437 gic_irqs = gic_data[gic_nr].gic_irqs;
438 dist_base = gic_data[gic_nr].dist_base;
439
440 if (!dist_base)
441 return;
442
443 writel_relaxed(0, dist_base + GIC_DIST_CTRL);
444
445 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
446 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
447 dist_base + GIC_DIST_CONFIG + i * 4);
448
449 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
450 writel_relaxed(0xa0a0a0a0,
451 dist_base + GIC_DIST_PRI + i * 4);
452
453 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
454 writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
455 dist_base + GIC_DIST_TARGET + i * 4);
456
457 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
458 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
459 dist_base + GIC_DIST_ENABLE_SET + i * 4);
460
461 writel_relaxed(1, dist_base + GIC_DIST_CTRL);
462}
463
464static void gic_cpu_save(unsigned int gic_nr)
465{
466 int i;
467 u32 *ptr;
468 void __iomem *dist_base;
469 void __iomem *cpu_base;
470
471 if (gic_nr >= MAX_GIC_NR)
472 BUG();
473
474 dist_base = gic_data[gic_nr].dist_base;
475 cpu_base = gic_data[gic_nr].cpu_base;
476
477 if (!dist_base || !cpu_base)
478 return;
479
480 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
481 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
482 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
483
484 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
485 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
486 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
487
488}
489
490static void gic_cpu_restore(unsigned int gic_nr)
491{
492 int i;
493 u32 *ptr;
494 void __iomem *dist_base;
495 void __iomem *cpu_base;
496
497 if (gic_nr >= MAX_GIC_NR)
498 BUG();
499
500 dist_base = gic_data[gic_nr].dist_base;
501 cpu_base = gic_data[gic_nr].cpu_base;
502
503 if (!dist_base || !cpu_base)
504 return;
505
506 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
507 for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
508 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
509
510 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
511 for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
512 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
513
514 for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
515 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4);
516
517 writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK);
518 writel_relaxed(1, cpu_base + GIC_CPU_CTRL);
519}
520
521static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
522{
523 int i;
524
525 for (i = 0; i < MAX_GIC_NR; i++) {
526 switch (cmd) {
527 case CPU_PM_ENTER:
528 gic_cpu_save(i);
529 break;
530 case CPU_PM_ENTER_FAILED:
531 case CPU_PM_EXIT:
532 gic_cpu_restore(i);
533 break;
534 case CPU_CLUSTER_PM_ENTER:
535 gic_dist_save(i);
536 break;
537 case CPU_CLUSTER_PM_ENTER_FAILED:
538 case CPU_CLUSTER_PM_EXIT:
539 gic_dist_restore(i);
540 break;
541 }
542 }
543
544 return NOTIFY_OK;
545}
546
547static struct notifier_block gic_notifier_block = {
548 .notifier_call = gic_notifier,
549};
550
551static void __init gic_pm_init(struct gic_chip_data *gic)
552{
553 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
554 sizeof(u32));
555 BUG_ON(!gic->saved_ppi_enable);
556
557 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
558 sizeof(u32));
559 BUG_ON(!gic->saved_ppi_conf);
560
561 cpu_pm_register_notifier(&gic_notifier_block);
562}
563#else
564static void __init gic_pm_init(struct gic_chip_data *gic)
565{
566}
567#endif
568
352void __init gic_init(unsigned int gic_nr, unsigned int irq_start, 569void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
353 void __iomem *dist_base, void __iomem *cpu_base) 570 void __iomem *dist_base, void __iomem *cpu_base)
354{ 571{
@@ -364,8 +581,10 @@ void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
364 if (gic_nr == 0) 581 if (gic_nr == 0)
365 gic_cpu_base_addr = cpu_base; 582 gic_cpu_base_addr = cpu_base;
366 583
584 gic_chip.flags |= gic_arch_extn.flags;
367 gic_dist_init(gic, irq_start); 585 gic_dist_init(gic, irq_start);
368 gic_cpu_init(gic); 586 gic_cpu_init(gic);
587 gic_pm_init(gic);
369} 588}
370 589
371void __cpuinit gic_secondary_init(unsigned int gic_nr) 590void __cpuinit gic_secondary_init(unsigned int gic_nr)
@@ -375,16 +594,6 @@ void __cpuinit gic_secondary_init(unsigned int gic_nr)
375 gic_cpu_init(&gic_data[gic_nr]); 594 gic_cpu_init(&gic_data[gic_nr]);
376} 595}
377 596
378void __cpuinit gic_enable_ppi(unsigned int irq)
379{
380 unsigned long flags;
381
382 local_irq_save(flags);
383 irq_set_status_flags(irq, IRQ_NOPROBE);
384 gic_unmask_irq(irq_get_irq_data(irq));
385 local_irq_restore(flags);
386}
387
388#ifdef CONFIG_SMP 597#ifdef CONFIG_SMP
389void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 598void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
390{ 599{
diff --git a/arch/arm/include/asm/dma-mapping.h b/arch/arm/include/asm/dma-mapping.h
index 28b7ee8d7398..cb3b7c981c4b 100644
--- a/arch/arm/include/asm/dma-mapping.h
+++ b/arch/arm/include/asm/dma-mapping.h
@@ -205,6 +205,13 @@ extern void *dma_alloc_writecombine(struct device *, size_t, dma_addr_t *,
205int dma_mmap_writecombine(struct device *, struct vm_area_struct *, 205int dma_mmap_writecombine(struct device *, struct vm_area_struct *,
206 void *, dma_addr_t, size_t); 206 void *, dma_addr_t, size_t);
207 207
208/*
209 * This can be called during boot to increase the size of the consistent
210 * DMA region above it's default value of 2MB. It must be called before the
211 * memory allocator is initialised, i.e. before any core_initcall.
212 */
213extern void __init init_consistent_dma_size(unsigned long size);
214
208 215
209#ifdef CONFIG_DMABOUNCE 216#ifdef CONFIG_DMABOUNCE
210/* 217/*
diff --git a/arch/arm/include/asm/entry-macro-multi.S b/arch/arm/include/asm/entry-macro-multi.S
index 2f1e2098dfe7..88d61815f0c0 100644
--- a/arch/arm/include/asm/entry-macro-multi.S
+++ b/arch/arm/include/asm/entry-macro-multi.S
@@ -25,13 +25,6 @@
25 movne r1, sp 25 movne r1, sp
26 adrne lr, BSYM(1b) 26 adrne lr, BSYM(1b)
27 bne do_IPI 27 bne do_IPI
28
29#ifdef CONFIG_LOCAL_TIMERS
30 test_for_ltirq r0, r2, r6, lr
31 movne r0, sp
32 adrne lr, BSYM(1b)
33 bne do_local_timer
34#endif
35#endif 28#endif
369997: 299997:
37 .endm 30 .endm
diff --git a/arch/arm/include/asm/hardirq.h b/arch/arm/include/asm/hardirq.h
index 89ad1805e579..ddf07a92a6c8 100644
--- a/arch/arm/include/asm/hardirq.h
+++ b/arch/arm/include/asm/hardirq.h
@@ -9,9 +9,6 @@
9 9
10typedef struct { 10typedef struct {
11 unsigned int __softirq_pending; 11 unsigned int __softirq_pending;
12#ifdef CONFIG_LOCAL_TIMERS
13 unsigned int local_timer_irqs;
14#endif
15#ifdef CONFIG_SMP 12#ifdef CONFIG_SMP
16 unsigned int ipi_irqs[NR_IPI]; 13 unsigned int ipi_irqs[NR_IPI];
17#endif 14#endif
diff --git a/arch/arm/include/asm/hardware/entry-macro-gic.S b/arch/arm/include/asm/hardware/entry-macro-gic.S
index c115b82fe80a..74ebc803904d 100644
--- a/arch/arm/include/asm/hardware/entry-macro-gic.S
+++ b/arch/arm/include/asm/hardware/entry-macro-gic.S
@@ -22,15 +22,11 @@
22 * interrupt controller spec. To wit: 22 * interrupt controller spec. To wit:
23 * 23 *
24 * Interrupts 0-15 are IPI 24 * Interrupts 0-15 are IPI
25 * 16-28 are reserved 25 * 16-31 are local. We allow 30 to be used for the watchdog.
26 * 29-31 are local. We allow 30 to be used for the watchdog.
27 * 32-1020 are global 26 * 32-1020 are global
28 * 1021-1022 are reserved 27 * 1021-1022 are reserved
29 * 1023 is "spurious" (no interrupt) 28 * 1023 is "spurious" (no interrupt)
30 * 29 *
31 * For now, we ignore all local interrupts so only return an interrupt if it's
32 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
33 *
34 * A simple read from the controller will tell us the number of the highest 30 * A simple read from the controller will tell us the number of the highest
35 * priority enabled interrupt. We then just need to check whether it is in the 31 * priority enabled interrupt. We then just need to check whether it is in the
36 * valid range for an IRQ (30-1020 inclusive). 32 * valid range for an IRQ (30-1020 inclusive).
@@ -43,7 +39,7 @@
43 39
44 ldr \tmp, =1021 40 ldr \tmp, =1021
45 bic \irqnr, \irqstat, #0x1c00 41 bic \irqnr, \irqstat, #0x1c00
46 cmp \irqnr, #29 42 cmp \irqnr, #15
47 cmpcc \irqnr, \irqnr 43 cmpcc \irqnr, \irqnr
48 cmpne \irqnr, \tmp 44 cmpne \irqnr, \tmp
49 cmpcs \irqnr, \irqnr 45 cmpcs \irqnr, \irqnr
@@ -62,14 +58,3 @@
62 strcc \irqstat, [\base, #GIC_CPU_EOI] 58 strcc \irqstat, [\base, #GIC_CPU_EOI]
63 cmpcs \irqnr, \irqnr 59 cmpcs \irqnr, \irqnr
64 .endm 60 .endm
65
66/* As above, this assumes that irqstat and base are preserved.. */
67
68 .macro test_for_ltirq, irqnr, irqstat, base, tmp
69 bic \irqnr, \irqstat, #0x1c00
70 mov \tmp, #0
71 cmp \irqnr, #29
72 moveq \tmp, #1
73 streq \irqstat, [\base, #GIC_CPU_EOI]
74 cmp \tmp, #0
75 .endm
diff --git a/arch/arm/include/asm/hardware/gic.h b/arch/arm/include/asm/hardware/gic.h
index 435d3f86c708..14867e12f205 100644
--- a/arch/arm/include/asm/hardware/gic.h
+++ b/arch/arm/include/asm/hardware/gic.h
@@ -40,12 +40,19 @@ void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
40void gic_secondary_init(unsigned int); 40void gic_secondary_init(unsigned int);
41void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); 41void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
42void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); 42void gic_raise_softirq(const struct cpumask *mask, unsigned int irq);
43void gic_enable_ppi(unsigned int);
44 43
45struct gic_chip_data { 44struct gic_chip_data {
46 unsigned int irq_offset; 45 unsigned int irq_offset;
47 void __iomem *dist_base; 46 void __iomem *dist_base;
48 void __iomem *cpu_base; 47 void __iomem *cpu_base;
48#ifdef CONFIG_CPU_PM
49 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
50 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
51 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
52 u32 __percpu *saved_ppi_enable;
53 u32 __percpu *saved_ppi_conf;
54#endif
55 unsigned int gic_irqs;
49}; 56};
50#endif 57#endif
51 58
diff --git a/arch/arm/include/asm/hw_breakpoint.h b/arch/arm/include/asm/hw_breakpoint.h
index f389b2704d82..c190bc992f0e 100644
--- a/arch/arm/include/asm/hw_breakpoint.h
+++ b/arch/arm/include/asm/hw_breakpoint.h
@@ -50,6 +50,7 @@ static inline void decode_ctrl_reg(u32 reg,
50#define ARM_DEBUG_ARCH_V6_1 2 50#define ARM_DEBUG_ARCH_V6_1 2
51#define ARM_DEBUG_ARCH_V7_ECP14 3 51#define ARM_DEBUG_ARCH_V7_ECP14 3
52#define ARM_DEBUG_ARCH_V7_MM 4 52#define ARM_DEBUG_ARCH_V7_MM 4
53#define ARM_DEBUG_ARCH_V7_1 5
53 54
54/* Breakpoint */ 55/* Breakpoint */
55#define ARM_BREAKPOINT_EXECUTE 0 56#define ARM_BREAKPOINT_EXECUTE 0
@@ -57,6 +58,7 @@ static inline void decode_ctrl_reg(u32 reg,
57/* Watchpoints */ 58/* Watchpoints */
58#define ARM_BREAKPOINT_LOAD 1 59#define ARM_BREAKPOINT_LOAD 1
59#define ARM_BREAKPOINT_STORE 2 60#define ARM_BREAKPOINT_STORE 2
61#define ARM_FSR_ACCESS_MASK (1 << 11)
60 62
61/* Privilege Levels */ 63/* Privilege Levels */
62#define ARM_BREAKPOINT_PRIV 1 64#define ARM_BREAKPOINT_PRIV 1
diff --git a/arch/arm/include/asm/localtimer.h b/arch/arm/include/asm/localtimer.h
index 6fd955d34c65..c6a18424888e 100644
--- a/arch/arm/include/asm/localtimer.h
+++ b/arch/arm/include/asm/localtimer.h
@@ -11,6 +11,7 @@
11#define __ASM_ARM_LOCALTIMER_H 11#define __ASM_ARM_LOCALTIMER_H
12 12
13#include <linux/errno.h> 13#include <linux/errno.h>
14#include <linux/interrupt.h>
14 15
15struct clock_event_device; 16struct clock_event_device;
16 17
@@ -19,31 +20,20 @@ struct clock_event_device;
19 */ 20 */
20void percpu_timer_setup(void); 21void percpu_timer_setup(void);
21 22
22/*
23 * Called from assembly, this is the local timer IRQ handler
24 */
25asmlinkage void do_local_timer(struct pt_regs *);
26
27/*
28 * Called from C code
29 */
30void handle_local_timer(struct pt_regs *);
31
32#ifdef CONFIG_LOCAL_TIMERS 23#ifdef CONFIG_LOCAL_TIMERS
33 24
34#ifdef CONFIG_HAVE_ARM_TWD 25#ifdef CONFIG_HAVE_ARM_TWD
35 26
36#include "smp_twd.h" 27#include "smp_twd.h"
37 28
38#define local_timer_ack() twd_timer_ack() 29#define local_timer_stop(c) twd_timer_stop((c))
39 30
40#else 31#else
41 32
42/* 33/*
43 * Platform provides this to acknowledge a local timer IRQ. 34 * Stop the local timer
44 * Returns true if the local timer IRQ is to be processed.
45 */ 35 */
46int local_timer_ack(void); 36void local_timer_stop(struct clock_event_device *);
47 37
48#endif 38#endif
49 39
@@ -58,6 +48,10 @@ static inline int local_timer_setup(struct clock_event_device *evt)
58{ 48{
59 return -ENXIO; 49 return -ENXIO;
60} 50}
51
52static inline void local_timer_stop(struct clock_event_device *evt)
53{
54}
61#endif 55#endif
62 56
63#endif 57#endif
diff --git a/arch/arm/include/asm/mach/arch.h b/arch/arm/include/asm/mach/arch.h
index c5699987fa98..7d19425dd496 100644
--- a/arch/arm/include/asm/mach/arch.h
+++ b/arch/arm/include/asm/mach/arch.h
@@ -17,7 +17,7 @@ struct sys_timer;
17struct machine_desc { 17struct machine_desc {
18 unsigned int nr; /* architecture number */ 18 unsigned int nr; /* architecture number */
19 const char *name; /* architecture name */ 19 const char *name; /* architecture name */
20 unsigned long boot_params; /* tagged list */ 20 unsigned long atag_offset; /* tagged list (relative) */
21 const char **dt_compat; /* array of device tree 21 const char **dt_compat; /* array of device tree
22 * 'compatible' strings */ 22 * 'compatible' strings */
23 23
diff --git a/arch/arm/include/asm/mach/map.h b/arch/arm/include/asm/mach/map.h
index d2fedb5aeb1f..b36f3654bf54 100644
--- a/arch/arm/include/asm/mach/map.h
+++ b/arch/arm/include/asm/mach/map.h
@@ -29,6 +29,7 @@ struct map_desc {
29#define MT_MEMORY_NONCACHED 11 29#define MT_MEMORY_NONCACHED 11
30#define MT_MEMORY_DTCM 12 30#define MT_MEMORY_DTCM 12
31#define MT_MEMORY_ITCM 13 31#define MT_MEMORY_ITCM 13
32#define MT_MEMORY_SO 14
32 33
33#ifdef CONFIG_MMU 34#ifdef CONFIG_MMU
34extern void iotable_init(struct map_desc *, int); 35extern void iotable_init(struct map_desc *, int);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 441fc4fe8263..a8997d71084e 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -16,9 +16,12 @@
16#include <linux/compiler.h> 16#include <linux/compiler.h>
17#include <linux/const.h> 17#include <linux/const.h>
18#include <linux/types.h> 18#include <linux/types.h>
19#include <mach/memory.h>
20#include <asm/sizes.h> 19#include <asm/sizes.h>
21 20
21#ifdef CONFIG_NEED_MACH_MEMORY_H
22#include <mach/memory.h>
23#endif
24
22/* 25/*
23 * Allow for constants defined here to be used from assembly code 26 * Allow for constants defined here to be used from assembly code
24 * by prepending the UL suffix only with actual C code compilation. 27 * by prepending the UL suffix only with actual C code compilation.
@@ -77,16 +80,7 @@
77 */ 80 */
78#define IOREMAP_MAX_ORDER 24 81#define IOREMAP_MAX_ORDER 24
79 82
80/*
81 * Size of DMA-consistent memory region. Must be multiple of 2M,
82 * between 2MB and 14MB inclusive.
83 */
84#ifndef CONSISTENT_DMA_SIZE
85#define CONSISTENT_DMA_SIZE SZ_2M
86#endif
87
88#define CONSISTENT_END (0xffe00000UL) 83#define CONSISTENT_END (0xffe00000UL)
89#define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE)
90 84
91#else /* CONFIG_MMU */ 85#else /* CONFIG_MMU */
92 86
@@ -193,7 +187,11 @@ static inline unsigned long __phys_to_virt(unsigned long x)
193#endif 187#endif
194 188
195#ifndef PHYS_OFFSET 189#ifndef PHYS_OFFSET
190#ifdef PLAT_PHYS_OFFSET
196#define PHYS_OFFSET PLAT_PHYS_OFFSET 191#define PHYS_OFFSET PLAT_PHYS_OFFSET
192#else
193#define PHYS_OFFSET UL(CONFIG_PHYS_OFFSET)
194#endif
197#endif 195#endif
198 196
199/* 197/*
diff --git a/arch/arm/include/asm/pgtable.h b/arch/arm/include/asm/pgtable.h
index 8ade1840c6f2..9451dce3a553 100644
--- a/arch/arm/include/asm/pgtable.h
+++ b/arch/arm/include/asm/pgtable.h
@@ -101,6 +101,9 @@ extern pgprot_t pgprot_kernel;
101#define pgprot_writecombine(prot) \ 101#define pgprot_writecombine(prot) \
102 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE) 102 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
103 103
104#define pgprot_stronglyordered(prot) \
105 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
106
104#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE 107#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
105#define pgprot_dmacoherent(prot) \ 108#define pgprot_dmacoherent(prot) \
106 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN) 109 __pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE | L_PTE_XN)
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index b7e82c4aced6..71d99b83cdb9 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -13,7 +13,12 @@
13#define __ARM_PMU_H__ 13#define __ARM_PMU_H__
14 14
15#include <linux/interrupt.h> 15#include <linux/interrupt.h>
16#include <linux/perf_event.h>
16 17
18/*
19 * Types of PMUs that can be accessed directly and require mutual
20 * exclusion between profiling tools.
21 */
17enum arm_pmu_type { 22enum arm_pmu_type {
18 ARM_PMU_DEVICE_CPU = 0, 23 ARM_PMU_DEVICE_CPU = 0,
19 ARM_NUM_PMU_DEVICES, 24 ARM_NUM_PMU_DEVICES,
@@ -37,21 +42,17 @@ struct arm_pmu_platdata {
37 * reserve_pmu() - reserve the hardware performance counters 42 * reserve_pmu() - reserve the hardware performance counters
38 * 43 *
39 * Reserve the hardware performance counters in the system for exclusive use. 44 * Reserve the hardware performance counters in the system for exclusive use.
40 * The platform_device for the system is returned on success, ERR_PTR() 45 * Returns 0 on success or -EBUSY if the lock is already held.
41 * encoded error on failure.
42 */ 46 */
43extern struct platform_device * 47extern int
44reserve_pmu(enum arm_pmu_type type); 48reserve_pmu(enum arm_pmu_type type);
45 49
46/** 50/**
47 * release_pmu() - Relinquish control of the performance counters 51 * release_pmu() - Relinquish control of the performance counters
48 * 52 *
49 * Release the performance counters and allow someone else to use them. 53 * Release the performance counters and allow someone else to use them.
50 * Callers must have disabled the counters and released IRQs before calling
51 * this. The platform_device returned from reserve_pmu() must be passed as
52 * a cookie.
53 */ 54 */
54extern int 55extern void
55release_pmu(enum arm_pmu_type type); 56release_pmu(enum arm_pmu_type type);
56 57
57/** 58/**
@@ -68,24 +69,78 @@ init_pmu(enum arm_pmu_type type);
68 69
69#include <linux/err.h> 70#include <linux/err.h>
70 71
71static inline struct platform_device *
72reserve_pmu(enum arm_pmu_type type)
73{
74 return ERR_PTR(-ENODEV);
75}
76
77static inline int 72static inline int
78release_pmu(enum arm_pmu_type type) 73reserve_pmu(enum arm_pmu_type type)
79{ 74{
80 return -ENODEV; 75 return -ENODEV;
81} 76}
82 77
83static inline int 78static inline void
84init_pmu(enum arm_pmu_type type) 79release_pmu(enum arm_pmu_type type) { }
85{
86 return -ENODEV;
87}
88 80
89#endif /* CONFIG_CPU_HAS_PMU */ 81#endif /* CONFIG_CPU_HAS_PMU */
90 82
83#ifdef CONFIG_HW_PERF_EVENTS
84
85/* The events for a given PMU register set. */
86struct pmu_hw_events {
87 /*
88 * The events that are active on the PMU for the given index.
89 */
90 struct perf_event **events;
91
92 /*
93 * A 1 bit for an index indicates that the counter is being used for
94 * an event. A 0 means that the counter can be used.
95 */
96 unsigned long *used_mask;
97
98 /*
99 * Hardware lock to serialize accesses to PMU registers. Needed for the
100 * read/modify/write sequences.
101 */
102 raw_spinlock_t pmu_lock;
103};
104
105struct arm_pmu {
106 struct pmu pmu;
107 enum arm_perf_pmu_ids id;
108 enum arm_pmu_type type;
109 cpumask_t active_irqs;
110 const char *name;
111 irqreturn_t (*handle_irq)(int irq_num, void *dev);
112 void (*enable)(struct hw_perf_event *evt, int idx);
113 void (*disable)(struct hw_perf_event *evt, int idx);
114 int (*get_event_idx)(struct pmu_hw_events *hw_events,
115 struct hw_perf_event *hwc);
116 int (*set_event_filter)(struct hw_perf_event *evt,
117 struct perf_event_attr *attr);
118 u32 (*read_counter)(int idx);
119 void (*write_counter)(int idx, u32 val);
120 void (*start)(void);
121 void (*stop)(void);
122 void (*reset)(void *);
123 int (*map_event)(struct perf_event *event);
124 int num_events;
125 atomic_t active_events;
126 struct mutex reserve_mutex;
127 u64 max_period;
128 struct platform_device *plat_device;
129 struct pmu_hw_events *(*get_hw_events)(void);
130};
131
132#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
133
134int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
135
136u64 armpmu_event_update(struct perf_event *event,
137 struct hw_perf_event *hwc,
138 int idx, int overflow);
139
140int armpmu_event_set_period(struct perf_event *event,
141 struct hw_perf_event *hwc,
142 int idx);
143
144#endif /* CONFIG_HW_PERF_EVENTS */
145
91#endif /* __ARM_PMU_H__ */ 146#endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/include/asm/proc-fns.h b/arch/arm/include/asm/proc-fns.h
index 633d1cb84d87..9e92cb205e65 100644
--- a/arch/arm/include/asm/proc-fns.h
+++ b/arch/arm/include/asm/proc-fns.h
@@ -81,6 +81,10 @@ extern void cpu_dcache_clean_area(void *, int);
81extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm); 81extern void cpu_do_switch_mm(unsigned long pgd_phys, struct mm_struct *mm);
82extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext); 82extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
83extern void cpu_reset(unsigned long addr) __attribute__((noreturn)); 83extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
84
85/* These three are private to arch/arm/kernel/suspend.c */
86extern void cpu_do_suspend(void *);
87extern void cpu_do_resume(void *);
84#else 88#else
85#define cpu_proc_init processor._proc_init 89#define cpu_proc_init processor._proc_init
86#define cpu_proc_fin processor._proc_fin 90#define cpu_proc_fin processor._proc_fin
@@ -89,6 +93,10 @@ extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
89#define cpu_dcache_clean_area processor.dcache_clean_area 93#define cpu_dcache_clean_area processor.dcache_clean_area
90#define cpu_set_pte_ext processor.set_pte_ext 94#define cpu_set_pte_ext processor.set_pte_ext
91#define cpu_do_switch_mm processor.switch_mm 95#define cpu_do_switch_mm processor.switch_mm
96
97/* These three are private to arch/arm/kernel/suspend.c */
98#define cpu_do_suspend processor.do_suspend
99#define cpu_do_resume processor.do_resume
92#endif 100#endif
93 101
94extern void cpu_resume(void); 102extern void cpu_resume(void);
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 0a17b62538c2..1e5717afc4ac 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -99,9 +99,4 @@ extern void platform_cpu_enable(unsigned int cpu);
99extern void arch_send_call_function_single_ipi(int cpu); 99extern void arch_send_call_function_single_ipi(int cpu);
100extern void arch_send_call_function_ipi_mask(const struct cpumask *mask); 100extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
101 101
102/*
103 * show local interrupt info
104 */
105extern void show_local_irqs(struct seq_file *, int);
106
107#endif /* ifndef __ASM_ARM_SMP_H */ 102#endif /* ifndef __ASM_ARM_SMP_H */
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index fed9981fba08..ef9ffba97ad8 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -22,7 +22,7 @@ struct clock_event_device;
22 22
23extern void __iomem *twd_base; 23extern void __iomem *twd_base;
24 24
25int twd_timer_ack(void);
26void twd_timer_setup(struct clock_event_device *); 25void twd_timer_setup(struct clock_event_device *);
26void twd_timer_stop(struct clock_event_device *);
27 27
28#endif 28#endif
diff --git a/arch/arm/include/asm/suspend.h b/arch/arm/include/asm/suspend.h
index b0e4e1a02318..1c0a551ae375 100644
--- a/arch/arm/include/asm/suspend.h
+++ b/arch/arm/include/asm/suspend.h
@@ -1,22 +1,7 @@
1#ifndef __ASM_ARM_SUSPEND_H 1#ifndef __ASM_ARM_SUSPEND_H
2#define __ASM_ARM_SUSPEND_H 2#define __ASM_ARM_SUSPEND_H
3 3
4#include <asm/memory.h>
5#include <asm/tlbflush.h>
6
7extern void cpu_resume(void); 4extern void cpu_resume(void);
8 5extern int cpu_suspend(unsigned long, int (*)(unsigned long));
9/*
10 * Hide the first two arguments to __cpu_suspend - these are an implementation
11 * detail which platform code shouldn't have to know about.
12 */
13static inline int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
14{
15 extern int __cpu_suspend(int, long, unsigned long,
16 int (*)(unsigned long));
17 int ret = __cpu_suspend(0, PHYS_OFFSET - PAGE_OFFSET, arg, fn);
18 flush_tlb_all();
19 return ret;
20}
21 6
22#endif 7#endif
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 68036eece340..16eed6aebfa4 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_MODULES) += armksyms.o module.o
29obj-$(CONFIG_ARTHUR) += arthur.o 29obj-$(CONFIG_ARTHUR) += arthur.o
30obj-$(CONFIG_ISA_DMA) += dma-isa.o 30obj-$(CONFIG_ISA_DMA) += dma-isa.o
31obj-$(CONFIG_PCI) += bios32.o isa.o 31obj-$(CONFIG_PCI) += bios32.o isa.o
32obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o 32obj-$(CONFIG_ARM_CPU_SUSPEND) += sleep.o suspend.o
33obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o 33obj-$(CONFIG_HAVE_SCHED_CLOCK) += sched_clock.o
34obj-$(CONFIG_SMP) += smp.o smp_tlb.o 34obj-$(CONFIG_SMP) += smp.o smp_tlb.o
35obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o 35obj-$(CONFIG_HAVE_ARM_SCU) += smp_scu.o
@@ -43,6 +43,13 @@ obj-$(CONFIG_KPROBES) += kprobes-thumb.o
43else 43else
44obj-$(CONFIG_KPROBES) += kprobes-arm.o 44obj-$(CONFIG_KPROBES) += kprobes-arm.o
45endif 45endif
46obj-$(CONFIG_ARM_KPROBES_TEST) += test-kprobes.o
47test-kprobes-objs := kprobes-test.o
48ifdef CONFIG_THUMB2_KERNEL
49test-kprobes-objs += kprobes-test-thumb.o
50else
51test-kprobes-objs += kprobes-test-arm.o
52endif
46obj-$(CONFIG_ATAGS_PROC) += atags.o 53obj-$(CONFIG_ATAGS_PROC) += atags.o
47obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o 54obj-$(CONFIG_OABI_COMPAT) += sys_oabi-compat.o
48obj-$(CONFIG_ARM_THUMBEE) += thumbee.o 55obj-$(CONFIG_ARM_THUMBEE) += thumbee.o
diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index 0f852d082fcf..204e2160cfcc 100644
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -22,7 +22,7 @@
22#if defined(CONFIG_DEBUG_ICEDCC) 22#if defined(CONFIG_DEBUG_ICEDCC)
23 @@ debug using ARM EmbeddedICE DCC channel 23 @@ debug using ARM EmbeddedICE DCC channel
24 24
25 .macro addruart, rp, rv 25 .macro addruart, rp, rv, tmp
26 .endm 26 .endm
27 27
28#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7) 28#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K) || defined(CONFIG_CPU_V7)
@@ -106,7 +106,7 @@
106 106
107#ifdef CONFIG_MMU 107#ifdef CONFIG_MMU
108 .macro addruart_current, rx, tmp1, tmp2 108 .macro addruart_current, rx, tmp1, tmp2
109 addruart \tmp1, \tmp2 109 addruart \tmp1, \tmp2, \rx
110 mrc p15, 0, \rx, c1, c0 110 mrc p15, 0, \rx, c1, c0
111 tst \rx, #1 111 tst \rx, #1
112 moveq \rx, \tmp1 112 moveq \rx, \tmp1
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 239703dbdf4f..566c54c2a1fe 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -99,7 +99,7 @@ ENTRY(stext)
99 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET) 99 sub r4, r3, r4 @ (PHYS_OFFSET - PAGE_OFFSET)
100 add r8, r8, r4 @ PHYS_OFFSET 100 add r8, r8, r4 @ PHYS_OFFSET
101#else 101#else
102 ldr r8, =PLAT_PHYS_OFFSET 102 ldr r8, =PHYS_OFFSET @ always constant in this case
103#endif 103#endif
104 104
105 /* 105 /*
@@ -238,7 +238,7 @@ __create_page_tables:
238 * This allows debug messages to be output 238 * This allows debug messages to be output
239 * via a serial console before paging_init. 239 * via a serial console before paging_init.
240 */ 240 */
241 addruart r7, r3 241 addruart r7, r3, r0
242 242
243 mov r3, r3, lsr #SECTION_SHIFT 243 mov r3, r3, lsr #SECTION_SHIFT
244 mov r3, r3, lsl #PMD_ORDER 244 mov r3, r3, lsl #PMD_ORDER
diff --git a/arch/arm/kernel/hw_breakpoint.c b/arch/arm/kernel/hw_breakpoint.c
index a927ca1f5566..814a52a9dc39 100644
--- a/arch/arm/kernel/hw_breakpoint.c
+++ b/arch/arm/kernel/hw_breakpoint.c
@@ -45,7 +45,6 @@ static DEFINE_PER_CPU(struct perf_event *, wp_on_reg[ARM_MAX_WRP]);
45 45
46/* Number of BRP/WRP registers on this CPU. */ 46/* Number of BRP/WRP registers on this CPU. */
47static int core_num_brps; 47static int core_num_brps;
48static int core_num_reserved_brps;
49static int core_num_wrps; 48static int core_num_wrps;
50 49
51/* Debug architecture version. */ 50/* Debug architecture version. */
@@ -137,10 +136,11 @@ static u8 get_debug_arch(void)
137 u32 didr; 136 u32 didr;
138 137
139 /* Do we implement the extended CPUID interface? */ 138 /* Do we implement the extended CPUID interface? */
140 if (WARN_ONCE((((read_cpuid_id() >> 16) & 0xf) != 0xf), 139 if (((read_cpuid_id() >> 16) & 0xf) != 0xf) {
141 "CPUID feature registers not supported. " 140 pr_warning("CPUID feature registers not supported. "
142 "Assuming v6 debug is present.\n")) 141 "Assuming v6 debug is present.\n");
143 return ARM_DEBUG_ARCH_V6; 142 return ARM_DEBUG_ARCH_V6;
143 }
144 144
145 ARM_DBG_READ(c0, 0, didr); 145 ARM_DBG_READ(c0, 0, didr);
146 return (didr >> 16) & 0xf; 146 return (didr >> 16) & 0xf;
@@ -154,10 +154,21 @@ u8 arch_get_debug_arch(void)
154static int debug_arch_supported(void) 154static int debug_arch_supported(void)
155{ 155{
156 u8 arch = get_debug_arch(); 156 u8 arch = get_debug_arch();
157 return arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14; 157
158 /* We don't support the memory-mapped interface. */
159 return (arch >= ARM_DEBUG_ARCH_V6 && arch <= ARM_DEBUG_ARCH_V7_ECP14) ||
160 arch >= ARM_DEBUG_ARCH_V7_1;
161}
162
163/* Determine number of WRP registers available. */
164static int get_num_wrp_resources(void)
165{
166 u32 didr;
167 ARM_DBG_READ(c0, 0, didr);
168 return ((didr >> 28) & 0xf) + 1;
158} 169}
159 170
160/* Determine number of BRP register available. */ 171/* Determine number of BRP registers available. */
161static int get_num_brp_resources(void) 172static int get_num_brp_resources(void)
162{ 173{
163 u32 didr; 174 u32 didr;
@@ -176,9 +187,10 @@ static int core_has_mismatch_brps(void)
176static int get_num_wrps(void) 187static int get_num_wrps(void)
177{ 188{
178 /* 189 /*
179 * FIXME: When a watchpoint fires, the only way to work out which 190 * On debug architectures prior to 7.1, when a watchpoint fires, the
180 * watchpoint it was is by disassembling the faulting instruction 191 * only way to work out which watchpoint it was is by disassembling
181 * and working out the address of the memory access. 192 * the faulting instruction and working out the address of the memory
193 * access.
182 * 194 *
183 * Furthermore, we can only do this if the watchpoint was precise 195 * Furthermore, we can only do this if the watchpoint was precise
184 * since imprecise watchpoints prevent us from calculating register 196 * since imprecise watchpoints prevent us from calculating register
@@ -192,36 +204,17 @@ static int get_num_wrps(void)
192 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows 204 * [the ARM ARM states that the DFAR is UNKNOWN, but experience shows
193 * that it is set on some implementations]. 205 * that it is set on some implementations].
194 */ 206 */
207 if (get_debug_arch() < ARM_DEBUG_ARCH_V7_1)
208 return 1;
195 209
196#if 0 210 return get_num_wrp_resources();
197 int wrps;
198 u32 didr;
199 ARM_DBG_READ(c0, 0, didr);
200 wrps = ((didr >> 28) & 0xf) + 1;
201#endif
202 int wrps = 1;
203
204 if (core_has_mismatch_brps() && wrps >= get_num_brp_resources())
205 wrps = get_num_brp_resources() - 1;
206
207 return wrps;
208}
209
210/* We reserve one breakpoint for each watchpoint. */
211static int get_num_reserved_brps(void)
212{
213 if (core_has_mismatch_brps())
214 return get_num_wrps();
215 return 0;
216} 211}
217 212
218/* Determine number of usable BRPs available. */ 213/* Determine number of usable BRPs available. */
219static int get_num_brps(void) 214static int get_num_brps(void)
220{ 215{
221 int brps = get_num_brp_resources(); 216 int brps = get_num_brp_resources();
222 if (core_has_mismatch_brps()) 217 return core_has_mismatch_brps() ? brps - 1 : brps;
223 brps -= get_num_reserved_brps();
224 return brps;
225} 218}
226 219
227/* 220/*
@@ -239,7 +232,7 @@ static int enable_monitor_mode(void)
239 232
240 /* Ensure that halting mode is disabled. */ 233 /* Ensure that halting mode is disabled. */
241 if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN, 234 if (WARN_ONCE(dscr & ARM_DSCR_HDBGEN,
242 "halting debug mode enabled. Unable to access hardware resources.\n")) { 235 "halting debug mode enabled. Unable to access hardware resources.\n")) {
243 ret = -EPERM; 236 ret = -EPERM;
244 goto out; 237 goto out;
245 } 238 }
@@ -255,6 +248,7 @@ static int enable_monitor_mode(void)
255 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN)); 248 ARM_DBG_WRITE(c1, 0, (dscr | ARM_DSCR_MDBGEN));
256 break; 249 break;
257 case ARM_DEBUG_ARCH_V7_ECP14: 250 case ARM_DEBUG_ARCH_V7_ECP14:
251 case ARM_DEBUG_ARCH_V7_1:
258 ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN)); 252 ARM_DBG_WRITE(c2, 2, (dscr | ARM_DSCR_MDBGEN));
259 break; 253 break;
260 default: 254 default:
@@ -346,24 +340,10 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
346 val_base = ARM_BASE_BVR; 340 val_base = ARM_BASE_BVR;
347 slots = (struct perf_event **)__get_cpu_var(bp_on_reg); 341 slots = (struct perf_event **)__get_cpu_var(bp_on_reg);
348 max_slots = core_num_brps; 342 max_slots = core_num_brps;
349 if (info->step_ctrl.enabled) {
350 /* Override the breakpoint data with the step data. */
351 addr = info->trigger & ~0x3;
352 ctrl = encode_ctrl_reg(info->step_ctrl);
353 }
354 } else { 343 } else {
355 /* Watchpoint */ 344 /* Watchpoint */
356 if (info->step_ctrl.enabled) { 345 ctrl_base = ARM_BASE_WCR;
357 /* Install into the reserved breakpoint region. */ 346 val_base = ARM_BASE_WVR;
358 ctrl_base = ARM_BASE_BCR + core_num_brps;
359 val_base = ARM_BASE_BVR + core_num_brps;
360 /* Override the watchpoint data with the step data. */
361 addr = info->trigger & ~0x3;
362 ctrl = encode_ctrl_reg(info->step_ctrl);
363 } else {
364 ctrl_base = ARM_BASE_WCR;
365 val_base = ARM_BASE_WVR;
366 }
367 slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 347 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
368 max_slots = core_num_wrps; 348 max_slots = core_num_wrps;
369 } 349 }
@@ -382,6 +362,17 @@ int arch_install_hw_breakpoint(struct perf_event *bp)
382 goto out; 362 goto out;
383 } 363 }
384 364
365 /* Override the breakpoint data with the step data. */
366 if (info->step_ctrl.enabled) {
367 addr = info->trigger & ~0x3;
368 ctrl = encode_ctrl_reg(info->step_ctrl);
369 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE) {
370 i = 0;
371 ctrl_base = ARM_BASE_BCR + core_num_brps;
372 val_base = ARM_BASE_BVR + core_num_brps;
373 }
374 }
375
385 /* Setup the address register. */ 376 /* Setup the address register. */
386 write_wb_reg(val_base + i, addr); 377 write_wb_reg(val_base + i, addr);
387 378
@@ -405,10 +396,7 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
405 max_slots = core_num_brps; 396 max_slots = core_num_brps;
406 } else { 397 } else {
407 /* Watchpoint */ 398 /* Watchpoint */
408 if (info->step_ctrl.enabled) 399 base = ARM_BASE_WCR;
409 base = ARM_BASE_BCR + core_num_brps;
410 else
411 base = ARM_BASE_WCR;
412 slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 400 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
413 max_slots = core_num_wrps; 401 max_slots = core_num_wrps;
414 } 402 }
@@ -426,6 +414,13 @@ void arch_uninstall_hw_breakpoint(struct perf_event *bp)
426 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n")) 414 if (WARN_ONCE(i == max_slots, "Can't find any breakpoint slot\n"))
427 return; 415 return;
428 416
417 /* Ensure that we disable the mismatch breakpoint. */
418 if (info->ctrl.type != ARM_BREAKPOINT_EXECUTE &&
419 info->step_ctrl.enabled) {
420 i = 0;
421 base = ARM_BASE_BCR + core_num_brps;
422 }
423
429 /* Reset the control register. */ 424 /* Reset the control register. */
430 write_wb_reg(base + i, 0); 425 write_wb_reg(base + i, 0);
431} 426}
@@ -632,10 +627,9 @@ int arch_validate_hwbkpt_settings(struct perf_event *bp)
632 * we can use the mismatch feature as a poor-man's hardware 627 * we can use the mismatch feature as a poor-man's hardware
633 * single-step, but this only works for per-task breakpoints. 628 * single-step, but this only works for per-task breakpoints.
634 */ 629 */
635 if (WARN_ONCE(!bp->overflow_handler && 630 if (!bp->overflow_handler && (arch_check_bp_in_kernelspace(bp) ||
636 (arch_check_bp_in_kernelspace(bp) || !core_has_mismatch_brps() 631 !core_has_mismatch_brps() || !bp->hw.bp_target)) {
637 || !bp->hw.bp_target), 632 pr_warning("overflow handler required but none found\n");
638 "overflow handler required but none found\n")) {
639 ret = -EINVAL; 633 ret = -EINVAL;
640 } 634 }
641out: 635out:
@@ -666,34 +660,62 @@ static void disable_single_step(struct perf_event *bp)
666 arch_install_hw_breakpoint(bp); 660 arch_install_hw_breakpoint(bp);
667} 661}
668 662
669static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs) 663static void watchpoint_handler(unsigned long addr, unsigned int fsr,
664 struct pt_regs *regs)
670{ 665{
671 int i; 666 int i, access;
667 u32 val, ctrl_reg, alignment_mask;
672 struct perf_event *wp, **slots; 668 struct perf_event *wp, **slots;
673 struct arch_hw_breakpoint *info; 669 struct arch_hw_breakpoint *info;
670 struct arch_hw_breakpoint_ctrl ctrl;
674 671
675 slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 672 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
676 673
677 /* Without a disassembler, we can only handle 1 watchpoint. */
678 BUG_ON(core_num_wrps > 1);
679
680 for (i = 0; i < core_num_wrps; ++i) { 674 for (i = 0; i < core_num_wrps; ++i) {
681 rcu_read_lock(); 675 rcu_read_lock();
682 676
683 wp = slots[i]; 677 wp = slots[i];
684 678
685 if (wp == NULL) { 679 if (wp == NULL)
686 rcu_read_unlock(); 680 goto unlock;
687 continue;
688 }
689 681
682 info = counter_arch_bp(wp);
690 /* 683 /*
691 * The DFAR is an unknown value. Since we only allow a 684 * The DFAR is an unknown value on debug architectures prior
692 * single watchpoint, we can set the trigger to the lowest 685 * to 7.1. Since we only allow a single watchpoint on these
693 * possible faulting address. 686 * older CPUs, we can set the trigger to the lowest possible
687 * faulting address.
694 */ 688 */
695 info = counter_arch_bp(wp); 689 if (debug_arch < ARM_DEBUG_ARCH_V7_1) {
696 info->trigger = wp->attr.bp_addr; 690 BUG_ON(i > 0);
691 info->trigger = wp->attr.bp_addr;
692 } else {
693 if (info->ctrl.len == ARM_BREAKPOINT_LEN_8)
694 alignment_mask = 0x7;
695 else
696 alignment_mask = 0x3;
697
698 /* Check if the watchpoint value matches. */
699 val = read_wb_reg(ARM_BASE_WVR + i);
700 if (val != (addr & ~alignment_mask))
701 goto unlock;
702
703 /* Possible match, check the byte address select. */
704 ctrl_reg = read_wb_reg(ARM_BASE_WCR + i);
705 decode_ctrl_reg(ctrl_reg, &ctrl);
706 if (!((1 << (addr & alignment_mask)) & ctrl.len))
707 goto unlock;
708
709 /* Check that the access type matches. */
710 access = (fsr & ARM_FSR_ACCESS_MASK) ? HW_BREAKPOINT_W :
711 HW_BREAKPOINT_R;
712 if (!(access & hw_breakpoint_type(wp)))
713 goto unlock;
714
715 /* We have a winner. */
716 info->trigger = addr;
717 }
718
697 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger); 719 pr_debug("watchpoint fired: address = 0x%x\n", info->trigger);
698 perf_bp_event(wp, regs); 720 perf_bp_event(wp, regs);
699 721
@@ -705,6 +727,7 @@ static void watchpoint_handler(unsigned long unknown, struct pt_regs *regs)
705 if (!wp->overflow_handler) 727 if (!wp->overflow_handler)
706 enable_single_step(wp, instruction_pointer(regs)); 728 enable_single_step(wp, instruction_pointer(regs));
707 729
730unlock:
708 rcu_read_unlock(); 731 rcu_read_unlock();
709 } 732 }
710} 733}
@@ -717,7 +740,7 @@ static void watchpoint_single_step_handler(unsigned long pc)
717 740
718 slots = (struct perf_event **)__get_cpu_var(wp_on_reg); 741 slots = (struct perf_event **)__get_cpu_var(wp_on_reg);
719 742
720 for (i = 0; i < core_num_reserved_brps; ++i) { 743 for (i = 0; i < core_num_wrps; ++i) {
721 rcu_read_lock(); 744 rcu_read_lock();
722 745
723 wp = slots[i]; 746 wp = slots[i];
@@ -820,7 +843,7 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
820 case ARM_ENTRY_ASYNC_WATCHPOINT: 843 case ARM_ENTRY_ASYNC_WATCHPOINT:
821 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n"); 844 WARN(1, "Asynchronous watchpoint exception taken. Debugging results may be unreliable\n");
822 case ARM_ENTRY_SYNC_WATCHPOINT: 845 case ARM_ENTRY_SYNC_WATCHPOINT:
823 watchpoint_handler(addr, regs); 846 watchpoint_handler(addr, fsr, regs);
824 break; 847 break;
825 default: 848 default:
826 ret = 1; /* Unhandled fault. */ 849 ret = 1; /* Unhandled fault. */
@@ -834,11 +857,31 @@ static int hw_breakpoint_pending(unsigned long addr, unsigned int fsr,
834/* 857/*
835 * One-time initialisation. 858 * One-time initialisation.
836 */ 859 */
837static void reset_ctrl_regs(void *info) 860static cpumask_t debug_err_mask;
861
862static int debug_reg_trap(struct pt_regs *regs, unsigned int instr)
838{ 863{
839 int i, cpu = smp_processor_id(); 864 int cpu = smp_processor_id();
865
866 pr_warning("Debug register access (0x%x) caused undefined instruction on CPU %d\n",
867 instr, cpu);
868
869 /* Set the error flag for this CPU and skip the faulting instruction. */
870 cpumask_set_cpu(cpu, &debug_err_mask);
871 instruction_pointer(regs) += 4;
872 return 0;
873}
874
875static struct undef_hook debug_reg_hook = {
876 .instr_mask = 0x0fe80f10,
877 .instr_val = 0x0e000e10,
878 .fn = debug_reg_trap,
879};
880
881static void reset_ctrl_regs(void *unused)
882{
883 int i, raw_num_brps, err = 0, cpu = smp_processor_id();
840 u32 dbg_power; 884 u32 dbg_power;
841 cpumask_t *cpumask = info;
842 885
843 /* 886 /*
844 * v7 debug contains save and restore registers so that debug state 887 * v7 debug contains save and restore registers so that debug state
@@ -848,38 +891,57 @@ static void reset_ctrl_regs(void *info)
848 * Access Register to avoid taking undefined instruction exceptions 891 * Access Register to avoid taking undefined instruction exceptions
849 * later on. 892 * later on.
850 */ 893 */
851 if (debug_arch >= ARM_DEBUG_ARCH_V7_ECP14) { 894 switch (debug_arch) {
895 case ARM_DEBUG_ARCH_V6:
896 case ARM_DEBUG_ARCH_V6_1:
897 /* ARMv6 cores just need to reset the registers. */
898 goto reset_regs;
899 case ARM_DEBUG_ARCH_V7_ECP14:
852 /* 900 /*
853 * Ensure sticky power-down is clear (i.e. debug logic is 901 * Ensure sticky power-down is clear (i.e. debug logic is
854 * powered up). 902 * powered up).
855 */ 903 */
856 asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power)); 904 asm volatile("mrc p14, 0, %0, c1, c5, 4" : "=r" (dbg_power));
857 if ((dbg_power & 0x1) == 0) { 905 if ((dbg_power & 0x1) == 0)
858 pr_warning("CPU %d debug is powered down!\n", cpu); 906 err = -EPERM;
859 cpumask_or(cpumask, cpumask, cpumask_of(cpu)); 907 break;
860 return; 908 case ARM_DEBUG_ARCH_V7_1:
861 }
862
863 /* 909 /*
864 * Unconditionally clear the lock by writing a value 910 * Ensure the OS double lock is clear.
865 * other than 0xC5ACCE55 to the access register.
866 */ 911 */
867 asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0)); 912 asm volatile("mrc p14, 0, %0, c1, c3, 4" : "=r" (dbg_power));
868 isb(); 913 if ((dbg_power & 0x1) == 1)
914 err = -EPERM;
915 break;
916 }
869 917
870 /* 918 if (err) {
871 * Clear any configured vector-catch events before 919 pr_warning("CPU %d debug is powered down!\n", cpu);
872 * enabling monitor mode. 920 cpumask_or(&debug_err_mask, &debug_err_mask, cpumask_of(cpu));
873 */ 921 return;
874 asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
875 isb();
876 } 922 }
877 923
924 /*
925 * Unconditionally clear the lock by writing a value
926 * other than 0xC5ACCE55 to the access register.
927 */
928 asm volatile("mcr p14, 0, %0, c1, c0, 4" : : "r" (0));
929 isb();
930
931 /*
932 * Clear any configured vector-catch events before
933 * enabling monitor mode.
934 */
935 asm volatile("mcr p14, 0, %0, c0, c7, 0" : : "r" (0));
936 isb();
937
938reset_regs:
878 if (enable_monitor_mode()) 939 if (enable_monitor_mode())
879 return; 940 return;
880 941
881 /* We must also reset any reserved registers. */ 942 /* We must also reset any reserved registers. */
882 for (i = 0; i < core_num_brps + core_num_reserved_brps; ++i) { 943 raw_num_brps = get_num_brp_resources();
944 for (i = 0; i < raw_num_brps; ++i) {
883 write_wb_reg(ARM_BASE_BCR + i, 0UL); 945 write_wb_reg(ARM_BASE_BCR + i, 0UL);
884 write_wb_reg(ARM_BASE_BVR + i, 0UL); 946 write_wb_reg(ARM_BASE_BVR + i, 0UL);
885 } 947 }
@@ -895,6 +957,7 @@ static int __cpuinit dbg_reset_notify(struct notifier_block *self,
895{ 957{
896 if (action == CPU_ONLINE) 958 if (action == CPU_ONLINE)
897 smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1); 959 smp_call_function_single((int)cpu, reset_ctrl_regs, NULL, 1);
960
898 return NOTIFY_OK; 961 return NOTIFY_OK;
899} 962}
900 963
@@ -905,7 +968,6 @@ static struct notifier_block __cpuinitdata dbg_reset_nb = {
905static int __init arch_hw_breakpoint_init(void) 968static int __init arch_hw_breakpoint_init(void)
906{ 969{
907 u32 dscr; 970 u32 dscr;
908 cpumask_t cpumask = { CPU_BITS_NONE };
909 971
910 debug_arch = get_debug_arch(); 972 debug_arch = get_debug_arch();
911 973
@@ -916,28 +978,31 @@ static int __init arch_hw_breakpoint_init(void)
916 978
917 /* Determine how many BRPs/WRPs are available. */ 979 /* Determine how many BRPs/WRPs are available. */
918 core_num_brps = get_num_brps(); 980 core_num_brps = get_num_brps();
919 core_num_reserved_brps = get_num_reserved_brps();
920 core_num_wrps = get_num_wrps(); 981 core_num_wrps = get_num_wrps();
921 982
922 pr_info("found %d breakpoint and %d watchpoint registers.\n", 983 /*
923 core_num_brps + core_num_reserved_brps, core_num_wrps); 984 * We need to tread carefully here because DBGSWENABLE may be
924 985 * driven low on this core and there isn't an architected way to
925 if (core_num_reserved_brps) 986 * determine that.
926 pr_info("%d breakpoint(s) reserved for watchpoint " 987 */
927 "single-step.\n", core_num_reserved_brps); 988 register_undef_hook(&debug_reg_hook);
928 989
929 /* 990 /*
930 * Reset the breakpoint resources. We assume that a halting 991 * Reset the breakpoint resources. We assume that a halting
931 * debugger will leave the world in a nice state for us. 992 * debugger will leave the world in a nice state for us.
932 */ 993 */
933 on_each_cpu(reset_ctrl_regs, &cpumask, 1); 994 on_each_cpu(reset_ctrl_regs, NULL, 1);
934 if (!cpumask_empty(&cpumask)) { 995 unregister_undef_hook(&debug_reg_hook);
996 if (!cpumask_empty(&debug_err_mask)) {
935 core_num_brps = 0; 997 core_num_brps = 0;
936 core_num_reserved_brps = 0;
937 core_num_wrps = 0; 998 core_num_wrps = 0;
938 return 0; 999 return 0;
939 } 1000 }
940 1001
1002 pr_info("found %d " "%s" "breakpoint and %d watchpoint registers.\n",
1003 core_num_brps, core_has_mismatch_brps() ? "(+1 reserved) " :
1004 "", core_num_wrps);
1005
941 ARM_DBG_READ(c1, 0, dscr); 1006 ARM_DBG_READ(c1, 0, dscr);
942 if (dscr & ARM_DSCR_HDBGEN) { 1007 if (dscr & ARM_DSCR_HDBGEN) {
943 max_watchpoint_len = 4; 1008 max_watchpoint_len = 4;
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 53919b230e8b..7cb29261249a 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -59,9 +59,6 @@ int arch_show_interrupts(struct seq_file *p, int prec)
59#ifdef CONFIG_SMP 59#ifdef CONFIG_SMP
60 show_ipi_list(p, prec); 60 show_ipi_list(p, prec);
61#endif 61#endif
62#ifdef CONFIG_LOCAL_TIMERS
63 show_local_irqs(p, prec);
64#endif
65 seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count); 62 seq_printf(p, "%*s: %10lu\n", prec, "Err", irq_err_count);
66 return 0; 63 return 0;
67} 64}
diff --git a/arch/arm/kernel/kprobes-arm.c b/arch/arm/kernel/kprobes-arm.c
index 79203ee1d039..9fe8910308af 100644
--- a/arch/arm/kernel/kprobes-arm.c
+++ b/arch/arm/kernel/kprobes-arm.c
@@ -60,6 +60,7 @@
60 60
61#include <linux/kernel.h> 61#include <linux/kernel.h>
62#include <linux/kprobes.h> 62#include <linux/kprobes.h>
63#include <linux/module.h>
63 64
64#include "kprobes.h" 65#include "kprobes.h"
65 66
@@ -971,6 +972,9 @@ const union decode_item kprobe_decode_arm_table[] = {
971 972
972 DECODE_END 973 DECODE_END
973}; 974};
975#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
976EXPORT_SYMBOL_GPL(kprobe_decode_arm_table);
977#endif
974 978
975static void __kprobes arm_singlestep(struct kprobe *p, struct pt_regs *regs) 979static void __kprobes arm_singlestep(struct kprobe *p, struct pt_regs *regs)
976{ 980{
diff --git a/arch/arm/kernel/kprobes-test-arm.c b/arch/arm/kernel/kprobes-test-arm.c
new file mode 100644
index 000000000000..fc82de8bdcce
--- /dev/null
+++ b/arch/arm/kernel/kprobes-test-arm.c
@@ -0,0 +1,1323 @@
1/*
2 * arch/arm/kernel/kprobes-test-arm.c
3 *
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13
14#include "kprobes-test.h"
15
16
17#define TEST_ISA "32"
18
19#define TEST_ARM_TO_THUMB_INTERWORK_R(code1, reg, val, code2) \
20 TESTCASE_START(code1 #reg code2) \
21 TEST_ARG_REG(reg, val) \
22 TEST_ARG_REG(14, 99f) \
23 TEST_ARG_END("") \
24 "50: nop \n\t" \
25 "1: "code1 #reg code2" \n\t" \
26 " bx lr \n\t" \
27 ".thumb \n\t" \
28 "3: adr lr, 2f \n\t" \
29 " bx lr \n\t" \
30 ".arm \n\t" \
31 "2: nop \n\t" \
32 TESTCASE_END
33
34#define TEST_ARM_TO_THUMB_INTERWORK_P(code1, reg, val, code2) \
35 TESTCASE_START(code1 #reg code2) \
36 TEST_ARG_PTR(reg, val) \
37 TEST_ARG_REG(14, 99f) \
38 TEST_ARG_MEM(15, 3f+1) \
39 TEST_ARG_END("") \
40 "50: nop \n\t" \
41 "1: "code1 #reg code2" \n\t" \
42 " bx lr \n\t" \
43 ".thumb \n\t" \
44 "3: adr lr, 2f \n\t" \
45 " bx lr \n\t" \
46 ".arm \n\t" \
47 "2: nop \n\t" \
48 TESTCASE_END
49
50
51void kprobe_arm_test_cases(void)
52{
53 kprobe_test_flags = 0;
54
55 TEST_GROUP("Data-processing (register), (register-shifted register), (immediate)")
56
57#define _DATA_PROCESSING_DNM(op,s,val) \
58 TEST_RR( op "eq" s " r0, r",1, VAL1,", r",2, val, "") \
59 TEST_RR( op "ne" s " r1, r",1, VAL1,", r",2, val, ", lsl #3") \
60 TEST_RR( op "cs" s " r2, r",3, VAL1,", r",2, val, ", lsr #4") \
61 TEST_RR( op "cc" s " r3, r",3, VAL1,", r",2, val, ", asr #5") \
62 TEST_RR( op "mi" s " r4, r",5, VAL1,", r",2, N(val),", asr #6") \
63 TEST_RR( op "pl" s " r5, r",5, VAL1,", r",2, val, ", ror #7") \
64 TEST_RR( op "vs" s " r6, r",7, VAL1,", r",2, val, ", rrx") \
65 TEST_R( op "vc" s " r6, r",7, VAL1,", pc, lsl #3") \
66 TEST_R( op "vc" s " r6, r",7, VAL1,", sp, lsr #4") \
67 TEST_R( op "vc" s " r6, pc, r",7, VAL1,", asr #5") \
68 TEST_R( op "vc" s " r6, sp, r",7, VAL1,", ror #6") \
69 TEST_RRR( op "hi" s " r8, r",9, VAL1,", r",14,val, ", lsl r",0, 3,"")\
70 TEST_RRR( op "ls" s " r9, r",9, VAL1,", r",14,val, ", lsr r",7, 4,"")\
71 TEST_RRR( op "ge" s " r10, r",11,VAL1,", r",14,val, ", asr r",7, 5,"")\
72 TEST_RRR( op "lt" s " r11, r",11,VAL1,", r",14,N(val),", asr r",7, 6,"")\
73 TEST_RR( op "gt" s " r12, r13" ", r",14,val, ", ror r",14,7,"")\
74 TEST_RR( op "le" s " r14, r",0, val, ", r13" ", lsl r",14,8,"")\
75 TEST_RR( op s " r12, pc" ", r",14,val, ", ror r",14,7,"")\
76 TEST_RR( op s " r14, r",0, val, ", pc" ", lsl r",14,8,"")\
77 TEST_R( op "eq" s " r0, r",11,VAL1,", #0xf5") \
78 TEST_R( op "ne" s " r11, r",0, VAL1,", #0xf5000000") \
79 TEST_R( op s " r7, r",8, VAL2,", #0x000af000") \
80 TEST( op s " r4, pc" ", #0x00005a00")
81
82#define DATA_PROCESSING_DNM(op,val) \
83 _DATA_PROCESSING_DNM(op,"",val) \
84 _DATA_PROCESSING_DNM(op,"s",val)
85
86#define DATA_PROCESSING_NM(op,val) \
87 TEST_RR( op "ne r",1, VAL1,", r",2, val, "") \
88 TEST_RR( op "eq r",1, VAL1,", r",2, val, ", lsl #3") \
89 TEST_RR( op "cc r",3, VAL1,", r",2, val, ", lsr #4") \
90 TEST_RR( op "cs r",3, VAL1,", r",2, val, ", asr #5") \
91 TEST_RR( op "pl r",5, VAL1,", r",2, N(val),", asr #6") \
92 TEST_RR( op "mi r",5, VAL1,", r",2, val, ", ror #7") \
93 TEST_RR( op "vc r",7, VAL1,", r",2, val, ", rrx") \
94 TEST_R ( op "vs r",7, VAL1,", pc, lsl #3") \
95 TEST_R ( op "vs r",7, VAL1,", sp, lsr #4") \
96 TEST_R( op "vs pc, r",7, VAL1,", asr #5") \
97 TEST_R( op "vs sp, r",7, VAL1,", ror #6") \
98 TEST_RRR( op "ls r",9, VAL1,", r",14,val, ", lsl r",0, 3,"") \
99 TEST_RRR( op "hi r",9, VAL1,", r",14,val, ", lsr r",7, 4,"") \
100 TEST_RRR( op "lt r",11,VAL1,", r",14,val, ", asr r",7, 5,"") \
101 TEST_RRR( op "ge r",11,VAL1,", r",14,N(val),", asr r",7, 6,"") \
102 TEST_RR( op "le r13" ", r",14,val, ", ror r",14,7,"") \
103 TEST_RR( op "gt r",0, val, ", r13" ", lsl r",14,8,"") \
104 TEST_RR( op " pc" ", r",14,val, ", ror r",14,7,"") \
105 TEST_RR( op " r",0, val, ", pc" ", lsl r",14,8,"") \
106 TEST_R( op "eq r",11,VAL1,", #0xf5") \
107 TEST_R( op "ne r",0, VAL1,", #0xf5000000") \
108 TEST_R( op " r",8, VAL2,", #0x000af000")
109
110#define _DATA_PROCESSING_DM(op,s,val) \
111 TEST_R( op "eq" s " r0, r",1, val, "") \
112 TEST_R( op "ne" s " r1, r",1, val, ", lsl #3") \
113 TEST_R( op "cs" s " r2, r",3, val, ", lsr #4") \
114 TEST_R( op "cc" s " r3, r",3, val, ", asr #5") \
115 TEST_R( op "mi" s " r4, r",5, N(val),", asr #6") \
116 TEST_R( op "pl" s " r5, r",5, val, ", ror #7") \
117 TEST_R( op "vs" s " r6, r",10,val, ", rrx") \
118 TEST( op "vs" s " r7, pc, lsl #3") \
119 TEST( op "vs" s " r7, sp, lsr #4") \
120 TEST_RR( op "vc" s " r8, r",7, val, ", lsl r",0, 3,"") \
121 TEST_RR( op "hi" s " r9, r",9, val, ", lsr r",7, 4,"") \
122 TEST_RR( op "ls" s " r10, r",9, val, ", asr r",7, 5,"") \
123 TEST_RR( op "ge" s " r11, r",11,N(val),", asr r",7, 6,"") \
124 TEST_RR( op "lt" s " r12, r",11,val, ", ror r",14,7,"") \
125 TEST_R( op "gt" s " r14, r13" ", lsl r",14,8,"") \
126 TEST_R( op "le" s " r14, pc" ", lsl r",14,8,"") \
127 TEST( op "eq" s " r0, #0xf5") \
128 TEST( op "ne" s " r11, #0xf5000000") \
129 TEST( op s " r7, #0x000af000") \
130 TEST( op s " r4, #0x00005a00")
131
132#define DATA_PROCESSING_DM(op,val) \
133 _DATA_PROCESSING_DM(op,"",val) \
134 _DATA_PROCESSING_DM(op,"s",val)
135
136 DATA_PROCESSING_DNM("and",0xf00f00ff)
137 DATA_PROCESSING_DNM("eor",0xf00f00ff)
138 DATA_PROCESSING_DNM("sub",VAL2)
139 DATA_PROCESSING_DNM("rsb",VAL2)
140 DATA_PROCESSING_DNM("add",VAL2)
141 DATA_PROCESSING_DNM("adc",VAL2)
142 DATA_PROCESSING_DNM("sbc",VAL2)
143 DATA_PROCESSING_DNM("rsc",VAL2)
144 DATA_PROCESSING_NM("tst",0xf00f00ff)
145 DATA_PROCESSING_NM("teq",0xf00f00ff)
146 DATA_PROCESSING_NM("cmp",VAL2)
147 DATA_PROCESSING_NM("cmn",VAL2)
148 DATA_PROCESSING_DNM("orr",0xf00f00ff)
149 DATA_PROCESSING_DM("mov",VAL2)
150 DATA_PROCESSING_DNM("bic",0xf00f00ff)
151 DATA_PROCESSING_DM("mvn",VAL2)
152
153 TEST("mov ip, sp") /* This has special case emulation code */
154
155 TEST_SUPPORTED("mov pc, #0x1000");
156 TEST_SUPPORTED("mov sp, #0x1000");
157 TEST_SUPPORTED("cmp pc, #0x1000");
158 TEST_SUPPORTED("cmp sp, #0x1000");
159
160 /* Data-processing with PC as shift*/
161 TEST_UNSUPPORTED(".word 0xe15c0f1e @ cmp r12, r14, asl pc")
162 TEST_UNSUPPORTED(".word 0xe1a0cf1e @ mov r12, r14, asl pc")
163 TEST_UNSUPPORTED(".word 0xe08caf1e @ add r10, r12, r14, asl pc")
164
165 /* Data-processing with PC as shift*/
166 TEST_UNSUPPORTED("movs pc, r1")
167 TEST_UNSUPPORTED("movs pc, r1, lsl r2")
168 TEST_UNSUPPORTED("movs pc, #0x10000")
169 TEST_UNSUPPORTED("adds pc, lr, r1")
170 TEST_UNSUPPORTED("adds pc, lr, r1, lsl r2")
171 TEST_UNSUPPORTED("adds pc, lr, #4")
172
173 /* Data-processing with SP as target */
174 TEST("add sp, sp, #16")
175 TEST("sub sp, sp, #8")
176 TEST("bic sp, sp, #0x20")
177 TEST("orr sp, sp, #0x20")
178 TEST_PR( "add sp, r",10,0,", r",11,4,"")
179 TEST_PRR("add sp, r",10,0,", r",11,4,", asl r",12,1,"")
180 TEST_P( "mov sp, r",10,0,"")
181 TEST_PR( "mov sp, r",10,0,", asl r",12,0,"")
182
183 /* Data-processing with PC as target */
184 TEST_BF( "add pc, pc, #2f-1b-8")
185 TEST_BF_R ("add pc, pc, r",14,2f-1f-8,"")
186 TEST_BF_R ("add pc, r",14,2f-1f-8,", pc")
187 TEST_BF_R ("mov pc, r",0,2f,"")
188 TEST_BF_RR("mov pc, r",0,2f,", asl r",1,0,"")
189 TEST_BB( "sub pc, pc, #1b-2b+8")
190#if __LINUX_ARM_ARCH__ >= 6
191 TEST_BB( "sub pc, pc, #1b-2b+8-2") /* UNPREDICTABLE before ARMv6 */
192#endif
193 TEST_BB_R( "sub pc, pc, r",14, 1f-2f+8,"")
194 TEST_BB_R( "rsb pc, r",14,1f-2f+8,", pc")
195 TEST_RR( "add pc, pc, r",10,-2,", asl r",11,1,"")
196#ifdef CONFIG_THUMB2_KERNEL
197 TEST_ARM_TO_THUMB_INTERWORK_R("add pc, pc, r",0,3f-1f-8+1,"")
198 TEST_ARM_TO_THUMB_INTERWORK_R("sub pc, r",0,3f+8+1,", #8")
199#endif
200 TEST_GROUP("Miscellaneous instructions")
201
202 TEST("mrs r0, cpsr")
203 TEST("mrspl r7, cpsr")
204 TEST("mrs r14, cpsr")
205 TEST_UNSUPPORTED(".word 0xe10ff000 @ mrs r15, cpsr")
206 TEST_UNSUPPORTED("mrs r0, spsr")
207 TEST_UNSUPPORTED("mrs lr, spsr")
208
209 TEST_UNSUPPORTED("msr cpsr, r0")
210 TEST_UNSUPPORTED("msr cpsr_f, lr")
211 TEST_UNSUPPORTED("msr spsr, r0")
212
213 TEST_BF_R("bx r",0,2f,"")
214 TEST_BB_R("bx r",7,2f,"")
215 TEST_BF_R("bxeq r",14,2f,"")
216
217 TEST_R("clz r0, r",0, 0x0,"")
218 TEST_R("clzeq r7, r",14,0x1,"")
219 TEST_R("clz lr, r",7, 0xffffffff,"")
220 TEST( "clz r4, sp")
221 TEST_UNSUPPORTED(".word 0x016fff10 @ clz pc, r0")
222 TEST_UNSUPPORTED(".word 0x016f0f1f @ clz r0, pc")
223
224#if __LINUX_ARM_ARCH__ >= 6
225 TEST_UNSUPPORTED("bxj r0")
226#endif
227
228 TEST_BF_R("blx r",0,2f,"")
229 TEST_BB_R("blx r",7,2f,"")
230 TEST_BF_R("blxeq r",14,2f,"")
231 TEST_UNSUPPORTED(".word 0x0120003f @ blx pc")
232
233 TEST_RR( "qadd r0, r",1, VAL1,", r",2, VAL2,"")
234 TEST_RR( "qaddvs lr, r",9, VAL2,", r",8, VAL1,"")
235 TEST_R( "qadd lr, r",9, VAL2,", r13")
236 TEST_RR( "qsub r0, r",1, VAL1,", r",2, VAL2,"")
237 TEST_RR( "qsubvs lr, r",9, VAL2,", r",8, VAL1,"")
238 TEST_R( "qsub lr, r",9, VAL2,", r13")
239 TEST_RR( "qdadd r0, r",1, VAL1,", r",2, VAL2,"")
240 TEST_RR( "qdaddvs lr, r",9, VAL2,", r",8, VAL1,"")
241 TEST_R( "qdadd lr, r",9, VAL2,", r13")
242 TEST_RR( "qdsub r0, r",1, VAL1,", r",2, VAL2,"")
243 TEST_RR( "qdsubvs lr, r",9, VAL2,", r",8, VAL1,"")
244 TEST_R( "qdsub lr, r",9, VAL2,", r13")
245 TEST_UNSUPPORTED(".word 0xe101f050 @ qadd pc, r0, r1")
246 TEST_UNSUPPORTED(".word 0xe121f050 @ qsub pc, r0, r1")
247 TEST_UNSUPPORTED(".word 0xe141f050 @ qdadd pc, r0, r1")
248 TEST_UNSUPPORTED(".word 0xe161f050 @ qdsub pc, r0, r1")
249 TEST_UNSUPPORTED(".word 0xe16f2050 @ qdsub r2, r0, pc")
250 TEST_UNSUPPORTED(".word 0xe161205f @ qdsub r2, pc, r1")
251
252 TEST_UNSUPPORTED("bkpt 0xffff")
253 TEST_UNSUPPORTED("bkpt 0x0000")
254
255 TEST_UNSUPPORTED(".word 0xe1600070 @ smc #0")
256
257 TEST_GROUP("Halfword multiply and multiply-accumulate")
258
259 TEST_RRR( "smlabb r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
260 TEST_RRR( "smlabbge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
261 TEST_RR( "smlabb lr, r",1, VAL2,", r",2, VAL3,", r13")
262 TEST_UNSUPPORTED(".word 0xe10f3281 @ smlabb pc, r1, r2, r3")
263 TEST_RRR( "smlatb r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
264 TEST_RRR( "smlatbge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
265 TEST_RR( "smlatb lr, r",1, VAL2,", r",2, VAL3,", r13")
266 TEST_UNSUPPORTED(".word 0xe10f32a1 @ smlatb pc, r1, r2, r3")
267 TEST_RRR( "smlabt r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
268 TEST_RRR( "smlabtge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
269 TEST_RR( "smlabt lr, r",1, VAL2,", r",2, VAL3,", r13")
270 TEST_UNSUPPORTED(".word 0xe10f32c1 @ smlabt pc, r1, r2, r3")
271 TEST_RRR( "smlatt r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
272 TEST_RRR( "smlattge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
273 TEST_RR( "smlatt lr, r",1, VAL2,", r",2, VAL3,", r13")
274 TEST_UNSUPPORTED(".word 0xe10f32e1 @ smlatt pc, r1, r2, r3")
275
276 TEST_RRR( "smlawb r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
277 TEST_RRR( "smlawbge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
278 TEST_RR( "smlawb lr, r",1, VAL2,", r",2, VAL3,", r13")
279 TEST_UNSUPPORTED(".word 0xe12f3281 @ smlawb pc, r1, r2, r3")
280 TEST_RRR( "smlawt r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
281 TEST_RRR( "smlawtge r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
282 TEST_RR( "smlawt lr, r",1, VAL2,", r",2, VAL3,", r13")
283 TEST_UNSUPPORTED(".word 0xe12f32c1 @ smlawt pc, r1, r2, r3")
284 TEST_UNSUPPORTED(".word 0xe12032cf @ smlawt r0, pc, r2, r3")
285 TEST_UNSUPPORTED(".word 0xe1203fc1 @ smlawt r0, r1, pc, r3")
286 TEST_UNSUPPORTED(".word 0xe120f2c1 @ smlawt r0, r1, r2, pc")
287
288 TEST_RR( "smulwb r0, r",1, VAL1,", r",2, VAL2,"")
289 TEST_RR( "smulwbge r7, r",8, VAL3,", r",9, VAL1,"")
290 TEST_R( "smulwb lr, r",1, VAL2,", r13")
291 TEST_UNSUPPORTED(".word 0xe12f02a1 @ smulwb pc, r1, r2")
292 TEST_RR( "smulwt r0, r",1, VAL1,", r",2, VAL2,"")
293 TEST_RR( "smulwtge r7, r",8, VAL3,", r",9, VAL1,"")
294 TEST_R( "smulwt lr, r",1, VAL2,", r13")
295 TEST_UNSUPPORTED(".word 0xe12f02e1 @ smulwt pc, r1, r2")
296
297 TEST_RRRR( "smlalbb r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
298 TEST_RRRR( "smlalbble r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
299 TEST_RRR( "smlalbb r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
300 TEST_UNSUPPORTED(".word 0xe14f1382 @ smlalbb pc, r1, r2, r3")
301 TEST_UNSUPPORTED(".word 0xe141f382 @ smlalbb r1, pc, r2, r3")
302 TEST_RRRR( "smlaltb r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
303 TEST_RRRR( "smlaltble r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
304 TEST_RRR( "smlaltb r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
305 TEST_UNSUPPORTED(".word 0xe14f13a2 @ smlaltb pc, r1, r2, r3")
306 TEST_UNSUPPORTED(".word 0xe141f3a2 @ smlaltb r1, pc, r2, r3")
307 TEST_RRRR( "smlalbt r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
308 TEST_RRRR( "smlalbtle r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
309 TEST_RRR( "smlalbt r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
310 TEST_UNSUPPORTED(".word 0xe14f13c2 @ smlalbt pc, r1, r2, r3")
311 TEST_UNSUPPORTED(".word 0xe141f3c2 @ smlalbt r1, pc, r2, r3")
312 TEST_RRRR( "smlaltt r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
313 TEST_RRRR( "smlalttle r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
314 TEST_RRR( "smlaltt r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
315 TEST_UNSUPPORTED(".word 0xe14f13e2 @ smlalbb pc, r1, r2, r3")
316 TEST_UNSUPPORTED(".word 0xe140f3e2 @ smlalbb r0, pc, r2, r3")
317 TEST_UNSUPPORTED(".word 0xe14013ef @ smlalbb r0, r1, pc, r3")
318 TEST_UNSUPPORTED(".word 0xe1401fe2 @ smlalbb r0, r1, r2, pc")
319
320 TEST_RR( "smulbb r0, r",1, VAL1,", r",2, VAL2,"")
321 TEST_RR( "smulbbge r7, r",8, VAL3,", r",9, VAL1,"")
322 TEST_R( "smulbb lr, r",1, VAL2,", r13")
323 TEST_UNSUPPORTED(".word 0xe16f0281 @ smulbb pc, r1, r2")
324 TEST_RR( "smultb r0, r",1, VAL1,", r",2, VAL2,"")
325 TEST_RR( "smultbge r7, r",8, VAL3,", r",9, VAL1,"")
326 TEST_R( "smultb lr, r",1, VAL2,", r13")
327 TEST_UNSUPPORTED(".word 0xe16f02a1 @ smultb pc, r1, r2")
328 TEST_RR( "smulbt r0, r",1, VAL1,", r",2, VAL2,"")
329 TEST_RR( "smulbtge r7, r",8, VAL3,", r",9, VAL1,"")
330 TEST_R( "smulbt lr, r",1, VAL2,", r13")
331 TEST_UNSUPPORTED(".word 0xe16f02c1 @ smultb pc, r1, r2")
332 TEST_RR( "smultt r0, r",1, VAL1,", r",2, VAL2,"")
333 TEST_RR( "smulttge r7, r",8, VAL3,", r",9, VAL1,"")
334 TEST_R( "smultt lr, r",1, VAL2,", r13")
335 TEST_UNSUPPORTED(".word 0xe16f02e1 @ smultt pc, r1, r2")
336 TEST_UNSUPPORTED(".word 0xe16002ef @ smultt r0, pc, r2")
337 TEST_UNSUPPORTED(".word 0xe1600fe1 @ smultt r0, r1, pc")
338
339 TEST_GROUP("Multiply and multiply-accumulate")
340
341 TEST_RR( "mul r0, r",1, VAL1,", r",2, VAL2,"")
342 TEST_RR( "mulls r7, r",8, VAL2,", r",9, VAL2,"")
343 TEST_R( "mul lr, r",4, VAL3,", r13")
344 TEST_UNSUPPORTED(".word 0xe00f0291 @ mul pc, r1, r2")
345 TEST_UNSUPPORTED(".word 0xe000029f @ mul r0, pc, r2")
346 TEST_UNSUPPORTED(".word 0xe0000f91 @ mul r0, r1, pc")
347 TEST_RR( "muls r0, r",1, VAL1,", r",2, VAL2,"")
348 TEST_RR( "mullss r7, r",8, VAL2,", r",9, VAL2,"")
349 TEST_R( "muls lr, r",4, VAL3,", r13")
350 TEST_UNSUPPORTED(".word 0xe01f0291 @ muls pc, r1, r2")
351
352 TEST_RRR( "mla r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
353 TEST_RRR( "mlahi r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
354 TEST_RR( "mla lr, r",1, VAL2,", r",2, VAL3,", r13")
355 TEST_UNSUPPORTED(".word 0xe02f3291 @ mla pc, r1, r2, r3")
356 TEST_RRR( "mlas r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
357 TEST_RRR( "mlahis r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
358 TEST_RR( "mlas lr, r",1, VAL2,", r",2, VAL3,", r13")
359 TEST_UNSUPPORTED(".word 0xe03f3291 @ mlas pc, r1, r2, r3")
360
361#if __LINUX_ARM_ARCH__ >= 6
362 TEST_RR( "umaal r0, r1, r",2, VAL1,", r",3, VAL2,"")
363 TEST_RR( "umaalls r7, r8, r",9, VAL2,", r",10, VAL1,"")
364 TEST_R( "umaal lr, r12, r",11,VAL3,", r13")
365 TEST_UNSUPPORTED(".word 0xe041f392 @ umaal pc, r1, r2, r3")
366 TEST_UNSUPPORTED(".word 0xe04f0392 @ umaal r0, pc, r2, r3")
367 TEST_UNSUPPORTED(".word 0xe0500090 @ undef")
368 TEST_UNSUPPORTED(".word 0xe05fff9f @ undef")
369
370 TEST_RRR( "mls r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
371 TEST_RRR( "mlshi r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
372 TEST_RR( "mls lr, r",1, VAL2,", r",2, VAL3,", r13")
373 TEST_UNSUPPORTED(".word 0xe06f3291 @ mls pc, r1, r2, r3")
374 TEST_UNSUPPORTED(".word 0xe060329f @ mls r0, pc, r2, r3")
375 TEST_UNSUPPORTED(".word 0xe0603f91 @ mls r0, r1, pc, r3")
376 TEST_UNSUPPORTED(".word 0xe060f291 @ mls r0, r1, r2, pc")
377#endif
378
379 TEST_UNSUPPORTED(".word 0xe0700090 @ undef")
380 TEST_UNSUPPORTED(".word 0xe07fff9f @ undef")
381
382 TEST_RR( "umull r0, r1, r",2, VAL1,", r",3, VAL2,"")
383 TEST_RR( "umullls r7, r8, r",9, VAL2,", r",10, VAL1,"")
384 TEST_R( "umull lr, r12, r",11,VAL3,", r13")
385 TEST_UNSUPPORTED(".word 0xe081f392 @ umull pc, r1, r2, r3")
386 TEST_UNSUPPORTED(".word 0xe08f1392 @ umull r1, pc, r2, r3")
387 TEST_RR( "umulls r0, r1, r",2, VAL1,", r",3, VAL2,"")
388 TEST_RR( "umulllss r7, r8, r",9, VAL2,", r",10, VAL1,"")
389 TEST_R( "umulls lr, r12, r",11,VAL3,", r13")
390 TEST_UNSUPPORTED(".word 0xe091f392 @ umulls pc, r1, r2, r3")
391 TEST_UNSUPPORTED(".word 0xe09f1392 @ umulls r1, pc, r2, r3")
392
393 TEST_RRRR( "umlal r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
394 TEST_RRRR( "umlalle r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
395 TEST_RRR( "umlal r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
396 TEST_UNSUPPORTED(".word 0xe0af1392 @ umlal pc, r1, r2, r3")
397 TEST_UNSUPPORTED(".word 0xe0a1f392 @ umlal r1, pc, r2, r3")
398 TEST_RRRR( "umlals r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
399 TEST_RRRR( "umlalles r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
400 TEST_RRR( "umlals r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
401 TEST_UNSUPPORTED(".word 0xe0bf1392 @ umlals pc, r1, r2, r3")
402 TEST_UNSUPPORTED(".word 0xe0b1f392 @ umlals r1, pc, r2, r3")
403
404 TEST_RR( "smull r0, r1, r",2, VAL1,", r",3, VAL2,"")
405 TEST_RR( "smullls r7, r8, r",9, VAL2,", r",10, VAL1,"")
406 TEST_R( "smull lr, r12, r",11,VAL3,", r13")
407 TEST_UNSUPPORTED(".word 0xe0c1f392 @ smull pc, r1, r2, r3")
408 TEST_UNSUPPORTED(".word 0xe0cf1392 @ smull r1, pc, r2, r3")
409 TEST_RR( "smulls r0, r1, r",2, VAL1,", r",3, VAL2,"")
410 TEST_RR( "smulllss r7, r8, r",9, VAL2,", r",10, VAL1,"")
411 TEST_R( "smulls lr, r12, r",11,VAL3,", r13")
412 TEST_UNSUPPORTED(".word 0xe0d1f392 @ smulls pc, r1, r2, r3")
413 TEST_UNSUPPORTED(".word 0xe0df1392 @ smulls r1, pc, r2, r3")
414
415 TEST_RRRR( "smlal r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
416 TEST_RRRR( "smlalle r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
417 TEST_RRR( "smlal r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
418 TEST_UNSUPPORTED(".word 0xe0ef1392 @ smlal pc, r1, r2, r3")
419 TEST_UNSUPPORTED(".word 0xe0e1f392 @ smlal r1, pc, r2, r3")
420 TEST_RRRR( "smlals r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
421 TEST_RRRR( "smlalles r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
422 TEST_RRR( "smlals r",14,VAL3,", r",7, VAL4,", r",5, VAL1,", r13")
423 TEST_UNSUPPORTED(".word 0xe0ff1392 @ smlals pc, r1, r2, r3")
424 TEST_UNSUPPORTED(".word 0xe0f0f392 @ smlals r0, pc, r2, r3")
425 TEST_UNSUPPORTED(".word 0xe0f0139f @ smlals r0, r1, pc, r3")
426 TEST_UNSUPPORTED(".word 0xe0f01f92 @ smlals r0, r1, r2, pc")
427
428 TEST_GROUP("Synchronization primitives")
429
430 /*
431 * Use hard coded constants for SWP instructions to avoid warnings
432 * about deprecated instructions.
433 */
434 TEST_RP( ".word 0xe108e097 @ swp lr, r",7,VAL2,", [r",8,0,"]")
435 TEST_R( ".word 0x610d0091 @ swpvs r0, r",1,VAL1,", [sp]")
436 TEST_RP( ".word 0xe10cd09e @ swp sp, r",14,VAL2,", [r",12,13*4,"]")
437 TEST_UNSUPPORTED(".word 0xe102f091 @ swp pc, r1, [r2]")
438 TEST_UNSUPPORTED(".word 0xe102009f @ swp r0, pc, [r2]")
439 TEST_UNSUPPORTED(".word 0xe10f0091 @ swp r0, r1, [pc]")
440 TEST_RP( ".word 0xe148e097 @ swpb lr, r",7,VAL2,", [r",8,0,"]")
441 TEST_R( ".word 0x614d0091 @ swpvsb r0, r",1,VAL1,", [sp]")
442 TEST_UNSUPPORTED(".word 0xe142f091 @ swpb pc, r1, [r2]")
443
444 TEST_UNSUPPORTED(".word 0xe1100090") /* Unallocated space */
445 TEST_UNSUPPORTED(".word 0xe1200090") /* Unallocated space */
446 TEST_UNSUPPORTED(".word 0xe1300090") /* Unallocated space */
447 TEST_UNSUPPORTED(".word 0xe1500090") /* Unallocated space */
448 TEST_UNSUPPORTED(".word 0xe1600090") /* Unallocated space */
449 TEST_UNSUPPORTED(".word 0xe1700090") /* Unallocated space */
450#if __LINUX_ARM_ARCH__ >= 6
451 TEST_UNSUPPORTED("ldrex r2, [sp]")
452 TEST_UNSUPPORTED("strexd r0, r2, r3, [sp]")
453 TEST_UNSUPPORTED("ldrexd r2, r3, [sp]")
454 TEST_UNSUPPORTED("strexb r0, r2, [sp]")
455 TEST_UNSUPPORTED("ldrexb r2, [sp]")
456 TEST_UNSUPPORTED("strexh r0, r2, [sp]")
457 TEST_UNSUPPORTED("ldrexh r2, [sp]")
458#endif
459 TEST_GROUP("Extra load/store instructions")
460
461 TEST_RPR( "strh r",0, VAL1,", [r",1, 48,", -r",2, 24,"]")
462 TEST_RPR( "streqh r",14,VAL2,", [r",13,0, ", r",12, 48,"]")
463 TEST_RPR( "strh r",1, VAL1,", [r",2, 24,", r",3, 48,"]!")
464 TEST_RPR( "strneh r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
465 TEST_RPR( "strh r",2, VAL1,", [r",3, 24,"], r",4, 48,"")
466 TEST_RPR( "strh r",10,VAL2,", [r",9, 48,"], -r",11,24,"")
467 TEST_UNSUPPORTED(".word 0xe1afc0ba @ strh r12, [pc, r10]!")
468 TEST_UNSUPPORTED(".word 0xe089f0bb @ strh pc, [r9], r11")
469 TEST_UNSUPPORTED(".word 0xe089a0bf @ strh r10, [r9], pc")
470
471 TEST_PR( "ldrh r0, [r",0, 48,", -r",2, 24,"]")
472 TEST_PR( "ldrcsh r14, [r",13,0, ", r",12, 48,"]")
473 TEST_PR( "ldrh r1, [r",2, 24,", r",3, 48,"]!")
474 TEST_PR( "ldrcch r12, [r",11,48,", -r",10,24,"]!")
475 TEST_PR( "ldrh r2, [r",3, 24,"], r",4, 48,"")
476 TEST_PR( "ldrh r10, [r",9, 48,"], -r",11,24,"")
477 TEST_UNSUPPORTED(".word 0xe1bfc0ba @ ldrh r12, [pc, r10]!")
478 TEST_UNSUPPORTED(".word 0xe099f0bb @ ldrh pc, [r9], r11")
479 TEST_UNSUPPORTED(".word 0xe099a0bf @ ldrh r10, [r9], pc")
480
481 TEST_RP( "strh r",0, VAL1,", [r",1, 24,", #-2]")
482 TEST_RP( "strmih r",14,VAL2,", [r",13,0, ", #2]")
483 TEST_RP( "strh r",1, VAL1,", [r",2, 24,", #4]!")
484 TEST_RP( "strplh r",12,VAL2,", [r",11,24,", #-4]!")
485 TEST_RP( "strh r",2, VAL1,", [r",3, 24,"], #48")
486 TEST_RP( "strh r",10,VAL2,", [r",9, 64,"], #-48")
487 TEST_UNSUPPORTED(".word 0xe1efc3b0 @ strh r12, [pc, #48]!")
488 TEST_UNSUPPORTED(".word 0xe0c9f3b0 @ strh pc, [r9], #48")
489
490 TEST_P( "ldrh r0, [r",0, 24,", #-2]")
491 TEST_P( "ldrvsh r14, [r",13,0, ", #2]")
492 TEST_P( "ldrh r1, [r",2, 24,", #4]!")
493 TEST_P( "ldrvch r12, [r",11,24,", #-4]!")
494 TEST_P( "ldrh r2, [r",3, 24,"], #48")
495 TEST_P( "ldrh r10, [r",9, 64,"], #-48")
496 TEST( "ldrh r0, [pc, #0]")
497 TEST_UNSUPPORTED(".word 0xe1ffc3b0 @ ldrh r12, [pc, #48]!")
498 TEST_UNSUPPORTED(".word 0xe0d9f3b0 @ ldrh pc, [r9], #48")
499
500 TEST_PR( "ldrsb r0, [r",0, 48,", -r",2, 24,"]")
501 TEST_PR( "ldrhisb r14, [r",13,0,", r",12, 48,"]")
502 TEST_PR( "ldrsb r1, [r",2, 24,", r",3, 48,"]!")
503 TEST_PR( "ldrlssb r12, [r",11,48,", -r",10,24,"]!")
504 TEST_PR( "ldrsb r2, [r",3, 24,"], r",4, 48,"")
505 TEST_PR( "ldrsb r10, [r",9, 48,"], -r",11,24,"")
506 TEST_UNSUPPORTED(".word 0xe1bfc0da @ ldrsb r12, [pc, r10]!")
507 TEST_UNSUPPORTED(".word 0xe099f0db @ ldrsb pc, [r9], r11")
508
509 TEST_P( "ldrsb r0, [r",0, 24,", #-1]")
510 TEST_P( "ldrgesb r14, [r",13,0, ", #1]")
511 TEST_P( "ldrsb r1, [r",2, 24,", #4]!")
512 TEST_P( "ldrltsb r12, [r",11,24,", #-4]!")
513 TEST_P( "ldrsb r2, [r",3, 24,"], #48")
514 TEST_P( "ldrsb r10, [r",9, 64,"], #-48")
515 TEST( "ldrsb r0, [pc, #0]")
516 TEST_UNSUPPORTED(".word 0xe1ffc3d0 @ ldrsb r12, [pc, #48]!")
517 TEST_UNSUPPORTED(".word 0xe0d9f3d0 @ ldrsb pc, [r9], #48")
518
519 TEST_PR( "ldrsh r0, [r",0, 48,", -r",2, 24,"]")
520 TEST_PR( "ldrgtsh r14, [r",13,0, ", r",12, 48,"]")
521 TEST_PR( "ldrsh r1, [r",2, 24,", r",3, 48,"]!")
522 TEST_PR( "ldrlesh r12, [r",11,48,", -r",10,24,"]!")
523 TEST_PR( "ldrsh r2, [r",3, 24,"], r",4, 48,"")
524 TEST_PR( "ldrsh r10, [r",9, 48,"], -r",11,24,"")
525 TEST_UNSUPPORTED(".word 0xe1bfc0fa @ ldrsh r12, [pc, r10]!")
526 TEST_UNSUPPORTED(".word 0xe099f0fb @ ldrsh pc, [r9], r11")
527
528 TEST_P( "ldrsh r0, [r",0, 24,", #-1]")
529 TEST_P( "ldreqsh r14, [r",13,0 ,", #1]")
530 TEST_P( "ldrsh r1, [r",2, 24,", #4]!")
531 TEST_P( "ldrnesh r12, [r",11,24,", #-4]!")
532 TEST_P( "ldrsh r2, [r",3, 24,"], #48")
533 TEST_P( "ldrsh r10, [r",9, 64,"], #-48")
534 TEST( "ldrsh r0, [pc, #0]")
535 TEST_UNSUPPORTED(".word 0xe1ffc3f0 @ ldrsh r12, [pc, #48]!")
536 TEST_UNSUPPORTED(".word 0xe0d9f3f0 @ ldrsh pc, [r9], #48")
537
538#if __LINUX_ARM_ARCH__ >= 7
539 TEST_UNSUPPORTED("strht r1, [r2], r3")
540 TEST_UNSUPPORTED("ldrht r1, [r2], r3")
541 TEST_UNSUPPORTED("strht r1, [r2], #48")
542 TEST_UNSUPPORTED("ldrht r1, [r2], #48")
543 TEST_UNSUPPORTED("ldrsbt r1, [r2], r3")
544 TEST_UNSUPPORTED("ldrsbt r1, [r2], #48")
545 TEST_UNSUPPORTED("ldrsht r1, [r2], r3")
546 TEST_UNSUPPORTED("ldrsht r1, [r2], #48")
547#endif
548
549 TEST_RPR( "strd r",0, VAL1,", [r",1, 48,", -r",2,24,"]")
550 TEST_RPR( "strccd r",8, VAL2,", [r",13,0, ", r",12,48,"]")
551 TEST_RPR( "strd r",4, VAL1,", [r",2, 24,", r",3, 48,"]!")
552 TEST_RPR( "strcsd r",12,VAL2,", [r",11,48,", -r",10,24,"]!")
553 TEST_RPR( "strd r",2, VAL1,", [r",3, 24,"], r",4,48,"")
554 TEST_RPR( "strd r",10,VAL2,", [r",9, 48,"], -r",7,24,"")
555 TEST_UNSUPPORTED(".word 0xe1afc0fa @ strd r12, [pc, r10]!")
556
557 TEST_PR( "ldrd r0, [r",0, 48,", -r",2,24,"]")
558 TEST_PR( "ldrmid r8, [r",13,0, ", r",12,48,"]")
559 TEST_PR( "ldrd r4, [r",2, 24,", r",3, 48,"]!")
560 TEST_PR( "ldrpld r6, [r",11,48,", -r",10,24,"]!")
561 TEST_PR( "ldrd r2, [r",5, 24,"], r",4,48,"")
562 TEST_PR( "ldrd r10, [r",9,48,"], -r",7,24,"")
563 TEST_UNSUPPORTED(".word 0xe1afc0da @ ldrd r12, [pc, r10]!")
564 TEST_UNSUPPORTED(".word 0xe089f0db @ ldrd pc, [r9], r11")
565 TEST_UNSUPPORTED(".word 0xe089e0db @ ldrd lr, [r9], r11")
566 TEST_UNSUPPORTED(".word 0xe089c0df @ ldrd r12, [r9], pc")
567
568 TEST_RP( "strd r",0, VAL1,", [r",1, 24,", #-8]")
569 TEST_RP( "strvsd r",8, VAL2,", [r",13,0, ", #8]")
570 TEST_RP( "strd r",4, VAL1,", [r",2, 24,", #16]!")
571 TEST_RP( "strvcd r",12,VAL2,", [r",11,24,", #-16]!")
572 TEST_RP( "strd r",2, VAL1,", [r",4, 24,"], #48")
573 TEST_RP( "strd r",10,VAL2,", [r",9, 64,"], #-48")
574 TEST_UNSUPPORTED(".word 0xe1efc3f0 @ strd r12, [pc, #48]!")
575
576 TEST_P( "ldrd r0, [r",0, 24,", #-8]")
577 TEST_P( "ldrhid r8, [r",13,0, ", #8]")
578 TEST_P( "ldrd r4, [r",2, 24,", #16]!")
579 TEST_P( "ldrlsd r6, [r",11,24,", #-16]!")
580 TEST_P( "ldrd r2, [r",5, 24,"], #48")
581 TEST_P( "ldrd r10, [r",9,6,"], #-48")
582 TEST_UNSUPPORTED(".word 0xe1efc3d0 @ ldrd r12, [pc, #48]!")
583 TEST_UNSUPPORTED(".word 0xe0c9f3d0 @ ldrd pc, [r9], #48")
584 TEST_UNSUPPORTED(".word 0xe0c9e3d0 @ ldrd lr, [r9], #48")
585
586 TEST_GROUP("Miscellaneous")
587
588#if __LINUX_ARM_ARCH__ >= 7
589 TEST("movw r0, #0")
590 TEST("movw r0, #0xffff")
591 TEST("movw lr, #0xffff")
592 TEST_UNSUPPORTED(".word 0xe300f000 @ movw pc, #0")
593 TEST_R("movt r",0, VAL1,", #0")
594 TEST_R("movt r",0, VAL2,", #0xffff")
595 TEST_R("movt r",14,VAL1,", #0xffff")
596 TEST_UNSUPPORTED(".word 0xe340f000 @ movt pc, #0")
597#endif
598
599 TEST_UNSUPPORTED("msr cpsr, 0x13")
600 TEST_UNSUPPORTED("msr cpsr_f, 0xf0000000")
601 TEST_UNSUPPORTED("msr spsr, 0x13")
602
603#if __LINUX_ARM_ARCH__ >= 7
604 TEST_SUPPORTED("yield")
605 TEST("sev")
606 TEST("nop")
607 TEST("wfi")
608 TEST_SUPPORTED("wfe")
609 TEST_UNSUPPORTED("dbg #0")
610#endif
611
612 TEST_GROUP("Load/store word and unsigned byte")
613
614#define LOAD_STORE(byte) \
615 TEST_RP( "str"byte" r",0, VAL1,", [r",1, 24,", #-2]") \
616 TEST_RP( "str"byte" r",14,VAL2,", [r",13,0, ", #2]") \
617 TEST_RP( "str"byte" r",1, VAL1,", [r",2, 24,", #4]!") \
618 TEST_RP( "str"byte" r",12,VAL2,", [r",11,24,", #-4]!") \
619 TEST_RP( "str"byte" r",2, VAL1,", [r",3, 24,"], #48") \
620 TEST_RP( "str"byte" r",10,VAL2,", [r",9, 64,"], #-48") \
621 TEST_RPR("str"byte" r",0, VAL1,", [r",1, 48,", -r",2, 24,"]") \
622 TEST_RPR("str"byte" r",14,VAL2,", [r",13,0, ", r",12, 48,"]") \
623 TEST_RPR("str"byte" r",1, VAL1,", [r",2, 24,", r",3, 48,"]!") \
624 TEST_RPR("str"byte" r",12,VAL2,", [r",11,48,", -r",10,24,"]!") \
625 TEST_RPR("str"byte" r",2, VAL1,", [r",3, 24,"], r",4, 48,"") \
626 TEST_RPR("str"byte" r",10,VAL2,", [r",9, 48,"], -r",11,24,"") \
627 TEST_RPR("str"byte" r",0, VAL1,", [r",1, 24,", r",2, 32,", asl #1]")\
628 TEST_RPR("str"byte" r",14,VAL2,", [r",13,0, ", r",12, 32,", lsr #2]")\
629 TEST_RPR("str"byte" r",1, VAL1,", [r",2, 24,", r",3, 32,", asr #3]!")\
630 TEST_RPR("str"byte" r",12,VAL2,", [r",11,24,", r",10, 4,", ror #31]!")\
631 TEST_P( "ldr"byte" r0, [r",0, 24,", #-2]") \
632 TEST_P( "ldr"byte" r14, [r",13,0, ", #2]") \
633 TEST_P( "ldr"byte" r1, [r",2, 24,", #4]!") \
634 TEST_P( "ldr"byte" r12, [r",11,24,", #-4]!") \
635 TEST_P( "ldr"byte" r2, [r",3, 24,"], #48") \
636 TEST_P( "ldr"byte" r10, [r",9, 64,"], #-48") \
637 TEST_PR( "ldr"byte" r0, [r",0, 48,", -r",2, 24,"]") \
638 TEST_PR( "ldr"byte" r14, [r",13,0, ", r",12, 48,"]") \
639 TEST_PR( "ldr"byte" r1, [r",2, 24,", r",3, 48,"]!") \
640 TEST_PR( "ldr"byte" r12, [r",11,48,", -r",10,24,"]!") \
641 TEST_PR( "ldr"byte" r2, [r",3, 24,"], r",4, 48,"") \
642 TEST_PR( "ldr"byte" r10, [r",9, 48,"], -r",11,24,"") \
643 TEST_PR( "ldr"byte" r0, [r",0, 24,", r",2, 32,", asl #1]") \
644 TEST_PR( "ldr"byte" r14, [r",13,0, ", r",12, 32,", lsr #2]") \
645 TEST_PR( "ldr"byte" r1, [r",2, 24,", r",3, 32,", asr #3]!") \
646 TEST_PR( "ldr"byte" r12, [r",11,24,", r",10, 4,", ror #31]!") \
647 TEST( "ldr"byte" r0, [pc, #0]") \
648 TEST_R( "ldr"byte" r12, [pc, r",14,0,"]")
649
650 LOAD_STORE("")
651 TEST_P( "str pc, [r",0,0,", #15*4]")
652 TEST_R( "str pc, [sp, r",2,15*4,"]")
653 TEST_BF( "ldr pc, [sp, #15*4]")
654 TEST_BF_R("ldr pc, [sp, r",2,15*4,"]")
655
656 TEST_P( "str sp, [r",0,0,", #13*4]")
657 TEST_R( "str sp, [sp, r",2,13*4,"]")
658 TEST_BF( "ldr sp, [sp, #13*4]")
659 TEST_BF_R("ldr sp, [sp, r",2,13*4,"]")
660
661#ifdef CONFIG_THUMB2_KERNEL
662 TEST_ARM_TO_THUMB_INTERWORK_P("ldr pc, [r",0,0,", #15*4]")
663#endif
664 TEST_UNSUPPORTED(".word 0xe5af6008 @ str r6, [pc, #8]!")
665 TEST_UNSUPPORTED(".word 0xe7af6008 @ str r6, [pc, r8]!")
666 TEST_UNSUPPORTED(".word 0xe5bf6008 @ ldr r6, [pc, #8]!")
667 TEST_UNSUPPORTED(".word 0xe7bf6008 @ ldr r6, [pc, r8]!")
668 TEST_UNSUPPORTED(".word 0xe788600f @ str r6, [r8, pc]")
669 TEST_UNSUPPORTED(".word 0xe798600f @ ldr r6, [r8, pc]")
670
671 LOAD_STORE("b")
672 TEST_UNSUPPORTED(".word 0xe5f7f008 @ ldrb pc, [r7, #8]!")
673 TEST_UNSUPPORTED(".word 0xe7f7f008 @ ldrb pc, [r7, r8]!")
674 TEST_UNSUPPORTED(".word 0xe5ef6008 @ strb r6, [pc, #8]!")
675 TEST_UNSUPPORTED(".word 0xe7ef6008 @ strb r6, [pc, r3]!")
676 TEST_UNSUPPORTED(".word 0xe5ff6008 @ ldrb r6, [pc, #8]!")
677 TEST_UNSUPPORTED(".word 0xe7ff6008 @ ldrb r6, [pc, r3]!")
678
679 TEST_UNSUPPORTED("ldrt r0, [r1], #4")
680 TEST_UNSUPPORTED("ldrt r1, [r2], r3")
681 TEST_UNSUPPORTED("strt r2, [r3], #4")
682 TEST_UNSUPPORTED("strt r3, [r4], r5")
683 TEST_UNSUPPORTED("ldrbt r4, [r5], #4")
684 TEST_UNSUPPORTED("ldrbt r5, [r6], r7")
685 TEST_UNSUPPORTED("strbt r6, [r7], #4")
686 TEST_UNSUPPORTED("strbt r7, [r8], r9")
687
688#if __LINUX_ARM_ARCH__ >= 7
689 TEST_GROUP("Parallel addition and subtraction, signed")
690
691 TEST_UNSUPPORTED(".word 0xe6000010") /* Unallocated space */
692 TEST_UNSUPPORTED(".word 0xe60fffff") /* Unallocated space */
693
694 TEST_RR( "sadd16 r0, r",0, HH1,", r",1, HH2,"")
695 TEST_RR( "sadd16 r14, r",12,HH2,", r",10,HH1,"")
696 TEST_UNSUPPORTED(".word 0xe61cff1a @ sadd16 pc, r12, r10")
697 TEST_RR( "sasx r0, r",0, HH1,", r",1, HH2,"")
698 TEST_RR( "sasx r14, r",12,HH2,", r",10,HH1,"")
699 TEST_UNSUPPORTED(".word 0xe61cff3a @ sasx pc, r12, r10")
700 TEST_RR( "ssax r0, r",0, HH1,", r",1, HH2,"")
701 TEST_RR( "ssax r14, r",12,HH2,", r",10,HH1,"")
702 TEST_UNSUPPORTED(".word 0xe61cff5a @ ssax pc, r12, r10")
703 TEST_RR( "ssub16 r0, r",0, HH1,", r",1, HH2,"")
704 TEST_RR( "ssub16 r14, r",12,HH2,", r",10,HH1,"")
705 TEST_UNSUPPORTED(".word 0xe61cff7a @ ssub16 pc, r12, r10")
706 TEST_RR( "sadd8 r0, r",0, HH1,", r",1, HH2,"")
707 TEST_RR( "sadd8 r14, r",12,HH2,", r",10,HH1,"")
708 TEST_UNSUPPORTED(".word 0xe61cff9a @ sadd8 pc, r12, r10")
709 TEST_UNSUPPORTED(".word 0xe61000b0") /* Unallocated space */
710 TEST_UNSUPPORTED(".word 0xe61fffbf") /* Unallocated space */
711 TEST_UNSUPPORTED(".word 0xe61000d0") /* Unallocated space */
712 TEST_UNSUPPORTED(".word 0xe61fffdf") /* Unallocated space */
713 TEST_RR( "ssub8 r0, r",0, HH1,", r",1, HH2,"")
714 TEST_RR( "ssub8 r14, r",12,HH2,", r",10,HH1,"")
715 TEST_UNSUPPORTED(".word 0xe61cfffa @ ssub8 pc, r12, r10")
716
717 TEST_RR( "qadd16 r0, r",0, HH1,", r",1, HH2,"")
718 TEST_RR( "qadd16 r14, r",12,HH2,", r",10,HH1,"")
719 TEST_UNSUPPORTED(".word 0xe62cff1a @ qadd16 pc, r12, r10")
720 TEST_RR( "qasx r0, r",0, HH1,", r",1, HH2,"")
721 TEST_RR( "qasx r14, r",12,HH2,", r",10,HH1,"")
722 TEST_UNSUPPORTED(".word 0xe62cff3a @ qasx pc, r12, r10")
723 TEST_RR( "qsax r0, r",0, HH1,", r",1, HH2,"")
724 TEST_RR( "qsax r14, r",12,HH2,", r",10,HH1,"")
725 TEST_UNSUPPORTED(".word 0xe62cff5a @ qsax pc, r12, r10")
726 TEST_RR( "qsub16 r0, r",0, HH1,", r",1, HH2,"")
727 TEST_RR( "qsub16 r14, r",12,HH2,", r",10,HH1,"")
728 TEST_UNSUPPORTED(".word 0xe62cff7a @ qsub16 pc, r12, r10")
729 TEST_RR( "qadd8 r0, r",0, HH1,", r",1, HH2,"")
730 TEST_RR( "qadd8 r14, r",12,HH2,", r",10,HH1,"")
731 TEST_UNSUPPORTED(".word 0xe62cff9a @ qadd8 pc, r12, r10")
732 TEST_UNSUPPORTED(".word 0xe62000b0") /* Unallocated space */
733 TEST_UNSUPPORTED(".word 0xe62fffbf") /* Unallocated space */
734 TEST_UNSUPPORTED(".word 0xe62000d0") /* Unallocated space */
735 TEST_UNSUPPORTED(".word 0xe62fffdf") /* Unallocated space */
736 TEST_RR( "qsub8 r0, r",0, HH1,", r",1, HH2,"")
737 TEST_RR( "qsub8 r14, r",12,HH2,", r",10,HH1,"")
738 TEST_UNSUPPORTED(".word 0xe62cfffa @ qsub8 pc, r12, r10")
739
740 TEST_RR( "shadd16 r0, r",0, HH1,", r",1, HH2,"")
741 TEST_RR( "shadd16 r14, r",12,HH2,", r",10,HH1,"")
742 TEST_UNSUPPORTED(".word 0xe63cff1a @ shadd16 pc, r12, r10")
743 TEST_RR( "shasx r0, r",0, HH1,", r",1, HH2,"")
744 TEST_RR( "shasx r14, r",12,HH2,", r",10,HH1,"")
745 TEST_UNSUPPORTED(".word 0xe63cff3a @ shasx pc, r12, r10")
746 TEST_RR( "shsax r0, r",0, HH1,", r",1, HH2,"")
747 TEST_RR( "shsax r14, r",12,HH2,", r",10,HH1,"")
748 TEST_UNSUPPORTED(".word 0xe63cff5a @ shsax pc, r12, r10")
749 TEST_RR( "shsub16 r0, r",0, HH1,", r",1, HH2,"")
750 TEST_RR( "shsub16 r14, r",12,HH2,", r",10,HH1,"")
751 TEST_UNSUPPORTED(".word 0xe63cff7a @ shsub16 pc, r12, r10")
752 TEST_RR( "shadd8 r0, r",0, HH1,", r",1, HH2,"")
753 TEST_RR( "shadd8 r14, r",12,HH2,", r",10,HH1,"")
754 TEST_UNSUPPORTED(".word 0xe63cff9a @ shadd8 pc, r12, r10")
755 TEST_UNSUPPORTED(".word 0xe63000b0") /* Unallocated space */
756 TEST_UNSUPPORTED(".word 0xe63fffbf") /* Unallocated space */
757 TEST_UNSUPPORTED(".word 0xe63000d0") /* Unallocated space */
758 TEST_UNSUPPORTED(".word 0xe63fffdf") /* Unallocated space */
759 TEST_RR( "shsub8 r0, r",0, HH1,", r",1, HH2,"")
760 TEST_RR( "shsub8 r14, r",12,HH2,", r",10,HH1,"")
761 TEST_UNSUPPORTED(".word 0xe63cfffa @ shsub8 pc, r12, r10")
762
763 TEST_GROUP("Parallel addition and subtraction, unsigned")
764
765 TEST_UNSUPPORTED(".word 0xe6400010") /* Unallocated space */
766 TEST_UNSUPPORTED(".word 0xe64fffff") /* Unallocated space */
767
768 TEST_RR( "uadd16 r0, r",0, HH1,", r",1, HH2,"")
769 TEST_RR( "uadd16 r14, r",12,HH2,", r",10,HH1,"")
770 TEST_UNSUPPORTED(".word 0xe65cff1a @ uadd16 pc, r12, r10")
771 TEST_RR( "uasx r0, r",0, HH1,", r",1, HH2,"")
772 TEST_RR( "uasx r14, r",12,HH2,", r",10,HH1,"")
773 TEST_UNSUPPORTED(".word 0xe65cff3a @ uasx pc, r12, r10")
774 TEST_RR( "usax r0, r",0, HH1,", r",1, HH2,"")
775 TEST_RR( "usax r14, r",12,HH2,", r",10,HH1,"")
776 TEST_UNSUPPORTED(".word 0xe65cff5a @ usax pc, r12, r10")
777 TEST_RR( "usub16 r0, r",0, HH1,", r",1, HH2,"")
778 TEST_RR( "usub16 r14, r",12,HH2,", r",10,HH1,"")
779 TEST_UNSUPPORTED(".word 0xe65cff7a @ usub16 pc, r12, r10")
780 TEST_RR( "uadd8 r0, r",0, HH1,", r",1, HH2,"")
781 TEST_RR( "uadd8 r14, r",12,HH2,", r",10,HH1,"")
782 TEST_UNSUPPORTED(".word 0xe65cff9a @ uadd8 pc, r12, r10")
783 TEST_UNSUPPORTED(".word 0xe65000b0") /* Unallocated space */
784 TEST_UNSUPPORTED(".word 0xe65fffbf") /* Unallocated space */
785 TEST_UNSUPPORTED(".word 0xe65000d0") /* Unallocated space */
786 TEST_UNSUPPORTED(".word 0xe65fffdf") /* Unallocated space */
787 TEST_RR( "usub8 r0, r",0, HH1,", r",1, HH2,"")
788 TEST_RR( "usub8 r14, r",12,HH2,", r",10,HH1,"")
789 TEST_UNSUPPORTED(".word 0xe65cfffa @ usub8 pc, r12, r10")
790
791 TEST_RR( "uqadd16 r0, r",0, HH1,", r",1, HH2,"")
792 TEST_RR( "uqadd16 r14, r",12,HH2,", r",10,HH1,"")
793 TEST_UNSUPPORTED(".word 0xe66cff1a @ uqadd16 pc, r12, r10")
794 TEST_RR( "uqasx r0, r",0, HH1,", r",1, HH2,"")
795 TEST_RR( "uqasx r14, r",12,HH2,", r",10,HH1,"")
796 TEST_UNSUPPORTED(".word 0xe66cff3a @ uqasx pc, r12, r10")
797 TEST_RR( "uqsax r0, r",0, HH1,", r",1, HH2,"")
798 TEST_RR( "uqsax r14, r",12,HH2,", r",10,HH1,"")
799 TEST_UNSUPPORTED(".word 0xe66cff5a @ uqsax pc, r12, r10")
800 TEST_RR( "uqsub16 r0, r",0, HH1,", r",1, HH2,"")
801 TEST_RR( "uqsub16 r14, r",12,HH2,", r",10,HH1,"")
802 TEST_UNSUPPORTED(".word 0xe66cff7a @ uqsub16 pc, r12, r10")
803 TEST_RR( "uqadd8 r0, r",0, HH1,", r",1, HH2,"")
804 TEST_RR( "uqadd8 r14, r",12,HH2,", r",10,HH1,"")
805 TEST_UNSUPPORTED(".word 0xe66cff9a @ uqadd8 pc, r12, r10")
806 TEST_UNSUPPORTED(".word 0xe66000b0") /* Unallocated space */
807 TEST_UNSUPPORTED(".word 0xe66fffbf") /* Unallocated space */
808 TEST_UNSUPPORTED(".word 0xe66000d0") /* Unallocated space */
809 TEST_UNSUPPORTED(".word 0xe66fffdf") /* Unallocated space */
810 TEST_RR( "uqsub8 r0, r",0, HH1,", r",1, HH2,"")
811 TEST_RR( "uqsub8 r14, r",12,HH2,", r",10,HH1,"")
812 TEST_UNSUPPORTED(".word 0xe66cfffa @ uqsub8 pc, r12, r10")
813
814 TEST_RR( "uhadd16 r0, r",0, HH1,", r",1, HH2,"")
815 TEST_RR( "uhadd16 r14, r",12,HH2,", r",10,HH1,"")
816 TEST_UNSUPPORTED(".word 0xe67cff1a @ uhadd16 pc, r12, r10")
817 TEST_RR( "uhasx r0, r",0, HH1,", r",1, HH2,"")
818 TEST_RR( "uhasx r14, r",12,HH2,", r",10,HH1,"")
819 TEST_UNSUPPORTED(".word 0xe67cff3a @ uhasx pc, r12, r10")
820 TEST_RR( "uhsax r0, r",0, HH1,", r",1, HH2,"")
821 TEST_RR( "uhsax r14, r",12,HH2,", r",10,HH1,"")
822 TEST_UNSUPPORTED(".word 0xe67cff5a @ uhsax pc, r12, r10")
823 TEST_RR( "uhsub16 r0, r",0, HH1,", r",1, HH2,"")
824 TEST_RR( "uhsub16 r14, r",12,HH2,", r",10,HH1,"")
825 TEST_UNSUPPORTED(".word 0xe67cff7a @ uhsub16 pc, r12, r10")
826 TEST_RR( "uhadd8 r0, r",0, HH1,", r",1, HH2,"")
827 TEST_RR( "uhadd8 r14, r",12,HH2,", r",10,HH1,"")
828 TEST_UNSUPPORTED(".word 0xe67cff9a @ uhadd8 pc, r12, r10")
829 TEST_UNSUPPORTED(".word 0xe67000b0") /* Unallocated space */
830 TEST_UNSUPPORTED(".word 0xe67fffbf") /* Unallocated space */
831 TEST_UNSUPPORTED(".word 0xe67000d0") /* Unallocated space */
832 TEST_UNSUPPORTED(".word 0xe67fffdf") /* Unallocated space */
833 TEST_RR( "uhsub8 r0, r",0, HH1,", r",1, HH2,"")
834 TEST_RR( "uhsub8 r14, r",12,HH2,", r",10,HH1,"")
835 TEST_UNSUPPORTED(".word 0xe67cfffa @ uhsub8 pc, r12, r10")
836 TEST_UNSUPPORTED(".word 0xe67feffa @ uhsub8 r14, pc, r10")
837 TEST_UNSUPPORTED(".word 0xe67cefff @ uhsub8 r14, r12, pc")
838#endif /* __LINUX_ARM_ARCH__ >= 7 */
839
840#if __LINUX_ARM_ARCH__ >= 6
841 TEST_GROUP("Packing, unpacking, saturation, and reversal")
842
843 TEST_RR( "pkhbt r0, r",0, HH1,", r",1, HH2,"")
844 TEST_RR( "pkhbt r14,r",12, HH1,", r",10,HH2,", lsl #2")
845 TEST_UNSUPPORTED(".word 0xe68cf11a @ pkhbt pc, r12, r10, lsl #2")
846 TEST_RR( "pkhtb r0, r",0, HH1,", r",1, HH2,"")
847 TEST_RR( "pkhtb r14,r",12, HH1,", r",10,HH2,", asr #2")
848 TEST_UNSUPPORTED(".word 0xe68cf15a @ pkhtb pc, r12, r10, asr #2")
849 TEST_UNSUPPORTED(".word 0xe68fe15a @ pkhtb r14, pc, r10, asr #2")
850 TEST_UNSUPPORTED(".word 0xe68ce15f @ pkhtb r14, r12, pc, asr #2")
851 TEST_UNSUPPORTED(".word 0xe6900010") /* Unallocated space */
852 TEST_UNSUPPORTED(".word 0xe69fffdf") /* Unallocated space */
853
854 TEST_R( "ssat r0, #24, r",0, VAL1,"")
855 TEST_R( "ssat r14, #24, r",12, VAL2,"")
856 TEST_R( "ssat r0, #24, r",0, VAL1,", lsl #8")
857 TEST_R( "ssat r14, #24, r",12, VAL2,", asr #8")
858 TEST_UNSUPPORTED(".word 0xe6b7f01c @ ssat pc, #24, r12")
859
860 TEST_R( "usat r0, #24, r",0, VAL1,"")
861 TEST_R( "usat r14, #24, r",12, VAL2,"")
862 TEST_R( "usat r0, #24, r",0, VAL1,", lsl #8")
863 TEST_R( "usat r14, #24, r",12, VAL2,", asr #8")
864 TEST_UNSUPPORTED(".word 0xe6f7f01c @ usat pc, #24, r12")
865
866 TEST_RR( "sxtab16 r0, r",0, HH1,", r",1, HH2,"")
867 TEST_RR( "sxtab16 r14,r",12, HH2,", r",10,HH1,", ror #8")
868 TEST_R( "sxtb16 r8, r",7, HH1,"")
869 TEST_UNSUPPORTED(".word 0xe68cf47a @ sxtab16 pc,r12, r10, ror #8")
870
871 TEST_RR( "sel r0, r",0, VAL1,", r",1, VAL2,"")
872 TEST_RR( "sel r14, r",12,VAL1,", r",10, VAL2,"")
873 TEST_UNSUPPORTED(".word 0xe68cffba @ sel pc, r12, r10")
874 TEST_UNSUPPORTED(".word 0xe68fefba @ sel r14, pc, r10")
875 TEST_UNSUPPORTED(".word 0xe68cefbf @ sel r14, r12, pc")
876
877 TEST_R( "ssat16 r0, #12, r",0, HH1,"")
878 TEST_R( "ssat16 r14, #12, r",12, HH2,"")
879 TEST_UNSUPPORTED(".word 0xe6abff3c @ ssat16 pc, #12, r12")
880
881 TEST_RR( "sxtab r0, r",0, HH1,", r",1, HH2,"")
882 TEST_RR( "sxtab r14,r",12, HH2,", r",10,HH1,", ror #8")
883 TEST_R( "sxtb r8, r",7, HH1,"")
884 TEST_UNSUPPORTED(".word 0xe6acf47a @ sxtab pc,r12, r10, ror #8")
885
886 TEST_R( "rev r0, r",0, VAL1,"")
887 TEST_R( "rev r14, r",12, VAL2,"")
888 TEST_UNSUPPORTED(".word 0xe6bfff3c @ rev pc, r12")
889
890 TEST_RR( "sxtah r0, r",0, HH1,", r",1, HH2,"")
891 TEST_RR( "sxtah r14,r",12, HH2,", r",10,HH1,", ror #8")
892 TEST_R( "sxth r8, r",7, HH1,"")
893 TEST_UNSUPPORTED(".word 0xe6bcf47a @ sxtah pc,r12, r10, ror #8")
894
895 TEST_R( "rev16 r0, r",0, VAL1,"")
896 TEST_R( "rev16 r14, r",12, VAL2,"")
897 TEST_UNSUPPORTED(".word 0xe6bfffbc @ rev16 pc, r12")
898
899 TEST_RR( "uxtab16 r0, r",0, HH1,", r",1, HH2,"")
900 TEST_RR( "uxtab16 r14,r",12, HH2,", r",10,HH1,", ror #8")
901 TEST_R( "uxtb16 r8, r",7, HH1,"")
902 TEST_UNSUPPORTED(".word 0xe6ccf47a @ uxtab16 pc,r12, r10, ror #8")
903
904 TEST_R( "usat16 r0, #12, r",0, HH1,"")
905 TEST_R( "usat16 r14, #12, r",12, HH2,"")
906 TEST_UNSUPPORTED(".word 0xe6ecff3c @ usat16 pc, #12, r12")
907 TEST_UNSUPPORTED(".word 0xe6ecef3f @ usat16 r14, #12, pc")
908
909 TEST_RR( "uxtab r0, r",0, HH1,", r",1, HH2,"")
910 TEST_RR( "uxtab r14,r",12, HH2,", r",10,HH1,", ror #8")
911 TEST_R( "uxtb r8, r",7, HH1,"")
912 TEST_UNSUPPORTED(".word 0xe6ecf47a @ uxtab pc,r12, r10, ror #8")
913
914#if __LINUX_ARM_ARCH__ >= 7
915 TEST_R( "rbit r0, r",0, VAL1,"")
916 TEST_R( "rbit r14, r",12, VAL2,"")
917 TEST_UNSUPPORTED(".word 0xe6ffff3c @ rbit pc, r12")
918#endif
919
920 TEST_RR( "uxtah r0, r",0, HH1,", r",1, HH2,"")
921 TEST_RR( "uxtah r14,r",12, HH2,", r",10,HH1,", ror #8")
922 TEST_R( "uxth r8, r",7, HH1,"")
923 TEST_UNSUPPORTED(".word 0xe6fff077 @ uxth pc, r7")
924 TEST_UNSUPPORTED(".word 0xe6ff807f @ uxth r8, pc")
925 TEST_UNSUPPORTED(".word 0xe6fcf47a @ uxtah pc, r12, r10, ror #8")
926 TEST_UNSUPPORTED(".word 0xe6fce47f @ uxtah r14, r12, pc, ror #8")
927
928 TEST_R( "revsh r0, r",0, VAL1,"")
929 TEST_R( "revsh r14, r",12, VAL2,"")
930 TEST_UNSUPPORTED(".word 0xe6ffff3c @ revsh pc, r12")
931 TEST_UNSUPPORTED(".word 0xe6ffef3f @ revsh r14, pc")
932
933 TEST_UNSUPPORTED(".word 0xe6900070") /* Unallocated space */
934 TEST_UNSUPPORTED(".word 0xe69fff7f") /* Unallocated space */
935
936 TEST_UNSUPPORTED(".word 0xe6d00070") /* Unallocated space */
937 TEST_UNSUPPORTED(".word 0xe6dfff7f") /* Unallocated space */
938#endif /* __LINUX_ARM_ARCH__ >= 6 */
939
940#if __LINUX_ARM_ARCH__ >= 6
941 TEST_GROUP("Signed multiplies")
942
943 TEST_RRR( "smlad r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"")
944 TEST_RRR( "smlad r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
945 TEST_UNSUPPORTED(".word 0xe70f8a1c @ smlad pc, r12, r10, r8")
946 TEST_RRR( "smladx r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"")
947 TEST_RRR( "smladx r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
948 TEST_UNSUPPORTED(".word 0xe70f8a3c @ smladx pc, r12, r10, r8")
949
950 TEST_RR( "smuad r0, r",0, HH1,", r",1, HH2,"")
951 TEST_RR( "smuad r14, r",12,HH2,", r",10,HH1,"")
952 TEST_UNSUPPORTED(".word 0xe70ffa1c @ smuad pc, r12, r10")
953 TEST_RR( "smuadx r0, r",0, HH1,", r",1, HH2,"")
954 TEST_RR( "smuadx r14, r",12,HH2,", r",10,HH1,"")
955 TEST_UNSUPPORTED(".word 0xe70ffa3c @ smuadx pc, r12, r10")
956
957 TEST_RRR( "smlsd r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"")
958 TEST_RRR( "smlsd r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
959 TEST_UNSUPPORTED(".word 0xe70f8a5c @ smlsd pc, r12, r10, r8")
960 TEST_RRR( "smlsdx r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"")
961 TEST_RRR( "smlsdx r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
962 TEST_UNSUPPORTED(".word 0xe70f8a7c @ smlsdx pc, r12, r10, r8")
963
964 TEST_RR( "smusd r0, r",0, HH1,", r",1, HH2,"")
965 TEST_RR( "smusd r14, r",12,HH2,", r",10,HH1,"")
966 TEST_UNSUPPORTED(".word 0xe70ffa5c @ smusd pc, r12, r10")
967 TEST_RR( "smusdx r0, r",0, HH1,", r",1, HH2,"")
968 TEST_RR( "smusdx r14, r",12,HH2,", r",10,HH1,"")
969 TEST_UNSUPPORTED(".word 0xe70ffa7c @ smusdx pc, r12, r10")
970
971 TEST_RRRR( "smlald r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
972 TEST_RRRR( "smlald r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
973 TEST_UNSUPPORTED(".word 0xe74af819 @ smlald pc, r10, r9, r8")
974 TEST_UNSUPPORTED(".word 0xe74fb819 @ smlald r11, pc, r9, r8")
975 TEST_UNSUPPORTED(".word 0xe74ab81f @ smlald r11, r10, pc, r8")
976 TEST_UNSUPPORTED(".word 0xe74abf19 @ smlald r11, r10, r9, pc")
977
978 TEST_RRRR( "smlaldx r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
979 TEST_RRRR( "smlaldx r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
980 TEST_UNSUPPORTED(".word 0xe74af839 @ smlaldx pc, r10, r9, r8")
981 TEST_UNSUPPORTED(".word 0xe74fb839 @ smlaldx r11, pc, r9, r8")
982
983 TEST_RRR( "smmla r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"")
984 TEST_RRR( "smmla r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
985 TEST_UNSUPPORTED(".word 0xe75f8a1c @ smmla pc, r12, r10, r8")
986 TEST_RRR( "smmlar r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"")
987 TEST_RRR( "smmlar r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
988 TEST_UNSUPPORTED(".word 0xe75f8a3c @ smmlar pc, r12, r10, r8")
989
990 TEST_RR( "smmul r0, r",0, VAL1,", r",1, VAL2,"")
991 TEST_RR( "smmul r14, r",12,VAL2,", r",10,VAL1,"")
992 TEST_UNSUPPORTED(".word 0xe75ffa1c @ smmul pc, r12, r10")
993 TEST_RR( "smmulr r0, r",0, VAL1,", r",1, VAL2,"")
994 TEST_RR( "smmulr r14, r",12,VAL2,", r",10,VAL1,"")
995 TEST_UNSUPPORTED(".word 0xe75ffa3c @ smmulr pc, r12, r10")
996
997 TEST_RRR( "smmls r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"")
998 TEST_RRR( "smmls r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
999 TEST_UNSUPPORTED(".word 0xe75f8adc @ smmls pc, r12, r10, r8")
1000 TEST_RRR( "smmlsr r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"")
1001 TEST_RRR( "smmlsr r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
1002 TEST_UNSUPPORTED(".word 0xe75f8afc @ smmlsr pc, r12, r10, r8")
1003 TEST_UNSUPPORTED(".word 0xe75e8aff @ smmlsr r14, pc, r10, r8")
1004 TEST_UNSUPPORTED(".word 0xe75e8ffc @ smmlsr r14, r12, pc, r8")
1005 TEST_UNSUPPORTED(".word 0xe75efafc @ smmlsr r14, r12, r10, pc")
1006
1007 TEST_RR( "usad8 r0, r",0, VAL1,", r",1, VAL2,"")
1008 TEST_RR( "usad8 r14, r",12,VAL2,", r",10,VAL1,"")
1009 TEST_UNSUPPORTED(".word 0xe75ffa1c @ usad8 pc, r12, r10")
1010 TEST_UNSUPPORTED(".word 0xe75efa1f @ usad8 r14, pc, r10")
1011 TEST_UNSUPPORTED(".word 0xe75eff1c @ usad8 r14, r12, pc")
1012
1013 TEST_RRR( "usada8 r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL3,"")
1014 TEST_RRR( "usada8 r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL3,"")
1015 TEST_UNSUPPORTED(".word 0xe78f8a1c @ usada8 pc, r12, r10, r8")
1016 TEST_UNSUPPORTED(".word 0xe78e8a1f @ usada8 r14, pc, r10, r8")
1017 TEST_UNSUPPORTED(".word 0xe78e8f1c @ usada8 r14, r12, pc, r8")
1018#endif /* __LINUX_ARM_ARCH__ >= 6 */
1019
1020#if __LINUX_ARM_ARCH__ >= 7
1021 TEST_GROUP("Bit Field")
1022
1023 TEST_R( "sbfx r0, r",0 , VAL1,", #0, #31")
1024 TEST_R( "sbfxeq r14, r",12, VAL2,", #8, #16")
1025 TEST_R( "sbfx r4, r",10, VAL1,", #16, #15")
1026 TEST_UNSUPPORTED(".word 0xe7aff45c @ sbfx pc, r12, #8, #16")
1027
1028 TEST_R( "ubfx r0, r",0 , VAL1,", #0, #31")
1029 TEST_R( "ubfxcs r14, r",12, VAL2,", #8, #16")
1030 TEST_R( "ubfx r4, r",10, VAL1,", #16, #15")
1031 TEST_UNSUPPORTED(".word 0xe7eff45c @ ubfx pc, r12, #8, #16")
1032 TEST_UNSUPPORTED(".word 0xe7efc45f @ ubfx r12, pc, #8, #16")
1033
1034 TEST_R( "bfc r",0, VAL1,", #4, #20")
1035 TEST_R( "bfcvs r",14,VAL2,", #4, #20")
1036 TEST_R( "bfc r",7, VAL1,", #0, #31")
1037 TEST_R( "bfc r",8, VAL2,", #0, #31")
1038 TEST_UNSUPPORTED(".word 0xe7def01f @ bfc pc, #0, #31");
1039
1040 TEST_RR( "bfi r",0, VAL1,", r",0 , VAL2,", #0, #31")
1041 TEST_RR( "bfipl r",12,VAL1,", r",14 , VAL2,", #4, #20")
1042 TEST_UNSUPPORTED(".word 0xe7d7f21e @ bfi pc, r14, #4, #20")
1043
1044 TEST_UNSUPPORTED(".word 0x07f000f0") /* Permanently UNDEFINED */
1045 TEST_UNSUPPORTED(".word 0x07ffffff") /* Permanently UNDEFINED */
1046#endif /* __LINUX_ARM_ARCH__ >= 6 */
1047
1048 TEST_GROUP("Branch, branch with link, and block data transfer")
1049
1050 TEST_P( "stmda r",0, 16*4,", {r0}")
1051 TEST_P( "stmeqda r",4, 16*4,", {r0-r15}")
1052 TEST_P( "stmneda r",8, 16*4,"!, {r8-r15}")
1053 TEST_P( "stmda r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
1054 TEST_P( "stmda r",13,0, "!, {pc}")
1055
1056 TEST_P( "ldmda r",0, 16*4,", {r0}")
1057 TEST_BF_P("ldmcsda r",4, 15*4,", {r0-r15}")
1058 TEST_BF_P("ldmccda r",7, 15*4,"!, {r8-r15}")
1059 TEST_P( "ldmda r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
1060 TEST_BF_P("ldmda r",14,15*4,"!, {pc}")
1061
1062 TEST_P( "stmia r",0, 16*4,", {r0}")
1063 TEST_P( "stmmiia r",4, 16*4,", {r0-r15}")
1064 TEST_P( "stmplia r",8, 16*4,"!, {r8-r15}")
1065 TEST_P( "stmia r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
1066 TEST_P( "stmia r",14,0, "!, {pc}")
1067
1068 TEST_P( "ldmia r",0, 16*4,", {r0}")
1069 TEST_BF_P("ldmvsia r",4, 0, ", {r0-r15}")
1070 TEST_BF_P("ldmvcia r",7, 8*4, "!, {r8-r15}")
1071 TEST_P( "ldmia r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
1072 TEST_BF_P("ldmia r",14,15*4,"!, {pc}")
1073
1074 TEST_P( "stmdb r",0, 16*4,", {r0}")
1075 TEST_P( "stmhidb r",4, 16*4,", {r0-r15}")
1076 TEST_P( "stmlsdb r",8, 16*4,"!, {r8-r15}")
1077 TEST_P( "stmdb r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
1078 TEST_P( "stmdb r",13,4, "!, {pc}")
1079
1080 TEST_P( "ldmdb r",0, 16*4,", {r0}")
1081 TEST_BF_P("ldmgedb r",4, 16*4,", {r0-r15}")
1082 TEST_BF_P("ldmltdb r",7, 16*4,"!, {r8-r15}")
1083 TEST_P( "ldmdb r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
1084 TEST_BF_P("ldmdb r",14,16*4,"!, {pc}")
1085
1086 TEST_P( "stmib r",0, 16*4,", {r0}")
1087 TEST_P( "stmgtib r",4, 16*4,", {r0-r15}")
1088 TEST_P( "stmleib r",8, 16*4,"!, {r8-r15}")
1089 TEST_P( "stmib r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
1090 TEST_P( "stmib r",13,-4, "!, {pc}")
1091
1092 TEST_P( "ldmib r",0, 16*4,", {r0}")
1093 TEST_BF_P("ldmeqib r",4, -4,", {r0-r15}")
1094 TEST_BF_P("ldmneib r",7, 7*4,"!, {r8-r15}")
1095 TEST_P( "ldmib r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
1096 TEST_BF_P("ldmib r",14,14*4,"!, {pc}")
1097
1098 TEST_P( "stmdb r",13,16*4,"!, {r3-r12,lr}")
1099 TEST_P( "stmeqdb r",13,16*4,"!, {r3-r12}")
1100 TEST_P( "stmnedb r",2, 16*4,", {r3-r12,lr}")
1101 TEST_P( "stmdb r",13,16*4,"!, {r2-r12,lr}")
1102 TEST_P( "stmdb r",0, 16*4,", {r0-r12}")
1103 TEST_P( "stmdb r",0, 16*4,", {r0-r12,lr}")
1104
1105 TEST_BF_P("ldmia r",13,5*4, "!, {r3-r12,pc}")
1106 TEST_P( "ldmccia r",13,5*4, "!, {r3-r12}")
1107 TEST_BF_P("ldmcsia r",2, 5*4, "!, {r3-r12,pc}")
1108 TEST_BF_P("ldmia r",13,4*4, "!, {r2-r12,pc}")
1109 TEST_P( "ldmia r",0, 16*4,", {r0-r12}")
1110 TEST_P( "ldmia r",0, 16*4,", {r0-r12,lr}")
1111
1112#ifdef CONFIG_THUMB2_KERNEL
1113 TEST_ARM_TO_THUMB_INTERWORK_P("ldmplia r",0,15*4,", {pc}")
1114 TEST_ARM_TO_THUMB_INTERWORK_P("ldmmiia r",13,0,", {r0-r15}")
1115#endif
1116 TEST_BF("b 2f")
1117 TEST_BF("bl 2f")
1118 TEST_BB("b 2b")
1119 TEST_BB("bl 2b")
1120
1121 TEST_BF("beq 2f")
1122 TEST_BF("bleq 2f")
1123 TEST_BB("bne 2b")
1124 TEST_BB("blne 2b")
1125
1126 TEST_BF("bgt 2f")
1127 TEST_BF("blgt 2f")
1128 TEST_BB("blt 2b")
1129 TEST_BB("bllt 2b")
1130
1131 TEST_GROUP("Supervisor Call, and coprocessor instructions")
1132
1133 /*
1134 * We can't really test these by executing them, so all
1135 * we can do is check that probes are, or are not allowed.
1136 * At the moment none are allowed...
1137 */
1138#define TEST_COPROCESSOR(code) TEST_UNSUPPORTED(code)
1139
1140#define COPROCESSOR_INSTRUCTIONS_ST_LD(two,cc) \
1141 TEST_COPROCESSOR("stc"two" 0, cr0, [r13, #4]") \
1142 TEST_COPROCESSOR("stc"two" 0, cr0, [r13, #-4]") \
1143 TEST_COPROCESSOR("stc"two" 0, cr0, [r13, #4]!") \
1144 TEST_COPROCESSOR("stc"two" 0, cr0, [r13, #-4]!") \
1145 TEST_COPROCESSOR("stc"two" 0, cr0, [r13], #4") \
1146 TEST_COPROCESSOR("stc"two" 0, cr0, [r13], #-4") \
1147 TEST_COPROCESSOR("stc"two" 0, cr0, [r13], {1}") \
1148 TEST_COPROCESSOR("stc"two"l 0, cr0, [r13, #4]") \
1149 TEST_COPROCESSOR("stc"two"l 0, cr0, [r13, #-4]") \
1150 TEST_COPROCESSOR("stc"two"l 0, cr0, [r13, #4]!") \
1151 TEST_COPROCESSOR("stc"two"l 0, cr0, [r13, #-4]!") \
1152 TEST_COPROCESSOR("stc"two"l 0, cr0, [r13], #4") \
1153 TEST_COPROCESSOR("stc"two"l 0, cr0, [r13], #-4") \
1154 TEST_COPROCESSOR("stc"two"l 0, cr0, [r13], {1}") \
1155 TEST_COPROCESSOR("ldc"two" 0, cr0, [r13, #4]") \
1156 TEST_COPROCESSOR("ldc"two" 0, cr0, [r13, #-4]") \
1157 TEST_COPROCESSOR("ldc"two" 0, cr0, [r13, #4]!") \
1158 TEST_COPROCESSOR("ldc"two" 0, cr0, [r13, #-4]!") \
1159 TEST_COPROCESSOR("ldc"two" 0, cr0, [r13], #4") \
1160 TEST_COPROCESSOR("ldc"two" 0, cr0, [r13], #-4") \
1161 TEST_COPROCESSOR("ldc"two" 0, cr0, [r13], {1}") \
1162 TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13, #4]") \
1163 TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13, #-4]") \
1164 TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13, #4]!") \
1165 TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13, #-4]!") \
1166 TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13], #4") \
1167 TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13], #-4") \
1168 TEST_COPROCESSOR("ldc"two"l 0, cr0, [r13], {1}") \
1169 \
1170 TEST_COPROCESSOR( "stc"two" 0, cr0, [r15, #4]") \
1171 TEST_COPROCESSOR( "stc"two" 0, cr0, [r15, #-4]") \
1172 TEST_UNSUPPORTED(".word 0x"cc"daf0001 @ stc"two" 0, cr0, [r15, #4]!") \
1173 TEST_UNSUPPORTED(".word 0x"cc"d2f0001 @ stc"two" 0, cr0, [r15, #-4]!") \
1174 TEST_UNSUPPORTED(".word 0x"cc"caf0001 @ stc"two" 0, cr0, [r15], #4") \
1175 TEST_UNSUPPORTED(".word 0x"cc"c2f0001 @ stc"two" 0, cr0, [r15], #-4") \
1176 TEST_COPROCESSOR( "stc"two" 0, cr0, [r15], {1}") \
1177 TEST_COPROCESSOR( "stc"two"l 0, cr0, [r15, #4]") \
1178 TEST_COPROCESSOR( "stc"two"l 0, cr0, [r15, #-4]") \
1179 TEST_UNSUPPORTED(".word 0x"cc"def0001 @ stc"two"l 0, cr0, [r15, #4]!") \
1180 TEST_UNSUPPORTED(".word 0x"cc"d6f0001 @ stc"two"l 0, cr0, [r15, #-4]!") \
1181 TEST_UNSUPPORTED(".word 0x"cc"cef0001 @ stc"two"l 0, cr0, [r15], #4") \
1182 TEST_UNSUPPORTED(".word 0x"cc"c6f0001 @ stc"two"l 0, cr0, [r15], #-4") \
1183 TEST_COPROCESSOR( "stc"two"l 0, cr0, [r15], {1}") \
1184 TEST_COPROCESSOR( "ldc"two" 0, cr0, [r15, #4]") \
1185 TEST_COPROCESSOR( "ldc"two" 0, cr0, [r15, #-4]") \
1186 TEST_UNSUPPORTED(".word 0x"cc"dbf0001 @ ldc"two" 0, cr0, [r15, #4]!") \
1187 TEST_UNSUPPORTED(".word 0x"cc"d3f0001 @ ldc"two" 0, cr0, [r15, #-4]!") \
1188 TEST_UNSUPPORTED(".word 0x"cc"cbf0001 @ ldc"two" 0, cr0, [r15], #4") \
1189 TEST_UNSUPPORTED(".word 0x"cc"c3f0001 @ ldc"two" 0, cr0, [r15], #-4") \
1190 TEST_COPROCESSOR( "ldc"two" 0, cr0, [r15], {1}") \
1191 TEST_COPROCESSOR( "ldc"two"l 0, cr0, [r15, #4]") \
1192 TEST_COPROCESSOR( "ldc"two"l 0, cr0, [r15, #-4]") \
1193 TEST_UNSUPPORTED(".word 0x"cc"dff0001 @ ldc"two"l 0, cr0, [r15, #4]!") \
1194 TEST_UNSUPPORTED(".word 0x"cc"d7f0001 @ ldc"two"l 0, cr0, [r15, #-4]!") \
1195 TEST_UNSUPPORTED(".word 0x"cc"cff0001 @ ldc"two"l 0, cr0, [r15], #4") \
1196 TEST_UNSUPPORTED(".word 0x"cc"c7f0001 @ ldc"two"l 0, cr0, [r15], #-4") \
1197 TEST_COPROCESSOR( "ldc"two"l 0, cr0, [r15], {1}")
1198
1199#define COPROCESSOR_INSTRUCTIONS_MC_MR(two,cc) \
1200 \
1201 TEST_COPROCESSOR( "mcrr"two" 0, 15, r0, r14, cr0") \
1202 TEST_COPROCESSOR( "mcrr"two" 15, 0, r14, r0, cr15") \
1203 TEST_UNSUPPORTED(".word 0x"cc"c4f00f0 @ mcrr"two" 0, 15, r0, r15, cr0") \
1204 TEST_UNSUPPORTED(".word 0x"cc"c40ff0f @ mcrr"two" 15, 0, r15, r0, cr15") \
1205 TEST_COPROCESSOR( "mrrc"two" 0, 15, r0, r14, cr0") \
1206 TEST_COPROCESSOR( "mrrc"two" 15, 0, r14, r0, cr15") \
1207 TEST_UNSUPPORTED(".word 0x"cc"c5f00f0 @ mrrc"two" 0, 15, r0, r15, cr0") \
1208 TEST_UNSUPPORTED(".word 0x"cc"c50ff0f @ mrrc"two" 15, 0, r15, r0, cr15") \
1209 TEST_COPROCESSOR( "cdp"two" 15, 15, cr15, cr15, cr15, 7") \
1210 TEST_COPROCESSOR( "cdp"two" 0, 0, cr0, cr0, cr0, 0") \
1211 TEST_COPROCESSOR( "mcr"two" 15, 7, r15, cr15, cr15, 7") \
1212 TEST_COPROCESSOR( "mcr"two" 0, 0, r0, cr0, cr0, 0") \
1213 TEST_COPROCESSOR( "mrc"two" 15, 7, r15, cr15, cr15, 7") \
1214 TEST_COPROCESSOR( "mrc"two" 0, 0, r0, cr0, cr0, 0")
1215
1216 COPROCESSOR_INSTRUCTIONS_ST_LD("","e")
1217 COPROCESSOR_INSTRUCTIONS_MC_MR("","e")
1218 TEST_UNSUPPORTED("svc 0")
1219 TEST_UNSUPPORTED("svc 0xffffff")
1220
1221 TEST_UNSUPPORTED("svc 0")
1222
1223 TEST_GROUP("Unconditional instruction")
1224
1225#if __LINUX_ARM_ARCH__ >= 6
1226 TEST_UNSUPPORTED("srsda sp, 0x13")
1227 TEST_UNSUPPORTED("srsdb sp, 0x13")
1228 TEST_UNSUPPORTED("srsia sp, 0x13")
1229 TEST_UNSUPPORTED("srsib sp, 0x13")
1230 TEST_UNSUPPORTED("srsda sp!, 0x13")
1231 TEST_UNSUPPORTED("srsdb sp!, 0x13")
1232 TEST_UNSUPPORTED("srsia sp!, 0x13")
1233 TEST_UNSUPPORTED("srsib sp!, 0x13")
1234
1235 TEST_UNSUPPORTED("rfeda sp")
1236 TEST_UNSUPPORTED("rfedb sp")
1237 TEST_UNSUPPORTED("rfeia sp")
1238 TEST_UNSUPPORTED("rfeib sp")
1239 TEST_UNSUPPORTED("rfeda sp!")
1240 TEST_UNSUPPORTED("rfedb sp!")
1241 TEST_UNSUPPORTED("rfeia sp!")
1242 TEST_UNSUPPORTED("rfeib sp!")
1243 TEST_UNSUPPORTED(".word 0xf81d0a00 @ rfeda pc")
1244 TEST_UNSUPPORTED(".word 0xf91d0a00 @ rfedb pc")
1245 TEST_UNSUPPORTED(".word 0xf89d0a00 @ rfeia pc")
1246 TEST_UNSUPPORTED(".word 0xf99d0a00 @ rfeib pc")
1247 TEST_UNSUPPORTED(".word 0xf83d0a00 @ rfeda pc!")
1248 TEST_UNSUPPORTED(".word 0xf93d0a00 @ rfedb pc!")
1249 TEST_UNSUPPORTED(".word 0xf8bd0a00 @ rfeia pc!")
1250 TEST_UNSUPPORTED(".word 0xf9bd0a00 @ rfeib pc!")
1251#endif /* __LINUX_ARM_ARCH__ >= 6 */
1252
1253#if __LINUX_ARM_ARCH__ >= 6
1254 TEST_X( "blx __dummy_thumb_subroutine_even",
1255 ".thumb \n\t"
1256 ".space 4 \n\t"
1257 ".type __dummy_thumb_subroutine_even, %%function \n\t"
1258 "__dummy_thumb_subroutine_even: \n\t"
1259 "mov r0, pc \n\t"
1260 "bx lr \n\t"
1261 ".arm \n\t"
1262 )
1263 TEST( "blx __dummy_thumb_subroutine_even")
1264
1265 TEST_X( "blx __dummy_thumb_subroutine_odd",
1266 ".thumb \n\t"
1267 ".space 2 \n\t"
1268 ".type __dummy_thumb_subroutine_odd, %%function \n\t"
1269 "__dummy_thumb_subroutine_odd: \n\t"
1270 "mov r0, pc \n\t"
1271 "bx lr \n\t"
1272 ".arm \n\t"
1273 )
1274 TEST( "blx __dummy_thumb_subroutine_odd")
1275#endif /* __LINUX_ARM_ARCH__ >= 6 */
1276
1277 COPROCESSOR_INSTRUCTIONS_ST_LD("2","f")
1278#if __LINUX_ARM_ARCH__ >= 6
1279 COPROCESSOR_INSTRUCTIONS_MC_MR("2","f")
1280#endif
1281
1282 TEST_GROUP("Miscellaneous instructions, memory hints, and Advanced SIMD instructions")
1283
1284#if __LINUX_ARM_ARCH__ >= 6
1285 TEST_UNSUPPORTED("cps 0x13")
1286 TEST_UNSUPPORTED("cpsie i")
1287 TEST_UNSUPPORTED("cpsid i")
1288 TEST_UNSUPPORTED("cpsie i,0x13")
1289 TEST_UNSUPPORTED("cpsid i,0x13")
1290 TEST_UNSUPPORTED("setend le")
1291 TEST_UNSUPPORTED("setend be")
1292#endif
1293
1294#if __LINUX_ARM_ARCH__ >= 7
1295 TEST_P("pli [r",0,0b,", #16]")
1296 TEST( "pli [pc, #0]")
1297 TEST_RR("pli [r",12,0b,", r",0, 16,"]")
1298 TEST_RR("pli [r",0, 0b,", -r",12,16,", lsl #4]")
1299#endif
1300
1301#if __LINUX_ARM_ARCH__ >= 5
1302 TEST_P("pld [r",0,32,", #-16]")
1303 TEST( "pld [pc, #0]")
1304 TEST_PR("pld [r",7, 24, ", r",0, 16,"]")
1305 TEST_PR("pld [r",8, 24, ", -r",12,16,", lsl #4]")
1306#endif
1307
1308#if __LINUX_ARM_ARCH__ >= 7
1309 TEST_SUPPORTED( ".word 0xf590f000 @ pldw [r0, #0]")
1310 TEST_SUPPORTED( ".word 0xf797f000 @ pldw [r7, r0]")
1311 TEST_SUPPORTED( ".word 0xf798f18c @ pldw [r8, r12, lsl #3]");
1312#endif
1313
1314#if __LINUX_ARM_ARCH__ >= 7
1315 TEST_UNSUPPORTED("clrex")
1316 TEST_UNSUPPORTED("dsb")
1317 TEST_UNSUPPORTED("dmb")
1318 TEST_UNSUPPORTED("isb")
1319#endif
1320
1321 verbose("\n");
1322}
1323
diff --git a/arch/arm/kernel/kprobes-test-thumb.c b/arch/arm/kernel/kprobes-test-thumb.c
new file mode 100644
index 000000000000..5e726c31c45a
--- /dev/null
+++ b/arch/arm/kernel/kprobes-test-thumb.c
@@ -0,0 +1,1187 @@
1/*
2 * arch/arm/kernel/kprobes-test-thumb.c
3 *
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/module.h>
13
14#include "kprobes-test.h"
15
16
17#define TEST_ISA "16"
18
19#define DONT_TEST_IN_ITBLOCK(tests) \
20 kprobe_test_flags |= TEST_FLAG_NO_ITBLOCK; \
21 tests \
22 kprobe_test_flags &= ~TEST_FLAG_NO_ITBLOCK;
23
24#define CONDITION_INSTRUCTIONS(cc_pos, tests) \
25 kprobe_test_cc_position = cc_pos; \
26 DONT_TEST_IN_ITBLOCK(tests) \
27 kprobe_test_cc_position = 0;
28
29#define TEST_ITBLOCK(code) \
30 kprobe_test_flags |= TEST_FLAG_FULL_ITBLOCK; \
31 TESTCASE_START(code) \
32 TEST_ARG_END("") \
33 "50: nop \n\t" \
34 "1: "code" \n\t" \
35 " mov r1, #0x11 \n\t" \
36 " mov r2, #0x22 \n\t" \
37 " mov r3, #0x33 \n\t" \
38 "2: nop \n\t" \
39 TESTCASE_END \
40 kprobe_test_flags &= ~TEST_FLAG_FULL_ITBLOCK;
41
42#define TEST_THUMB_TO_ARM_INTERWORK_P(code1, reg, val, code2) \
43 TESTCASE_START(code1 #reg code2) \
44 TEST_ARG_PTR(reg, val) \
45 TEST_ARG_REG(14, 99f+1) \
46 TEST_ARG_MEM(15, 3f) \
47 TEST_ARG_END("") \
48 " nop \n\t" /* To align 1f */ \
49 "50: nop \n\t" \
50 "1: "code1 #reg code2" \n\t" \
51 " bx lr \n\t" \
52 ".arm \n\t" \
53 "3: adr lr, 2f+1 \n\t" \
54 " bx lr \n\t" \
55 ".thumb \n\t" \
56 "2: nop \n\t" \
57 TESTCASE_END
58
59
60void kprobe_thumb16_test_cases(void)
61{
62 kprobe_test_flags = TEST_FLAG_NARROW_INSTR;
63
64 TEST_GROUP("Shift (immediate), add, subtract, move, and compare")
65
66 TEST_R( "lsls r7, r",0,VAL1,", #5")
67 TEST_R( "lsls r0, r",7,VAL2,", #11")
68 TEST_R( "lsrs r7, r",0,VAL1,", #5")
69 TEST_R( "lsrs r0, r",7,VAL2,", #11")
70 TEST_R( "asrs r7, r",0,VAL1,", #5")
71 TEST_R( "asrs r0, r",7,VAL2,", #11")
72 TEST_RR( "adds r2, r",0,VAL1,", r",7,VAL2,"")
73 TEST_RR( "adds r5, r",7,VAL2,", r",0,VAL2,"")
74 TEST_RR( "subs r2, r",0,VAL1,", r",7,VAL2,"")
75 TEST_RR( "subs r5, r",7,VAL2,", r",0,VAL2,"")
76 TEST_R( "adds r7, r",0,VAL1,", #5")
77 TEST_R( "adds r0, r",7,VAL2,", #2")
78 TEST_R( "subs r7, r",0,VAL1,", #5")
79 TEST_R( "subs r0, r",7,VAL2,", #2")
80 TEST( "movs.n r0, #0x5f")
81 TEST( "movs.n r7, #0xa0")
82 TEST_R( "cmp.n r",0,0x5e, ", #0x5f")
83 TEST_R( "cmp.n r",5,0x15f,", #0x5f")
84 TEST_R( "cmp.n r",7,0xa0, ", #0xa0")
85 TEST_R( "adds.n r",0,VAL1,", #0x5f")
86 TEST_R( "adds.n r",7,VAL2,", #0xa0")
87 TEST_R( "subs.n r",0,VAL1,", #0x5f")
88 TEST_R( "subs.n r",7,VAL2,", #0xa0")
89
90 TEST_GROUP("16-bit Thumb data-processing instructions")
91
92#define DATA_PROCESSING16(op,val) \
93 TEST_RR( op" r",0,VAL1,", r",7,val,"") \
94 TEST_RR( op" r",7,VAL2,", r",0,val,"")
95
96 DATA_PROCESSING16("ands",0xf00f00ff)
97 DATA_PROCESSING16("eors",0xf00f00ff)
98 DATA_PROCESSING16("lsls",11)
99 DATA_PROCESSING16("lsrs",11)
100 DATA_PROCESSING16("asrs",11)
101 DATA_PROCESSING16("adcs",VAL2)
102 DATA_PROCESSING16("sbcs",VAL2)
103 DATA_PROCESSING16("rors",11)
104 DATA_PROCESSING16("tst",0xf00f00ff)
105 TEST_R("rsbs r",0,VAL1,", #0")
106 TEST_R("rsbs r",7,VAL2,", #0")
107 DATA_PROCESSING16("cmp",0xf00f00ff)
108 DATA_PROCESSING16("cmn",0xf00f00ff)
109 DATA_PROCESSING16("orrs",0xf00f00ff)
110 DATA_PROCESSING16("muls",VAL2)
111 DATA_PROCESSING16("bics",0xf00f00ff)
112 DATA_PROCESSING16("mvns",VAL2)
113
114 TEST_GROUP("Special data instructions and branch and exchange")
115
116 TEST_RR( "add r",0, VAL1,", r",7,VAL2,"")
117 TEST_RR( "add r",3, VAL2,", r",8,VAL3,"")
118 TEST_RR( "add r",8, VAL3,", r",0,VAL1,"")
119 TEST_R( "add sp" ", r",8,-8, "")
120 TEST_R( "add r",14,VAL1,", pc")
121 TEST_BF_R("add pc" ", r",0,2f-1f-8,"")
122 TEST_UNSUPPORTED(".short 0x44ff @ add pc, pc")
123
124 TEST_RR( "cmp r",3,VAL1,", r",8,VAL2,"")
125 TEST_RR( "cmp r",8,VAL2,", r",0,VAL1,"")
126 TEST_R( "cmp sp" ", r",8,-8, "")
127
128 TEST_R( "mov r0, r",7,VAL2,"")
129 TEST_R( "mov r3, r",8,VAL3,"")
130 TEST_R( "mov r8, r",0,VAL1,"")
131 TEST_P( "mov sp, r",8,-8, "")
132 TEST( "mov lr, pc")
133 TEST_BF_R("mov pc, r",0,2f, "")
134
135 TEST_BF_R("bx r",0, 2f+1,"")
136 TEST_BF_R("bx r",14,2f+1,"")
137 TESTCASE_START("bx pc")
138 TEST_ARG_REG(14, 99f+1)
139 TEST_ARG_END("")
140 " nop \n\t" /* To align the bx pc*/
141 "50: nop \n\t"
142 "1: bx pc \n\t"
143 " bx lr \n\t"
144 ".arm \n\t"
145 " adr lr, 2f+1 \n\t"
146 " bx lr \n\t"
147 ".thumb \n\t"
148 "2: nop \n\t"
149 TESTCASE_END
150
151 TEST_BF_R("blx r",0, 2f+1,"")
152 TEST_BB_R("blx r",14,2f+1,"")
153 TEST_UNSUPPORTED(".short 0x47f8 @ blx pc")
154
155 TEST_GROUP("Load from Literal Pool")
156
157 TEST_X( "ldr r0, 3f",
158 ".align \n\t"
159 "3: .word "__stringify(VAL1))
160 TEST_X( "ldr r7, 3f",
161 ".space 128 \n\t"
162 ".align \n\t"
163 "3: .word "__stringify(VAL2))
164
165 TEST_GROUP("16-bit Thumb Load/store instructions")
166
167 TEST_RPR("str r",0, VAL1,", [r",1, 24,", r",2, 48,"]")
168 TEST_RPR("str r",7, VAL2,", [r",6, 24,", r",5, 48,"]")
169 TEST_RPR("strh r",0, VAL1,", [r",1, 24,", r",2, 48,"]")
170 TEST_RPR("strh r",7, VAL2,", [r",6, 24,", r",5, 48,"]")
171 TEST_RPR("strb r",0, VAL1,", [r",1, 24,", r",2, 48,"]")
172 TEST_RPR("strb r",7, VAL2,", [r",6, 24,", r",5, 48,"]")
173 TEST_PR( "ldrsb r0, [r",1, 24,", r",2, 48,"]")
174 TEST_PR( "ldrsb r7, [r",6, 24,", r",5, 50,"]")
175 TEST_PR( "ldr r0, [r",1, 24,", r",2, 48,"]")
176 TEST_PR( "ldr r7, [r",6, 24,", r",5, 48,"]")
177 TEST_PR( "ldrh r0, [r",1, 24,", r",2, 48,"]")
178 TEST_PR( "ldrh r7, [r",6, 24,", r",5, 50,"]")
179 TEST_PR( "ldrb r0, [r",1, 24,", r",2, 48,"]")
180 TEST_PR( "ldrb r7, [r",6, 24,", r",5, 50,"]")
181 TEST_PR( "ldrsh r0, [r",1, 24,", r",2, 48,"]")
182 TEST_PR( "ldrsh r7, [r",6, 24,", r",5, 50,"]")
183
184 TEST_RP("str r",0, VAL1,", [r",1, 24,", #120]")
185 TEST_RP("str r",7, VAL2,", [r",6, 24,", #120]")
186 TEST_P( "ldr r0, [r",1, 24,", #120]")
187 TEST_P( "ldr r7, [r",6, 24,", #120]")
188 TEST_RP("strb r",0, VAL1,", [r",1, 24,", #30]")
189 TEST_RP("strb r",7, VAL2,", [r",6, 24,", #30]")
190 TEST_P( "ldrb r0, [r",1, 24,", #30]")
191 TEST_P( "ldrb r7, [r",6, 24,", #30]")
192 TEST_RP("strh r",0, VAL1,", [r",1, 24,", #60]")
193 TEST_RP("strh r",7, VAL2,", [r",6, 24,", #60]")
194 TEST_P( "ldrh r0, [r",1, 24,", #60]")
195 TEST_P( "ldrh r7, [r",6, 24,", #60]")
196
197 TEST_R( "str r",0, VAL1,", [sp, #0]")
198 TEST_R( "str r",7, VAL2,", [sp, #160]")
199 TEST( "ldr r0, [sp, #0]")
200 TEST( "ldr r7, [sp, #160]")
201
202 TEST_RP("str r",0, VAL1,", [r",0, 24,"]")
203 TEST_P( "ldr r0, [r",0, 24,"]")
204
205 TEST_GROUP("Generate PC-/SP-relative address")
206
207 TEST("add r0, pc, #4")
208 TEST("add r7, pc, #1020")
209 TEST("add r0, sp, #4")
210 TEST("add r7, sp, #1020")
211
212 TEST_GROUP("Miscellaneous 16-bit instructions")
213
214 TEST_UNSUPPORTED( "cpsie i")
215 TEST_UNSUPPORTED( "cpsid i")
216 TEST_UNSUPPORTED( "setend le")
217 TEST_UNSUPPORTED( "setend be")
218
219 TEST("add sp, #"__stringify(TEST_MEMORY_SIZE)) /* Assumes TEST_MEMORY_SIZE < 0x400 */
220 TEST("sub sp, #0x7f*4")
221
222DONT_TEST_IN_ITBLOCK(
223 TEST_BF_R( "cbnz r",0,0, ", 2f")
224 TEST_BF_R( "cbz r",2,-1,", 2f")
225 TEST_BF_RX( "cbnz r",4,1, ", 2f",0x20)
226 TEST_BF_RX( "cbz r",7,0, ", 2f",0x40)
227)
228 TEST_R("sxth r0, r",7, HH1,"")
229 TEST_R("sxth r7, r",0, HH2,"")
230 TEST_R("sxtb r0, r",7, HH1,"")
231 TEST_R("sxtb r7, r",0, HH2,"")
232 TEST_R("uxth r0, r",7, HH1,"")
233 TEST_R("uxth r7, r",0, HH2,"")
234 TEST_R("uxtb r0, r",7, HH1,"")
235 TEST_R("uxtb r7, r",0, HH2,"")
236 TEST_R("rev r0, r",7, VAL1,"")
237 TEST_R("rev r7, r",0, VAL2,"")
238 TEST_R("rev16 r0, r",7, VAL1,"")
239 TEST_R("rev16 r7, r",0, VAL2,"")
240 TEST_UNSUPPORTED(".short 0xba80")
241 TEST_UNSUPPORTED(".short 0xbabf")
242 TEST_R("revsh r0, r",7, VAL1,"")
243 TEST_R("revsh r7, r",0, VAL2,"")
244
245#define TEST_POPPC(code, offset) \
246 TESTCASE_START(code) \
247 TEST_ARG_PTR(13, offset) \
248 TEST_ARG_END("") \
249 TEST_BRANCH_F(code,0) \
250 TESTCASE_END
251
252 TEST("push {r0}")
253 TEST("push {r7}")
254 TEST("push {r14}")
255 TEST("push {r0-r7,r14}")
256 TEST("push {r0,r2,r4,r6,r14}")
257 TEST("push {r1,r3,r5,r7}")
258 TEST("pop {r0}")
259 TEST("pop {r7}")
260 TEST("pop {r0,r2,r4,r6}")
261 TEST_POPPC("pop {pc}",15*4)
262 TEST_POPPC("pop {r0-r7,pc}",7*4)
263 TEST_POPPC("pop {r1,r3,r5,r7,pc}",11*4)
264 TEST_THUMB_TO_ARM_INTERWORK_P("pop {pc} @ ",13,15*4,"")
265 TEST_THUMB_TO_ARM_INTERWORK_P("pop {r0-r7,pc} @ ",13,7*4,"")
266
267 TEST_UNSUPPORTED("bkpt.n 0")
268 TEST_UNSUPPORTED("bkpt.n 255")
269
270 TEST_SUPPORTED("yield")
271 TEST("sev")
272 TEST("nop")
273 TEST("wfi")
274 TEST_SUPPORTED("wfe")
275 TEST_UNSUPPORTED(".short 0xbf50") /* Unassigned hints */
276 TEST_UNSUPPORTED(".short 0xbff0") /* Unassigned hints */
277
278#define TEST_IT(code, code2) \
279 TESTCASE_START(code) \
280 TEST_ARG_END("") \
281 "50: nop \n\t" \
282 "1: "code" \n\t" \
283 " "code2" \n\t" \
284 "2: nop \n\t" \
285 TESTCASE_END
286
287DONT_TEST_IN_ITBLOCK(
288 TEST_IT("it eq","moveq r0,#0")
289 TEST_IT("it vc","movvc r0,#0")
290 TEST_IT("it le","movle r0,#0")
291 TEST_IT("ite eq","moveq r0,#0\n\t movne r1,#1")
292 TEST_IT("itet vc","movvc r0,#0\n\t movvs r1,#1\n\t movvc r2,#2")
293 TEST_IT("itete le","movle r0,#0\n\t movgt r1,#1\n\t movle r2,#2\n\t movgt r3,#3")
294 TEST_IT("itttt le","movle r0,#0\n\t movle r1,#1\n\t movle r2,#2\n\t movle r3,#3")
295 TEST_IT("iteee le","movle r0,#0\n\t movgt r1,#1\n\t movgt r2,#2\n\t movgt r3,#3")
296)
297
298 TEST_GROUP("Load and store multiple")
299
300 TEST_P("ldmia r",4, 16*4,"!, {r0,r7}")
301 TEST_P("ldmia r",7, 16*4,"!, {r0-r6}")
302 TEST_P("stmia r",4, 16*4,"!, {r0,r7}")
303 TEST_P("stmia r",0, 16*4,"!, {r0-r7}")
304
305 TEST_GROUP("Conditional branch and Supervisor Call instructions")
306
307CONDITION_INSTRUCTIONS(8,
308 TEST_BF("beq 2f")
309 TEST_BB("bne 2b")
310 TEST_BF("bgt 2f")
311 TEST_BB("blt 2b")
312)
313 TEST_UNSUPPORTED(".short 0xde00")
314 TEST_UNSUPPORTED(".short 0xdeff")
315 TEST_UNSUPPORTED("svc #0x00")
316 TEST_UNSUPPORTED("svc #0xff")
317
318 TEST_GROUP("Unconditional branch")
319
320 TEST_BF( "b 2f")
321 TEST_BB( "b 2b")
322 TEST_BF_X("b 2f", 0x400)
323 TEST_BB_X("b 2b", 0x400)
324
325 TEST_GROUP("Testing instructions in IT blocks")
326
327 TEST_ITBLOCK("subs.n r0, r0")
328
329 verbose("\n");
330}
331
332
333void kprobe_thumb32_test_cases(void)
334{
335 kprobe_test_flags = 0;
336
337 TEST_GROUP("Load/store multiple")
338
339 TEST_UNSUPPORTED("rfedb sp")
340 TEST_UNSUPPORTED("rfeia sp")
341 TEST_UNSUPPORTED("rfedb sp!")
342 TEST_UNSUPPORTED("rfeia sp!")
343
344 TEST_P( "stmia r",0, 16*4,", {r0,r8}")
345 TEST_P( "stmia r",4, 16*4,", {r0-r12,r14}")
346 TEST_P( "stmia r",7, 16*4,"!, {r8-r12,r14}")
347 TEST_P( "stmia r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
348
349 TEST_P( "ldmia r",0, 16*4,", {r0,r8}")
350 TEST_P( "ldmia r",4, 0, ", {r0-r12,r14}")
351 TEST_BF_P("ldmia r",5, 8*4, "!, {r6-r12,r15}")
352 TEST_P( "ldmia r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
353 TEST_BF_P("ldmia r",14,14*4,"!, {r4,pc}")
354
355 TEST_P( "stmdb r",0, 16*4,", {r0,r8}")
356 TEST_P( "stmdb r",4, 16*4,", {r0-r12,r14}")
357 TEST_P( "stmdb r",5, 16*4,"!, {r8-r12,r14}")
358 TEST_P( "stmdb r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
359
360 TEST_P( "ldmdb r",0, 16*4,", {r0,r8}")
361 TEST_P( "ldmdb r",4, 16*4,", {r0-r12,r14}")
362 TEST_BF_P("ldmdb r",5, 16*4,"!, {r6-r12,r15}")
363 TEST_P( "ldmdb r",12,16*4,"!, {r1,r3,r5,r7,r8-r11,r14}")
364 TEST_BF_P("ldmdb r",14,16*4,"!, {r4,pc}")
365
366 TEST_P( "stmdb r",13,16*4,"!, {r3-r12,lr}")
367 TEST_P( "stmdb r",13,16*4,"!, {r3-r12}")
368 TEST_P( "stmdb r",2, 16*4,", {r3-r12,lr}")
369 TEST_P( "stmdb r",13,16*4,"!, {r2-r12,lr}")
370 TEST_P( "stmdb r",0, 16*4,", {r0-r12}")
371 TEST_P( "stmdb r",0, 16*4,", {r0-r12,lr}")
372
373 TEST_BF_P("ldmia r",13,5*4, "!, {r3-r12,pc}")
374 TEST_P( "ldmia r",13,5*4, "!, {r3-r12}")
375 TEST_BF_P("ldmia r",2, 5*4, "!, {r3-r12,pc}")
376 TEST_BF_P("ldmia r",13,4*4, "!, {r2-r12,pc}")
377 TEST_P( "ldmia r",0, 16*4,", {r0-r12}")
378 TEST_P( "ldmia r",0, 16*4,", {r0-r12,lr}")
379
380 TEST_THUMB_TO_ARM_INTERWORK_P("ldmia r",0,14*4,", {r12,pc}")
381 TEST_THUMB_TO_ARM_INTERWORK_P("ldmia r",13,2*4,", {r0-r12,pc}")
382
383 TEST_UNSUPPORTED(".short 0xe88f,0x0101 @ stmia pc, {r0,r8}")
384 TEST_UNSUPPORTED(".short 0xe92f,0x5f00 @ stmdb pc!, {r8-r12,r14}")
385 TEST_UNSUPPORTED(".short 0xe8bd,0xc000 @ ldmia r13!, {r14,pc}")
386 TEST_UNSUPPORTED(".short 0xe93e,0xc000 @ ldmdb r14!, {r14,pc}")
387 TEST_UNSUPPORTED(".short 0xe8a7,0x3f00 @ stmia r7!, {r8-r12,sp}")
388 TEST_UNSUPPORTED(".short 0xe8a7,0x9f00 @ stmia r7!, {r8-r12,pc}")
389 TEST_UNSUPPORTED(".short 0xe93e,0x2010 @ ldmdb r14!, {r4,sp}")
390
391 TEST_GROUP("Load/store double or exclusive, table branch")
392
393 TEST_P( "ldrd r0, r1, [r",1, 24,", #-16]")
394 TEST( "ldrd r12, r14, [sp, #16]")
395 TEST_P( "ldrd r1, r0, [r",7, 24,", #-16]!")
396 TEST( "ldrd r14, r12, [sp, #16]!")
397 TEST_P( "ldrd r1, r0, [r",7, 24,"], #16")
398 TEST( "ldrd r7, r8, [sp], #-16")
399
400 TEST_X( "ldrd r12, r14, 3f",
401 ".align 3 \n\t"
402 "3: .word "__stringify(VAL1)" \n\t"
403 " .word "__stringify(VAL2))
404
405 TEST_UNSUPPORTED(".short 0xe9ff,0xec04 @ ldrd r14, r12, [pc, #16]!")
406 TEST_UNSUPPORTED(".short 0xe8ff,0xec04 @ ldrd r14, r12, [pc], #16")
407 TEST_UNSUPPORTED(".short 0xe9d4,0xd800 @ ldrd sp, r8, [r4]")
408 TEST_UNSUPPORTED(".short 0xe9d4,0xf800 @ ldrd pc, r8, [r4]")
409 TEST_UNSUPPORTED(".short 0xe9d4,0x7d00 @ ldrd r7, sp, [r4]")
410 TEST_UNSUPPORTED(".short 0xe9d4,0x7f00 @ ldrd r7, pc, [r4]")
411
412 TEST_RRP("strd r",0, VAL1,", r",1, VAL2,", [r",1, 24,", #-16]")
413 TEST_RR( "strd r",12,VAL2,", r",14,VAL1,", [sp, #16]")
414 TEST_RRP("strd r",1, VAL1,", r",0, VAL2,", [r",7, 24,", #-16]!")
415 TEST_RR( "strd r",14,VAL2,", r",12,VAL1,", [sp, #16]!")
416 TEST_RRP("strd r",1, VAL1,", r",0, VAL2,", [r",7, 24,"], #16")
417 TEST_RR( "strd r",7, VAL2,", r",8, VAL1,", [sp], #-16")
418 TEST_UNSUPPORTED(".short 0xe9ef,0xec04 @ strd r14, r12, [pc, #16]!")
419 TEST_UNSUPPORTED(".short 0xe8ef,0xec04 @ strd r14, r12, [pc], #16")
420
421 TEST_RX("tbb [pc, r",0, (9f-(1f+4)),"]",
422 "9: \n\t"
423 ".byte (2f-1b-4)>>1 \n\t"
424 ".byte (3f-1b-4)>>1 \n\t"
425 "3: mvn r0, r0 \n\t"
426 "2: nop \n\t")
427
428 TEST_RX("tbb [pc, r",4, (9f-(1f+4)+1),"]",
429 "9: \n\t"
430 ".byte (2f-1b-4)>>1 \n\t"
431 ".byte (3f-1b-4)>>1 \n\t"
432 "3: mvn r0, r0 \n\t"
433 "2: nop \n\t")
434
435 TEST_RRX("tbb [r",1,9f,", r",2,0,"]",
436 "9: \n\t"
437 ".byte (2f-1b-4)>>1 \n\t"
438 ".byte (3f-1b-4)>>1 \n\t"
439 "3: mvn r0, r0 \n\t"
440 "2: nop \n\t")
441
442 TEST_RX("tbh [pc, r",7, (9f-(1f+4))>>1,"]",
443 "9: \n\t"
444 ".short (2f-1b-4)>>1 \n\t"
445 ".short (3f-1b-4)>>1 \n\t"
446 "3: mvn r0, r0 \n\t"
447 "2: nop \n\t")
448
449 TEST_RX("tbh [pc, r",12, ((9f-(1f+4))>>1)+1,"]",
450 "9: \n\t"
451 ".short (2f-1b-4)>>1 \n\t"
452 ".short (3f-1b-4)>>1 \n\t"
453 "3: mvn r0, r0 \n\t"
454 "2: nop \n\t")
455
456 TEST_RRX("tbh [r",1,9f, ", r",14,1,"]",
457 "9: \n\t"
458 ".short (2f-1b-4)>>1 \n\t"
459 ".short (3f-1b-4)>>1 \n\t"
460 "3: mvn r0, r0 \n\t"
461 "2: nop \n\t")
462
463 TEST_UNSUPPORTED(".short 0xe8d1,0xf01f @ tbh [r1, pc]")
464 TEST_UNSUPPORTED(".short 0xe8d1,0xf01d @ tbh [r1, sp]")
465 TEST_UNSUPPORTED(".short 0xe8dd,0xf012 @ tbh [sp, r2]")
466
467 TEST_UNSUPPORTED("strexb r0, r1, [r2]")
468 TEST_UNSUPPORTED("strexh r0, r1, [r2]")
469 TEST_UNSUPPORTED("strexd r0, r1, [r2]")
470 TEST_UNSUPPORTED("ldrexb r0, [r1]")
471 TEST_UNSUPPORTED("ldrexh r0, [r1]")
472 TEST_UNSUPPORTED("ldrexd r0, [r1]")
473
474 TEST_GROUP("Data-processing (shifted register) and (modified immediate)")
475
476#define _DATA_PROCESSING32_DNM(op,s,val) \
477 TEST_RR(op s".w r0, r",1, VAL1,", r",2, val, "") \
478 TEST_RR(op s" r1, r",1, VAL1,", r",2, val, ", lsl #3") \
479 TEST_RR(op s" r2, r",3, VAL1,", r",2, val, ", lsr #4") \
480 TEST_RR(op s" r3, r",3, VAL1,", r",2, val, ", asr #5") \
481 TEST_RR(op s" r4, r",5, VAL1,", r",2, N(val),", asr #6") \
482 TEST_RR(op s" r5, r",5, VAL1,", r",2, val, ", ror #7") \
483 TEST_RR(op s" r8, r",9, VAL1,", r",10,val, ", rrx") \
484 TEST_R( op s" r0, r",11,VAL1,", #0x00010001") \
485 TEST_R( op s" r11, r",0, VAL1,", #0xf5000000") \
486 TEST_R( op s" r7, r",8, VAL2,", #0x000af000")
487
488#define DATA_PROCESSING32_DNM(op,val) \
489 _DATA_PROCESSING32_DNM(op,"",val) \
490 _DATA_PROCESSING32_DNM(op,"s",val)
491
492#define DATA_PROCESSING32_NM(op,val) \
493 TEST_RR(op".w r",1, VAL1,", r",2, val, "") \
494 TEST_RR(op" r",1, VAL1,", r",2, val, ", lsl #3") \
495 TEST_RR(op" r",3, VAL1,", r",2, val, ", lsr #4") \
496 TEST_RR(op" r",3, VAL1,", r",2, val, ", asr #5") \
497 TEST_RR(op" r",5, VAL1,", r",2, N(val),", asr #6") \
498 TEST_RR(op" r",5, VAL1,", r",2, val, ", ror #7") \
499 TEST_RR(op" r",9, VAL1,", r",10,val, ", rrx") \
500 TEST_R( op" r",11,VAL1,", #0x00010001") \
501 TEST_R( op" r",0, VAL1,", #0xf5000000") \
502 TEST_R( op" r",8, VAL2,", #0x000af000")
503
504#define _DATA_PROCESSING32_DM(op,s,val) \
505 TEST_R( op s".w r0, r",14, val, "") \
506 TEST_R( op s" r1, r",12, val, ", lsl #3") \
507 TEST_R( op s" r2, r",11, val, ", lsr #4") \
508 TEST_R( op s" r3, r",10, val, ", asr #5") \
509 TEST_R( op s" r4, r",9, N(val),", asr #6") \
510 TEST_R( op s" r5, r",8, val, ", ror #7") \
511 TEST_R( op s" r8, r",7,val, ", rrx") \
512 TEST( op s" r0, #0x00010001") \
513 TEST( op s" r11, #0xf5000000") \
514 TEST( op s" r7, #0x000af000") \
515 TEST( op s" r4, #0x00005a00")
516
517#define DATA_PROCESSING32_DM(op,val) \
518 _DATA_PROCESSING32_DM(op,"",val) \
519 _DATA_PROCESSING32_DM(op,"s",val)
520
521 DATA_PROCESSING32_DNM("and",0xf00f00ff)
522 DATA_PROCESSING32_NM("tst",0xf00f00ff)
523 DATA_PROCESSING32_DNM("bic",0xf00f00ff)
524 DATA_PROCESSING32_DNM("orr",0xf00f00ff)
525 DATA_PROCESSING32_DM("mov",VAL2)
526 DATA_PROCESSING32_DNM("orn",0xf00f00ff)
527 DATA_PROCESSING32_DM("mvn",VAL2)
528 DATA_PROCESSING32_DNM("eor",0xf00f00ff)
529 DATA_PROCESSING32_NM("teq",0xf00f00ff)
530 DATA_PROCESSING32_DNM("add",VAL2)
531 DATA_PROCESSING32_NM("cmn",VAL2)
532 DATA_PROCESSING32_DNM("adc",VAL2)
533 DATA_PROCESSING32_DNM("sbc",VAL2)
534 DATA_PROCESSING32_DNM("sub",VAL2)
535 DATA_PROCESSING32_NM("cmp",VAL2)
536 DATA_PROCESSING32_DNM("rsb",VAL2)
537
538 TEST_RR("pkhbt r0, r",0, HH1,", r",1, HH2,"")
539 TEST_RR("pkhbt r14,r",12, HH1,", r",10,HH2,", lsl #2")
540 TEST_RR("pkhtb r0, r",0, HH1,", r",1, HH2,"")
541 TEST_RR("pkhtb r14,r",12, HH1,", r",10,HH2,", asr #2")
542
543 TEST_UNSUPPORTED(".short 0xea17,0x0f0d @ tst.w r7, sp")
544 TEST_UNSUPPORTED(".short 0xea17,0x0f0f @ tst.w r7, pc")
545 TEST_UNSUPPORTED(".short 0xea1d,0x0f07 @ tst.w sp, r7")
546 TEST_UNSUPPORTED(".short 0xea1f,0x0f07 @ tst.w pc, r7")
547 TEST_UNSUPPORTED(".short 0xf01d,0x1f08 @ tst sp, #0x00080008")
548 TEST_UNSUPPORTED(".short 0xf01f,0x1f08 @ tst pc, #0x00080008")
549
550 TEST_UNSUPPORTED(".short 0xea97,0x0f0d @ teq.w r7, sp")
551 TEST_UNSUPPORTED(".short 0xea97,0x0f0f @ teq.w r7, pc")
552 TEST_UNSUPPORTED(".short 0xea9d,0x0f07 @ teq.w sp, r7")
553 TEST_UNSUPPORTED(".short 0xea9f,0x0f07 @ teq.w pc, r7")
554 TEST_UNSUPPORTED(".short 0xf09d,0x1f08 @ tst sp, #0x00080008")
555 TEST_UNSUPPORTED(".short 0xf09f,0x1f08 @ tst pc, #0x00080008")
556
557 TEST_UNSUPPORTED(".short 0xeb17,0x0f0d @ cmn.w r7, sp")
558 TEST_UNSUPPORTED(".short 0xeb17,0x0f0f @ cmn.w r7, pc")
559 TEST_P("cmn.w sp, r",7,0,"")
560 TEST_UNSUPPORTED(".short 0xeb1f,0x0f07 @ cmn.w pc, r7")
561 TEST( "cmn sp, #0x00080008")
562 TEST_UNSUPPORTED(".short 0xf11f,0x1f08 @ cmn pc, #0x00080008")
563
564 TEST_UNSUPPORTED(".short 0xebb7,0x0f0d @ cmp.w r7, sp")
565 TEST_UNSUPPORTED(".short 0xebb7,0x0f0f @ cmp.w r7, pc")
566 TEST_P("cmp.w sp, r",7,0,"")
567 TEST_UNSUPPORTED(".short 0xebbf,0x0f07 @ cmp.w pc, r7")
568 TEST( "cmp sp, #0x00080008")
569 TEST_UNSUPPORTED(".short 0xf1bf,0x1f08 @ cmp pc, #0x00080008")
570
571 TEST_UNSUPPORTED(".short 0xea5f,0x070d @ movs.w r7, sp")
572 TEST_UNSUPPORTED(".short 0xea5f,0x070f @ movs.w r7, pc")
573 TEST_UNSUPPORTED(".short 0xea5f,0x0d07 @ movs.w sp, r7")
574 TEST_UNSUPPORTED(".short 0xea4f,0x0f07 @ mov.w pc, r7")
575 TEST_UNSUPPORTED(".short 0xf04f,0x1d08 @ mov sp, #0x00080008")
576 TEST_UNSUPPORTED(".short 0xf04f,0x1f08 @ mov pc, #0x00080008")
577
578 TEST_R("add.w r0, sp, r",1, 4,"")
579 TEST_R("adds r0, sp, r",1, 4,", asl #3")
580 TEST_R("add r0, sp, r",1, 4,", asl #4")
581 TEST_R("add r0, sp, r",1, 16,", ror #1")
582 TEST_R("add.w sp, sp, r",1, 4,"")
583 TEST_R("add sp, sp, r",1, 4,", asl #3")
584 TEST_UNSUPPORTED(".short 0xeb0d,0x1d01 @ add sp, sp, r1, asl #4")
585 TEST_UNSUPPORTED(".short 0xeb0d,0x0d71 @ add sp, sp, r1, ror #1")
586 TEST( "add.w r0, sp, #24")
587 TEST( "add.w sp, sp, #24")
588 TEST_UNSUPPORTED(".short 0xeb0d,0x0f01 @ add pc, sp, r1")
589 TEST_UNSUPPORTED(".short 0xeb0d,0x000f @ add r0, sp, pc")
590 TEST_UNSUPPORTED(".short 0xeb0d,0x000d @ add r0, sp, sp")
591 TEST_UNSUPPORTED(".short 0xeb0d,0x0d0f @ add sp, sp, pc")
592 TEST_UNSUPPORTED(".short 0xeb0d,0x0d0d @ add sp, sp, sp")
593
594 TEST_R("sub.w r0, sp, r",1, 4,"")
595 TEST_R("subs r0, sp, r",1, 4,", asl #3")
596 TEST_R("sub r0, sp, r",1, 4,", asl #4")
597 TEST_R("sub r0, sp, r",1, 16,", ror #1")
598 TEST_R("sub.w sp, sp, r",1, 4,"")
599 TEST_R("sub sp, sp, r",1, 4,", asl #3")
600 TEST_UNSUPPORTED(".short 0xebad,0x1d01 @ sub sp, sp, r1, asl #4")
601 TEST_UNSUPPORTED(".short 0xebad,0x0d71 @ sub sp, sp, r1, ror #1")
602 TEST_UNSUPPORTED(".short 0xebad,0x0f01 @ sub pc, sp, r1")
603 TEST( "sub.w r0, sp, #24")
604 TEST( "sub.w sp, sp, #24")
605
606 TEST_UNSUPPORTED(".short 0xea02,0x010f @ and r1, r2, pc")
607 TEST_UNSUPPORTED(".short 0xea0f,0x0103 @ and r1, pc, r3")
608 TEST_UNSUPPORTED(".short 0xea02,0x0f03 @ and pc, r2, r3")
609 TEST_UNSUPPORTED(".short 0xea02,0x010d @ and r1, r2, sp")
610 TEST_UNSUPPORTED(".short 0xea0d,0x0103 @ and r1, sp, r3")
611 TEST_UNSUPPORTED(".short 0xea02,0x0d03 @ and sp, r2, r3")
612 TEST_UNSUPPORTED(".short 0xf00d,0x1108 @ and r1, sp, #0x00080008")
613 TEST_UNSUPPORTED(".short 0xf00f,0x1108 @ and r1, pc, #0x00080008")
614 TEST_UNSUPPORTED(".short 0xf002,0x1d08 @ and sp, r8, #0x00080008")
615 TEST_UNSUPPORTED(".short 0xf002,0x1f08 @ and pc, r8, #0x00080008")
616
617 TEST_UNSUPPORTED(".short 0xeb02,0x010f @ add r1, r2, pc")
618 TEST_UNSUPPORTED(".short 0xeb0f,0x0103 @ add r1, pc, r3")
619 TEST_UNSUPPORTED(".short 0xeb02,0x0f03 @ add pc, r2, r3")
620 TEST_UNSUPPORTED(".short 0xeb02,0x010d @ add r1, r2, sp")
621 TEST_SUPPORTED( ".short 0xeb0d,0x0103 @ add r1, sp, r3")
622 TEST_UNSUPPORTED(".short 0xeb02,0x0d03 @ add sp, r2, r3")
623 TEST_SUPPORTED( ".short 0xf10d,0x1108 @ add r1, sp, #0x00080008")
624 TEST_UNSUPPORTED(".short 0xf10d,0x1f08 @ add pc, sp, #0x00080008")
625 TEST_UNSUPPORTED(".short 0xf10f,0x1108 @ add r1, pc, #0x00080008")
626 TEST_UNSUPPORTED(".short 0xf102,0x1d08 @ add sp, r8, #0x00080008")
627 TEST_UNSUPPORTED(".short 0xf102,0x1f08 @ add pc, r8, #0x00080008")
628
629 TEST_UNSUPPORTED(".short 0xeaa0,0x0000")
630 TEST_UNSUPPORTED(".short 0xeaf0,0x0000")
631 TEST_UNSUPPORTED(".short 0xeb20,0x0000")
632 TEST_UNSUPPORTED(".short 0xeb80,0x0000")
633 TEST_UNSUPPORTED(".short 0xebe0,0x0000")
634
635 TEST_UNSUPPORTED(".short 0xf0a0,0x0000")
636 TEST_UNSUPPORTED(".short 0xf0c0,0x0000")
637 TEST_UNSUPPORTED(".short 0xf0f0,0x0000")
638 TEST_UNSUPPORTED(".short 0xf120,0x0000")
639 TEST_UNSUPPORTED(".short 0xf180,0x0000")
640 TEST_UNSUPPORTED(".short 0xf1e0,0x0000")
641
642 TEST_GROUP("Coprocessor instructions")
643
644 TEST_UNSUPPORTED(".short 0xec00,0x0000")
645 TEST_UNSUPPORTED(".short 0xeff0,0x0000")
646 TEST_UNSUPPORTED(".short 0xfc00,0x0000")
647 TEST_UNSUPPORTED(".short 0xfff0,0x0000")
648
649 TEST_GROUP("Data-processing (plain binary immediate)")
650
651 TEST_R("addw r0, r",1, VAL1,", #0x123")
652 TEST( "addw r14, sp, #0xf5a")
653 TEST( "addw sp, sp, #0x20")
654 TEST( "addw r7, pc, #0x888")
655 TEST_UNSUPPORTED(".short 0xf20f,0x1f20 @ addw pc, pc, #0x120")
656 TEST_UNSUPPORTED(".short 0xf20d,0x1f20 @ addw pc, sp, #0x120")
657 TEST_UNSUPPORTED(".short 0xf20f,0x1d20 @ addw sp, pc, #0x120")
658 TEST_UNSUPPORTED(".short 0xf200,0x1d20 @ addw sp, r0, #0x120")
659
660 TEST_R("subw r0, r",1, VAL1,", #0x123")
661 TEST( "subw r14, sp, #0xf5a")
662 TEST( "subw sp, sp, #0x20")
663 TEST( "subw r7, pc, #0x888")
664 TEST_UNSUPPORTED(".short 0xf2af,0x1f20 @ subw pc, pc, #0x120")
665 TEST_UNSUPPORTED(".short 0xf2ad,0x1f20 @ subw pc, sp, #0x120")
666 TEST_UNSUPPORTED(".short 0xf2af,0x1d20 @ subw sp, pc, #0x120")
667 TEST_UNSUPPORTED(".short 0xf2a0,0x1d20 @ subw sp, r0, #0x120")
668
669 TEST("movw r0, #0")
670 TEST("movw r0, #0xffff")
671 TEST("movw lr, #0xffff")
672 TEST_UNSUPPORTED(".short 0xf240,0x0d00 @ movw sp, #0")
673 TEST_UNSUPPORTED(".short 0xf240,0x0f00 @ movw pc, #0")
674
675 TEST_R("movt r",0, VAL1,", #0")
676 TEST_R("movt r",0, VAL2,", #0xffff")
677 TEST_R("movt r",14,VAL1,", #0xffff")
678 TEST_UNSUPPORTED(".short 0xf2c0,0x0d00 @ movt sp, #0")
679 TEST_UNSUPPORTED(".short 0xf2c0,0x0f00 @ movt pc, #0")
680
681 TEST_R( "ssat r0, #24, r",0, VAL1,"")
682 TEST_R( "ssat r14, #24, r",12, VAL2,"")
683 TEST_R( "ssat r0, #24, r",0, VAL1,", lsl #8")
684 TEST_R( "ssat r14, #24, r",12, VAL2,", asr #8")
685 TEST_UNSUPPORTED(".short 0xf30c,0x0d17 @ ssat sp, #24, r12")
686 TEST_UNSUPPORTED(".short 0xf30c,0x0f17 @ ssat pc, #24, r12")
687 TEST_UNSUPPORTED(".short 0xf30d,0x0c17 @ ssat r12, #24, sp")
688 TEST_UNSUPPORTED(".short 0xf30f,0x0c17 @ ssat r12, #24, pc")
689
690 TEST_R( "usat r0, #24, r",0, VAL1,"")
691 TEST_R( "usat r14, #24, r",12, VAL2,"")
692 TEST_R( "usat r0, #24, r",0, VAL1,", lsl #8")
693 TEST_R( "usat r14, #24, r",12, VAL2,", asr #8")
694 TEST_UNSUPPORTED(".short 0xf38c,0x0d17 @ usat sp, #24, r12")
695 TEST_UNSUPPORTED(".short 0xf38c,0x0f17 @ usat pc, #24, r12")
696 TEST_UNSUPPORTED(".short 0xf38d,0x0c17 @ usat r12, #24, sp")
697 TEST_UNSUPPORTED(".short 0xf38f,0x0c17 @ usat r12, #24, pc")
698
699 TEST_R( "ssat16 r0, #12, r",0, HH1,"")
700 TEST_R( "ssat16 r14, #12, r",12, HH2,"")
701 TEST_UNSUPPORTED(".short 0xf32c,0x0d0b @ ssat16 sp, #12, r12")
702 TEST_UNSUPPORTED(".short 0xf32c,0x0f0b @ ssat16 pc, #12, r12")
703 TEST_UNSUPPORTED(".short 0xf32d,0x0c0b @ ssat16 r12, #12, sp")
704 TEST_UNSUPPORTED(".short 0xf32f,0x0c0b @ ssat16 r12, #12, pc")
705
706 TEST_R( "usat16 r0, #12, r",0, HH1,"")
707 TEST_R( "usat16 r14, #12, r",12, HH2,"")
708 TEST_UNSUPPORTED(".short 0xf3ac,0x0d0b @ usat16 sp, #12, r12")
709 TEST_UNSUPPORTED(".short 0xf3ac,0x0f0b @ usat16 pc, #12, r12")
710 TEST_UNSUPPORTED(".short 0xf3ad,0x0c0b @ usat16 r12, #12, sp")
711 TEST_UNSUPPORTED(".short 0xf3af,0x0c0b @ usat16 r12, #12, pc")
712
713 TEST_R( "sbfx r0, r",0 , VAL1,", #0, #31")
714 TEST_R( "sbfx r14, r",12, VAL2,", #8, #16")
715 TEST_R( "sbfx r4, r",10, VAL1,", #16, #15")
716 TEST_UNSUPPORTED(".short 0xf34c,0x2d0f @ sbfx sp, r12, #8, #16")
717 TEST_UNSUPPORTED(".short 0xf34c,0x2f0f @ sbfx pc, r12, #8, #16")
718 TEST_UNSUPPORTED(".short 0xf34d,0x2c0f @ sbfx r12, sp, #8, #16")
719 TEST_UNSUPPORTED(".short 0xf34f,0x2c0f @ sbfx r12, pc, #8, #16")
720
721 TEST_R( "ubfx r0, r",0 , VAL1,", #0, #31")
722 TEST_R( "ubfx r14, r",12, VAL2,", #8, #16")
723 TEST_R( "ubfx r4, r",10, VAL1,", #16, #15")
724 TEST_UNSUPPORTED(".short 0xf3cc,0x2d0f @ ubfx sp, r12, #8, #16")
725 TEST_UNSUPPORTED(".short 0xf3cc,0x2f0f @ ubfx pc, r12, #8, #16")
726 TEST_UNSUPPORTED(".short 0xf3cd,0x2c0f @ ubfx r12, sp, #8, #16")
727 TEST_UNSUPPORTED(".short 0xf3cf,0x2c0f @ ubfx r12, pc, #8, #16")
728
729 TEST_R( "bfc r",0, VAL1,", #4, #20")
730 TEST_R( "bfc r",14,VAL2,", #4, #20")
731 TEST_R( "bfc r",7, VAL1,", #0, #31")
732 TEST_R( "bfc r",8, VAL2,", #0, #31")
733 TEST_UNSUPPORTED(".short 0xf36f,0x0d1e @ bfc sp, #0, #31")
734 TEST_UNSUPPORTED(".short 0xf36f,0x0f1e @ bfc pc, #0, #31")
735
736 TEST_RR( "bfi r",0, VAL1,", r",0 , VAL2,", #0, #31")
737 TEST_RR( "bfi r",12,VAL1,", r",14 , VAL2,", #4, #20")
738 TEST_UNSUPPORTED(".short 0xf36e,0x1d17 @ bfi sp, r14, #4, #20")
739 TEST_UNSUPPORTED(".short 0xf36e,0x1f17 @ bfi pc, r14, #4, #20")
740 TEST_UNSUPPORTED(".short 0xf36d,0x1e17 @ bfi r14, sp, #4, #20")
741
742 TEST_GROUP("Branches and miscellaneous control")
743
744CONDITION_INSTRUCTIONS(22,
745 TEST_BF("beq.w 2f")
746 TEST_BB("bne.w 2b")
747 TEST_BF("bgt.w 2f")
748 TEST_BB("blt.w 2b")
749 TEST_BF_X("bpl.w 2f",0x1000)
750)
751
752 TEST_UNSUPPORTED("msr cpsr, r0")
753 TEST_UNSUPPORTED("msr cpsr_f, r1")
754 TEST_UNSUPPORTED("msr spsr, r2")
755
756 TEST_UNSUPPORTED("cpsie.w i")
757 TEST_UNSUPPORTED("cpsid.w i")
758 TEST_UNSUPPORTED("cps 0x13")
759
760 TEST_SUPPORTED("yield.w")
761 TEST("sev.w")
762 TEST("nop.w")
763 TEST("wfi.w")
764 TEST_SUPPORTED("wfe.w")
765 TEST_UNSUPPORTED("dbg.w #0")
766
767 TEST_UNSUPPORTED("clrex")
768 TEST_UNSUPPORTED("dsb")
769 TEST_UNSUPPORTED("dmb")
770 TEST_UNSUPPORTED("isb")
771
772 TEST_UNSUPPORTED("bxj r0")
773
774 TEST_UNSUPPORTED("subs pc, lr, #4")
775
776 TEST("mrs r0, cpsr")
777 TEST("mrs r14, cpsr")
778 TEST_UNSUPPORTED(".short 0xf3ef,0x8d00 @ mrs sp, spsr")
779 TEST_UNSUPPORTED(".short 0xf3ef,0x8f00 @ mrs pc, spsr")
780 TEST_UNSUPPORTED("mrs r0, spsr")
781 TEST_UNSUPPORTED("mrs lr, spsr")
782
783 TEST_UNSUPPORTED(".short 0xf7f0,0x8000 @ smc #0")
784
785 TEST_UNSUPPORTED(".short 0xf7f0,0xa000 @ undefeined")
786
787 TEST_BF( "b.w 2f")
788 TEST_BB( "b.w 2b")
789 TEST_BF_X("b.w 2f", 0x1000)
790
791 TEST_BF( "bl.w 2f")
792 TEST_BB( "bl.w 2b")
793 TEST_BB_X("bl.w 2b", 0x1000)
794
795 TEST_X( "blx __dummy_arm_subroutine",
796 ".arm \n\t"
797 ".align \n\t"
798 ".type __dummy_arm_subroutine, %%function \n\t"
799 "__dummy_arm_subroutine: \n\t"
800 "mov r0, pc \n\t"
801 "bx lr \n\t"
802 ".thumb \n\t"
803 )
804 TEST( "blx __dummy_arm_subroutine")
805
806 TEST_GROUP("Store single data item")
807
808#define SINGLE_STORE(size) \
809 TEST_RP( "str"size" r",0, VAL1,", [r",11,-1024,", #1024]") \
810 TEST_RP( "str"size" r",14,VAL2,", [r",1, -1024,", #1080]") \
811 TEST_RP( "str"size" r",0, VAL1,", [r",11,256, ", #-120]") \
812 TEST_RP( "str"size" r",14,VAL2,", [r",1, 256, ", #-128]") \
813 TEST_RP( "str"size" r",0, VAL1,", [r",11,24, "], #120") \
814 TEST_RP( "str"size" r",14,VAL2,", [r",1, 24, "], #128") \
815 TEST_RP( "str"size" r",0, VAL1,", [r",11,24, "], #-120") \
816 TEST_RP( "str"size" r",14,VAL2,", [r",1, 24, "], #-128") \
817 TEST_RP( "str"size" r",0, VAL1,", [r",11,24, ", #120]!") \
818 TEST_RP( "str"size" r",14,VAL2,", [r",1, 24, ", #128]!") \
819 TEST_RP( "str"size" r",0, VAL1,", [r",11,256, ", #-120]!") \
820 TEST_RP( "str"size" r",14,VAL2,", [r",1, 256, ", #-128]!") \
821 TEST_RPR("str"size".w r",0, VAL1,", [r",1, 0,", r",2, 4,"]") \
822 TEST_RPR("str"size" r",14,VAL2,", [r",10,0,", r",11,4,", lsl #1]") \
823 TEST_R( "str"size".w r",7, VAL1,", [sp, #24]") \
824 TEST_RP( "str"size".w r",0, VAL2,", [r",0,0, "]") \
825 TEST_UNSUPPORTED("str"size"t r0, [r1, #4]")
826
827 SINGLE_STORE("b")
828 SINGLE_STORE("h")
829 SINGLE_STORE("")
830
831 TEST("str sp, [sp]")
832 TEST_UNSUPPORTED(".short 0xf8cf,0xe000 @ str r14, [pc]")
833 TEST_UNSUPPORTED(".short 0xf8ce,0xf000 @ str pc, [r14]")
834
835 TEST_GROUP("Advanced SIMD element or structure load/store instructions")
836
837 TEST_UNSUPPORTED(".short 0xf900,0x0000")
838 TEST_UNSUPPORTED(".short 0xf92f,0xffff")
839 TEST_UNSUPPORTED(".short 0xf980,0x0000")
840 TEST_UNSUPPORTED(".short 0xf9ef,0xffff")
841
842 TEST_GROUP("Load single data item and memory hints")
843
844#define SINGLE_LOAD(size) \
845 TEST_P( "ldr"size" r0, [r",11,-1024, ", #1024]") \
846 TEST_P( "ldr"size" r14, [r",1, -1024,", #1080]") \
847 TEST_P( "ldr"size" r0, [r",11,256, ", #-120]") \
848 TEST_P( "ldr"size" r14, [r",1, 256, ", #-128]") \
849 TEST_P( "ldr"size" r0, [r",11,24, "], #120") \
850 TEST_P( "ldr"size" r14, [r",1, 24, "], #128") \
851 TEST_P( "ldr"size" r0, [r",11,24, "], #-120") \
852 TEST_P( "ldr"size" r14, [r",1,24, "], #-128") \
853 TEST_P( "ldr"size" r0, [r",11,24, ", #120]!") \
854 TEST_P( "ldr"size" r14, [r",1, 24, ", #128]!") \
855 TEST_P( "ldr"size" r0, [r",11,256, ", #-120]!") \
856 TEST_P( "ldr"size" r14, [r",1, 256, ", #-128]!") \
857 TEST_PR("ldr"size".w r0, [r",1, 0,", r",2, 4,"]") \
858 TEST_PR("ldr"size" r14, [r",10,0,", r",11,4,", lsl #1]") \
859 TEST_X( "ldr"size".w r0, 3f", \
860 ".align 3 \n\t" \
861 "3: .word "__stringify(VAL1)) \
862 TEST_X( "ldr"size".w r14, 3f", \
863 ".align 3 \n\t" \
864 "3: .word "__stringify(VAL2)) \
865 TEST( "ldr"size".w r7, 3b") \
866 TEST( "ldr"size".w r7, [sp, #24]") \
867 TEST_P( "ldr"size".w r0, [r",0,0, "]") \
868 TEST_UNSUPPORTED("ldr"size"t r0, [r1, #4]")
869
870 SINGLE_LOAD("b")
871 SINGLE_LOAD("sb")
872 SINGLE_LOAD("h")
873 SINGLE_LOAD("sh")
874 SINGLE_LOAD("")
875
876 TEST_BF_P("ldr pc, [r",14, 15*4,"]")
877 TEST_P( "ldr sp, [r",14, 13*4,"]")
878 TEST_BF_R("ldr pc, [sp, r",14, 15*4,"]")
879 TEST_R( "ldr sp, [sp, r",14, 13*4,"]")
880 TEST_THUMB_TO_ARM_INTERWORK_P("ldr pc, [r",0,0,", #15*4]")
881 TEST_SUPPORTED("ldr sp, 99f")
882 TEST_SUPPORTED("ldr pc, 99f")
883
884 TEST_UNSUPPORTED(".short 0xf854,0x700d @ ldr r7, [r4, sp]")
885 TEST_UNSUPPORTED(".short 0xf854,0x700f @ ldr r7, [r4, pc]")
886 TEST_UNSUPPORTED(".short 0xf814,0x700d @ ldrb r7, [r4, sp]")
887 TEST_UNSUPPORTED(".short 0xf814,0x700f @ ldrb r7, [r4, pc]")
888 TEST_UNSUPPORTED(".short 0xf89f,0xd004 @ ldrb sp, 99f")
889 TEST_UNSUPPORTED(".short 0xf814,0xd008 @ ldrb sp, [r4, r8]")
890 TEST_UNSUPPORTED(".short 0xf894,0xd000 @ ldrb sp, [r4]")
891
892 TEST_UNSUPPORTED(".short 0xf860,0x0000") /* Unallocated space */
893 TEST_UNSUPPORTED(".short 0xf9ff,0xffff") /* Unallocated space */
894 TEST_UNSUPPORTED(".short 0xf950,0x0000") /* Unallocated space */
895 TEST_UNSUPPORTED(".short 0xf95f,0xffff") /* Unallocated space */
896 TEST_UNSUPPORTED(".short 0xf800,0x0800") /* Unallocated space */
897 TEST_UNSUPPORTED(".short 0xf97f,0xfaff") /* Unallocated space */
898
899 TEST( "pli [pc, #4]")
900 TEST( "pli [pc, #-4]")
901 TEST( "pld [pc, #4]")
902 TEST( "pld [pc, #-4]")
903
904 TEST_P( "pld [r",0,-1024,", #1024]")
905 TEST( ".short 0xf8b0,0xf400 @ pldw [r0, #1024]")
906 TEST_P( "pli [r",4, 0b,", #1024]")
907 TEST_P( "pld [r",7, 120,", #-120]")
908 TEST( ".short 0xf837,0xfc78 @ pldw [r7, #-120]")
909 TEST_P( "pli [r",11,120,", #-120]")
910 TEST( "pld [sp, #0]")
911
912 TEST_PR("pld [r",7, 24, ", r",0, 16,"]")
913 TEST_PR("pld [r",8, 24, ", r",12,16,", lsl #3]")
914 TEST_SUPPORTED(".short 0xf837,0xf000 @ pldw [r7, r0]")
915 TEST_SUPPORTED(".short 0xf838,0xf03c @ pldw [r8, r12, lsl #3]");
916 TEST_RR("pli [r",12,0b,", r",0, 16,"]")
917 TEST_RR("pli [r",0, 0b,", r",12,16,", lsl #3]")
918 TEST_R( "pld [sp, r",1, 16,"]")
919 TEST_UNSUPPORTED(".short 0xf817,0xf00d @pld [r7, sp]")
920 TEST_UNSUPPORTED(".short 0xf817,0xf00f @pld [r7, pc]")
921
922 TEST_GROUP("Data-processing (register)")
923
924#define SHIFTS32(op) \
925 TEST_RR(op" r0, r",1, VAL1,", r",2, 3, "") \
926 TEST_RR(op" r14, r",12,VAL2,", r",11,10,"")
927
928 SHIFTS32("lsl")
929 SHIFTS32("lsls")
930 SHIFTS32("lsr")
931 SHIFTS32("lsrs")
932 SHIFTS32("asr")
933 SHIFTS32("asrs")
934 SHIFTS32("ror")
935 SHIFTS32("rors")
936
937 TEST_UNSUPPORTED(".short 0xfa01,0xff02 @ lsl pc, r1, r2")
938 TEST_UNSUPPORTED(".short 0xfa01,0xfd02 @ lsl sp, r1, r2")
939 TEST_UNSUPPORTED(".short 0xfa0f,0xf002 @ lsl r0, pc, r2")
940 TEST_UNSUPPORTED(".short 0xfa0d,0xf002 @ lsl r0, sp, r2")
941 TEST_UNSUPPORTED(".short 0xfa01,0xf00f @ lsl r0, r1, pc")
942 TEST_UNSUPPORTED(".short 0xfa01,0xf00d @ lsl r0, r1, sp")
943
944 TEST_RR( "sxtah r0, r",0, HH1,", r",1, HH2,"")
945 TEST_RR( "sxtah r14,r",12, HH2,", r",10,HH1,", ror #8")
946 TEST_R( "sxth r8, r",7, HH1,"")
947
948 TEST_UNSUPPORTED(".short 0xfa0f,0xff87 @ sxth pc, r7");
949 TEST_UNSUPPORTED(".short 0xfa0f,0xfd87 @ sxth sp, r7");
950 TEST_UNSUPPORTED(".short 0xfa0f,0xf88f @ sxth r8, pc");
951 TEST_UNSUPPORTED(".short 0xfa0f,0xf88d @ sxth r8, sp");
952
953 TEST_RR( "uxtah r0, r",0, HH1,", r",1, HH2,"")
954 TEST_RR( "uxtah r14,r",12, HH2,", r",10,HH1,", ror #8")
955 TEST_R( "uxth r8, r",7, HH1,"")
956
957 TEST_RR( "sxtab16 r0, r",0, HH1,", r",1, HH2,"")
958 TEST_RR( "sxtab16 r14,r",12, HH2,", r",10,HH1,", ror #8")
959 TEST_R( "sxtb16 r8, r",7, HH1,"")
960
961 TEST_RR( "uxtab16 r0, r",0, HH1,", r",1, HH2,"")
962 TEST_RR( "uxtab16 r14,r",12, HH2,", r",10,HH1,", ror #8")
963 TEST_R( "uxtb16 r8, r",7, HH1,"")
964
965 TEST_RR( "sxtab r0, r",0, HH1,", r",1, HH2,"")
966 TEST_RR( "sxtab r14,r",12, HH2,", r",10,HH1,", ror #8")
967 TEST_R( "sxtb r8, r",7, HH1,"")
968
969 TEST_RR( "uxtab r0, r",0, HH1,", r",1, HH2,"")
970 TEST_RR( "uxtab r14,r",12, HH2,", r",10,HH1,", ror #8")
971 TEST_R( "uxtb r8, r",7, HH1,"")
972
973 TEST_UNSUPPORTED(".short 0xfa60,0x00f0")
974 TEST_UNSUPPORTED(".short 0xfa7f,0xffff")
975
976#define PARALLEL_ADD_SUB(op) \
977 TEST_RR( op"add16 r0, r",0, HH1,", r",1, HH2,"") \
978 TEST_RR( op"add16 r14, r",12,HH2,", r",10,HH1,"") \
979 TEST_RR( op"asx r0, r",0, HH1,", r",1, HH2,"") \
980 TEST_RR( op"asx r14, r",12,HH2,", r",10,HH1,"") \
981 TEST_RR( op"sax r0, r",0, HH1,", r",1, HH2,"") \
982 TEST_RR( op"sax r14, r",12,HH2,", r",10,HH1,"") \
983 TEST_RR( op"sub16 r0, r",0, HH1,", r",1, HH2,"") \
984 TEST_RR( op"sub16 r14, r",12,HH2,", r",10,HH1,"") \
985 TEST_RR( op"add8 r0, r",0, HH1,", r",1, HH2,"") \
986 TEST_RR( op"add8 r14, r",12,HH2,", r",10,HH1,"") \
987 TEST_RR( op"sub8 r0, r",0, HH1,", r",1, HH2,"") \
988 TEST_RR( op"sub8 r14, r",12,HH2,", r",10,HH1,"")
989
990 TEST_GROUP("Parallel addition and subtraction, signed")
991
992 PARALLEL_ADD_SUB("s")
993 PARALLEL_ADD_SUB("q")
994 PARALLEL_ADD_SUB("sh")
995
996 TEST_GROUP("Parallel addition and subtraction, unsigned")
997
998 PARALLEL_ADD_SUB("u")
999 PARALLEL_ADD_SUB("uq")
1000 PARALLEL_ADD_SUB("uh")
1001
1002 TEST_GROUP("Miscellaneous operations")
1003
1004 TEST_RR("qadd r0, r",1, VAL1,", r",2, VAL2,"")
1005 TEST_RR("qadd lr, r",9, VAL2,", r",8, VAL1,"")
1006 TEST_RR("qsub r0, r",1, VAL1,", r",2, VAL2,"")
1007 TEST_RR("qsub lr, r",9, VAL2,", r",8, VAL1,"")
1008 TEST_RR("qdadd r0, r",1, VAL1,", r",2, VAL2,"")
1009 TEST_RR("qdadd lr, r",9, VAL2,", r",8, VAL1,"")
1010 TEST_RR("qdsub r0, r",1, VAL1,", r",2, VAL2,"")
1011 TEST_RR("qdsub lr, r",9, VAL2,", r",8, VAL1,"")
1012
1013 TEST_R("rev.w r0, r",0, VAL1,"")
1014 TEST_R("rev r14, r",12, VAL2,"")
1015 TEST_R("rev16.w r0, r",0, VAL1,"")
1016 TEST_R("rev16 r14, r",12, VAL2,"")
1017 TEST_R("rbit r0, r",0, VAL1,"")
1018 TEST_R("rbit r14, r",12, VAL2,"")
1019 TEST_R("revsh.w r0, r",0, VAL1,"")
1020 TEST_R("revsh r14, r",12, VAL2,"")
1021
1022 TEST_UNSUPPORTED(".short 0xfa9c,0xff8c @ rev pc, r12");
1023 TEST_UNSUPPORTED(".short 0xfa9c,0xfd8c @ rev sp, r12");
1024 TEST_UNSUPPORTED(".short 0xfa9f,0xfe8f @ rev r14, pc");
1025 TEST_UNSUPPORTED(".short 0xfa9d,0xfe8d @ rev r14, sp");
1026
1027 TEST_RR("sel r0, r",0, VAL1,", r",1, VAL2,"")
1028 TEST_RR("sel r14, r",12,VAL1,", r",10, VAL2,"")
1029
1030 TEST_R("clz r0, r",0, 0x0,"")
1031 TEST_R("clz r7, r",14,0x1,"")
1032 TEST_R("clz lr, r",7, 0xffffffff,"")
1033
1034 TEST_UNSUPPORTED(".short 0xfa80,0xf030") /* Unallocated space */
1035 TEST_UNSUPPORTED(".short 0xfaff,0xff7f") /* Unallocated space */
1036 TEST_UNSUPPORTED(".short 0xfab0,0xf000") /* Unallocated space */
1037 TEST_UNSUPPORTED(".short 0xfaff,0xff7f") /* Unallocated space */
1038
1039 TEST_GROUP("Multiply, multiply accumulate, and absolute difference operations")
1040
1041 TEST_RR( "mul r0, r",1, VAL1,", r",2, VAL2,"")
1042 TEST_RR( "mul r7, r",8, VAL2,", r",9, VAL2,"")
1043 TEST_UNSUPPORTED(".short 0xfb08,0xff09 @ mul pc, r8, r9")
1044 TEST_UNSUPPORTED(".short 0xfb08,0xfd09 @ mul sp, r8, r9")
1045 TEST_UNSUPPORTED(".short 0xfb0f,0xf709 @ mul r7, pc, r9")
1046 TEST_UNSUPPORTED(".short 0xfb0d,0xf709 @ mul r7, sp, r9")
1047 TEST_UNSUPPORTED(".short 0xfb08,0xf70f @ mul r7, r8, pc")
1048 TEST_UNSUPPORTED(".short 0xfb08,0xf70d @ mul r7, r8, sp")
1049
1050 TEST_RRR( "mla r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
1051 TEST_RRR( "mla r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
1052 TEST_UNSUPPORTED(".short 0xfb08,0xaf09 @ mla pc, r8, r9, r10");
1053 TEST_UNSUPPORTED(".short 0xfb08,0xad09 @ mla sp, r8, r9, r10");
1054 TEST_UNSUPPORTED(".short 0xfb0f,0xa709 @ mla r7, pc, r9, r10");
1055 TEST_UNSUPPORTED(".short 0xfb0d,0xa709 @ mla r7, sp, r9, r10");
1056 TEST_UNSUPPORTED(".short 0xfb08,0xa70f @ mla r7, r8, pc, r10");
1057 TEST_UNSUPPORTED(".short 0xfb08,0xa70d @ mla r7, r8, sp, r10");
1058 TEST_UNSUPPORTED(".short 0xfb08,0xd709 @ mla r7, r8, r9, sp");
1059
1060 TEST_RRR( "mls r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
1061 TEST_RRR( "mls r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
1062
1063 TEST_RRR( "smlabb r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
1064 TEST_RRR( "smlabb r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
1065 TEST_RRR( "smlatb r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
1066 TEST_RRR( "smlatb r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
1067 TEST_RRR( "smlabt r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
1068 TEST_RRR( "smlabt r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
1069 TEST_RRR( "smlatt r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
1070 TEST_RRR( "smlatt r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
1071 TEST_RR( "smulbb r0, r",1, VAL1,", r",2, VAL2,"")
1072 TEST_RR( "smulbb r7, r",8, VAL3,", r",9, VAL1,"")
1073 TEST_RR( "smultb r0, r",1, VAL1,", r",2, VAL2,"")
1074 TEST_RR( "smultb r7, r",8, VAL3,", r",9, VAL1,"")
1075 TEST_RR( "smulbt r0, r",1, VAL1,", r",2, VAL2,"")
1076 TEST_RR( "smulbt r7, r",8, VAL3,", r",9, VAL1,"")
1077 TEST_RR( "smultt r0, r",1, VAL1,", r",2, VAL2,"")
1078 TEST_RR( "smultt r7, r",8, VAL3,", r",9, VAL1,"")
1079
1080 TEST_RRR( "smlad r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"")
1081 TEST_RRR( "smlad r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
1082 TEST_RRR( "smladx r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"")
1083 TEST_RRR( "smladx r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
1084 TEST_RR( "smuad r0, r",0, HH1,", r",1, HH2,"")
1085 TEST_RR( "smuad r14, r",12,HH2,", r",10,HH1,"")
1086 TEST_RR( "smuadx r0, r",0, HH1,", r",1, HH2,"")
1087 TEST_RR( "smuadx r14, r",12,HH2,", r",10,HH1,"")
1088
1089 TEST_RRR( "smlawb r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
1090 TEST_RRR( "smlawb r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
1091 TEST_RRR( "smlawt r0, r",1, VAL1,", r",2, VAL2,", r",3, VAL3,"")
1092 TEST_RRR( "smlawt r7, r",8, VAL3,", r",9, VAL1,", r",10, VAL2,"")
1093 TEST_RR( "smulwb r0, r",1, VAL1,", r",2, VAL2,"")
1094 TEST_RR( "smulwb r7, r",8, VAL3,", r",9, VAL1,"")
1095 TEST_RR( "smulwt r0, r",1, VAL1,", r",2, VAL2,"")
1096 TEST_RR( "smulwt r7, r",8, VAL3,", r",9, VAL1,"")
1097
1098 TEST_RRR( "smlsd r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"")
1099 TEST_RRR( "smlsd r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
1100 TEST_RRR( "smlsdx r0, r",0, HH1,", r",1, HH2,", r",2, VAL1,"")
1101 TEST_RRR( "smlsdx r14, r",12,HH2,", r",10,HH1,", r",8, VAL2,"")
1102 TEST_RR( "smusd r0, r",0, HH1,", r",1, HH2,"")
1103 TEST_RR( "smusd r14, r",12,HH2,", r",10,HH1,"")
1104 TEST_RR( "smusdx r0, r",0, HH1,", r",1, HH2,"")
1105 TEST_RR( "smusdx r14, r",12,HH2,", r",10,HH1,"")
1106
1107 TEST_RRR( "smmla r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"")
1108 TEST_RRR( "smmla r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
1109 TEST_RRR( "smmlar r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"")
1110 TEST_RRR( "smmlar r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
1111 TEST_RR( "smmul r0, r",0, VAL1,", r",1, VAL2,"")
1112 TEST_RR( "smmul r14, r",12,VAL2,", r",10,VAL1,"")
1113 TEST_RR( "smmulr r0, r",0, VAL1,", r",1, VAL2,"")
1114 TEST_RR( "smmulr r14, r",12,VAL2,", r",10,VAL1,"")
1115
1116 TEST_RRR( "smmls r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"")
1117 TEST_RRR( "smmls r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
1118 TEST_RRR( "smmlsr r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL1,"")
1119 TEST_RRR( "smmlsr r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL2,"")
1120
1121 TEST_RRR( "usada8 r0, r",0, VAL1,", r",1, VAL2,", r",2, VAL3,"")
1122 TEST_RRR( "usada8 r14, r",12,VAL2,", r",10,VAL1,", r",8, VAL3,"")
1123 TEST_RR( "usad8 r0, r",0, VAL1,", r",1, VAL2,"")
1124 TEST_RR( "usad8 r14, r",12,VAL2,", r",10,VAL1,"")
1125
1126 TEST_UNSUPPORTED(".short 0xfb00,0xf010") /* Unallocated space */
1127 TEST_UNSUPPORTED(".short 0xfb0f,0xff1f") /* Unallocated space */
1128 TEST_UNSUPPORTED(".short 0xfb70,0xf010") /* Unallocated space */
1129 TEST_UNSUPPORTED(".short 0xfb7f,0xff1f") /* Unallocated space */
1130 TEST_UNSUPPORTED(".short 0xfb70,0x0010") /* Unallocated space */
1131 TEST_UNSUPPORTED(".short 0xfb7f,0xff1f") /* Unallocated space */
1132
1133 TEST_GROUP("Long multiply, long multiply accumulate, and divide")
1134
1135 TEST_RR( "smull r0, r1, r",2, VAL1,", r",3, VAL2,"")
1136 TEST_RR( "smull r7, r8, r",9, VAL2,", r",10, VAL1,"")
1137 TEST_UNSUPPORTED(".short 0xfb89,0xf80a @ smull pc, r8, r9, r10");
1138 TEST_UNSUPPORTED(".short 0xfb89,0xd80a @ smull sp, r8, r9, r10");
1139 TEST_UNSUPPORTED(".short 0xfb89,0x7f0a @ smull r7, pc, r9, r10");
1140 TEST_UNSUPPORTED(".short 0xfb89,0x7d0a @ smull r7, sp, r9, r10");
1141 TEST_UNSUPPORTED(".short 0xfb8f,0x780a @ smull r7, r8, pc, r10");
1142 TEST_UNSUPPORTED(".short 0xfb8d,0x780a @ smull r7, r8, sp, r10");
1143 TEST_UNSUPPORTED(".short 0xfb89,0x780f @ smull r7, r8, r9, pc");
1144 TEST_UNSUPPORTED(".short 0xfb89,0x780d @ smull r7, r8, r9, sp");
1145
1146 TEST_RR( "umull r0, r1, r",2, VAL1,", r",3, VAL2,"")
1147 TEST_RR( "umull r7, r8, r",9, VAL2,", r",10, VAL1,"")
1148
1149 TEST_RRRR( "smlal r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
1150 TEST_RRRR( "smlal r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
1151
1152 TEST_RRRR( "smlalbb r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
1153 TEST_RRRR( "smlalbb r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
1154 TEST_RRRR( "smlalbt r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
1155 TEST_RRRR( "smlalbt r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
1156 TEST_RRRR( "smlaltb r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
1157 TEST_RRRR( "smlaltb r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
1158 TEST_RRRR( "smlaltt r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
1159 TEST_RRRR( "smlaltt r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
1160
1161 TEST_RRRR( "smlald r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
1162 TEST_RRRR( "smlald r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
1163 TEST_RRRR( "smlaldx r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
1164 TEST_RRRR( "smlaldx r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
1165
1166 TEST_RRRR( "smlsld r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
1167 TEST_RRRR( "smlsld r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
1168 TEST_RRRR( "smlsldx r",0, VAL1,", r",1, VAL2, ", r",0, HH1,", r",1, HH2)
1169 TEST_RRRR( "smlsldx r",11,VAL2,", r",10,VAL1, ", r",9, HH2,", r",8, HH1)
1170
1171 TEST_RRRR( "umlal r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
1172 TEST_RRRR( "umlal r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
1173 TEST_RRRR( "umaal r",0, VAL1,", r",1, VAL2,", r",2, VAL3,", r",3, VAL4)
1174 TEST_RRRR( "umaal r",8, VAL4,", r",9, VAL1,", r",10,VAL2,", r",11,VAL3)
1175
1176 TEST_GROUP("Coprocessor instructions")
1177
1178 TEST_UNSUPPORTED(".short 0xfc00,0x0000")
1179 TEST_UNSUPPORTED(".short 0xffff,0xffff")
1180
1181 TEST_GROUP("Testing instructions in IT blocks")
1182
1183 TEST_ITBLOCK("sub.w r0, r0")
1184
1185 verbose("\n");
1186}
1187
diff --git a/arch/arm/kernel/kprobes-test.c b/arch/arm/kernel/kprobes-test.c
new file mode 100644
index 000000000000..e17cdd6d90d8
--- /dev/null
+++ b/arch/arm/kernel/kprobes-test.c
@@ -0,0 +1,1748 @@
1/*
2 * arch/arm/kernel/kprobes-test.c
3 *
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/*
12 * This file contains test code for ARM kprobes.
13 *
14 * The top level function run_all_tests() executes tests for all of the
15 * supported instruction sets: ARM, 16-bit Thumb, and 32-bit Thumb. These tests
16 * fall into two categories; run_api_tests() checks basic functionality of the
17 * kprobes API, and run_test_cases() is a comprehensive test for kprobes
18 * instruction decoding and simulation.
19 *
20 * run_test_cases() first checks the kprobes decoding table for self consistency
21 * (using table_test()) then executes a series of test cases for each of the CPU
22 * instruction forms. coverage_start() and coverage_end() are used to verify
23 * that these test cases cover all of the possible combinations of instructions
24 * described by the kprobes decoding tables.
25 *
26 * The individual test cases are in kprobes-test-arm.c and kprobes-test-thumb.c
27 * which use the macros defined in kprobes-test.h. The rest of this
28 * documentation will describe the operation of the framework used by these
29 * test cases.
30 */
31
32/*
33 * TESTING METHODOLOGY
34 * -------------------
35 *
36 * The methodology used to test an ARM instruction 'test_insn' is to use
37 * inline assembler like:
38 *
39 * test_before: nop
40 * test_case: test_insn
41 * test_after: nop
42 *
43 * When the test case is run a kprobe is placed of each nop. The
44 * post-handler of the test_before probe is used to modify the saved CPU
45 * register context to that which we require for the test case. The
46 * pre-handler of the of the test_after probe saves a copy of the CPU
47 * register context. In this way we can execute test_insn with a specific
48 * register context and see the results afterwards.
49 *
50 * To actually test the kprobes instruction emulation we perform the above
51 * step a second time but with an additional kprobe on the test_case
52 * instruction itself. If the emulation is accurate then the results seen
53 * by the test_after probe will be identical to the first run which didn't
54 * have a probe on test_case.
55 *
56 * Each test case is run several times with a variety of variations in the
57 * flags value of stored in CPSR, and for Thumb code, different ITState.
58 *
59 * For instructions which can modify PC, a second test_after probe is used
60 * like this:
61 *
62 * test_before: nop
63 * test_case: test_insn
64 * test_after: nop
65 * b test_done
66 * test_after2: nop
67 * test_done:
68 *
69 * The test case is constructed such that test_insn branches to
70 * test_after2, or, if testing a conditional instruction, it may just
71 * continue to test_after. The probes inserted at both locations let us
72 * determine which happened. A similar approach is used for testing
73 * backwards branches...
74 *
75 * b test_before
76 * b test_done @ helps to cope with off by 1 branches
77 * test_after2: nop
78 * b test_done
79 * test_before: nop
80 * test_case: test_insn
81 * test_after: nop
82 * test_done:
83 *
84 * The macros used to generate the assembler instructions describe above
85 * are TEST_INSTRUCTION, TEST_BRANCH_F (branch forwards) and TEST_BRANCH_B
86 * (branch backwards). In these, the local variables numbered 1, 50, 2 and
87 * 99 represent: test_before, test_case, test_after2 and test_done.
88 *
89 * FRAMEWORK
90 * ---------
91 *
92 * Each test case is wrapped between the pair of macros TESTCASE_START and
93 * TESTCASE_END. As well as performing the inline assembler boilerplate,
94 * these call out to the kprobes_test_case_start() and
95 * kprobes_test_case_end() functions which drive the execution of the test
96 * case. The specific arguments to use for each test case are stored as
97 * inline data constructed using the various TEST_ARG_* macros. Putting
98 * this all together, a simple test case may look like:
99 *
100 * TESTCASE_START("Testing mov r0, r7")
101 * TEST_ARG_REG(7, 0x12345678) // Set r7=0x12345678
102 * TEST_ARG_END("")
103 * TEST_INSTRUCTION("mov r0, r7")
104 * TESTCASE_END
105 *
106 * Note, in practice the single convenience macro TEST_R would be used for this
107 * instead.
108 *
109 * The above would expand to assembler looking something like:
110 *
111 * @ TESTCASE_START
112 * bl __kprobes_test_case_start
113 * @ start of inline data...
114 * .ascii "mov r0, r7" @ text title for test case
115 * .byte 0
116 * .align 2
117 *
118 * @ TEST_ARG_REG
119 * .byte ARG_TYPE_REG
120 * .byte 7
121 * .short 0
122 * .word 0x1234567
123 *
124 * @ TEST_ARG_END
125 * .byte ARG_TYPE_END
126 * .byte TEST_ISA @ flags, including ISA being tested
127 * .short 50f-0f @ offset of 'test_before'
128 * .short 2f-0f @ offset of 'test_after2' (if relevent)
129 * .short 99f-0f @ offset of 'test_done'
130 * @ start of test case code...
131 * 0:
132 * .code TEST_ISA @ switch to ISA being tested
133 *
134 * @ TEST_INSTRUCTION
135 * 50: nop @ location for 'test_before' probe
136 * 1: mov r0, r7 @ the test case instruction 'test_insn'
137 * nop @ location for 'test_after' probe
138 *
139 * // TESTCASE_END
140 * 2:
141 * 99: bl __kprobes_test_case_end_##TEST_ISA
142 * .code NONMAL_ISA
143 *
144 * When the above is execute the following happens...
145 *
146 * __kprobes_test_case_start() is an assembler wrapper which sets up space
147 * for a stack buffer and calls the C function kprobes_test_case_start().
148 * This C function will do some initial processing of the inline data and
149 * setup some global state. It then inserts the test_before and test_after
150 * kprobes and returns a value which causes the assembler wrapper to jump
151 * to the start of the test case code, (local label '0').
152 *
153 * When the test case code executes, the test_before probe will be hit and
154 * test_before_post_handler will call setup_test_context(). This fills the
155 * stack buffer and CPU registers with a test pattern and then processes
156 * the test case arguments. In our example there is one TEST_ARG_REG which
157 * indicates that R7 should be loaded with the value 0x12345678.
158 *
159 * When the test_before probe ends, the test case continues and executes
160 * the "mov r0, r7" instruction. It then hits the test_after probe and the
161 * pre-handler for this (test_after_pre_handler) will save a copy of the
162 * CPU register context. This should now have R0 holding the same value as
163 * R7.
164 *
165 * Finally we get to the call to __kprobes_test_case_end_{32,16}. This is
166 * an assembler wrapper which switches back to the ISA used by the test
167 * code and calls the C function kprobes_test_case_end().
168 *
169 * For each run through the test case, test_case_run_count is incremented
170 * by one. For even runs, kprobes_test_case_end() saves a copy of the
171 * register and stack buffer contents from the test case just run. It then
172 * inserts a kprobe on the test case instruction 'test_insn' and returns a
173 * value to cause the test case code to be re-run.
174 *
175 * For odd numbered runs, kprobes_test_case_end() compares the register and
176 * stack buffer contents to those that were saved on the previous even
177 * numbered run (the one without the kprobe on test_insn). These should be
178 * the same if the kprobe instruction simulation routine is correct.
179 *
180 * The pair of test case runs is repeated with different combinations of
181 * flag values in CPSR and, for Thumb, different ITState. This is
182 * controlled by test_context_cpsr().
183 *
184 * BUILDING TEST CASES
185 * -------------------
186 *
187 *
188 * As an aid to building test cases, the stack buffer is initialised with
189 * some special values:
190 *
191 * [SP+13*4] Contains SP+120. This can be used to test instructions
192 * which load a value into SP.
193 *
194 * [SP+15*4] When testing branching instructions using TEST_BRANCH_{F,B},
195 * this holds the target address of the branch, 'test_after2'.
196 * This can be used to test instructions which load a PC value
197 * from memory.
198 */
199
200#include <linux/kernel.h>
201#include <linux/module.h>
202#include <linux/slab.h>
203#include <linux/kprobes.h>
204
205#include "kprobes.h"
206#include "kprobes-test.h"
207
208
209#define BENCHMARKING 1
210
211
212/*
213 * Test basic API
214 */
215
216static bool test_regs_ok;
217static int test_func_instance;
218static int pre_handler_called;
219static int post_handler_called;
220static int jprobe_func_called;
221static int kretprobe_handler_called;
222
223#define FUNC_ARG1 0x12345678
224#define FUNC_ARG2 0xabcdef
225
226
227#ifndef CONFIG_THUMB2_KERNEL
228
229long arm_func(long r0, long r1);
230
231static void __used __naked __arm_kprobes_test_func(void)
232{
233 __asm__ __volatile__ (
234 ".arm \n\t"
235 ".type arm_func, %%function \n\t"
236 "arm_func: \n\t"
237 "adds r0, r0, r1 \n\t"
238 "bx lr \n\t"
239 ".code "NORMAL_ISA /* Back to Thumb if necessary */
240 : : : "r0", "r1", "cc"
241 );
242}
243
244#else /* CONFIG_THUMB2_KERNEL */
245
246long thumb16_func(long r0, long r1);
247long thumb32even_func(long r0, long r1);
248long thumb32odd_func(long r0, long r1);
249
250static void __used __naked __thumb_kprobes_test_funcs(void)
251{
252 __asm__ __volatile__ (
253 ".type thumb16_func, %%function \n\t"
254 "thumb16_func: \n\t"
255 "adds.n r0, r0, r1 \n\t"
256 "bx lr \n\t"
257
258 ".align \n\t"
259 ".type thumb32even_func, %%function \n\t"
260 "thumb32even_func: \n\t"
261 "adds.w r0, r0, r1 \n\t"
262 "bx lr \n\t"
263
264 ".align \n\t"
265 "nop.n \n\t"
266 ".type thumb32odd_func, %%function \n\t"
267 "thumb32odd_func: \n\t"
268 "adds.w r0, r0, r1 \n\t"
269 "bx lr \n\t"
270
271 : : : "r0", "r1", "cc"
272 );
273}
274
275#endif /* CONFIG_THUMB2_KERNEL */
276
277
278static int call_test_func(long (*func)(long, long), bool check_test_regs)
279{
280 long ret;
281
282 ++test_func_instance;
283 test_regs_ok = false;
284
285 ret = (*func)(FUNC_ARG1, FUNC_ARG2);
286 if (ret != FUNC_ARG1 + FUNC_ARG2) {
287 pr_err("FAIL: call_test_func: func returned %lx\n", ret);
288 return false;
289 }
290
291 if (check_test_regs && !test_regs_ok) {
292 pr_err("FAIL: test regs not OK\n");
293 return false;
294 }
295
296 return true;
297}
298
299static int __kprobes pre_handler(struct kprobe *p, struct pt_regs *regs)
300{
301 pre_handler_called = test_func_instance;
302 if (regs->ARM_r0 == FUNC_ARG1 && regs->ARM_r1 == FUNC_ARG2)
303 test_regs_ok = true;
304 return 0;
305}
306
307static void __kprobes post_handler(struct kprobe *p, struct pt_regs *regs,
308 unsigned long flags)
309{
310 post_handler_called = test_func_instance;
311 if (regs->ARM_r0 != FUNC_ARG1 + FUNC_ARG2 || regs->ARM_r1 != FUNC_ARG2)
312 test_regs_ok = false;
313}
314
315static struct kprobe the_kprobe = {
316 .addr = 0,
317 .pre_handler = pre_handler,
318 .post_handler = post_handler
319};
320
321static int test_kprobe(long (*func)(long, long))
322{
323 int ret;
324
325 the_kprobe.addr = (kprobe_opcode_t *)func;
326 ret = register_kprobe(&the_kprobe);
327 if (ret < 0) {
328 pr_err("FAIL: register_kprobe failed with %d\n", ret);
329 return ret;
330 }
331
332 ret = call_test_func(func, true);
333
334 unregister_kprobe(&the_kprobe);
335 the_kprobe.flags = 0; /* Clear disable flag to allow reuse */
336
337 if (!ret)
338 return -EINVAL;
339 if (pre_handler_called != test_func_instance) {
340 pr_err("FAIL: kprobe pre_handler not called\n");
341 return -EINVAL;
342 }
343 if (post_handler_called != test_func_instance) {
344 pr_err("FAIL: kprobe post_handler not called\n");
345 return -EINVAL;
346 }
347 if (!call_test_func(func, false))
348 return -EINVAL;
349 if (pre_handler_called == test_func_instance ||
350 post_handler_called == test_func_instance) {
351 pr_err("FAIL: probe called after unregistering\n");
352 return -EINVAL;
353 }
354
355 return 0;
356}
357
358static void __kprobes jprobe_func(long r0, long r1)
359{
360 jprobe_func_called = test_func_instance;
361 if (r0 == FUNC_ARG1 && r1 == FUNC_ARG2)
362 test_regs_ok = true;
363 jprobe_return();
364}
365
366static struct jprobe the_jprobe = {
367 .entry = jprobe_func,
368};
369
370static int test_jprobe(long (*func)(long, long))
371{
372 int ret;
373
374 the_jprobe.kp.addr = (kprobe_opcode_t *)func;
375 ret = register_jprobe(&the_jprobe);
376 if (ret < 0) {
377 pr_err("FAIL: register_jprobe failed with %d\n", ret);
378 return ret;
379 }
380
381 ret = call_test_func(func, true);
382
383 unregister_jprobe(&the_jprobe);
384 the_jprobe.kp.flags = 0; /* Clear disable flag to allow reuse */
385
386 if (!ret)
387 return -EINVAL;
388 if (jprobe_func_called != test_func_instance) {
389 pr_err("FAIL: jprobe handler function not called\n");
390 return -EINVAL;
391 }
392 if (!call_test_func(func, false))
393 return -EINVAL;
394 if (jprobe_func_called == test_func_instance) {
395 pr_err("FAIL: probe called after unregistering\n");
396 return -EINVAL;
397 }
398
399 return 0;
400}
401
402static int __kprobes
403kretprobe_handler(struct kretprobe_instance *ri, struct pt_regs *regs)
404{
405 kretprobe_handler_called = test_func_instance;
406 if (regs_return_value(regs) == FUNC_ARG1 + FUNC_ARG2)
407 test_regs_ok = true;
408 return 0;
409}
410
411static struct kretprobe the_kretprobe = {
412 .handler = kretprobe_handler,
413};
414
415static int test_kretprobe(long (*func)(long, long))
416{
417 int ret;
418
419 the_kretprobe.kp.addr = (kprobe_opcode_t *)func;
420 ret = register_kretprobe(&the_kretprobe);
421 if (ret < 0) {
422 pr_err("FAIL: register_kretprobe failed with %d\n", ret);
423 return ret;
424 }
425
426 ret = call_test_func(func, true);
427
428 unregister_kretprobe(&the_kretprobe);
429 the_kretprobe.kp.flags = 0; /* Clear disable flag to allow reuse */
430
431 if (!ret)
432 return -EINVAL;
433 if (kretprobe_handler_called != test_func_instance) {
434 pr_err("FAIL: kretprobe handler not called\n");
435 return -EINVAL;
436 }
437 if (!call_test_func(func, false))
438 return -EINVAL;
439 if (jprobe_func_called == test_func_instance) {
440 pr_err("FAIL: kretprobe called after unregistering\n");
441 return -EINVAL;
442 }
443
444 return 0;
445}
446
447static int run_api_tests(long (*func)(long, long))
448{
449 int ret;
450
451 pr_info(" kprobe\n");
452 ret = test_kprobe(func);
453 if (ret < 0)
454 return ret;
455
456 pr_info(" jprobe\n");
457 ret = test_jprobe(func);
458 if (ret < 0)
459 return ret;
460
461 pr_info(" kretprobe\n");
462 ret = test_kretprobe(func);
463 if (ret < 0)
464 return ret;
465
466 return 0;
467}
468
469
470/*
471 * Benchmarking
472 */
473
474#if BENCHMARKING
475
476static void __naked benchmark_nop(void)
477{
478 __asm__ __volatile__ (
479 "nop \n\t"
480 "bx lr"
481 );
482}
483
484#ifdef CONFIG_THUMB2_KERNEL
485#define wide ".w"
486#else
487#define wide
488#endif
489
490static void __naked benchmark_pushpop1(void)
491{
492 __asm__ __volatile__ (
493 "stmdb"wide" sp!, {r3-r11,lr} \n\t"
494 "ldmia"wide" sp!, {r3-r11,pc}"
495 );
496}
497
498static void __naked benchmark_pushpop2(void)
499{
500 __asm__ __volatile__ (
501 "stmdb"wide" sp!, {r0-r8,lr} \n\t"
502 "ldmia"wide" sp!, {r0-r8,pc}"
503 );
504}
505
506static void __naked benchmark_pushpop3(void)
507{
508 __asm__ __volatile__ (
509 "stmdb"wide" sp!, {r4,lr} \n\t"
510 "ldmia"wide" sp!, {r4,pc}"
511 );
512}
513
514static void __naked benchmark_pushpop4(void)
515{
516 __asm__ __volatile__ (
517 "stmdb"wide" sp!, {r0,lr} \n\t"
518 "ldmia"wide" sp!, {r0,pc}"
519 );
520}
521
522
523#ifdef CONFIG_THUMB2_KERNEL
524
525static void __naked benchmark_pushpop_thumb(void)
526{
527 __asm__ __volatile__ (
528 "push.n {r0-r7,lr} \n\t"
529 "pop.n {r0-r7,pc}"
530 );
531}
532
533#endif
534
535static int __kprobes
536benchmark_pre_handler(struct kprobe *p, struct pt_regs *regs)
537{
538 return 0;
539}
540
541static int benchmark(void(*fn)(void))
542{
543 unsigned n, i, t, t0;
544
545 for (n = 1000; ; n *= 2) {
546 t0 = sched_clock();
547 for (i = n; i > 0; --i)
548 fn();
549 t = sched_clock() - t0;
550 if (t >= 250000000)
551 break; /* Stop once we took more than 0.25 seconds */
552 }
553 return t / n; /* Time for one iteration in nanoseconds */
554};
555
556static int kprobe_benchmark(void(*fn)(void), unsigned offset)
557{
558 struct kprobe k = {
559 .addr = (kprobe_opcode_t *)((uintptr_t)fn + offset),
560 .pre_handler = benchmark_pre_handler,
561 };
562
563 int ret = register_kprobe(&k);
564 if (ret < 0) {
565 pr_err("FAIL: register_kprobe failed with %d\n", ret);
566 return ret;
567 }
568
569 ret = benchmark(fn);
570
571 unregister_kprobe(&k);
572 return ret;
573};
574
575struct benchmarks {
576 void (*fn)(void);
577 unsigned offset;
578 const char *title;
579};
580
581static int run_benchmarks(void)
582{
583 int ret;
584 struct benchmarks list[] = {
585 {&benchmark_nop, 0, "nop"},
586 /*
587 * benchmark_pushpop{1,3} will have the optimised
588 * instruction emulation, whilst benchmark_pushpop{2,4} will
589 * be the equivalent unoptimised instructions.
590 */
591 {&benchmark_pushpop1, 0, "stmdb sp!, {r3-r11,lr}"},
592 {&benchmark_pushpop1, 4, "ldmia sp!, {r3-r11,pc}"},
593 {&benchmark_pushpop2, 0, "stmdb sp!, {r0-r8,lr}"},
594 {&benchmark_pushpop2, 4, "ldmia sp!, {r0-r8,pc}"},
595 {&benchmark_pushpop3, 0, "stmdb sp!, {r4,lr}"},
596 {&benchmark_pushpop3, 4, "ldmia sp!, {r4,pc}"},
597 {&benchmark_pushpop4, 0, "stmdb sp!, {r0,lr}"},
598 {&benchmark_pushpop4, 4, "ldmia sp!, {r0,pc}"},
599#ifdef CONFIG_THUMB2_KERNEL
600 {&benchmark_pushpop_thumb, 0, "push.n {r0-r7,lr}"},
601 {&benchmark_pushpop_thumb, 2, "pop.n {r0-r7,pc}"},
602#endif
603 {0}
604 };
605
606 struct benchmarks *b;
607 for (b = list; b->fn; ++b) {
608 ret = kprobe_benchmark(b->fn, b->offset);
609 if (ret < 0)
610 return ret;
611 pr_info(" %dns for kprobe %s\n", ret, b->title);
612 }
613
614 pr_info("\n");
615 return 0;
616}
617
618#endif /* BENCHMARKING */
619
620
621/*
622 * Decoding table self-consistency tests
623 */
624
625static const int decode_struct_sizes[NUM_DECODE_TYPES] = {
626 [DECODE_TYPE_TABLE] = sizeof(struct decode_table),
627 [DECODE_TYPE_CUSTOM] = sizeof(struct decode_custom),
628 [DECODE_TYPE_SIMULATE] = sizeof(struct decode_simulate),
629 [DECODE_TYPE_EMULATE] = sizeof(struct decode_emulate),
630 [DECODE_TYPE_OR] = sizeof(struct decode_or),
631 [DECODE_TYPE_REJECT] = sizeof(struct decode_reject)
632};
633
634static int table_iter(const union decode_item *table,
635 int (*fn)(const struct decode_header *, void *),
636 void *args)
637{
638 const struct decode_header *h = (struct decode_header *)table;
639 int result;
640
641 for (;;) {
642 enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
643
644 if (type == DECODE_TYPE_END)
645 return 0;
646
647 result = fn(h, args);
648 if (result)
649 return result;
650
651 h = (struct decode_header *)
652 ((uintptr_t)h + decode_struct_sizes[type]);
653
654 }
655}
656
657static int table_test_fail(const struct decode_header *h, const char* message)
658{
659
660 pr_err("FAIL: kprobes test failure \"%s\" (mask %08x, value %08x)\n",
661 message, h->mask.bits, h->value.bits);
662 return -EINVAL;
663}
664
665struct table_test_args {
666 const union decode_item *root_table;
667 u32 parent_mask;
668 u32 parent_value;
669};
670
671static int table_test_fn(const struct decode_header *h, void *args)
672{
673 struct table_test_args *a = (struct table_test_args *)args;
674 enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
675
676 if (h->value.bits & ~h->mask.bits)
677 return table_test_fail(h, "Match value has bits not in mask");
678
679 if ((h->mask.bits & a->parent_mask) != a->parent_mask)
680 return table_test_fail(h, "Mask has bits not in parent mask");
681
682 if ((h->value.bits ^ a->parent_value) & a->parent_mask)
683 return table_test_fail(h, "Value is inconsistent with parent");
684
685 if (type == DECODE_TYPE_TABLE) {
686 struct decode_table *d = (struct decode_table *)h;
687 struct table_test_args args2 = *a;
688 args2.parent_mask = h->mask.bits;
689 args2.parent_value = h->value.bits;
690 return table_iter(d->table.table, table_test_fn, &args2);
691 }
692
693 return 0;
694}
695
696static int table_test(const union decode_item *table)
697{
698 struct table_test_args args = {
699 .root_table = table,
700 .parent_mask = 0,
701 .parent_value = 0
702 };
703 return table_iter(args.root_table, table_test_fn, &args);
704}
705
706
707/*
708 * Decoding table test coverage analysis
709 *
710 * coverage_start() builds a coverage_table which contains a list of
711 * coverage_entry's to match each entry in the specified kprobes instruction
712 * decoding table.
713 *
714 * When test cases are run, coverage_add() is called to process each case.
715 * This looks up the corresponding entry in the coverage_table and sets it as
716 * being matched, as well as clearing the regs flag appropriate for the test.
717 *
718 * After all test cases have been run, coverage_end() is called to check that
719 * all entries in coverage_table have been matched and that all regs flags are
720 * cleared. I.e. that all possible combinations of instructions described by
721 * the kprobes decoding tables have had a test case executed for them.
722 */
723
724bool coverage_fail;
725
726#define MAX_COVERAGE_ENTRIES 256
727
728struct coverage_entry {
729 const struct decode_header *header;
730 unsigned regs;
731 unsigned nesting;
732 char matched;
733};
734
735struct coverage_table {
736 struct coverage_entry *base;
737 unsigned num_entries;
738 unsigned nesting;
739};
740
741struct coverage_table coverage;
742
743#define COVERAGE_ANY_REG (1<<0)
744#define COVERAGE_SP (1<<1)
745#define COVERAGE_PC (1<<2)
746#define COVERAGE_PCWB (1<<3)
747
748static const char coverage_register_lookup[16] = {
749 [REG_TYPE_ANY] = COVERAGE_ANY_REG | COVERAGE_SP | COVERAGE_PC,
750 [REG_TYPE_SAMEAS16] = COVERAGE_ANY_REG,
751 [REG_TYPE_SP] = COVERAGE_SP,
752 [REG_TYPE_PC] = COVERAGE_PC,
753 [REG_TYPE_NOSP] = COVERAGE_ANY_REG | COVERAGE_SP,
754 [REG_TYPE_NOSPPC] = COVERAGE_ANY_REG | COVERAGE_SP | COVERAGE_PC,
755 [REG_TYPE_NOPC] = COVERAGE_ANY_REG | COVERAGE_PC,
756 [REG_TYPE_NOPCWB] = COVERAGE_ANY_REG | COVERAGE_PC | COVERAGE_PCWB,
757 [REG_TYPE_NOPCX] = COVERAGE_ANY_REG,
758 [REG_TYPE_NOSPPCX] = COVERAGE_ANY_REG | COVERAGE_SP,
759};
760
761unsigned coverage_start_registers(const struct decode_header *h)
762{
763 unsigned regs = 0;
764 int i;
765 for (i = 0; i < 20; i += 4) {
766 int r = (h->type_regs.bits >> (DECODE_TYPE_BITS + i)) & 0xf;
767 regs |= coverage_register_lookup[r] << i;
768 }
769 return regs;
770}
771
772static int coverage_start_fn(const struct decode_header *h, void *args)
773{
774 struct coverage_table *coverage = (struct coverage_table *)args;
775 enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
776 struct coverage_entry *entry = coverage->base + coverage->num_entries;
777
778 if (coverage->num_entries == MAX_COVERAGE_ENTRIES - 1) {
779 pr_err("FAIL: Out of space for test coverage data");
780 return -ENOMEM;
781 }
782
783 ++coverage->num_entries;
784
785 entry->header = h;
786 entry->regs = coverage_start_registers(h);
787 entry->nesting = coverage->nesting;
788 entry->matched = false;
789
790 if (type == DECODE_TYPE_TABLE) {
791 struct decode_table *d = (struct decode_table *)h;
792 int ret;
793 ++coverage->nesting;
794 ret = table_iter(d->table.table, coverage_start_fn, coverage);
795 --coverage->nesting;
796 return ret;
797 }
798
799 return 0;
800}
801
802static int coverage_start(const union decode_item *table)
803{
804 coverage.base = kmalloc(MAX_COVERAGE_ENTRIES *
805 sizeof(struct coverage_entry), GFP_KERNEL);
806 coverage.num_entries = 0;
807 coverage.nesting = 0;
808 return table_iter(table, coverage_start_fn, &coverage);
809}
810
811static void
812coverage_add_registers(struct coverage_entry *entry, kprobe_opcode_t insn)
813{
814 int regs = entry->header->type_regs.bits >> DECODE_TYPE_BITS;
815 int i;
816 for (i = 0; i < 20; i += 4) {
817 enum decode_reg_type reg_type = (regs >> i) & 0xf;
818 int reg = (insn >> i) & 0xf;
819 int flag;
820
821 if (!reg_type)
822 continue;
823
824 if (reg == 13)
825 flag = COVERAGE_SP;
826 else if (reg == 15)
827 flag = COVERAGE_PC;
828 else
829 flag = COVERAGE_ANY_REG;
830 entry->regs &= ~(flag << i);
831
832 switch (reg_type) {
833
834 case REG_TYPE_NONE:
835 case REG_TYPE_ANY:
836 case REG_TYPE_SAMEAS16:
837 break;
838
839 case REG_TYPE_SP:
840 if (reg != 13)
841 return;
842 break;
843
844 case REG_TYPE_PC:
845 if (reg != 15)
846 return;
847 break;
848
849 case REG_TYPE_NOSP:
850 if (reg == 13)
851 return;
852 break;
853
854 case REG_TYPE_NOSPPC:
855 case REG_TYPE_NOSPPCX:
856 if (reg == 13 || reg == 15)
857 return;
858 break;
859
860 case REG_TYPE_NOPCWB:
861 if (!is_writeback(insn))
862 break;
863 if (reg == 15) {
864 entry->regs &= ~(COVERAGE_PCWB << i);
865 return;
866 }
867 break;
868
869 case REG_TYPE_NOPC:
870 case REG_TYPE_NOPCX:
871 if (reg == 15)
872 return;
873 break;
874 }
875
876 }
877}
878
879static void coverage_add(kprobe_opcode_t insn)
880{
881 struct coverage_entry *entry = coverage.base;
882 struct coverage_entry *end = coverage.base + coverage.num_entries;
883 bool matched = false;
884 unsigned nesting = 0;
885
886 for (; entry < end; ++entry) {
887 const struct decode_header *h = entry->header;
888 enum decode_type type = h->type_regs.bits & DECODE_TYPE_MASK;
889
890 if (entry->nesting > nesting)
891 continue; /* Skip sub-table we didn't match */
892
893 if (entry->nesting < nesting)
894 break; /* End of sub-table we were scanning */
895
896 if (!matched) {
897 if ((insn & h->mask.bits) != h->value.bits)
898 continue;
899 entry->matched = true;
900 }
901
902 switch (type) {
903
904 case DECODE_TYPE_TABLE:
905 ++nesting;
906 break;
907
908 case DECODE_TYPE_CUSTOM:
909 case DECODE_TYPE_SIMULATE:
910 case DECODE_TYPE_EMULATE:
911 coverage_add_registers(entry, insn);
912 return;
913
914 case DECODE_TYPE_OR:
915 matched = true;
916 break;
917
918 case DECODE_TYPE_REJECT:
919 default:
920 return;
921 }
922
923 }
924}
925
926static void coverage_end(void)
927{
928 struct coverage_entry *entry = coverage.base;
929 struct coverage_entry *end = coverage.base + coverage.num_entries;
930
931 for (; entry < end; ++entry) {
932 u32 mask = entry->header->mask.bits;
933 u32 value = entry->header->value.bits;
934
935 if (entry->regs) {
936 pr_err("FAIL: Register test coverage missing for %08x %08x (%05x)\n",
937 mask, value, entry->regs);
938 coverage_fail = true;
939 }
940 if (!entry->matched) {
941 pr_err("FAIL: Test coverage entry missing for %08x %08x\n",
942 mask, value);
943 coverage_fail = true;
944 }
945 }
946
947 kfree(coverage.base);
948}
949
950
951/*
952 * Framework for instruction set test cases
953 */
954
955void __naked __kprobes_test_case_start(void)
956{
957 __asm__ __volatile__ (
958 "stmdb sp!, {r4-r11} \n\t"
959 "sub sp, sp, #"__stringify(TEST_MEMORY_SIZE)"\n\t"
960 "bic r0, lr, #1 @ r0 = inline title string \n\t"
961 "mov r1, sp \n\t"
962 "bl kprobes_test_case_start \n\t"
963 "bx r0 \n\t"
964 );
965}
966
967#ifndef CONFIG_THUMB2_KERNEL
968
969void __naked __kprobes_test_case_end_32(void)
970{
971 __asm__ __volatile__ (
972 "mov r4, lr \n\t"
973 "bl kprobes_test_case_end \n\t"
974 "cmp r0, #0 \n\t"
975 "movne pc, r0 \n\t"
976 "mov r0, r4 \n\t"
977 "add sp, sp, #"__stringify(TEST_MEMORY_SIZE)"\n\t"
978 "ldmia sp!, {r4-r11} \n\t"
979 "mov pc, r0 \n\t"
980 );
981}
982
983#else /* CONFIG_THUMB2_KERNEL */
984
985void __naked __kprobes_test_case_end_16(void)
986{
987 __asm__ __volatile__ (
988 "mov r4, lr \n\t"
989 "bl kprobes_test_case_end \n\t"
990 "cmp r0, #0 \n\t"
991 "bxne r0 \n\t"
992 "mov r0, r4 \n\t"
993 "add sp, sp, #"__stringify(TEST_MEMORY_SIZE)"\n\t"
994 "ldmia sp!, {r4-r11} \n\t"
995 "bx r0 \n\t"
996 );
997}
998
999void __naked __kprobes_test_case_end_32(void)
1000{
1001 __asm__ __volatile__ (
1002 ".arm \n\t"
1003 "orr lr, lr, #1 @ will return to Thumb code \n\t"
1004 "ldr pc, 1f \n\t"
1005 "1: \n\t"
1006 ".word __kprobes_test_case_end_16 \n\t"
1007 );
1008}
1009
1010#endif
1011
1012
1013int kprobe_test_flags;
1014int kprobe_test_cc_position;
1015
1016static int test_try_count;
1017static int test_pass_count;
1018static int test_fail_count;
1019
1020static struct pt_regs initial_regs;
1021static struct pt_regs expected_regs;
1022static struct pt_regs result_regs;
1023
1024static u32 expected_memory[TEST_MEMORY_SIZE/sizeof(u32)];
1025
1026static const char *current_title;
1027static struct test_arg *current_args;
1028static u32 *current_stack;
1029static uintptr_t current_branch_target;
1030
1031static uintptr_t current_code_start;
1032static kprobe_opcode_t current_instruction;
1033
1034
1035#define TEST_CASE_PASSED -1
1036#define TEST_CASE_FAILED -2
1037
1038static int test_case_run_count;
1039static bool test_case_is_thumb;
1040static int test_instance;
1041
1042/*
1043 * We ignore the state of the imprecise abort disable flag (CPSR.A) because this
1044 * can change randomly as the kernel doesn't take care to preserve or initialise
1045 * this across context switches. Also, with Security Extentions, the flag may
1046 * not be under control of the kernel; for this reason we ignore the state of
1047 * the FIQ disable flag CPSR.F as well.
1048 */
1049#define PSR_IGNORE_BITS (PSR_A_BIT | PSR_F_BIT)
1050
1051static unsigned long test_check_cc(int cc, unsigned long cpsr)
1052{
1053 unsigned long temp;
1054
1055 switch (cc) {
1056 case 0x0: /* eq */
1057 return cpsr & PSR_Z_BIT;
1058
1059 case 0x1: /* ne */
1060 return (~cpsr) & PSR_Z_BIT;
1061
1062 case 0x2: /* cs */
1063 return cpsr & PSR_C_BIT;
1064
1065 case 0x3: /* cc */
1066 return (~cpsr) & PSR_C_BIT;
1067
1068 case 0x4: /* mi */
1069 return cpsr & PSR_N_BIT;
1070
1071 case 0x5: /* pl */
1072 return (~cpsr) & PSR_N_BIT;
1073
1074 case 0x6: /* vs */
1075 return cpsr & PSR_V_BIT;
1076
1077 case 0x7: /* vc */
1078 return (~cpsr) & PSR_V_BIT;
1079
1080 case 0x8: /* hi */
1081 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1082 return cpsr & PSR_C_BIT;
1083
1084 case 0x9: /* ls */
1085 cpsr &= ~(cpsr >> 1); /* PSR_C_BIT &= ~PSR_Z_BIT */
1086 return (~cpsr) & PSR_C_BIT;
1087
1088 case 0xa: /* ge */
1089 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1090 return (~cpsr) & PSR_N_BIT;
1091
1092 case 0xb: /* lt */
1093 cpsr ^= (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1094 return cpsr & PSR_N_BIT;
1095
1096 case 0xc: /* gt */
1097 temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1098 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
1099 return (~temp) & PSR_N_BIT;
1100
1101 case 0xd: /* le */
1102 temp = cpsr ^ (cpsr << 3); /* PSR_N_BIT ^= PSR_V_BIT */
1103 temp |= (cpsr << 1); /* PSR_N_BIT |= PSR_Z_BIT */
1104 return temp & PSR_N_BIT;
1105
1106 case 0xe: /* al */
1107 case 0xf: /* unconditional */
1108 return true;
1109 }
1110 BUG();
1111 return false;
1112}
1113
1114static int is_last_scenario;
1115static int probe_should_run; /* 0 = no, 1 = yes, -1 = unknown */
1116static int memory_needs_checking;
1117
1118static unsigned long test_context_cpsr(int scenario)
1119{
1120 unsigned long cpsr;
1121
1122 probe_should_run = 1;
1123
1124 /* Default case is that we cycle through 16 combinations of flags */
1125 cpsr = (scenario & 0xf) << 28; /* N,Z,C,V flags */
1126 cpsr |= (scenario & 0xf) << 16; /* GE flags */
1127 cpsr |= (scenario & 0x1) << 27; /* Toggle Q flag */
1128
1129 if (!test_case_is_thumb) {
1130 /* Testing ARM code */
1131 probe_should_run = test_check_cc(current_instruction >> 28, cpsr) != 0;
1132 if (scenario == 15)
1133 is_last_scenario = true;
1134
1135 } else if (kprobe_test_flags & TEST_FLAG_NO_ITBLOCK) {
1136 /* Testing Thumb code without setting ITSTATE */
1137 if (kprobe_test_cc_position) {
1138 int cc = (current_instruction >> kprobe_test_cc_position) & 0xf;
1139 probe_should_run = test_check_cc(cc, cpsr) != 0;
1140 }
1141
1142 if (scenario == 15)
1143 is_last_scenario = true;
1144
1145 } else if (kprobe_test_flags & TEST_FLAG_FULL_ITBLOCK) {
1146 /* Testing Thumb code with all combinations of ITSTATE */
1147 unsigned x = (scenario >> 4);
1148 unsigned cond_base = x % 7; /* ITSTATE<7:5> */
1149 unsigned mask = x / 7 + 2; /* ITSTATE<4:0>, bits reversed */
1150
1151 if (mask > 0x1f) {
1152 /* Finish by testing state from instruction 'itt al' */
1153 cond_base = 7;
1154 mask = 0x4;
1155 if ((scenario & 0xf) == 0xf)
1156 is_last_scenario = true;
1157 }
1158
1159 cpsr |= cond_base << 13; /* ITSTATE<7:5> */
1160 cpsr |= (mask & 0x1) << 12; /* ITSTATE<4> */
1161 cpsr |= (mask & 0x2) << 10; /* ITSTATE<3> */
1162 cpsr |= (mask & 0x4) << 8; /* ITSTATE<2> */
1163 cpsr |= (mask & 0x8) << 23; /* ITSTATE<1> */
1164 cpsr |= (mask & 0x10) << 21; /* ITSTATE<0> */
1165
1166 probe_should_run = test_check_cc((cpsr >> 12) & 0xf, cpsr) != 0;
1167
1168 } else {
1169 /* Testing Thumb code with several combinations of ITSTATE */
1170 switch (scenario) {
1171 case 16: /* Clear NZCV flags and 'it eq' state (false as Z=0) */
1172 cpsr = 0x00000800;
1173 probe_should_run = 0;
1174 break;
1175 case 17: /* Set NZCV flags and 'it vc' state (false as V=1) */
1176 cpsr = 0xf0007800;
1177 probe_should_run = 0;
1178 break;
1179 case 18: /* Clear NZCV flags and 'it ls' state (true as C=0) */
1180 cpsr = 0x00009800;
1181 break;
1182 case 19: /* Set NZCV flags and 'it cs' state (true as C=1) */
1183 cpsr = 0xf0002800;
1184 is_last_scenario = true;
1185 break;
1186 }
1187 }
1188
1189 return cpsr;
1190}
1191
1192static void setup_test_context(struct pt_regs *regs)
1193{
1194 int scenario = test_case_run_count>>1;
1195 unsigned long val;
1196 struct test_arg *args;
1197 int i;
1198
1199 is_last_scenario = false;
1200 memory_needs_checking = false;
1201
1202 /* Initialise test memory on stack */
1203 val = (scenario & 1) ? VALM : ~VALM;
1204 for (i = 0; i < TEST_MEMORY_SIZE / sizeof(current_stack[0]); ++i)
1205 current_stack[i] = val + (i << 8);
1206 /* Put target of branch on stack for tests which load PC from memory */
1207 if (current_branch_target)
1208 current_stack[15] = current_branch_target;
1209 /* Put a value for SP on stack for tests which load SP from memory */
1210 current_stack[13] = (u32)current_stack + 120;
1211
1212 /* Initialise register values to their default state */
1213 val = (scenario & 2) ? VALR : ~VALR;
1214 for (i = 0; i < 13; ++i)
1215 regs->uregs[i] = val ^ (i << 8);
1216 regs->ARM_lr = val ^ (14 << 8);
1217 regs->ARM_cpsr &= ~(APSR_MASK | PSR_IT_MASK);
1218 regs->ARM_cpsr |= test_context_cpsr(scenario);
1219
1220 /* Perform testcase specific register setup */
1221 args = current_args;
1222 for (; args[0].type != ARG_TYPE_END; ++args)
1223 switch (args[0].type) {
1224 case ARG_TYPE_REG: {
1225 struct test_arg_regptr *arg =
1226 (struct test_arg_regptr *)args;
1227 regs->uregs[arg->reg] = arg->val;
1228 break;
1229 }
1230 case ARG_TYPE_PTR: {
1231 struct test_arg_regptr *arg =
1232 (struct test_arg_regptr *)args;
1233 regs->uregs[arg->reg] =
1234 (unsigned long)current_stack + arg->val;
1235 memory_needs_checking = true;
1236 break;
1237 }
1238 case ARG_TYPE_MEM: {
1239 struct test_arg_mem *arg = (struct test_arg_mem *)args;
1240 current_stack[arg->index] = arg->val;
1241 break;
1242 }
1243 default:
1244 break;
1245 }
1246}
1247
1248struct test_probe {
1249 struct kprobe kprobe;
1250 bool registered;
1251 int hit;
1252};
1253
1254static void unregister_test_probe(struct test_probe *probe)
1255{
1256 if (probe->registered) {
1257 unregister_kprobe(&probe->kprobe);
1258 probe->kprobe.flags = 0; /* Clear disable flag to allow reuse */
1259 }
1260 probe->registered = false;
1261}
1262
1263static int register_test_probe(struct test_probe *probe)
1264{
1265 int ret;
1266
1267 if (probe->registered)
1268 BUG();
1269
1270 ret = register_kprobe(&probe->kprobe);
1271 if (ret >= 0) {
1272 probe->registered = true;
1273 probe->hit = -1;
1274 }
1275 return ret;
1276}
1277
1278static int __kprobes
1279test_before_pre_handler(struct kprobe *p, struct pt_regs *regs)
1280{
1281 container_of(p, struct test_probe, kprobe)->hit = test_instance;
1282 return 0;
1283}
1284
1285static void __kprobes
1286test_before_post_handler(struct kprobe *p, struct pt_regs *regs,
1287 unsigned long flags)
1288{
1289 setup_test_context(regs);
1290 initial_regs = *regs;
1291 initial_regs.ARM_cpsr &= ~PSR_IGNORE_BITS;
1292}
1293
1294static int __kprobes
1295test_case_pre_handler(struct kprobe *p, struct pt_regs *regs)
1296{
1297 container_of(p, struct test_probe, kprobe)->hit = test_instance;
1298 return 0;
1299}
1300
1301static int __kprobes
1302test_after_pre_handler(struct kprobe *p, struct pt_regs *regs)
1303{
1304 if (container_of(p, struct test_probe, kprobe)->hit == test_instance)
1305 return 0; /* Already run for this test instance */
1306
1307 result_regs = *regs;
1308 result_regs.ARM_cpsr &= ~PSR_IGNORE_BITS;
1309
1310 /* Undo any changes done to SP by the test case */
1311 regs->ARM_sp = (unsigned long)current_stack;
1312
1313 container_of(p, struct test_probe, kprobe)->hit = test_instance;
1314 return 0;
1315}
1316
1317static struct test_probe test_before_probe = {
1318 .kprobe.pre_handler = test_before_pre_handler,
1319 .kprobe.post_handler = test_before_post_handler,
1320};
1321
1322static struct test_probe test_case_probe = {
1323 .kprobe.pre_handler = test_case_pre_handler,
1324};
1325
1326static struct test_probe test_after_probe = {
1327 .kprobe.pre_handler = test_after_pre_handler,
1328};
1329
1330static struct test_probe test_after2_probe = {
1331 .kprobe.pre_handler = test_after_pre_handler,
1332};
1333
1334static void test_case_cleanup(void)
1335{
1336 unregister_test_probe(&test_before_probe);
1337 unregister_test_probe(&test_case_probe);
1338 unregister_test_probe(&test_after_probe);
1339 unregister_test_probe(&test_after2_probe);
1340}
1341
1342static void print_registers(struct pt_regs *regs)
1343{
1344 pr_err("r0 %08lx | r1 %08lx | r2 %08lx | r3 %08lx\n",
1345 regs->ARM_r0, regs->ARM_r1, regs->ARM_r2, regs->ARM_r3);
1346 pr_err("r4 %08lx | r5 %08lx | r6 %08lx | r7 %08lx\n",
1347 regs->ARM_r4, regs->ARM_r5, regs->ARM_r6, regs->ARM_r7);
1348 pr_err("r8 %08lx | r9 %08lx | r10 %08lx | r11 %08lx\n",
1349 regs->ARM_r8, regs->ARM_r9, regs->ARM_r10, regs->ARM_fp);
1350 pr_err("r12 %08lx | sp %08lx | lr %08lx | pc %08lx\n",
1351 regs->ARM_ip, regs->ARM_sp, regs->ARM_lr, regs->ARM_pc);
1352 pr_err("cpsr %08lx\n", regs->ARM_cpsr);
1353}
1354
1355static void print_memory(u32 *mem, size_t size)
1356{
1357 int i;
1358 for (i = 0; i < size / sizeof(u32); i += 4)
1359 pr_err("%08x %08x %08x %08x\n", mem[i], mem[i+1],
1360 mem[i+2], mem[i+3]);
1361}
1362
1363static size_t expected_memory_size(u32 *sp)
1364{
1365 size_t size = sizeof(expected_memory);
1366 int offset = (uintptr_t)sp - (uintptr_t)current_stack;
1367 if (offset > 0)
1368 size -= offset;
1369 return size;
1370}
1371
1372static void test_case_failed(const char *message)
1373{
1374 test_case_cleanup();
1375
1376 pr_err("FAIL: %s\n", message);
1377 pr_err("FAIL: Test %s\n", current_title);
1378 pr_err("FAIL: Scenario %d\n", test_case_run_count >> 1);
1379}
1380
1381static unsigned long next_instruction(unsigned long pc)
1382{
1383#ifdef CONFIG_THUMB2_KERNEL
1384 if ((pc & 1) && !is_wide_instruction(*(u16 *)(pc - 1)))
1385 return pc + 2;
1386 else
1387#endif
1388 return pc + 4;
1389}
1390
1391static uintptr_t __used kprobes_test_case_start(const char *title, void *stack)
1392{
1393 struct test_arg *args;
1394 struct test_arg_end *end_arg;
1395 unsigned long test_code;
1396
1397 args = (struct test_arg *)PTR_ALIGN(title + strlen(title) + 1, 4);
1398
1399 current_title = title;
1400 current_args = args;
1401 current_stack = stack;
1402
1403 ++test_try_count;
1404
1405 while (args->type != ARG_TYPE_END)
1406 ++args;
1407 end_arg = (struct test_arg_end *)args;
1408
1409 test_code = (unsigned long)(args + 1); /* Code starts after args */
1410
1411 test_case_is_thumb = end_arg->flags & ARG_FLAG_THUMB;
1412 if (test_case_is_thumb)
1413 test_code |= 1;
1414
1415 current_code_start = test_code;
1416
1417 current_branch_target = 0;
1418 if (end_arg->branch_offset != end_arg->end_offset)
1419 current_branch_target = test_code + end_arg->branch_offset;
1420
1421 test_code += end_arg->code_offset;
1422 test_before_probe.kprobe.addr = (kprobe_opcode_t *)test_code;
1423
1424 test_code = next_instruction(test_code);
1425 test_case_probe.kprobe.addr = (kprobe_opcode_t *)test_code;
1426
1427 if (test_case_is_thumb) {
1428 u16 *p = (u16 *)(test_code & ~1);
1429 current_instruction = p[0];
1430 if (is_wide_instruction(current_instruction)) {
1431 current_instruction <<= 16;
1432 current_instruction |= p[1];
1433 }
1434 } else {
1435 current_instruction = *(u32 *)test_code;
1436 }
1437
1438 if (current_title[0] == '.')
1439 verbose("%s\n", current_title);
1440 else
1441 verbose("%s\t@ %0*x\n", current_title,
1442 test_case_is_thumb ? 4 : 8,
1443 current_instruction);
1444
1445 test_code = next_instruction(test_code);
1446 test_after_probe.kprobe.addr = (kprobe_opcode_t *)test_code;
1447
1448 if (kprobe_test_flags & TEST_FLAG_NARROW_INSTR) {
1449 if (!test_case_is_thumb ||
1450 is_wide_instruction(current_instruction)) {
1451 test_case_failed("expected 16-bit instruction");
1452 goto fail;
1453 }
1454 } else {
1455 if (test_case_is_thumb &&
1456 !is_wide_instruction(current_instruction)) {
1457 test_case_failed("expected 32-bit instruction");
1458 goto fail;
1459 }
1460 }
1461
1462 coverage_add(current_instruction);
1463
1464 if (end_arg->flags & ARG_FLAG_UNSUPPORTED) {
1465 if (register_test_probe(&test_case_probe) < 0)
1466 goto pass;
1467 test_case_failed("registered probe for unsupported instruction");
1468 goto fail;
1469 }
1470
1471 if (end_arg->flags & ARG_FLAG_SUPPORTED) {
1472 if (register_test_probe(&test_case_probe) >= 0)
1473 goto pass;
1474 test_case_failed("couldn't register probe for supported instruction");
1475 goto fail;
1476 }
1477
1478 if (register_test_probe(&test_before_probe) < 0) {
1479 test_case_failed("register test_before_probe failed");
1480 goto fail;
1481 }
1482 if (register_test_probe(&test_after_probe) < 0) {
1483 test_case_failed("register test_after_probe failed");
1484 goto fail;
1485 }
1486 if (current_branch_target) {
1487 test_after2_probe.kprobe.addr =
1488 (kprobe_opcode_t *)current_branch_target;
1489 if (register_test_probe(&test_after2_probe) < 0) {
1490 test_case_failed("register test_after2_probe failed");
1491 goto fail;
1492 }
1493 }
1494
1495 /* Start first run of test case */
1496 test_case_run_count = 0;
1497 ++test_instance;
1498 return current_code_start;
1499pass:
1500 test_case_run_count = TEST_CASE_PASSED;
1501 return (uintptr_t)test_after_probe.kprobe.addr;
1502fail:
1503 test_case_run_count = TEST_CASE_FAILED;
1504 return (uintptr_t)test_after_probe.kprobe.addr;
1505}
1506
1507static bool check_test_results(void)
1508{
1509 size_t mem_size = 0;
1510 u32 *mem = 0;
1511
1512 if (memcmp(&expected_regs, &result_regs, sizeof(expected_regs))) {
1513 test_case_failed("registers differ");
1514 goto fail;
1515 }
1516
1517 if (memory_needs_checking) {
1518 mem = (u32 *)result_regs.ARM_sp;
1519 mem_size = expected_memory_size(mem);
1520 if (memcmp(expected_memory, mem, mem_size)) {
1521 test_case_failed("test memory differs");
1522 goto fail;
1523 }
1524 }
1525
1526 return true;
1527
1528fail:
1529 pr_err("initial_regs:\n");
1530 print_registers(&initial_regs);
1531 pr_err("expected_regs:\n");
1532 print_registers(&expected_regs);
1533 pr_err("result_regs:\n");
1534 print_registers(&result_regs);
1535
1536 if (mem) {
1537 pr_err("current_stack=%p\n", current_stack);
1538 pr_err("expected_memory:\n");
1539 print_memory(expected_memory, mem_size);
1540 pr_err("result_memory:\n");
1541 print_memory(mem, mem_size);
1542 }
1543
1544 return false;
1545}
1546
1547static uintptr_t __used kprobes_test_case_end(void)
1548{
1549 if (test_case_run_count < 0) {
1550 if (test_case_run_count == TEST_CASE_PASSED)
1551 /* kprobes_test_case_start did all the needed testing */
1552 goto pass;
1553 else
1554 /* kprobes_test_case_start failed */
1555 goto fail;
1556 }
1557
1558 if (test_before_probe.hit != test_instance) {
1559 test_case_failed("test_before_handler not run");
1560 goto fail;
1561 }
1562
1563 if (test_after_probe.hit != test_instance &&
1564 test_after2_probe.hit != test_instance) {
1565 test_case_failed("test_after_handler not run");
1566 goto fail;
1567 }
1568
1569 /*
1570 * Even numbered test runs ran without a probe on the test case so
1571 * we can gather reference results. The subsequent odd numbered run
1572 * will have the probe inserted.
1573 */
1574 if ((test_case_run_count & 1) == 0) {
1575 /* Save results from run without probe */
1576 u32 *mem = (u32 *)result_regs.ARM_sp;
1577 expected_regs = result_regs;
1578 memcpy(expected_memory, mem, expected_memory_size(mem));
1579
1580 /* Insert probe onto test case instruction */
1581 if (register_test_probe(&test_case_probe) < 0) {
1582 test_case_failed("register test_case_probe failed");
1583 goto fail;
1584 }
1585 } else {
1586 /* Check probe ran as expected */
1587 if (probe_should_run == 1) {
1588 if (test_case_probe.hit != test_instance) {
1589 test_case_failed("test_case_handler not run");
1590 goto fail;
1591 }
1592 } else if (probe_should_run == 0) {
1593 if (test_case_probe.hit == test_instance) {
1594 test_case_failed("test_case_handler ran");
1595 goto fail;
1596 }
1597 }
1598
1599 /* Remove probe for any subsequent reference run */
1600 unregister_test_probe(&test_case_probe);
1601
1602 if (!check_test_results())
1603 goto fail;
1604
1605 if (is_last_scenario)
1606 goto pass;
1607 }
1608
1609 /* Do next test run */
1610 ++test_case_run_count;
1611 ++test_instance;
1612 return current_code_start;
1613fail:
1614 ++test_fail_count;
1615 goto end;
1616pass:
1617 ++test_pass_count;
1618end:
1619 test_case_cleanup();
1620 return 0;
1621}
1622
1623
1624/*
1625 * Top level test functions
1626 */
1627
1628static int run_test_cases(void (*tests)(void), const union decode_item *table)
1629{
1630 int ret;
1631
1632 pr_info(" Check decoding tables\n");
1633 ret = table_test(table);
1634 if (ret)
1635 return ret;
1636
1637 pr_info(" Run test cases\n");
1638 ret = coverage_start(table);
1639 if (ret)
1640 return ret;
1641
1642 tests();
1643
1644 coverage_end();
1645 return 0;
1646}
1647
1648
1649static int __init run_all_tests(void)
1650{
1651 int ret = 0;
1652
1653 pr_info("Begining kprobe tests...\n");
1654
1655#ifndef CONFIG_THUMB2_KERNEL
1656
1657 pr_info("Probe ARM code\n");
1658 ret = run_api_tests(arm_func);
1659 if (ret)
1660 goto out;
1661
1662 pr_info("ARM instruction simulation\n");
1663 ret = run_test_cases(kprobe_arm_test_cases, kprobe_decode_arm_table);
1664 if (ret)
1665 goto out;
1666
1667#else /* CONFIG_THUMB2_KERNEL */
1668
1669 pr_info("Probe 16-bit Thumb code\n");
1670 ret = run_api_tests(thumb16_func);
1671 if (ret)
1672 goto out;
1673
1674 pr_info("Probe 32-bit Thumb code, even halfword\n");
1675 ret = run_api_tests(thumb32even_func);
1676 if (ret)
1677 goto out;
1678
1679 pr_info("Probe 32-bit Thumb code, odd halfword\n");
1680 ret = run_api_tests(thumb32odd_func);
1681 if (ret)
1682 goto out;
1683
1684 pr_info("16-bit Thumb instruction simulation\n");
1685 ret = run_test_cases(kprobe_thumb16_test_cases,
1686 kprobe_decode_thumb16_table);
1687 if (ret)
1688 goto out;
1689
1690 pr_info("32-bit Thumb instruction simulation\n");
1691 ret = run_test_cases(kprobe_thumb32_test_cases,
1692 kprobe_decode_thumb32_table);
1693 if (ret)
1694 goto out;
1695#endif
1696
1697 pr_info("Total instruction simulation tests=%d, pass=%d fail=%d\n",
1698 test_try_count, test_pass_count, test_fail_count);
1699 if (test_fail_count) {
1700 ret = -EINVAL;
1701 goto out;
1702 }
1703
1704#if BENCHMARKING
1705 pr_info("Benchmarks\n");
1706 ret = run_benchmarks();
1707 if (ret)
1708 goto out;
1709#endif
1710
1711#if __LINUX_ARM_ARCH__ >= 7
1712 /* We are able to run all test cases so coverage should be complete */
1713 if (coverage_fail) {
1714 pr_err("FAIL: Test coverage checks failed\n");
1715 ret = -EINVAL;
1716 goto out;
1717 }
1718#endif
1719
1720out:
1721 if (ret == 0)
1722 pr_info("Finished kprobe tests OK\n");
1723 else
1724 pr_err("kprobe tests failed\n");
1725
1726 return ret;
1727}
1728
1729
1730/*
1731 * Module setup
1732 */
1733
1734#ifdef MODULE
1735
1736static void __exit kprobe_test_exit(void)
1737{
1738}
1739
1740module_init(run_all_tests)
1741module_exit(kprobe_test_exit)
1742MODULE_LICENSE("GPL");
1743
1744#else /* !MODULE */
1745
1746late_initcall(run_all_tests);
1747
1748#endif
diff --git a/arch/arm/kernel/kprobes-test.h b/arch/arm/kernel/kprobes-test.h
new file mode 100644
index 000000000000..0dc5d77b9356
--- /dev/null
+++ b/arch/arm/kernel/kprobes-test.h
@@ -0,0 +1,392 @@
1/*
2 * arch/arm/kernel/kprobes-test.h
3 *
4 * Copyright (C) 2011 Jon Medhurst <tixy@yxit.co.uk>.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#define VERBOSE 0 /* Set to '1' for more logging of test cases */
12
13#ifdef CONFIG_THUMB2_KERNEL
14#define NORMAL_ISA "16"
15#else
16#define NORMAL_ISA "32"
17#endif
18
19
20/* Flags used in kprobe_test_flags */
21#define TEST_FLAG_NO_ITBLOCK (1<<0)
22#define TEST_FLAG_FULL_ITBLOCK (1<<1)
23#define TEST_FLAG_NARROW_INSTR (1<<2)
24
25extern int kprobe_test_flags;
26extern int kprobe_test_cc_position;
27
28
29#define TEST_MEMORY_SIZE 256
30
31
32/*
33 * Test case structures.
34 *
35 * The arguments given to test cases can be one of three types.
36 *
37 * ARG_TYPE_REG
38 * Load a register with the given value.
39 *
40 * ARG_TYPE_PTR
41 * Load a register with a pointer into the stack buffer (SP + given value).
42 *
43 * ARG_TYPE_MEM
44 * Store the given value into the stack buffer at [SP+index].
45 *
46 */
47
48#define ARG_TYPE_END 0
49#define ARG_TYPE_REG 1
50#define ARG_TYPE_PTR 2
51#define ARG_TYPE_MEM 3
52
53#define ARG_FLAG_UNSUPPORTED 0x01
54#define ARG_FLAG_SUPPORTED 0x02
55#define ARG_FLAG_THUMB 0x10 /* Must be 16 so TEST_ISA can be used */
56#define ARG_FLAG_ARM 0x20 /* Must be 32 so TEST_ISA can be used */
57
58struct test_arg {
59 u8 type; /* ARG_TYPE_x */
60 u8 _padding[7];
61};
62
63struct test_arg_regptr {
64 u8 type; /* ARG_TYPE_REG or ARG_TYPE_PTR */
65 u8 reg;
66 u8 _padding[2];
67 u32 val;
68};
69
70struct test_arg_mem {
71 u8 type; /* ARG_TYPE_MEM */
72 u8 index;
73 u8 _padding[2];
74 u32 val;
75};
76
77struct test_arg_end {
78 u8 type; /* ARG_TYPE_END */
79 u8 flags; /* ARG_FLAG_x */
80 u16 code_offset;
81 u16 branch_offset;
82 u16 end_offset;
83};
84
85
86/*
87 * Building blocks for test cases.
88 *
89 * Each test case is wrapped between TESTCASE_START and TESTCASE_END.
90 *
91 * To specify arguments for a test case the TEST_ARG_{REG,PTR,MEM} macros are
92 * used followed by a terminating TEST_ARG_END.
93 *
94 * After this, the instruction to be tested is defined with TEST_INSTRUCTION.
95 * Or for branches, TEST_BRANCH_B and TEST_BRANCH_F (branch forwards/backwards).
96 *
97 * Some specific test cases may make use of other custom constructs.
98 */
99
100#if VERBOSE
101#define verbose(fmt, ...) pr_info(fmt, ##__VA_ARGS__)
102#else
103#define verbose(fmt, ...)
104#endif
105
106#define TEST_GROUP(title) \
107 verbose("\n"); \
108 verbose(title"\n"); \
109 verbose("---------------------------------------------------------\n");
110
111#define TESTCASE_START(title) \
112 __asm__ __volatile__ ( \
113 "bl __kprobes_test_case_start \n\t" \
114 /* don't use .asciz here as 'title' may be */ \
115 /* multiple strings to be concatenated. */ \
116 ".ascii "#title" \n\t" \
117 ".byte 0 \n\t" \
118 ".align 2 \n\t"
119
120#define TEST_ARG_REG(reg, val) \
121 ".byte "__stringify(ARG_TYPE_REG)" \n\t" \
122 ".byte "#reg" \n\t" \
123 ".short 0 \n\t" \
124 ".word "#val" \n\t"
125
126#define TEST_ARG_PTR(reg, val) \
127 ".byte "__stringify(ARG_TYPE_PTR)" \n\t" \
128 ".byte "#reg" \n\t" \
129 ".short 0 \n\t" \
130 ".word "#val" \n\t"
131
132#define TEST_ARG_MEM(index, val) \
133 ".byte "__stringify(ARG_TYPE_MEM)" \n\t" \
134 ".byte "#index" \n\t" \
135 ".short 0 \n\t" \
136 ".word "#val" \n\t"
137
138#define TEST_ARG_END(flags) \
139 ".byte "__stringify(ARG_TYPE_END)" \n\t" \
140 ".byte "TEST_ISA flags" \n\t" \
141 ".short 50f-0f \n\t" \
142 ".short 2f-0f \n\t" \
143 ".short 99f-0f \n\t" \
144 ".code "TEST_ISA" \n\t" \
145 "0: \n\t"
146
147#define TEST_INSTRUCTION(instruction) \
148 "50: nop \n\t" \
149 "1: "instruction" \n\t" \
150 " nop \n\t"
151
152#define TEST_BRANCH_F(instruction, xtra_dist) \
153 TEST_INSTRUCTION(instruction) \
154 ".if "#xtra_dist" \n\t" \
155 " b 99f \n\t" \
156 ".space "#xtra_dist" \n\t" \
157 ".endif \n\t" \
158 " b 99f \n\t" \
159 "2: nop \n\t"
160
161#define TEST_BRANCH_B(instruction, xtra_dist) \
162 " b 50f \n\t" \
163 " b 99f \n\t" \
164 "2: nop \n\t" \
165 " b 99f \n\t" \
166 ".if "#xtra_dist" \n\t" \
167 ".space "#xtra_dist" \n\t" \
168 ".endif \n\t" \
169 TEST_INSTRUCTION(instruction)
170
171#define TESTCASE_END \
172 "2: \n\t" \
173 "99: \n\t" \
174 " bl __kprobes_test_case_end_"TEST_ISA" \n\t" \
175 ".code "NORMAL_ISA" \n\t" \
176 : : \
177 : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc" \
178 );
179
180
181/*
182 * Macros to define test cases.
183 *
184 * Those of the form TEST_{R,P,M}* can be used to define test cases
185 * which take combinations of the three basic types of arguments. E.g.
186 *
187 * TEST_R One register argument
188 * TEST_RR Two register arguments
189 * TEST_RPR A register, a pointer, then a register argument
190 *
191 * For testing instructions which may branch, there are macros TEST_BF_*
192 * and TEST_BB_* for branching forwards and backwards.
193 *
194 * TEST_SUPPORTED and TEST_UNSUPPORTED don't cause the code to be executed,
195 * the just verify that a kprobe is or is not allowed on the given instruction.
196 */
197
198#define TEST(code) \
199 TESTCASE_START(code) \
200 TEST_ARG_END("") \
201 TEST_INSTRUCTION(code) \
202 TESTCASE_END
203
204#define TEST_UNSUPPORTED(code) \
205 TESTCASE_START(code) \
206 TEST_ARG_END("|"__stringify(ARG_FLAG_UNSUPPORTED)) \
207 TEST_INSTRUCTION(code) \
208 TESTCASE_END
209
210#define TEST_SUPPORTED(code) \
211 TESTCASE_START(code) \
212 TEST_ARG_END("|"__stringify(ARG_FLAG_SUPPORTED)) \
213 TEST_INSTRUCTION(code) \
214 TESTCASE_END
215
216#define TEST_R(code1, reg, val, code2) \
217 TESTCASE_START(code1 #reg code2) \
218 TEST_ARG_REG(reg, val) \
219 TEST_ARG_END("") \
220 TEST_INSTRUCTION(code1 #reg code2) \
221 TESTCASE_END
222
223#define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \
224 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
225 TEST_ARG_REG(reg1, val1) \
226 TEST_ARG_REG(reg2, val2) \
227 TEST_ARG_END("") \
228 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
229 TESTCASE_END
230
231#define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
232 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
233 TEST_ARG_REG(reg1, val1) \
234 TEST_ARG_REG(reg2, val2) \
235 TEST_ARG_REG(reg3, val3) \
236 TEST_ARG_END("") \
237 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
238 TESTCASE_END
239
240#define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \
241 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
242 TEST_ARG_REG(reg1, val1) \
243 TEST_ARG_REG(reg2, val2) \
244 TEST_ARG_REG(reg3, val3) \
245 TEST_ARG_REG(reg4, val4) \
246 TEST_ARG_END("") \
247 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \
248 TESTCASE_END
249
250#define TEST_P(code1, reg1, val1, code2) \
251 TESTCASE_START(code1 #reg1 code2) \
252 TEST_ARG_PTR(reg1, val1) \
253 TEST_ARG_END("") \
254 TEST_INSTRUCTION(code1 #reg1 code2) \
255 TESTCASE_END
256
257#define TEST_PR(code1, reg1, val1, code2, reg2, val2, code3) \
258 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
259 TEST_ARG_PTR(reg1, val1) \
260 TEST_ARG_REG(reg2, val2) \
261 TEST_ARG_END("") \
262 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
263 TESTCASE_END
264
265#define TEST_RP(code1, reg1, val1, code2, reg2, val2, code3) \
266 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
267 TEST_ARG_REG(reg1, val1) \
268 TEST_ARG_PTR(reg2, val2) \
269 TEST_ARG_END("") \
270 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \
271 TESTCASE_END
272
273#define TEST_PRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
274 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
275 TEST_ARG_PTR(reg1, val1) \
276 TEST_ARG_REG(reg2, val2) \
277 TEST_ARG_REG(reg3, val3) \
278 TEST_ARG_END("") \
279 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
280 TESTCASE_END
281
282#define TEST_RPR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
283 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
284 TEST_ARG_REG(reg1, val1) \
285 TEST_ARG_PTR(reg2, val2) \
286 TEST_ARG_REG(reg3, val3) \
287 TEST_ARG_END("") \
288 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
289 TESTCASE_END
290
291#define TEST_RRP(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\
292 TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
293 TEST_ARG_REG(reg1, val1) \
294 TEST_ARG_REG(reg2, val2) \
295 TEST_ARG_PTR(reg3, val3) \
296 TEST_ARG_END("") \
297 TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \
298 TESTCASE_END
299
300#define TEST_BF_P(code1, reg1, val1, code2) \
301 TESTCASE_START(code1 #reg1 code2) \
302 TEST_ARG_PTR(reg1, val1) \
303 TEST_ARG_END("") \
304 TEST_BRANCH_F(code1 #reg1 code2, 0) \
305 TESTCASE_END
306
307#define TEST_BF_X(code, xtra_dist) \
308 TESTCASE_START(code) \
309 TEST_ARG_END("") \
310 TEST_BRANCH_F(code, xtra_dist) \
311 TESTCASE_END
312
313#define TEST_BB_X(code, xtra_dist) \
314 TESTCASE_START(code) \
315 TEST_ARG_END("") \
316 TEST_BRANCH_B(code, xtra_dist) \
317 TESTCASE_END
318
319#define TEST_BF_RX(code1, reg, val, code2, xtra_dist) \
320 TESTCASE_START(code1 #reg code2) \
321 TEST_ARG_REG(reg, val) \
322 TEST_ARG_END("") \
323 TEST_BRANCH_F(code1 #reg code2, xtra_dist) \
324 TESTCASE_END
325
326#define TEST_BB_RX(code1, reg, val, code2, xtra_dist) \
327 TESTCASE_START(code1 #reg code2) \
328 TEST_ARG_REG(reg, val) \
329 TEST_ARG_END("") \
330 TEST_BRANCH_B(code1 #reg code2, xtra_dist) \
331 TESTCASE_END
332
333#define TEST_BF(code) TEST_BF_X(code, 0)
334#define TEST_BB(code) TEST_BB_X(code, 0)
335
336#define TEST_BF_R(code1, reg, val, code2) TEST_BF_RX(code1, reg, val, code2, 0)
337#define TEST_BB_R(code1, reg, val, code2) TEST_BB_RX(code1, reg, val, code2, 0)
338
339#define TEST_BF_RR(code1, reg1, val1, code2, reg2, val2, code3) \
340 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
341 TEST_ARG_REG(reg1, val1) \
342 TEST_ARG_REG(reg2, val2) \
343 TEST_ARG_END("") \
344 TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3, 0) \
345 TESTCASE_END
346
347#define TEST_X(code, codex) \
348 TESTCASE_START(code) \
349 TEST_ARG_END("") \
350 TEST_INSTRUCTION(code) \
351 " b 99f \n\t" \
352 " "codex" \n\t" \
353 TESTCASE_END
354
355#define TEST_RX(code1, reg, val, code2, codex) \
356 TESTCASE_START(code1 #reg code2) \
357 TEST_ARG_REG(reg, val) \
358 TEST_ARG_END("") \
359 TEST_INSTRUCTION(code1 __stringify(reg) code2) \
360 " b 99f \n\t" \
361 " "codex" \n\t" \
362 TESTCASE_END
363
364#define TEST_RRX(code1, reg1, val1, code2, reg2, val2, code3, codex) \
365 TESTCASE_START(code1 #reg1 code2 #reg2 code3) \
366 TEST_ARG_REG(reg1, val1) \
367 TEST_ARG_REG(reg2, val2) \
368 TEST_ARG_END("") \
369 TEST_INSTRUCTION(code1 __stringify(reg1) code2 __stringify(reg2) code3) \
370 " b 99f \n\t" \
371 " "codex" \n\t" \
372 TESTCASE_END
373
374
375/* Various values used in test cases... */
376#define N(val) (val ^ 0xffffffff)
377#define VAL1 0x12345678
378#define VAL2 N(VAL1)
379#define VAL3 0xa5f801
380#define VAL4 N(VAL3)
381#define VALM 0x456789ab
382#define VALR 0xdeaddead
383#define HH1 0x0123fecb
384#define HH2 0xa9874567
385
386
387#ifdef CONFIG_THUMB2_KERNEL
388void kprobe_thumb16_test_cases(void);
389void kprobe_thumb32_test_cases(void);
390#else
391void kprobe_arm_test_cases(void);
392#endif
diff --git a/arch/arm/kernel/kprobes-thumb.c b/arch/arm/kernel/kprobes-thumb.c
index 902ca59e8b11..8f96ec778e8d 100644
--- a/arch/arm/kernel/kprobes-thumb.c
+++ b/arch/arm/kernel/kprobes-thumb.c
@@ -10,6 +10,7 @@
10 10
11#include <linux/kernel.h> 11#include <linux/kernel.h>
12#include <linux/kprobes.h> 12#include <linux/kprobes.h>
13#include <linux/module.h>
13 14
14#include "kprobes.h" 15#include "kprobes.h"
15 16
@@ -943,6 +944,9 @@ const union decode_item kprobe_decode_thumb32_table[] = {
943 */ 944 */
944 DECODE_END 945 DECODE_END
945}; 946};
947#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
948EXPORT_SYMBOL_GPL(kprobe_decode_thumb32_table);
949#endif
946 950
947static void __kprobes 951static void __kprobes
948t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs) 952t16_simulate_bxblx(struct kprobe *p, struct pt_regs *regs)
@@ -1423,6 +1427,9 @@ const union decode_item kprobe_decode_thumb16_table[] = {
1423 1427
1424 DECODE_END 1428 DECODE_END
1425}; 1429};
1430#ifdef CONFIG_ARM_KPROBES_TEST_MODULE
1431EXPORT_SYMBOL_GPL(kprobe_decode_thumb16_table);
1432#endif
1426 1433
1427static unsigned long __kprobes thumb_check_cc(unsigned long cpsr) 1434static unsigned long __kprobes thumb_check_cc(unsigned long cpsr)
1428{ 1435{
diff --git a/arch/arm/kernel/kprobes.h b/arch/arm/kernel/kprobes.h
index a6aeda0a6c7f..38945f78f9f1 100644
--- a/arch/arm/kernel/kprobes.h
+++ b/arch/arm/kernel/kprobes.h
@@ -413,6 +413,14 @@ struct decode_reject {
413 DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0) 413 DECODE_HEADER(DECODE_TYPE_REJECT, _mask, _value, 0)
414 414
415 415
416#ifdef CONFIG_THUMB2_KERNEL
417extern const union decode_item kprobe_decode_thumb16_table[];
418extern const union decode_item kprobe_decode_thumb32_table[];
419#else
420extern const union decode_item kprobe_decode_arm_table[];
421#endif
422
423
416int kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi, 424int kprobe_decode_insn(kprobe_opcode_t insn, struct arch_specific_insn *asi,
417 const union decode_item *table, bool thumb16); 425 const union decode_item *table, bool thumb16);
418 426
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 53c9c2610cbc..e6e5d7c84f1a 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -12,6 +12,7 @@
12 */ 12 */
13#define pr_fmt(fmt) "hw perfevents: " fmt 13#define pr_fmt(fmt) "hw perfevents: " fmt
14 14
15#include <linux/bitmap.h>
15#include <linux/interrupt.h> 16#include <linux/interrupt.h>
16#include <linux/kernel.h> 17#include <linux/kernel.h>
17#include <linux/module.h> 18#include <linux/module.h>
@@ -26,16 +27,8 @@
26#include <asm/pmu.h> 27#include <asm/pmu.h>
27#include <asm/stacktrace.h> 28#include <asm/stacktrace.h>
28 29
29static struct platform_device *pmu_device;
30
31/*
32 * Hardware lock to serialize accesses to PMU registers. Needed for the
33 * read/modify/write sequences.
34 */
35static DEFINE_RAW_SPINLOCK(pmu_lock);
36
37/* 30/*
38 * ARMv6 supports a maximum of 3 events, starting from index 1. If we add 31 * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
39 * another platform that supports more, we need to increase this to be the 32 * another platform that supports more, we need to increase this to be the
40 * largest of all platforms. 33 * largest of all platforms.
41 * 34 *
@@ -43,62 +36,24 @@ static DEFINE_RAW_SPINLOCK(pmu_lock);
43 * cycle counter CCNT + 31 events counters CNT0..30. 36 * cycle counter CCNT + 31 events counters CNT0..30.
44 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters. 37 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
45 */ 38 */
46#define ARMPMU_MAX_HWEVENTS 33 39#define ARMPMU_MAX_HWEVENTS 32
47 40
48/* The events for a given CPU. */ 41static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
49struct cpu_hw_events { 42static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
50 /* 43static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
51 * The events that are active on the CPU for the given index. Index 0
52 * is reserved.
53 */
54 struct perf_event *events[ARMPMU_MAX_HWEVENTS];
55
56 /*
57 * A 1 bit for an index indicates that the counter is being used for
58 * an event. A 0 means that the counter can be used.
59 */
60 unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
61 44
62 /* 45#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
63 * A 1 bit for an index indicates that the counter is actively being
64 * used.
65 */
66 unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
67};
68static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
69
70struct arm_pmu {
71 enum arm_perf_pmu_ids id;
72 const char *name;
73 irqreturn_t (*handle_irq)(int irq_num, void *dev);
74 void (*enable)(struct hw_perf_event *evt, int idx);
75 void (*disable)(struct hw_perf_event *evt, int idx);
76 int (*get_event_idx)(struct cpu_hw_events *cpuc,
77 struct hw_perf_event *hwc);
78 u32 (*read_counter)(int idx);
79 void (*write_counter)(int idx, u32 val);
80 void (*start)(void);
81 void (*stop)(void);
82 void (*reset)(void *);
83 const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
84 [PERF_COUNT_HW_CACHE_OP_MAX]
85 [PERF_COUNT_HW_CACHE_RESULT_MAX];
86 const unsigned (*event_map)[PERF_COUNT_HW_MAX];
87 u32 raw_event_mask;
88 int num_events;
89 u64 max_period;
90};
91 46
92/* Set at runtime when we know what CPU type we are. */ 47/* Set at runtime when we know what CPU type we are. */
93static const struct arm_pmu *armpmu; 48static struct arm_pmu *cpu_pmu;
94 49
95enum arm_perf_pmu_ids 50enum arm_perf_pmu_ids
96armpmu_get_pmu_id(void) 51armpmu_get_pmu_id(void)
97{ 52{
98 int id = -ENODEV; 53 int id = -ENODEV;
99 54
100 if (armpmu != NULL) 55 if (cpu_pmu != NULL)
101 id = armpmu->id; 56 id = cpu_pmu->id;
102 57
103 return id; 58 return id;
104} 59}
@@ -109,8 +64,8 @@ armpmu_get_max_events(void)
109{ 64{
110 int max_events = 0; 65 int max_events = 0;
111 66
112 if (armpmu != NULL) 67 if (cpu_pmu != NULL)
113 max_events = armpmu->num_events; 68 max_events = cpu_pmu->num_events;
114 69
115 return max_events; 70 return max_events;
116} 71}
@@ -130,7 +85,11 @@ EXPORT_SYMBOL_GPL(perf_num_counters);
130#define CACHE_OP_UNSUPPORTED 0xFFFF 85#define CACHE_OP_UNSUPPORTED 0xFFFF
131 86
132static int 87static int
133armpmu_map_cache_event(u64 config) 88armpmu_map_cache_event(const unsigned (*cache_map)
89 [PERF_COUNT_HW_CACHE_MAX]
90 [PERF_COUNT_HW_CACHE_OP_MAX]
91 [PERF_COUNT_HW_CACHE_RESULT_MAX],
92 u64 config)
134{ 93{
135 unsigned int cache_type, cache_op, cache_result, ret; 94 unsigned int cache_type, cache_op, cache_result, ret;
136 95
@@ -146,7 +105,7 @@ armpmu_map_cache_event(u64 config)
146 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 105 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
147 return -EINVAL; 106 return -EINVAL;
148 107
149 ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result]; 108 ret = (int)(*cache_map)[cache_type][cache_op][cache_result];
150 109
151 if (ret == CACHE_OP_UNSUPPORTED) 110 if (ret == CACHE_OP_UNSUPPORTED)
152 return -ENOENT; 111 return -ENOENT;
@@ -155,23 +114,46 @@ armpmu_map_cache_event(u64 config)
155} 114}
156 115
157static int 116static int
158armpmu_map_event(u64 config) 117armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
159{ 118{
160 int mapping = (*armpmu->event_map)[config]; 119 int mapping = (*event_map)[config];
161 return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping; 120 return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
162} 121}
163 122
164static int 123static int
165armpmu_map_raw_event(u64 config) 124armpmu_map_raw_event(u32 raw_event_mask, u64 config)
166{ 125{
167 return (int)(config & armpmu->raw_event_mask); 126 return (int)(config & raw_event_mask);
168} 127}
169 128
170static int 129static int map_cpu_event(struct perf_event *event,
130 const unsigned (*event_map)[PERF_COUNT_HW_MAX],
131 const unsigned (*cache_map)
132 [PERF_COUNT_HW_CACHE_MAX]
133 [PERF_COUNT_HW_CACHE_OP_MAX]
134 [PERF_COUNT_HW_CACHE_RESULT_MAX],
135 u32 raw_event_mask)
136{
137 u64 config = event->attr.config;
138
139 switch (event->attr.type) {
140 case PERF_TYPE_HARDWARE:
141 return armpmu_map_event(event_map, config);
142 case PERF_TYPE_HW_CACHE:
143 return armpmu_map_cache_event(cache_map, config);
144 case PERF_TYPE_RAW:
145 return armpmu_map_raw_event(raw_event_mask, config);
146 }
147
148 return -ENOENT;
149}
150
151int
171armpmu_event_set_period(struct perf_event *event, 152armpmu_event_set_period(struct perf_event *event,
172 struct hw_perf_event *hwc, 153 struct hw_perf_event *hwc,
173 int idx) 154 int idx)
174{ 155{
156 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
175 s64 left = local64_read(&hwc->period_left); 157 s64 left = local64_read(&hwc->period_left);
176 s64 period = hwc->sample_period; 158 s64 period = hwc->sample_period;
177 int ret = 0; 159 int ret = 0;
@@ -202,11 +184,12 @@ armpmu_event_set_period(struct perf_event *event,
202 return ret; 184 return ret;
203} 185}
204 186
205static u64 187u64
206armpmu_event_update(struct perf_event *event, 188armpmu_event_update(struct perf_event *event,
207 struct hw_perf_event *hwc, 189 struct hw_perf_event *hwc,
208 int idx, int overflow) 190 int idx, int overflow)
209{ 191{
192 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
210 u64 delta, prev_raw_count, new_raw_count; 193 u64 delta, prev_raw_count, new_raw_count;
211 194
212again: 195again:
@@ -246,11 +229,9 @@ armpmu_read(struct perf_event *event)
246static void 229static void
247armpmu_stop(struct perf_event *event, int flags) 230armpmu_stop(struct perf_event *event, int flags)
248{ 231{
232 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
249 struct hw_perf_event *hwc = &event->hw; 233 struct hw_perf_event *hwc = &event->hw;
250 234
251 if (!armpmu)
252 return;
253
254 /* 235 /*
255 * ARM pmu always has to update the counter, so ignore 236 * ARM pmu always has to update the counter, so ignore
256 * PERF_EF_UPDATE, see comments in armpmu_start(). 237 * PERF_EF_UPDATE, see comments in armpmu_start().
@@ -266,11 +247,9 @@ armpmu_stop(struct perf_event *event, int flags)
266static void 247static void
267armpmu_start(struct perf_event *event, int flags) 248armpmu_start(struct perf_event *event, int flags)
268{ 249{
250 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
269 struct hw_perf_event *hwc = &event->hw; 251 struct hw_perf_event *hwc = &event->hw;
270 252
271 if (!armpmu)
272 return;
273
274 /* 253 /*
275 * ARM pmu always has to reprogram the period, so ignore 254 * ARM pmu always has to reprogram the period, so ignore
276 * PERF_EF_RELOAD, see the comment below. 255 * PERF_EF_RELOAD, see the comment below.
@@ -293,16 +272,16 @@ armpmu_start(struct perf_event *event, int flags)
293static void 272static void
294armpmu_del(struct perf_event *event, int flags) 273armpmu_del(struct perf_event *event, int flags)
295{ 274{
296 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 275 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
276 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
297 struct hw_perf_event *hwc = &event->hw; 277 struct hw_perf_event *hwc = &event->hw;
298 int idx = hwc->idx; 278 int idx = hwc->idx;
299 279
300 WARN_ON(idx < 0); 280 WARN_ON(idx < 0);
301 281
302 clear_bit(idx, cpuc->active_mask);
303 armpmu_stop(event, PERF_EF_UPDATE); 282 armpmu_stop(event, PERF_EF_UPDATE);
304 cpuc->events[idx] = NULL; 283 hw_events->events[idx] = NULL;
305 clear_bit(idx, cpuc->used_mask); 284 clear_bit(idx, hw_events->used_mask);
306 285
307 perf_event_update_userpage(event); 286 perf_event_update_userpage(event);
308} 287}
@@ -310,7 +289,8 @@ armpmu_del(struct perf_event *event, int flags)
310static int 289static int
311armpmu_add(struct perf_event *event, int flags) 290armpmu_add(struct perf_event *event, int flags)
312{ 291{
313 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 292 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
293 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
314 struct hw_perf_event *hwc = &event->hw; 294 struct hw_perf_event *hwc = &event->hw;
315 int idx; 295 int idx;
316 int err = 0; 296 int err = 0;
@@ -318,7 +298,7 @@ armpmu_add(struct perf_event *event, int flags)
318 perf_pmu_disable(event->pmu); 298 perf_pmu_disable(event->pmu);
319 299
320 /* If we don't have a space for the counter then finish early. */ 300 /* If we don't have a space for the counter then finish early. */
321 idx = armpmu->get_event_idx(cpuc, hwc); 301 idx = armpmu->get_event_idx(hw_events, hwc);
322 if (idx < 0) { 302 if (idx < 0) {
323 err = idx; 303 err = idx;
324 goto out; 304 goto out;
@@ -330,8 +310,7 @@ armpmu_add(struct perf_event *event, int flags)
330 */ 310 */
331 event->hw.idx = idx; 311 event->hw.idx = idx;
332 armpmu->disable(hwc, idx); 312 armpmu->disable(hwc, idx);
333 cpuc->events[idx] = event; 313 hw_events->events[idx] = event;
334 set_bit(idx, cpuc->active_mask);
335 314
336 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE; 315 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
337 if (flags & PERF_EF_START) 316 if (flags & PERF_EF_START)
@@ -345,25 +324,25 @@ out:
345 return err; 324 return err;
346} 325}
347 326
348static struct pmu pmu;
349
350static int 327static int
351validate_event(struct cpu_hw_events *cpuc, 328validate_event(struct pmu_hw_events *hw_events,
352 struct perf_event *event) 329 struct perf_event *event)
353{ 330{
331 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
354 struct hw_perf_event fake_event = event->hw; 332 struct hw_perf_event fake_event = event->hw;
333 struct pmu *leader_pmu = event->group_leader->pmu;
355 334
356 if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF) 335 if (event->pmu != leader_pmu || event->state <= PERF_EVENT_STATE_OFF)
357 return 1; 336 return 1;
358 337
359 return armpmu->get_event_idx(cpuc, &fake_event) >= 0; 338 return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
360} 339}
361 340
362static int 341static int
363validate_group(struct perf_event *event) 342validate_group(struct perf_event *event)
364{ 343{
365 struct perf_event *sibling, *leader = event->group_leader; 344 struct perf_event *sibling, *leader = event->group_leader;
366 struct cpu_hw_events fake_pmu; 345 struct pmu_hw_events fake_pmu;
367 346
368 memset(&fake_pmu, 0, sizeof(fake_pmu)); 347 memset(&fake_pmu, 0, sizeof(fake_pmu));
369 348
@@ -383,110 +362,119 @@ validate_group(struct perf_event *event)
383 362
384static irqreturn_t armpmu_platform_irq(int irq, void *dev) 363static irqreturn_t armpmu_platform_irq(int irq, void *dev)
385{ 364{
386 struct arm_pmu_platdata *plat = dev_get_platdata(&pmu_device->dev); 365 struct arm_pmu *armpmu = (struct arm_pmu *) dev;
366 struct platform_device *plat_device = armpmu->plat_device;
367 struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
387 368
388 return plat->handle_irq(irq, dev, armpmu->handle_irq); 369 return plat->handle_irq(irq, dev, armpmu->handle_irq);
389} 370}
390 371
372static void
373armpmu_release_hardware(struct arm_pmu *armpmu)
374{
375 int i, irq, irqs;
376 struct platform_device *pmu_device = armpmu->plat_device;
377
378 irqs = min(pmu_device->num_resources, num_possible_cpus());
379
380 for (i = 0; i < irqs; ++i) {
381 if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
382 continue;
383 irq = platform_get_irq(pmu_device, i);
384 if (irq >= 0)
385 free_irq(irq, armpmu);
386 }
387
388 release_pmu(armpmu->type);
389}
390
391static int 391static int
392armpmu_reserve_hardware(void) 392armpmu_reserve_hardware(struct arm_pmu *armpmu)
393{ 393{
394 struct arm_pmu_platdata *plat; 394 struct arm_pmu_platdata *plat;
395 irq_handler_t handle_irq; 395 irq_handler_t handle_irq;
396 int i, err = -ENODEV, irq; 396 int i, err, irq, irqs;
397 struct platform_device *pmu_device = armpmu->plat_device;
397 398
398 pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU); 399 err = reserve_pmu(armpmu->type);
399 if (IS_ERR(pmu_device)) { 400 if (err) {
400 pr_warning("unable to reserve pmu\n"); 401 pr_warning("unable to reserve pmu\n");
401 return PTR_ERR(pmu_device); 402 return err;
402 } 403 }
403 404
404 init_pmu(ARM_PMU_DEVICE_CPU);
405
406 plat = dev_get_platdata(&pmu_device->dev); 405 plat = dev_get_platdata(&pmu_device->dev);
407 if (plat && plat->handle_irq) 406 if (plat && plat->handle_irq)
408 handle_irq = armpmu_platform_irq; 407 handle_irq = armpmu_platform_irq;
409 else 408 else
410 handle_irq = armpmu->handle_irq; 409 handle_irq = armpmu->handle_irq;
411 410
412 if (pmu_device->num_resources < 1) { 411 irqs = min(pmu_device->num_resources, num_possible_cpus());
412 if (irqs < 1) {
413 pr_err("no irqs for PMUs defined\n"); 413 pr_err("no irqs for PMUs defined\n");
414 return -ENODEV; 414 return -ENODEV;
415 } 415 }
416 416
417 for (i = 0; i < pmu_device->num_resources; ++i) { 417 for (i = 0; i < irqs; ++i) {
418 err = 0;
418 irq = platform_get_irq(pmu_device, i); 419 irq = platform_get_irq(pmu_device, i);
419 if (irq < 0) 420 if (irq < 0)
420 continue; 421 continue;
421 422
423 /*
424 * If we have a single PMU interrupt that we can't shift,
425 * assume that we're running on a uniprocessor machine and
426 * continue. Otherwise, continue without this interrupt.
427 */
428 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
429 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
430 irq, i);
431 continue;
432 }
433
422 err = request_irq(irq, handle_irq, 434 err = request_irq(irq, handle_irq,
423 IRQF_DISABLED | IRQF_NOBALANCING, 435 IRQF_DISABLED | IRQF_NOBALANCING,
424 "armpmu", NULL); 436 "arm-pmu", armpmu);
425 if (err) { 437 if (err) {
426 pr_warning("unable to request IRQ%d for ARM perf " 438 pr_err("unable to request IRQ%d for ARM PMU counters\n",
427 "counters\n", irq); 439 irq);
428 break; 440 armpmu_release_hardware(armpmu);
441 return err;
429 } 442 }
430 }
431 443
432 if (err) { 444 cpumask_set_cpu(i, &armpmu->active_irqs);
433 for (i = i - 1; i >= 0; --i) {
434 irq = platform_get_irq(pmu_device, i);
435 if (irq >= 0)
436 free_irq(irq, NULL);
437 }
438 release_pmu(ARM_PMU_DEVICE_CPU);
439 pmu_device = NULL;
440 } 445 }
441 446
442 return err; 447 return 0;
443} 448}
444 449
445static void 450static void
446armpmu_release_hardware(void) 451hw_perf_event_destroy(struct perf_event *event)
447{ 452{
448 int i, irq; 453 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
454 atomic_t *active_events = &armpmu->active_events;
455 struct mutex *pmu_reserve_mutex = &armpmu->reserve_mutex;
449 456
450 for (i = pmu_device->num_resources - 1; i >= 0; --i) { 457 if (atomic_dec_and_mutex_lock(active_events, pmu_reserve_mutex)) {
451 irq = platform_get_irq(pmu_device, i); 458 armpmu_release_hardware(armpmu);
452 if (irq >= 0) 459 mutex_unlock(pmu_reserve_mutex);
453 free_irq(irq, NULL);
454 } 460 }
455 armpmu->stop();
456
457 release_pmu(ARM_PMU_DEVICE_CPU);
458 pmu_device = NULL;
459} 461}
460 462
461static atomic_t active_events = ATOMIC_INIT(0); 463static int
462static DEFINE_MUTEX(pmu_reserve_mutex); 464event_requires_mode_exclusion(struct perf_event_attr *attr)
463
464static void
465hw_perf_event_destroy(struct perf_event *event)
466{ 465{
467 if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) { 466 return attr->exclude_idle || attr->exclude_user ||
468 armpmu_release_hardware(); 467 attr->exclude_kernel || attr->exclude_hv;
469 mutex_unlock(&pmu_reserve_mutex);
470 }
471} 468}
472 469
473static int 470static int
474__hw_perf_event_init(struct perf_event *event) 471__hw_perf_event_init(struct perf_event *event)
475{ 472{
473 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
476 struct hw_perf_event *hwc = &event->hw; 474 struct hw_perf_event *hwc = &event->hw;
477 int mapping, err; 475 int mapping, err;
478 476
479 /* Decode the generic type into an ARM event identifier. */ 477 mapping = armpmu->map_event(event);
480 if (PERF_TYPE_HARDWARE == event->attr.type) {
481 mapping = armpmu_map_event(event->attr.config);
482 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
483 mapping = armpmu_map_cache_event(event->attr.config);
484 } else if (PERF_TYPE_RAW == event->attr.type) {
485 mapping = armpmu_map_raw_event(event->attr.config);
486 } else {
487 pr_debug("event type %x not supported\n", event->attr.type);
488 return -EOPNOTSUPP;
489 }
490 478
491 if (mapping < 0) { 479 if (mapping < 0) {
492 pr_debug("event %x:%llx not supported\n", event->attr.type, 480 pr_debug("event %x:%llx not supported\n", event->attr.type,
@@ -495,34 +483,31 @@ __hw_perf_event_init(struct perf_event *event)
495 } 483 }
496 484
497 /* 485 /*
486 * We don't assign an index until we actually place the event onto
487 * hardware. Use -1 to signify that we haven't decided where to put it
488 * yet. For SMP systems, each core has it's own PMU so we can't do any
489 * clever allocation or constraints checking at this point.
490 */
491 hwc->idx = -1;
492 hwc->config_base = 0;
493 hwc->config = 0;
494 hwc->event_base = 0;
495
496 /*
498 * Check whether we need to exclude the counter from certain modes. 497 * Check whether we need to exclude the counter from certain modes.
499 * The ARM performance counters are on all of the time so if someone
500 * has asked us for some excludes then we have to fail.
501 */ 498 */
502 if (event->attr.exclude_kernel || event->attr.exclude_user || 499 if ((!armpmu->set_event_filter ||
503 event->attr.exclude_hv || event->attr.exclude_idle) { 500 armpmu->set_event_filter(hwc, &event->attr)) &&
501 event_requires_mode_exclusion(&event->attr)) {
504 pr_debug("ARM performance counters do not support " 502 pr_debug("ARM performance counters do not support "
505 "mode exclusion\n"); 503 "mode exclusion\n");
506 return -EPERM; 504 return -EPERM;
507 } 505 }
508 506
509 /* 507 /*
510 * We don't assign an index until we actually place the event onto 508 * Store the event encoding into the config_base field.
511 * hardware. Use -1 to signify that we haven't decided where to put it
512 * yet. For SMP systems, each core has it's own PMU so we can't do any
513 * clever allocation or constraints checking at this point.
514 */ 509 */
515 hwc->idx = -1; 510 hwc->config_base |= (unsigned long)mapping;
516
517 /*
518 * Store the event encoding into the config_base field. config and
519 * event_base are unused as the only 2 things we need to know are
520 * the event mapping and the counter to use. The counter to use is
521 * also the indx and the config_base is the event type.
522 */
523 hwc->config_base = (unsigned long)mapping;
524 hwc->config = 0;
525 hwc->event_base = 0;
526 511
527 if (!hwc->sample_period) { 512 if (!hwc->sample_period) {
528 hwc->sample_period = armpmu->max_period; 513 hwc->sample_period = armpmu->max_period;
@@ -542,32 +527,23 @@ __hw_perf_event_init(struct perf_event *event)
542 527
543static int armpmu_event_init(struct perf_event *event) 528static int armpmu_event_init(struct perf_event *event)
544{ 529{
530 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
545 int err = 0; 531 int err = 0;
532 atomic_t *active_events = &armpmu->active_events;
546 533
547 switch (event->attr.type) { 534 if (armpmu->map_event(event) == -ENOENT)
548 case PERF_TYPE_RAW:
549 case PERF_TYPE_HARDWARE:
550 case PERF_TYPE_HW_CACHE:
551 break;
552
553 default:
554 return -ENOENT; 535 return -ENOENT;
555 }
556
557 if (!armpmu)
558 return -ENODEV;
559 536
560 event->destroy = hw_perf_event_destroy; 537 event->destroy = hw_perf_event_destroy;
561 538
562 if (!atomic_inc_not_zero(&active_events)) { 539 if (!atomic_inc_not_zero(active_events)) {
563 mutex_lock(&pmu_reserve_mutex); 540 mutex_lock(&armpmu->reserve_mutex);
564 if (atomic_read(&active_events) == 0) { 541 if (atomic_read(active_events) == 0)
565 err = armpmu_reserve_hardware(); 542 err = armpmu_reserve_hardware(armpmu);
566 }
567 543
568 if (!err) 544 if (!err)
569 atomic_inc(&active_events); 545 atomic_inc(active_events);
570 mutex_unlock(&pmu_reserve_mutex); 546 mutex_unlock(&armpmu->reserve_mutex);
571 } 547 }
572 548
573 if (err) 549 if (err)
@@ -582,22 +558,9 @@ static int armpmu_event_init(struct perf_event *event)
582 558
583static void armpmu_enable(struct pmu *pmu) 559static void armpmu_enable(struct pmu *pmu)
584{ 560{
585 /* Enable all of the perf events on hardware. */ 561 struct arm_pmu *armpmu = to_arm_pmu(pmu);
586 int idx, enabled = 0; 562 struct pmu_hw_events *hw_events = armpmu->get_hw_events();
587 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events); 563 int enabled = bitmap_weight(hw_events->used_mask, armpmu->num_events);
588
589 if (!armpmu)
590 return;
591
592 for (idx = 0; idx <= armpmu->num_events; ++idx) {
593 struct perf_event *event = cpuc->events[idx];
594
595 if (!event)
596 continue;
597
598 armpmu->enable(&event->hw, idx);
599 enabled = 1;
600 }
601 564
602 if (enabled) 565 if (enabled)
603 armpmu->start(); 566 armpmu->start();
@@ -605,20 +568,32 @@ static void armpmu_enable(struct pmu *pmu)
605 568
606static void armpmu_disable(struct pmu *pmu) 569static void armpmu_disable(struct pmu *pmu)
607{ 570{
608 if (armpmu) 571 struct arm_pmu *armpmu = to_arm_pmu(pmu);
609 armpmu->stop(); 572 armpmu->stop();
610} 573}
611 574
612static struct pmu pmu = { 575static void __init armpmu_init(struct arm_pmu *armpmu)
613 .pmu_enable = armpmu_enable, 576{
614 .pmu_disable = armpmu_disable, 577 atomic_set(&armpmu->active_events, 0);
615 .event_init = armpmu_event_init, 578 mutex_init(&armpmu->reserve_mutex);
616 .add = armpmu_add, 579
617 .del = armpmu_del, 580 armpmu->pmu = (struct pmu) {
618 .start = armpmu_start, 581 .pmu_enable = armpmu_enable,
619 .stop = armpmu_stop, 582 .pmu_disable = armpmu_disable,
620 .read = armpmu_read, 583 .event_init = armpmu_event_init,
621}; 584 .add = armpmu_add,
585 .del = armpmu_del,
586 .start = armpmu_start,
587 .stop = armpmu_stop,
588 .read = armpmu_read,
589 };
590}
591
592int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
593{
594 armpmu_init(armpmu);
595 return perf_pmu_register(&armpmu->pmu, name, type);
596}
622 597
623/* Include the PMU-specific implementations. */ 598/* Include the PMU-specific implementations. */
624#include "perf_event_xscale.c" 599#include "perf_event_xscale.c"
@@ -630,14 +605,72 @@ static struct pmu pmu = {
630 * This requires SMP to be available, so exists as a separate initcall. 605 * This requires SMP to be available, so exists as a separate initcall.
631 */ 606 */
632static int __init 607static int __init
633armpmu_reset(void) 608cpu_pmu_reset(void)
609{
610 if (cpu_pmu && cpu_pmu->reset)
611 return on_each_cpu(cpu_pmu->reset, NULL, 1);
612 return 0;
613}
614arch_initcall(cpu_pmu_reset);
615
616/*
617 * PMU platform driver and devicetree bindings.
618 */
619static struct of_device_id armpmu_of_device_ids[] = {
620 {.compatible = "arm,cortex-a9-pmu"},
621 {.compatible = "arm,cortex-a8-pmu"},
622 {.compatible = "arm,arm1136-pmu"},
623 {.compatible = "arm,arm1176-pmu"},
624 {},
625};
626
627static struct platform_device_id armpmu_plat_device_ids[] = {
628 {.name = "arm-pmu"},
629 {},
630};
631
632static int __devinit armpmu_device_probe(struct platform_device *pdev)
634{ 633{
635 if (armpmu && armpmu->reset) 634 cpu_pmu->plat_device = pdev;
636 return on_each_cpu(armpmu->reset, NULL, 1);
637 return 0; 635 return 0;
638} 636}
639arch_initcall(armpmu_reset);
640 637
638static struct platform_driver armpmu_driver = {
639 .driver = {
640 .name = "arm-pmu",
641 .of_match_table = armpmu_of_device_ids,
642 },
643 .probe = armpmu_device_probe,
644 .id_table = armpmu_plat_device_ids,
645};
646
647static int __init register_pmu_driver(void)
648{
649 return platform_driver_register(&armpmu_driver);
650}
651device_initcall(register_pmu_driver);
652
653static struct pmu_hw_events *armpmu_get_cpu_events(void)
654{
655 return &__get_cpu_var(cpu_hw_events);
656}
657
658static void __init cpu_pmu_init(struct arm_pmu *armpmu)
659{
660 int cpu;
661 for_each_possible_cpu(cpu) {
662 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
663 events->events = per_cpu(hw_events, cpu);
664 events->used_mask = per_cpu(used_mask, cpu);
665 raw_spin_lock_init(&events->pmu_lock);
666 }
667 armpmu->get_hw_events = armpmu_get_cpu_events;
668 armpmu->type = ARM_PMU_DEVICE_CPU;
669}
670
671/*
672 * CPU PMU identification and registration.
673 */
641static int __init 674static int __init
642init_hw_perf_events(void) 675init_hw_perf_events(void)
643{ 676{
@@ -651,22 +684,22 @@ init_hw_perf_events(void)
651 case 0xB360: /* ARM1136 */ 684 case 0xB360: /* ARM1136 */
652 case 0xB560: /* ARM1156 */ 685 case 0xB560: /* ARM1156 */
653 case 0xB760: /* ARM1176 */ 686 case 0xB760: /* ARM1176 */
654 armpmu = armv6pmu_init(); 687 cpu_pmu = armv6pmu_init();
655 break; 688 break;
656 case 0xB020: /* ARM11mpcore */ 689 case 0xB020: /* ARM11mpcore */
657 armpmu = armv6mpcore_pmu_init(); 690 cpu_pmu = armv6mpcore_pmu_init();
658 break; 691 break;
659 case 0xC080: /* Cortex-A8 */ 692 case 0xC080: /* Cortex-A8 */
660 armpmu = armv7_a8_pmu_init(); 693 cpu_pmu = armv7_a8_pmu_init();
661 break; 694 break;
662 case 0xC090: /* Cortex-A9 */ 695 case 0xC090: /* Cortex-A9 */
663 armpmu = armv7_a9_pmu_init(); 696 cpu_pmu = armv7_a9_pmu_init();
664 break; 697 break;
665 case 0xC050: /* Cortex-A5 */ 698 case 0xC050: /* Cortex-A5 */
666 armpmu = armv7_a5_pmu_init(); 699 cpu_pmu = armv7_a5_pmu_init();
667 break; 700 break;
668 case 0xC0F0: /* Cortex-A15 */ 701 case 0xC0F0: /* Cortex-A15 */
669 armpmu = armv7_a15_pmu_init(); 702 cpu_pmu = armv7_a15_pmu_init();
670 break; 703 break;
671 } 704 }
672 /* Intel CPUs [xscale]. */ 705 /* Intel CPUs [xscale]. */
@@ -674,23 +707,23 @@ init_hw_perf_events(void)
674 part_number = (cpuid >> 13) & 0x7; 707 part_number = (cpuid >> 13) & 0x7;
675 switch (part_number) { 708 switch (part_number) {
676 case 1: 709 case 1:
677 armpmu = xscale1pmu_init(); 710 cpu_pmu = xscale1pmu_init();
678 break; 711 break;
679 case 2: 712 case 2:
680 armpmu = xscale2pmu_init(); 713 cpu_pmu = xscale2pmu_init();
681 break; 714 break;
682 } 715 }
683 } 716 }
684 717
685 if (armpmu) { 718 if (cpu_pmu) {
686 pr_info("enabled with %s PMU driver, %d counters available\n", 719 pr_info("enabled with %s PMU driver, %d counters available\n",
687 armpmu->name, armpmu->num_events); 720 cpu_pmu->name, cpu_pmu->num_events);
721 cpu_pmu_init(cpu_pmu);
722 armpmu_register(cpu_pmu, "cpu", PERF_TYPE_RAW);
688 } else { 723 } else {
689 pr_info("no hardware support available\n"); 724 pr_info("no hardware support available\n");
690 } 725 }
691 726
692 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
693
694 return 0; 727 return 0;
695} 728}
696early_initcall(init_hw_perf_events); 729early_initcall(init_hw_perf_events);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index dd7f3b9f4cb3..e63d8115c01b 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -54,7 +54,7 @@ enum armv6_perf_types {
54}; 54};
55 55
56enum armv6_counters { 56enum armv6_counters {
57 ARMV6_CYCLE_COUNTER = 1, 57 ARMV6_CYCLE_COUNTER = 0,
58 ARMV6_COUNTER0, 58 ARMV6_COUNTER0,
59 ARMV6_COUNTER1, 59 ARMV6_COUNTER1,
60}; 60};
@@ -433,6 +433,7 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
433 int idx) 433 int idx)
434{ 434{
435 unsigned long val, mask, evt, flags; 435 unsigned long val, mask, evt, flags;
436 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
436 437
437 if (ARMV6_CYCLE_COUNTER == idx) { 438 if (ARMV6_CYCLE_COUNTER == idx) {
438 mask = 0; 439 mask = 0;
@@ -454,12 +455,29 @@ armv6pmu_enable_event(struct hw_perf_event *hwc,
454 * Mask out the current event and set the counter to count the event 455 * Mask out the current event and set the counter to count the event
455 * that we're interested in. 456 * that we're interested in.
456 */ 457 */
457 raw_spin_lock_irqsave(&pmu_lock, flags); 458 raw_spin_lock_irqsave(&events->pmu_lock, flags);
458 val = armv6_pmcr_read(); 459 val = armv6_pmcr_read();
459 val &= ~mask; 460 val &= ~mask;
460 val |= evt; 461 val |= evt;
461 armv6_pmcr_write(val); 462 armv6_pmcr_write(val);
462 raw_spin_unlock_irqrestore(&pmu_lock, flags); 463 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
464}
465
466static int counter_is_active(unsigned long pmcr, int idx)
467{
468 unsigned long mask = 0;
469 if (idx == ARMV6_CYCLE_COUNTER)
470 mask = ARMV6_PMCR_CCOUNT_IEN;
471 else if (idx == ARMV6_COUNTER0)
472 mask = ARMV6_PMCR_COUNT0_IEN;
473 else if (idx == ARMV6_COUNTER1)
474 mask = ARMV6_PMCR_COUNT1_IEN;
475
476 if (mask)
477 return pmcr & mask;
478
479 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
480 return 0;
463} 481}
464 482
465static irqreturn_t 483static irqreturn_t
@@ -468,7 +486,7 @@ armv6pmu_handle_irq(int irq_num,
468{ 486{
469 unsigned long pmcr = armv6_pmcr_read(); 487 unsigned long pmcr = armv6_pmcr_read();
470 struct perf_sample_data data; 488 struct perf_sample_data data;
471 struct cpu_hw_events *cpuc; 489 struct pmu_hw_events *cpuc;
472 struct pt_regs *regs; 490 struct pt_regs *regs;
473 int idx; 491 int idx;
474 492
@@ -487,11 +505,11 @@ armv6pmu_handle_irq(int irq_num,
487 perf_sample_data_init(&data, 0); 505 perf_sample_data_init(&data, 0);
488 506
489 cpuc = &__get_cpu_var(cpu_hw_events); 507 cpuc = &__get_cpu_var(cpu_hw_events);
490 for (idx = 0; idx <= armpmu->num_events; ++idx) { 508 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
491 struct perf_event *event = cpuc->events[idx]; 509 struct perf_event *event = cpuc->events[idx];
492 struct hw_perf_event *hwc; 510 struct hw_perf_event *hwc;
493 511
494 if (!test_bit(idx, cpuc->active_mask)) 512 if (!counter_is_active(pmcr, idx))
495 continue; 513 continue;
496 514
497 /* 515 /*
@@ -508,7 +526,7 @@ armv6pmu_handle_irq(int irq_num,
508 continue; 526 continue;
509 527
510 if (perf_event_overflow(event, &data, regs)) 528 if (perf_event_overflow(event, &data, regs))
511 armpmu->disable(hwc, idx); 529 cpu_pmu->disable(hwc, idx);
512 } 530 }
513 531
514 /* 532 /*
@@ -527,28 +545,30 @@ static void
527armv6pmu_start(void) 545armv6pmu_start(void)
528{ 546{
529 unsigned long flags, val; 547 unsigned long flags, val;
548 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
530 549
531 raw_spin_lock_irqsave(&pmu_lock, flags); 550 raw_spin_lock_irqsave(&events->pmu_lock, flags);
532 val = armv6_pmcr_read(); 551 val = armv6_pmcr_read();
533 val |= ARMV6_PMCR_ENABLE; 552 val |= ARMV6_PMCR_ENABLE;
534 armv6_pmcr_write(val); 553 armv6_pmcr_write(val);
535 raw_spin_unlock_irqrestore(&pmu_lock, flags); 554 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
536} 555}
537 556
538static void 557static void
539armv6pmu_stop(void) 558armv6pmu_stop(void)
540{ 559{
541 unsigned long flags, val; 560 unsigned long flags, val;
561 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
542 562
543 raw_spin_lock_irqsave(&pmu_lock, flags); 563 raw_spin_lock_irqsave(&events->pmu_lock, flags);
544 val = armv6_pmcr_read(); 564 val = armv6_pmcr_read();
545 val &= ~ARMV6_PMCR_ENABLE; 565 val &= ~ARMV6_PMCR_ENABLE;
546 armv6_pmcr_write(val); 566 armv6_pmcr_write(val);
547 raw_spin_unlock_irqrestore(&pmu_lock, flags); 567 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
548} 568}
549 569
550static int 570static int
551armv6pmu_get_event_idx(struct cpu_hw_events *cpuc, 571armv6pmu_get_event_idx(struct pmu_hw_events *cpuc,
552 struct hw_perf_event *event) 572 struct hw_perf_event *event)
553{ 573{
554 /* Always place a cycle counter into the cycle counter. */ 574 /* Always place a cycle counter into the cycle counter. */
@@ -578,6 +598,7 @@ armv6pmu_disable_event(struct hw_perf_event *hwc,
578 int idx) 598 int idx)
579{ 599{
580 unsigned long val, mask, evt, flags; 600 unsigned long val, mask, evt, flags;
601 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
581 602
582 if (ARMV6_CYCLE_COUNTER == idx) { 603 if (ARMV6_CYCLE_COUNTER == idx) {
583 mask = ARMV6_PMCR_CCOUNT_IEN; 604 mask = ARMV6_PMCR_CCOUNT_IEN;
@@ -598,12 +619,12 @@ armv6pmu_disable_event(struct hw_perf_event *hwc,
598 * of ETM bus signal assertion cycles. The external reporting should 619 * of ETM bus signal assertion cycles. The external reporting should
599 * be disabled and so this should never increment. 620 * be disabled and so this should never increment.
600 */ 621 */
601 raw_spin_lock_irqsave(&pmu_lock, flags); 622 raw_spin_lock_irqsave(&events->pmu_lock, flags);
602 val = armv6_pmcr_read(); 623 val = armv6_pmcr_read();
603 val &= ~mask; 624 val &= ~mask;
604 val |= evt; 625 val |= evt;
605 armv6_pmcr_write(val); 626 armv6_pmcr_write(val);
606 raw_spin_unlock_irqrestore(&pmu_lock, flags); 627 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
607} 628}
608 629
609static void 630static void
@@ -611,6 +632,7 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
611 int idx) 632 int idx)
612{ 633{
613 unsigned long val, mask, flags, evt = 0; 634 unsigned long val, mask, flags, evt = 0;
635 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
614 636
615 if (ARMV6_CYCLE_COUNTER == idx) { 637 if (ARMV6_CYCLE_COUNTER == idx) {
616 mask = ARMV6_PMCR_CCOUNT_IEN; 638 mask = ARMV6_PMCR_CCOUNT_IEN;
@@ -627,15 +649,21 @@ armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
627 * Unlike UP ARMv6, we don't have a way of stopping the counters. We 649 * Unlike UP ARMv6, we don't have a way of stopping the counters. We
628 * simply disable the interrupt reporting. 650 * simply disable the interrupt reporting.
629 */ 651 */
630 raw_spin_lock_irqsave(&pmu_lock, flags); 652 raw_spin_lock_irqsave(&events->pmu_lock, flags);
631 val = armv6_pmcr_read(); 653 val = armv6_pmcr_read();
632 val &= ~mask; 654 val &= ~mask;
633 val |= evt; 655 val |= evt;
634 armv6_pmcr_write(val); 656 armv6_pmcr_write(val);
635 raw_spin_unlock_irqrestore(&pmu_lock, flags); 657 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
658}
659
660static int armv6_map_event(struct perf_event *event)
661{
662 return map_cpu_event(event, &armv6_perf_map,
663 &armv6_perf_cache_map, 0xFF);
636} 664}
637 665
638static const struct arm_pmu armv6pmu = { 666static struct arm_pmu armv6pmu = {
639 .id = ARM_PERF_PMU_ID_V6, 667 .id = ARM_PERF_PMU_ID_V6,
640 .name = "v6", 668 .name = "v6",
641 .handle_irq = armv6pmu_handle_irq, 669 .handle_irq = armv6pmu_handle_irq,
@@ -646,14 +674,12 @@ static const struct arm_pmu armv6pmu = {
646 .get_event_idx = armv6pmu_get_event_idx, 674 .get_event_idx = armv6pmu_get_event_idx,
647 .start = armv6pmu_start, 675 .start = armv6pmu_start,
648 .stop = armv6pmu_stop, 676 .stop = armv6pmu_stop,
649 .cache_map = &armv6_perf_cache_map, 677 .map_event = armv6_map_event,
650 .event_map = &armv6_perf_map,
651 .raw_event_mask = 0xFF,
652 .num_events = 3, 678 .num_events = 3,
653 .max_period = (1LLU << 32) - 1, 679 .max_period = (1LLU << 32) - 1,
654}; 680};
655 681
656static const struct arm_pmu *__init armv6pmu_init(void) 682static struct arm_pmu *__init armv6pmu_init(void)
657{ 683{
658 return &armv6pmu; 684 return &armv6pmu;
659} 685}
@@ -665,7 +691,14 @@ static const struct arm_pmu *__init armv6pmu_init(void)
665 * disable the interrupt reporting and update the event. When unthrottling we 691 * disable the interrupt reporting and update the event. When unthrottling we
666 * reset the period and enable the interrupt reporting. 692 * reset the period and enable the interrupt reporting.
667 */ 693 */
668static const struct arm_pmu armv6mpcore_pmu = { 694
695static int armv6mpcore_map_event(struct perf_event *event)
696{
697 return map_cpu_event(event, &armv6mpcore_perf_map,
698 &armv6mpcore_perf_cache_map, 0xFF);
699}
700
701static struct arm_pmu armv6mpcore_pmu = {
669 .id = ARM_PERF_PMU_ID_V6MP, 702 .id = ARM_PERF_PMU_ID_V6MP,
670 .name = "v6mpcore", 703 .name = "v6mpcore",
671 .handle_irq = armv6pmu_handle_irq, 704 .handle_irq = armv6pmu_handle_irq,
@@ -676,24 +709,22 @@ static const struct arm_pmu armv6mpcore_pmu = {
676 .get_event_idx = armv6pmu_get_event_idx, 709 .get_event_idx = armv6pmu_get_event_idx,
677 .start = armv6pmu_start, 710 .start = armv6pmu_start,
678 .stop = armv6pmu_stop, 711 .stop = armv6pmu_stop,
679 .cache_map = &armv6mpcore_perf_cache_map, 712 .map_event = armv6mpcore_map_event,
680 .event_map = &armv6mpcore_perf_map,
681 .raw_event_mask = 0xFF,
682 .num_events = 3, 713 .num_events = 3,
683 .max_period = (1LLU << 32) - 1, 714 .max_period = (1LLU << 32) - 1,
684}; 715};
685 716
686static const struct arm_pmu *__init armv6mpcore_pmu_init(void) 717static struct arm_pmu *__init armv6mpcore_pmu_init(void)
687{ 718{
688 return &armv6mpcore_pmu; 719 return &armv6mpcore_pmu;
689} 720}
690#else 721#else
691static const struct arm_pmu *__init armv6pmu_init(void) 722static struct arm_pmu *__init armv6pmu_init(void)
692{ 723{
693 return NULL; 724 return NULL;
694} 725}
695 726
696static const struct arm_pmu *__init armv6mpcore_pmu_init(void) 727static struct arm_pmu *__init armv6mpcore_pmu_init(void)
697{ 728{
698 return NULL; 729 return NULL;
699} 730}
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index 6be3e2e4d838..1ef6d0034b85 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -17,6 +17,9 @@
17 */ 17 */
18 18
19#ifdef CONFIG_CPU_V7 19#ifdef CONFIG_CPU_V7
20
21static struct arm_pmu armv7pmu;
22
20/* 23/*
21 * Common ARMv7 event types 24 * Common ARMv7 event types
22 * 25 *
@@ -676,23 +679,24 @@ static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
676}; 679};
677 680
678/* 681/*
679 * Perf Events counters 682 * Perf Events' indices
680 */ 683 */
681enum armv7_counters { 684#define ARMV7_IDX_CYCLE_COUNTER 0
682 ARMV7_CYCLE_COUNTER = 1, /* Cycle counter */ 685#define ARMV7_IDX_COUNTER0 1
683 ARMV7_COUNTER0 = 2, /* First event counter */ 686#define ARMV7_IDX_COUNTER_LAST (ARMV7_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
684}; 687
688#define ARMV7_MAX_COUNTERS 32
689#define ARMV7_COUNTER_MASK (ARMV7_MAX_COUNTERS - 1)
685 690
686/* 691/*
687 * The cycle counter is ARMV7_CYCLE_COUNTER. 692 * ARMv7 low level PMNC access
688 * The first event counter is ARMV7_COUNTER0.
689 * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
690 */ 693 */
691#define ARMV7_COUNTER_LAST (ARMV7_COUNTER0 + armpmu->num_events - 1)
692 694
693/* 695/*
694 * ARMv7 low level PMNC access 696 * Perf Event to low level counters mapping
695 */ 697 */
698#define ARMV7_IDX_TO_COUNTER(x) \
699 (((x) - ARMV7_IDX_COUNTER0) & ARMV7_COUNTER_MASK)
696 700
697/* 701/*
698 * Per-CPU PMNC: config reg 702 * Per-CPU PMNC: config reg
@@ -708,103 +712,76 @@ enum armv7_counters {
708#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ 712#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
709 713
710/* 714/*
711 * Available counters 715 * FLAG: counters overflow flag status reg
712 */
713#define ARMV7_CNT0 0 /* First event counter */
714#define ARMV7_CCNT 31 /* Cycle counter */
715
716/* Perf Event to low level counters mapping */
717#define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
718
719/*
720 * CNTENS: counters enable reg
721 */
722#define ARMV7_CNTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
723#define ARMV7_CNTENS_C (1 << ARMV7_CCNT)
724
725/*
726 * CNTENC: counters disable reg
727 */
728#define ARMV7_CNTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
729#define ARMV7_CNTENC_C (1 << ARMV7_CCNT)
730
731/*
732 * INTENS: counters overflow interrupt enable reg
733 */
734#define ARMV7_INTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
735#define ARMV7_INTENS_C (1 << ARMV7_CCNT)
736
737/*
738 * INTENC: counters overflow interrupt disable reg
739 */
740#define ARMV7_INTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
741#define ARMV7_INTENC_C (1 << ARMV7_CCNT)
742
743/*
744 * EVTSEL: Event selection reg
745 */ 716 */
746#define ARMV7_EVTSEL_MASK 0xff /* Mask for writable bits */ 717#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
718#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK
747 719
748/* 720/*
749 * SELECT: Counter selection reg 721 * PMXEVTYPER: Event selection reg
750 */ 722 */
751#define ARMV7_SELECT_MASK 0x1f /* Mask for writable bits */ 723#define ARMV7_EVTYPE_MASK 0xc00000ff /* Mask for writable bits */
724#define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */
752 725
753/* 726/*
754 * FLAG: counters overflow flag status reg 727 * Event filters for PMUv2
755 */ 728 */
756#define ARMV7_FLAG_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx)) 729#define ARMV7_EXCLUDE_PL1 (1 << 31)
757#define ARMV7_FLAG_C (1 << ARMV7_CCNT) 730#define ARMV7_EXCLUDE_USER (1 << 30)
758#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ 731#define ARMV7_INCLUDE_HYP (1 << 27)
759#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK
760 732
761static inline unsigned long armv7_pmnc_read(void) 733static inline u32 armv7_pmnc_read(void)
762{ 734{
763 u32 val; 735 u32 val;
764 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); 736 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
765 return val; 737 return val;
766} 738}
767 739
768static inline void armv7_pmnc_write(unsigned long val) 740static inline void armv7_pmnc_write(u32 val)
769{ 741{
770 val &= ARMV7_PMNC_MASK; 742 val &= ARMV7_PMNC_MASK;
771 isb(); 743 isb();
772 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); 744 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
773} 745}
774 746
775static inline int armv7_pmnc_has_overflowed(unsigned long pmnc) 747static inline int armv7_pmnc_has_overflowed(u32 pmnc)
776{ 748{
777 return pmnc & ARMV7_OVERFLOWED_MASK; 749 return pmnc & ARMV7_OVERFLOWED_MASK;
778} 750}
779 751
780static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc, 752static inline int armv7_pmnc_counter_valid(int idx)
781 enum armv7_counters counter) 753{
754 return idx >= ARMV7_IDX_CYCLE_COUNTER && idx <= ARMV7_IDX_COUNTER_LAST;
755}
756
757static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx)
782{ 758{
783 int ret = 0; 759 int ret = 0;
760 u32 counter;
784 761
785 if (counter == ARMV7_CYCLE_COUNTER) 762 if (!armv7_pmnc_counter_valid(idx)) {
786 ret = pmnc & ARMV7_FLAG_C;
787 else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
788 ret = pmnc & ARMV7_FLAG_P(counter);
789 else
790 pr_err("CPU%u checking wrong counter %d overflow status\n", 763 pr_err("CPU%u checking wrong counter %d overflow status\n",
791 smp_processor_id(), counter); 764 smp_processor_id(), idx);
765 } else {
766 counter = ARMV7_IDX_TO_COUNTER(idx);
767 ret = pmnc & BIT(counter);
768 }
792 769
793 return ret; 770 return ret;
794} 771}
795 772
796static inline int armv7_pmnc_select_counter(unsigned int idx) 773static inline int armv7_pmnc_select_counter(int idx)
797{ 774{
798 u32 val; 775 u32 counter;
799 776
800 if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) { 777 if (!armv7_pmnc_counter_valid(idx)) {
801 pr_err("CPU%u selecting wrong PMNC counter" 778 pr_err("CPU%u selecting wrong PMNC counter %d\n",
802 " %d\n", smp_processor_id(), idx); 779 smp_processor_id(), idx);
803 return -1; 780 return -EINVAL;
804 } 781 }
805 782
806 val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK; 783 counter = ARMV7_IDX_TO_COUNTER(idx);
807 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val)); 784 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (counter));
808 isb(); 785 isb();
809 786
810 return idx; 787 return idx;
@@ -812,124 +789,95 @@ static inline int armv7_pmnc_select_counter(unsigned int idx)
812 789
813static inline u32 armv7pmu_read_counter(int idx) 790static inline u32 armv7pmu_read_counter(int idx)
814{ 791{
815 unsigned long value = 0; 792 u32 value = 0;
816 793
817 if (idx == ARMV7_CYCLE_COUNTER) 794 if (!armv7_pmnc_counter_valid(idx))
818 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
819 else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
820 if (armv7_pmnc_select_counter(idx) == idx)
821 asm volatile("mrc p15, 0, %0, c9, c13, 2"
822 : "=r" (value));
823 } else
824 pr_err("CPU%u reading wrong counter %d\n", 795 pr_err("CPU%u reading wrong counter %d\n",
825 smp_processor_id(), idx); 796 smp_processor_id(), idx);
797 else if (idx == ARMV7_IDX_CYCLE_COUNTER)
798 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
799 else if (armv7_pmnc_select_counter(idx) == idx)
800 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value));
826 801
827 return value; 802 return value;
828} 803}
829 804
830static inline void armv7pmu_write_counter(int idx, u32 value) 805static inline void armv7pmu_write_counter(int idx, u32 value)
831{ 806{
832 if (idx == ARMV7_CYCLE_COUNTER) 807 if (!armv7_pmnc_counter_valid(idx))
833 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
834 else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
835 if (armv7_pmnc_select_counter(idx) == idx)
836 asm volatile("mcr p15, 0, %0, c9, c13, 2"
837 : : "r" (value));
838 } else
839 pr_err("CPU%u writing wrong counter %d\n", 808 pr_err("CPU%u writing wrong counter %d\n",
840 smp_processor_id(), idx); 809 smp_processor_id(), idx);
810 else if (idx == ARMV7_IDX_CYCLE_COUNTER)
811 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
812 else if (armv7_pmnc_select_counter(idx) == idx)
813 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" (value));
841} 814}
842 815
843static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val) 816static inline void armv7_pmnc_write_evtsel(int idx, u32 val)
844{ 817{
845 if (armv7_pmnc_select_counter(idx) == idx) { 818 if (armv7_pmnc_select_counter(idx) == idx) {
846 val &= ARMV7_EVTSEL_MASK; 819 val &= ARMV7_EVTYPE_MASK;
847 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); 820 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
848 } 821 }
849} 822}
850 823
851static inline u32 armv7_pmnc_enable_counter(unsigned int idx) 824static inline int armv7_pmnc_enable_counter(int idx)
852{ 825{
853 u32 val; 826 u32 counter;
854 827
855 if ((idx != ARMV7_CYCLE_COUNTER) && 828 if (!armv7_pmnc_counter_valid(idx)) {
856 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { 829 pr_err("CPU%u enabling wrong PMNC counter %d\n",
857 pr_err("CPU%u enabling wrong PMNC counter" 830 smp_processor_id(), idx);
858 " %d\n", smp_processor_id(), idx); 831 return -EINVAL;
859 return -1;
860 } 832 }
861 833
862 if (idx == ARMV7_CYCLE_COUNTER) 834 counter = ARMV7_IDX_TO_COUNTER(idx);
863 val = ARMV7_CNTENS_C; 835 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(counter)));
864 else
865 val = ARMV7_CNTENS_P(idx);
866
867 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
868
869 return idx; 836 return idx;
870} 837}
871 838
872static inline u32 armv7_pmnc_disable_counter(unsigned int idx) 839static inline int armv7_pmnc_disable_counter(int idx)
873{ 840{
874 u32 val; 841 u32 counter;
875
876 842
877 if ((idx != ARMV7_CYCLE_COUNTER) && 843 if (!armv7_pmnc_counter_valid(idx)) {
878 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { 844 pr_err("CPU%u disabling wrong PMNC counter %d\n",
879 pr_err("CPU%u disabling wrong PMNC counter" 845 smp_processor_id(), idx);
880 " %d\n", smp_processor_id(), idx); 846 return -EINVAL;
881 return -1;
882 } 847 }
883 848
884 if (idx == ARMV7_CYCLE_COUNTER) 849 counter = ARMV7_IDX_TO_COUNTER(idx);
885 val = ARMV7_CNTENC_C; 850 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(counter)));
886 else
887 val = ARMV7_CNTENC_P(idx);
888
889 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
890
891 return idx; 851 return idx;
892} 852}
893 853
894static inline u32 armv7_pmnc_enable_intens(unsigned int idx) 854static inline int armv7_pmnc_enable_intens(int idx)
895{ 855{
896 u32 val; 856 u32 counter;
897 857
898 if ((idx != ARMV7_CYCLE_COUNTER) && 858 if (!armv7_pmnc_counter_valid(idx)) {
899 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { 859 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n",
900 pr_err("CPU%u enabling wrong PMNC counter" 860 smp_processor_id(), idx);
901 " interrupt enable %d\n", smp_processor_id(), idx); 861 return -EINVAL;
902 return -1;
903 } 862 }
904 863
905 if (idx == ARMV7_CYCLE_COUNTER) 864 counter = ARMV7_IDX_TO_COUNTER(idx);
906 val = ARMV7_INTENS_C; 865 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(counter)));
907 else
908 val = ARMV7_INTENS_P(idx);
909
910 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
911
912 return idx; 866 return idx;
913} 867}
914 868
915static inline u32 armv7_pmnc_disable_intens(unsigned int idx) 869static inline int armv7_pmnc_disable_intens(int idx)
916{ 870{
917 u32 val; 871 u32 counter;
918 872
919 if ((idx != ARMV7_CYCLE_COUNTER) && 873 if (!armv7_pmnc_counter_valid(idx)) {
920 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) { 874 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n",
921 pr_err("CPU%u disabling wrong PMNC counter" 875 smp_processor_id(), idx);
922 " interrupt enable %d\n", smp_processor_id(), idx); 876 return -EINVAL;
923 return -1;
924 } 877 }
925 878
926 if (idx == ARMV7_CYCLE_COUNTER) 879 counter = ARMV7_IDX_TO_COUNTER(idx);
927 val = ARMV7_INTENC_C; 880 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(counter)));
928 else
929 val = ARMV7_INTENC_P(idx);
930
931 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
932
933 return idx; 881 return idx;
934} 882}
935 883
@@ -973,14 +921,14 @@ static void armv7_pmnc_dump_regs(void)
973 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); 921 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
974 printk(KERN_INFO "CCNT =0x%08x\n", val); 922 printk(KERN_INFO "CCNT =0x%08x\n", val);
975 923
976 for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) { 924 for (cnt = ARMV7_IDX_COUNTER0; cnt <= ARMV7_IDX_COUNTER_LAST; cnt++) {
977 armv7_pmnc_select_counter(cnt); 925 armv7_pmnc_select_counter(cnt);
978 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); 926 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
979 printk(KERN_INFO "CNT[%d] count =0x%08x\n", 927 printk(KERN_INFO "CNT[%d] count =0x%08x\n",
980 cnt-ARMV7_EVENT_CNT_TO_CNTx, val); 928 ARMV7_IDX_TO_COUNTER(cnt), val);
981 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); 929 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
982 printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n", 930 printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
983 cnt-ARMV7_EVENT_CNT_TO_CNTx, val); 931 ARMV7_IDX_TO_COUNTER(cnt), val);
984 } 932 }
985} 933}
986#endif 934#endif
@@ -988,12 +936,13 @@ static void armv7_pmnc_dump_regs(void)
988static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx) 936static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
989{ 937{
990 unsigned long flags; 938 unsigned long flags;
939 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
991 940
992 /* 941 /*
993 * Enable counter and interrupt, and set the counter to count 942 * Enable counter and interrupt, and set the counter to count
994 * the event that we're interested in. 943 * the event that we're interested in.
995 */ 944 */
996 raw_spin_lock_irqsave(&pmu_lock, flags); 945 raw_spin_lock_irqsave(&events->pmu_lock, flags);
997 946
998 /* 947 /*
999 * Disable counter 948 * Disable counter
@@ -1002,9 +951,10 @@ static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
1002 951
1003 /* 952 /*
1004 * Set event (if destined for PMNx counters) 953 * Set event (if destined for PMNx counters)
1005 * We don't need to set the event if it's a cycle count 954 * We only need to set the event for the cycle counter if we
955 * have the ability to perform event filtering.
1006 */ 956 */
1007 if (idx != ARMV7_CYCLE_COUNTER) 957 if (armv7pmu.set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER)
1008 armv7_pmnc_write_evtsel(idx, hwc->config_base); 958 armv7_pmnc_write_evtsel(idx, hwc->config_base);
1009 959
1010 /* 960 /*
@@ -1017,17 +967,18 @@ static void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
1017 */ 967 */
1018 armv7_pmnc_enable_counter(idx); 968 armv7_pmnc_enable_counter(idx);
1019 969
1020 raw_spin_unlock_irqrestore(&pmu_lock, flags); 970 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1021} 971}
1022 972
1023static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx) 973static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
1024{ 974{
1025 unsigned long flags; 975 unsigned long flags;
976 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1026 977
1027 /* 978 /*
1028 * Disable counter and interrupt 979 * Disable counter and interrupt
1029 */ 980 */
1030 raw_spin_lock_irqsave(&pmu_lock, flags); 981 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1031 982
1032 /* 983 /*
1033 * Disable counter 984 * Disable counter
@@ -1039,14 +990,14 @@ static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
1039 */ 990 */
1040 armv7_pmnc_disable_intens(idx); 991 armv7_pmnc_disable_intens(idx);
1041 992
1042 raw_spin_unlock_irqrestore(&pmu_lock, flags); 993 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1043} 994}
1044 995
1045static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev) 996static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
1046{ 997{
1047 unsigned long pmnc; 998 u32 pmnc;
1048 struct perf_sample_data data; 999 struct perf_sample_data data;
1049 struct cpu_hw_events *cpuc; 1000 struct pmu_hw_events *cpuc;
1050 struct pt_regs *regs; 1001 struct pt_regs *regs;
1051 int idx; 1002 int idx;
1052 1003
@@ -1069,13 +1020,10 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
1069 perf_sample_data_init(&data, 0); 1020 perf_sample_data_init(&data, 0);
1070 1021
1071 cpuc = &__get_cpu_var(cpu_hw_events); 1022 cpuc = &__get_cpu_var(cpu_hw_events);
1072 for (idx = 0; idx <= armpmu->num_events; ++idx) { 1023 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
1073 struct perf_event *event = cpuc->events[idx]; 1024 struct perf_event *event = cpuc->events[idx];
1074 struct hw_perf_event *hwc; 1025 struct hw_perf_event *hwc;
1075 1026
1076 if (!test_bit(idx, cpuc->active_mask))
1077 continue;
1078
1079 /* 1027 /*
1080 * We have a single interrupt for all counters. Check that 1028 * We have a single interrupt for all counters. Check that
1081 * each counter has overflowed before we process it. 1029 * each counter has overflowed before we process it.
@@ -1090,7 +1038,7 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
1090 continue; 1038 continue;
1091 1039
1092 if (perf_event_overflow(event, &data, regs)) 1040 if (perf_event_overflow(event, &data, regs))
1093 armpmu->disable(hwc, idx); 1041 cpu_pmu->disable(hwc, idx);
1094 } 1042 }
1095 1043
1096 /* 1044 /*
@@ -1108,61 +1056,114 @@ static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
1108static void armv7pmu_start(void) 1056static void armv7pmu_start(void)
1109{ 1057{
1110 unsigned long flags; 1058 unsigned long flags;
1059 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1111 1060
1112 raw_spin_lock_irqsave(&pmu_lock, flags); 1061 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1113 /* Enable all counters */ 1062 /* Enable all counters */
1114 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); 1063 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
1115 raw_spin_unlock_irqrestore(&pmu_lock, flags); 1064 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1116} 1065}
1117 1066
1118static void armv7pmu_stop(void) 1067static void armv7pmu_stop(void)
1119{ 1068{
1120 unsigned long flags; 1069 unsigned long flags;
1070 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
1121 1071
1122 raw_spin_lock_irqsave(&pmu_lock, flags); 1072 raw_spin_lock_irqsave(&events->pmu_lock, flags);
1123 /* Disable all counters */ 1073 /* Disable all counters */
1124 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); 1074 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
1125 raw_spin_unlock_irqrestore(&pmu_lock, flags); 1075 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
1126} 1076}
1127 1077
1128static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc, 1078static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc,
1129 struct hw_perf_event *event) 1079 struct hw_perf_event *event)
1130{ 1080{
1131 int idx; 1081 int idx;
1082 unsigned long evtype = event->config_base & ARMV7_EVTYPE_EVENT;
1132 1083
1133 /* Always place a cycle counter into the cycle counter. */ 1084 /* Always place a cycle counter into the cycle counter. */
1134 if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) { 1085 if (evtype == ARMV7_PERFCTR_CPU_CYCLES) {
1135 if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask)) 1086 if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask))
1136 return -EAGAIN; 1087 return -EAGAIN;
1137 1088
1138 return ARMV7_CYCLE_COUNTER; 1089 return ARMV7_IDX_CYCLE_COUNTER;
1139 } else { 1090 }
1140 /*
1141 * For anything other than a cycle counter, try and use
1142 * the events counters
1143 */
1144 for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
1145 if (!test_and_set_bit(idx, cpuc->used_mask))
1146 return idx;
1147 }
1148 1091
1149 /* The counters are all in use. */ 1092 /*
1150 return -EAGAIN; 1093 * For anything other than a cycle counter, try and use
1094 * the events counters
1095 */
1096 for (idx = ARMV7_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
1097 if (!test_and_set_bit(idx, cpuc->used_mask))
1098 return idx;
1151 } 1099 }
1100
1101 /* The counters are all in use. */
1102 return -EAGAIN;
1103}
1104
1105/*
1106 * Add an event filter to a given event. This will only work for PMUv2 PMUs.
1107 */
1108static int armv7pmu_set_event_filter(struct hw_perf_event *event,
1109 struct perf_event_attr *attr)
1110{
1111 unsigned long config_base = 0;
1112
1113 if (attr->exclude_idle)
1114 return -EPERM;
1115 if (attr->exclude_user)
1116 config_base |= ARMV7_EXCLUDE_USER;
1117 if (attr->exclude_kernel)
1118 config_base |= ARMV7_EXCLUDE_PL1;
1119 if (!attr->exclude_hv)
1120 config_base |= ARMV7_INCLUDE_HYP;
1121
1122 /*
1123 * Install the filter into config_base as this is used to
1124 * construct the event type.
1125 */
1126 event->config_base = config_base;
1127
1128 return 0;
1152} 1129}
1153 1130
1154static void armv7pmu_reset(void *info) 1131static void armv7pmu_reset(void *info)
1155{ 1132{
1156 u32 idx, nb_cnt = armpmu->num_events; 1133 u32 idx, nb_cnt = cpu_pmu->num_events;
1157 1134
1158 /* The counter and interrupt enable registers are unknown at reset. */ 1135 /* The counter and interrupt enable registers are unknown at reset. */
1159 for (idx = 1; idx < nb_cnt; ++idx) 1136 for (idx = ARMV7_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx)
1160 armv7pmu_disable_event(NULL, idx); 1137 armv7pmu_disable_event(NULL, idx);
1161 1138
1162 /* Initialize & Reset PMNC: C and P bits */ 1139 /* Initialize & Reset PMNC: C and P bits */
1163 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); 1140 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
1164} 1141}
1165 1142
1143static int armv7_a8_map_event(struct perf_event *event)
1144{
1145 return map_cpu_event(event, &armv7_a8_perf_map,
1146 &armv7_a8_perf_cache_map, 0xFF);
1147}
1148
1149static int armv7_a9_map_event(struct perf_event *event)
1150{
1151 return map_cpu_event(event, &armv7_a9_perf_map,
1152 &armv7_a9_perf_cache_map, 0xFF);
1153}
1154
1155static int armv7_a5_map_event(struct perf_event *event)
1156{
1157 return map_cpu_event(event, &armv7_a5_perf_map,
1158 &armv7_a5_perf_cache_map, 0xFF);
1159}
1160
1161static int armv7_a15_map_event(struct perf_event *event)
1162{
1163 return map_cpu_event(event, &armv7_a15_perf_map,
1164 &armv7_a15_perf_cache_map, 0xFF);
1165}
1166
1166static struct arm_pmu armv7pmu = { 1167static struct arm_pmu armv7pmu = {
1167 .handle_irq = armv7pmu_handle_irq, 1168 .handle_irq = armv7pmu_handle_irq,
1168 .enable = armv7pmu_enable_event, 1169 .enable = armv7pmu_enable_event,
@@ -1173,7 +1174,6 @@ static struct arm_pmu armv7pmu = {
1173 .start = armv7pmu_start, 1174 .start = armv7pmu_start,
1174 .stop = armv7pmu_stop, 1175 .stop = armv7pmu_stop,
1175 .reset = armv7pmu_reset, 1176 .reset = armv7pmu_reset,
1176 .raw_event_mask = 0xFF,
1177 .max_period = (1LLU << 32) - 1, 1177 .max_period = (1LLU << 32) - 1,
1178}; 1178};
1179 1179
@@ -1188,62 +1188,59 @@ static u32 __init armv7_read_num_pmnc_events(void)
1188 return nb_cnt + 1; 1188 return nb_cnt + 1;
1189} 1189}
1190 1190
1191static const struct arm_pmu *__init armv7_a8_pmu_init(void) 1191static struct arm_pmu *__init armv7_a8_pmu_init(void)
1192{ 1192{
1193 armv7pmu.id = ARM_PERF_PMU_ID_CA8; 1193 armv7pmu.id = ARM_PERF_PMU_ID_CA8;
1194 armv7pmu.name = "ARMv7 Cortex-A8"; 1194 armv7pmu.name = "ARMv7 Cortex-A8";
1195 armv7pmu.cache_map = &armv7_a8_perf_cache_map; 1195 armv7pmu.map_event = armv7_a8_map_event;
1196 armv7pmu.event_map = &armv7_a8_perf_map;
1197 armv7pmu.num_events = armv7_read_num_pmnc_events(); 1196 armv7pmu.num_events = armv7_read_num_pmnc_events();
1198 return &armv7pmu; 1197 return &armv7pmu;
1199} 1198}
1200 1199
1201static const struct arm_pmu *__init armv7_a9_pmu_init(void) 1200static struct arm_pmu *__init armv7_a9_pmu_init(void)
1202{ 1201{
1203 armv7pmu.id = ARM_PERF_PMU_ID_CA9; 1202 armv7pmu.id = ARM_PERF_PMU_ID_CA9;
1204 armv7pmu.name = "ARMv7 Cortex-A9"; 1203 armv7pmu.name = "ARMv7 Cortex-A9";
1205 armv7pmu.cache_map = &armv7_a9_perf_cache_map; 1204 armv7pmu.map_event = armv7_a9_map_event;
1206 armv7pmu.event_map = &armv7_a9_perf_map;
1207 armv7pmu.num_events = armv7_read_num_pmnc_events(); 1205 armv7pmu.num_events = armv7_read_num_pmnc_events();
1208 return &armv7pmu; 1206 return &armv7pmu;
1209} 1207}
1210 1208
1211static const struct arm_pmu *__init armv7_a5_pmu_init(void) 1209static struct arm_pmu *__init armv7_a5_pmu_init(void)
1212{ 1210{
1213 armv7pmu.id = ARM_PERF_PMU_ID_CA5; 1211 armv7pmu.id = ARM_PERF_PMU_ID_CA5;
1214 armv7pmu.name = "ARMv7 Cortex-A5"; 1212 armv7pmu.name = "ARMv7 Cortex-A5";
1215 armv7pmu.cache_map = &armv7_a5_perf_cache_map; 1213 armv7pmu.map_event = armv7_a5_map_event;
1216 armv7pmu.event_map = &armv7_a5_perf_map;
1217 armv7pmu.num_events = armv7_read_num_pmnc_events(); 1214 armv7pmu.num_events = armv7_read_num_pmnc_events();
1218 return &armv7pmu; 1215 return &armv7pmu;
1219} 1216}
1220 1217
1221static const struct arm_pmu *__init armv7_a15_pmu_init(void) 1218static struct arm_pmu *__init armv7_a15_pmu_init(void)
1222{ 1219{
1223 armv7pmu.id = ARM_PERF_PMU_ID_CA15; 1220 armv7pmu.id = ARM_PERF_PMU_ID_CA15;
1224 armv7pmu.name = "ARMv7 Cortex-A15"; 1221 armv7pmu.name = "ARMv7 Cortex-A15";
1225 armv7pmu.cache_map = &armv7_a15_perf_cache_map; 1222 armv7pmu.map_event = armv7_a15_map_event;
1226 armv7pmu.event_map = &armv7_a15_perf_map;
1227 armv7pmu.num_events = armv7_read_num_pmnc_events(); 1223 armv7pmu.num_events = armv7_read_num_pmnc_events();
1224 armv7pmu.set_event_filter = armv7pmu_set_event_filter;
1228 return &armv7pmu; 1225 return &armv7pmu;
1229} 1226}
1230#else 1227#else
1231static const struct arm_pmu *__init armv7_a8_pmu_init(void) 1228static struct arm_pmu *__init armv7_a8_pmu_init(void)
1232{ 1229{
1233 return NULL; 1230 return NULL;
1234} 1231}
1235 1232
1236static const struct arm_pmu *__init armv7_a9_pmu_init(void) 1233static struct arm_pmu *__init armv7_a9_pmu_init(void)
1237{ 1234{
1238 return NULL; 1235 return NULL;
1239} 1236}
1240 1237
1241static const struct arm_pmu *__init armv7_a5_pmu_init(void) 1238static struct arm_pmu *__init armv7_a5_pmu_init(void)
1242{ 1239{
1243 return NULL; 1240 return NULL;
1244} 1241}
1245 1242
1246static const struct arm_pmu *__init armv7_a15_pmu_init(void) 1243static struct arm_pmu *__init armv7_a15_pmu_init(void)
1247{ 1244{
1248 return NULL; 1245 return NULL;
1249} 1246}
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index 3c4397491d08..e0cca10a8411 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -40,7 +40,7 @@ enum xscale_perf_types {
40}; 40};
41 41
42enum xscale_counters { 42enum xscale_counters {
43 XSCALE_CYCLE_COUNTER = 1, 43 XSCALE_CYCLE_COUNTER = 0,
44 XSCALE_COUNTER0, 44 XSCALE_COUNTER0,
45 XSCALE_COUNTER1, 45 XSCALE_COUNTER1,
46 XSCALE_COUNTER2, 46 XSCALE_COUNTER2,
@@ -222,7 +222,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
222{ 222{
223 unsigned long pmnc; 223 unsigned long pmnc;
224 struct perf_sample_data data; 224 struct perf_sample_data data;
225 struct cpu_hw_events *cpuc; 225 struct pmu_hw_events *cpuc;
226 struct pt_regs *regs; 226 struct pt_regs *regs;
227 int idx; 227 int idx;
228 228
@@ -249,13 +249,10 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
249 perf_sample_data_init(&data, 0); 249 perf_sample_data_init(&data, 0);
250 250
251 cpuc = &__get_cpu_var(cpu_hw_events); 251 cpuc = &__get_cpu_var(cpu_hw_events);
252 for (idx = 0; idx <= armpmu->num_events; ++idx) { 252 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
253 struct perf_event *event = cpuc->events[idx]; 253 struct perf_event *event = cpuc->events[idx];
254 struct hw_perf_event *hwc; 254 struct hw_perf_event *hwc;
255 255
256 if (!test_bit(idx, cpuc->active_mask))
257 continue;
258
259 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx)) 256 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
260 continue; 257 continue;
261 258
@@ -266,7 +263,7 @@ xscale1pmu_handle_irq(int irq_num, void *dev)
266 continue; 263 continue;
267 264
268 if (perf_event_overflow(event, &data, regs)) 265 if (perf_event_overflow(event, &data, regs))
269 armpmu->disable(hwc, idx); 266 cpu_pmu->disable(hwc, idx);
270 } 267 }
271 268
272 irq_work_run(); 269 irq_work_run();
@@ -284,6 +281,7 @@ static void
284xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx) 281xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
285{ 282{
286 unsigned long val, mask, evt, flags; 283 unsigned long val, mask, evt, flags;
284 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
287 285
288 switch (idx) { 286 switch (idx) {
289 case XSCALE_CYCLE_COUNTER: 287 case XSCALE_CYCLE_COUNTER:
@@ -305,18 +303,19 @@ xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
305 return; 303 return;
306 } 304 }
307 305
308 raw_spin_lock_irqsave(&pmu_lock, flags); 306 raw_spin_lock_irqsave(&events->pmu_lock, flags);
309 val = xscale1pmu_read_pmnc(); 307 val = xscale1pmu_read_pmnc();
310 val &= ~mask; 308 val &= ~mask;
311 val |= evt; 309 val |= evt;
312 xscale1pmu_write_pmnc(val); 310 xscale1pmu_write_pmnc(val);
313 raw_spin_unlock_irqrestore(&pmu_lock, flags); 311 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
314} 312}
315 313
316static void 314static void
317xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx) 315xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
318{ 316{
319 unsigned long val, mask, evt, flags; 317 unsigned long val, mask, evt, flags;
318 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
320 319
321 switch (idx) { 320 switch (idx) {
322 case XSCALE_CYCLE_COUNTER: 321 case XSCALE_CYCLE_COUNTER:
@@ -336,16 +335,16 @@ xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
336 return; 335 return;
337 } 336 }
338 337
339 raw_spin_lock_irqsave(&pmu_lock, flags); 338 raw_spin_lock_irqsave(&events->pmu_lock, flags);
340 val = xscale1pmu_read_pmnc(); 339 val = xscale1pmu_read_pmnc();
341 val &= ~mask; 340 val &= ~mask;
342 val |= evt; 341 val |= evt;
343 xscale1pmu_write_pmnc(val); 342 xscale1pmu_write_pmnc(val);
344 raw_spin_unlock_irqrestore(&pmu_lock, flags); 343 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
345} 344}
346 345
347static int 346static int
348xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc, 347xscale1pmu_get_event_idx(struct pmu_hw_events *cpuc,
349 struct hw_perf_event *event) 348 struct hw_perf_event *event)
350{ 349{
351 if (XSCALE_PERFCTR_CCNT == event->config_base) { 350 if (XSCALE_PERFCTR_CCNT == event->config_base) {
@@ -368,24 +367,26 @@ static void
368xscale1pmu_start(void) 367xscale1pmu_start(void)
369{ 368{
370 unsigned long flags, val; 369 unsigned long flags, val;
370 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
371 371
372 raw_spin_lock_irqsave(&pmu_lock, flags); 372 raw_spin_lock_irqsave(&events->pmu_lock, flags);
373 val = xscale1pmu_read_pmnc(); 373 val = xscale1pmu_read_pmnc();
374 val |= XSCALE_PMU_ENABLE; 374 val |= XSCALE_PMU_ENABLE;
375 xscale1pmu_write_pmnc(val); 375 xscale1pmu_write_pmnc(val);
376 raw_spin_unlock_irqrestore(&pmu_lock, flags); 376 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
377} 377}
378 378
379static void 379static void
380xscale1pmu_stop(void) 380xscale1pmu_stop(void)
381{ 381{
382 unsigned long flags, val; 382 unsigned long flags, val;
383 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
383 384
384 raw_spin_lock_irqsave(&pmu_lock, flags); 385 raw_spin_lock_irqsave(&events->pmu_lock, flags);
385 val = xscale1pmu_read_pmnc(); 386 val = xscale1pmu_read_pmnc();
386 val &= ~XSCALE_PMU_ENABLE; 387 val &= ~XSCALE_PMU_ENABLE;
387 xscale1pmu_write_pmnc(val); 388 xscale1pmu_write_pmnc(val);
388 raw_spin_unlock_irqrestore(&pmu_lock, flags); 389 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
389} 390}
390 391
391static inline u32 392static inline u32
@@ -424,7 +425,13 @@ xscale1pmu_write_counter(int counter, u32 val)
424 } 425 }
425} 426}
426 427
427static const struct arm_pmu xscale1pmu = { 428static int xscale_map_event(struct perf_event *event)
429{
430 return map_cpu_event(event, &xscale_perf_map,
431 &xscale_perf_cache_map, 0xFF);
432}
433
434static struct arm_pmu xscale1pmu = {
428 .id = ARM_PERF_PMU_ID_XSCALE1, 435 .id = ARM_PERF_PMU_ID_XSCALE1,
429 .name = "xscale1", 436 .name = "xscale1",
430 .handle_irq = xscale1pmu_handle_irq, 437 .handle_irq = xscale1pmu_handle_irq,
@@ -435,14 +442,12 @@ static const struct arm_pmu xscale1pmu = {
435 .get_event_idx = xscale1pmu_get_event_idx, 442 .get_event_idx = xscale1pmu_get_event_idx,
436 .start = xscale1pmu_start, 443 .start = xscale1pmu_start,
437 .stop = xscale1pmu_stop, 444 .stop = xscale1pmu_stop,
438 .cache_map = &xscale_perf_cache_map, 445 .map_event = xscale_map_event,
439 .event_map = &xscale_perf_map,
440 .raw_event_mask = 0xFF,
441 .num_events = 3, 446 .num_events = 3,
442 .max_period = (1LLU << 32) - 1, 447 .max_period = (1LLU << 32) - 1,
443}; 448};
444 449
445static const struct arm_pmu *__init xscale1pmu_init(void) 450static struct arm_pmu *__init xscale1pmu_init(void)
446{ 451{
447 return &xscale1pmu; 452 return &xscale1pmu;
448} 453}
@@ -560,7 +565,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
560{ 565{
561 unsigned long pmnc, of_flags; 566 unsigned long pmnc, of_flags;
562 struct perf_sample_data data; 567 struct perf_sample_data data;
563 struct cpu_hw_events *cpuc; 568 struct pmu_hw_events *cpuc;
564 struct pt_regs *regs; 569 struct pt_regs *regs;
565 int idx; 570 int idx;
566 571
@@ -581,13 +586,10 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
581 perf_sample_data_init(&data, 0); 586 perf_sample_data_init(&data, 0);
582 587
583 cpuc = &__get_cpu_var(cpu_hw_events); 588 cpuc = &__get_cpu_var(cpu_hw_events);
584 for (idx = 0; idx <= armpmu->num_events; ++idx) { 589 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
585 struct perf_event *event = cpuc->events[idx]; 590 struct perf_event *event = cpuc->events[idx];
586 struct hw_perf_event *hwc; 591 struct hw_perf_event *hwc;
587 592
588 if (!test_bit(idx, cpuc->active_mask))
589 continue;
590
591 if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx)) 593 if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
592 continue; 594 continue;
593 595
@@ -598,7 +600,7 @@ xscale2pmu_handle_irq(int irq_num, void *dev)
598 continue; 600 continue;
599 601
600 if (perf_event_overflow(event, &data, regs)) 602 if (perf_event_overflow(event, &data, regs))
601 armpmu->disable(hwc, idx); 603 cpu_pmu->disable(hwc, idx);
602 } 604 }
603 605
604 irq_work_run(); 606 irq_work_run();
@@ -616,6 +618,7 @@ static void
616xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx) 618xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
617{ 619{
618 unsigned long flags, ien, evtsel; 620 unsigned long flags, ien, evtsel;
621 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
619 622
620 ien = xscale2pmu_read_int_enable(); 623 ien = xscale2pmu_read_int_enable();
621 evtsel = xscale2pmu_read_event_select(); 624 evtsel = xscale2pmu_read_event_select();
@@ -649,16 +652,17 @@ xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
649 return; 652 return;
650 } 653 }
651 654
652 raw_spin_lock_irqsave(&pmu_lock, flags); 655 raw_spin_lock_irqsave(&events->pmu_lock, flags);
653 xscale2pmu_write_event_select(evtsel); 656 xscale2pmu_write_event_select(evtsel);
654 xscale2pmu_write_int_enable(ien); 657 xscale2pmu_write_int_enable(ien);
655 raw_spin_unlock_irqrestore(&pmu_lock, flags); 658 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
656} 659}
657 660
658static void 661static void
659xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx) 662xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
660{ 663{
661 unsigned long flags, ien, evtsel; 664 unsigned long flags, ien, evtsel;
665 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
662 666
663 ien = xscale2pmu_read_int_enable(); 667 ien = xscale2pmu_read_int_enable();
664 evtsel = xscale2pmu_read_event_select(); 668 evtsel = xscale2pmu_read_event_select();
@@ -692,14 +696,14 @@ xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
692 return; 696 return;
693 } 697 }
694 698
695 raw_spin_lock_irqsave(&pmu_lock, flags); 699 raw_spin_lock_irqsave(&events->pmu_lock, flags);
696 xscale2pmu_write_event_select(evtsel); 700 xscale2pmu_write_event_select(evtsel);
697 xscale2pmu_write_int_enable(ien); 701 xscale2pmu_write_int_enable(ien);
698 raw_spin_unlock_irqrestore(&pmu_lock, flags); 702 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
699} 703}
700 704
701static int 705static int
702xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc, 706xscale2pmu_get_event_idx(struct pmu_hw_events *cpuc,
703 struct hw_perf_event *event) 707 struct hw_perf_event *event)
704{ 708{
705 int idx = xscale1pmu_get_event_idx(cpuc, event); 709 int idx = xscale1pmu_get_event_idx(cpuc, event);
@@ -718,24 +722,26 @@ static void
718xscale2pmu_start(void) 722xscale2pmu_start(void)
719{ 723{
720 unsigned long flags, val; 724 unsigned long flags, val;
725 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
721 726
722 raw_spin_lock_irqsave(&pmu_lock, flags); 727 raw_spin_lock_irqsave(&events->pmu_lock, flags);
723 val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64; 728 val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
724 val |= XSCALE_PMU_ENABLE; 729 val |= XSCALE_PMU_ENABLE;
725 xscale2pmu_write_pmnc(val); 730 xscale2pmu_write_pmnc(val);
726 raw_spin_unlock_irqrestore(&pmu_lock, flags); 731 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
727} 732}
728 733
729static void 734static void
730xscale2pmu_stop(void) 735xscale2pmu_stop(void)
731{ 736{
732 unsigned long flags, val; 737 unsigned long flags, val;
738 struct pmu_hw_events *events = cpu_pmu->get_hw_events();
733 739
734 raw_spin_lock_irqsave(&pmu_lock, flags); 740 raw_spin_lock_irqsave(&events->pmu_lock, flags);
735 val = xscale2pmu_read_pmnc(); 741 val = xscale2pmu_read_pmnc();
736 val &= ~XSCALE_PMU_ENABLE; 742 val &= ~XSCALE_PMU_ENABLE;
737 xscale2pmu_write_pmnc(val); 743 xscale2pmu_write_pmnc(val);
738 raw_spin_unlock_irqrestore(&pmu_lock, flags); 744 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
739} 745}
740 746
741static inline u32 747static inline u32
@@ -786,7 +792,7 @@ xscale2pmu_write_counter(int counter, u32 val)
786 } 792 }
787} 793}
788 794
789static const struct arm_pmu xscale2pmu = { 795static struct arm_pmu xscale2pmu = {
790 .id = ARM_PERF_PMU_ID_XSCALE2, 796 .id = ARM_PERF_PMU_ID_XSCALE2,
791 .name = "xscale2", 797 .name = "xscale2",
792 .handle_irq = xscale2pmu_handle_irq, 798 .handle_irq = xscale2pmu_handle_irq,
@@ -797,24 +803,22 @@ static const struct arm_pmu xscale2pmu = {
797 .get_event_idx = xscale2pmu_get_event_idx, 803 .get_event_idx = xscale2pmu_get_event_idx,
798 .start = xscale2pmu_start, 804 .start = xscale2pmu_start,
799 .stop = xscale2pmu_stop, 805 .stop = xscale2pmu_stop,
800 .cache_map = &xscale_perf_cache_map, 806 .map_event = xscale_map_event,
801 .event_map = &xscale_perf_map,
802 .raw_event_mask = 0xFF,
803 .num_events = 5, 807 .num_events = 5,
804 .max_period = (1LLU << 32) - 1, 808 .max_period = (1LLU << 32) - 1,
805}; 809};
806 810
807static const struct arm_pmu *__init xscale2pmu_init(void) 811static struct arm_pmu *__init xscale2pmu_init(void)
808{ 812{
809 return &xscale2pmu; 813 return &xscale2pmu;
810} 814}
811#else 815#else
812static const struct arm_pmu *__init xscale1pmu_init(void) 816static struct arm_pmu *__init xscale1pmu_init(void)
813{ 817{
814 return NULL; 818 return NULL;
815} 819}
816 820
817static const struct arm_pmu *__init xscale2pmu_init(void) 821static struct arm_pmu *__init xscale2pmu_init(void)
818{ 822{
819 return NULL; 823 return NULL;
820} 824}
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
index c53474fe84df..2c3407ee8576 100644
--- a/arch/arm/kernel/pmu.c
+++ b/arch/arm/kernel/pmu.c
@@ -10,192 +10,26 @@
10 * 10 *
11 */ 11 */
12 12
13#define pr_fmt(fmt) "PMU: " fmt
14
15#include <linux/cpumask.h>
16#include <linux/err.h> 13#include <linux/err.h>
17#include <linux/interrupt.h>
18#include <linux/kernel.h> 14#include <linux/kernel.h>
19#include <linux/module.h> 15#include <linux/module.h>
20#include <linux/of_device.h>
21#include <linux/platform_device.h>
22 16
23#include <asm/pmu.h> 17#include <asm/pmu.h>
24 18
25static volatile long pmu_lock; 19/*
26 20 * PMU locking to ensure mutual exclusion between different subsystems.
27static struct platform_device *pmu_devices[ARM_NUM_PMU_DEVICES]; 21 */
28 22static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)];
29static int __devinit pmu_register(struct platform_device *pdev,
30 enum arm_pmu_type type)
31{
32 if (type < 0 || type >= ARM_NUM_PMU_DEVICES) {
33 pr_warning("received registration request for unknown "
34 "PMU device type %d\n", type);
35 return -EINVAL;
36 }
37
38 if (pmu_devices[type]) {
39 pr_warning("rejecting duplicate registration of PMU device "
40 "type %d.", type);
41 return -ENOSPC;
42 }
43
44 pr_info("registered new PMU device of type %d\n", type);
45 pmu_devices[type] = pdev;
46 return 0;
47}
48
49#define OF_MATCH_PMU(_name, _type) { \
50 .compatible = _name, \
51 .data = (void *)_type, \
52}
53
54#define OF_MATCH_CPU(name) OF_MATCH_PMU(name, ARM_PMU_DEVICE_CPU)
55
56static struct of_device_id armpmu_of_device_ids[] = {
57 OF_MATCH_CPU("arm,cortex-a9-pmu"),
58 OF_MATCH_CPU("arm,cortex-a8-pmu"),
59 OF_MATCH_CPU("arm,arm1136-pmu"),
60 OF_MATCH_CPU("arm,arm1176-pmu"),
61 {},
62};
63
64#define PLAT_MATCH_PMU(_name, _type) { \
65 .name = _name, \
66 .driver_data = _type, \
67}
68
69#define PLAT_MATCH_CPU(_name) PLAT_MATCH_PMU(_name, ARM_PMU_DEVICE_CPU)
70
71static struct platform_device_id armpmu_plat_device_ids[] = {
72 PLAT_MATCH_CPU("arm-pmu"),
73 {},
74};
75
76enum arm_pmu_type armpmu_device_type(struct platform_device *pdev)
77{
78 const struct of_device_id *of_id;
79 const struct platform_device_id *pdev_id;
80
81 /* provided by of_device_id table */
82 if (pdev->dev.of_node) {
83 of_id = of_match_device(armpmu_of_device_ids, &pdev->dev);
84 BUG_ON(!of_id);
85 return (enum arm_pmu_type)of_id->data;
86 }
87
88 /* Provided by platform_device_id table */
89 pdev_id = platform_get_device_id(pdev);
90 BUG_ON(!pdev_id);
91 return pdev_id->driver_data;
92}
93
94static int __devinit armpmu_device_probe(struct platform_device *pdev)
95{
96 return pmu_register(pdev, armpmu_device_type(pdev));
97}
98
99static struct platform_driver armpmu_driver = {
100 .driver = {
101 .name = "arm-pmu",
102 .of_match_table = armpmu_of_device_ids,
103 },
104 .probe = armpmu_device_probe,
105 .id_table = armpmu_plat_device_ids,
106};
107
108static int __init register_pmu_driver(void)
109{
110 return platform_driver_register(&armpmu_driver);
111}
112device_initcall(register_pmu_driver);
113 23
114struct platform_device * 24int
115reserve_pmu(enum arm_pmu_type type) 25reserve_pmu(enum arm_pmu_type type)
116{ 26{
117 struct platform_device *pdev; 27 return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0;
118
119 if (test_and_set_bit_lock(type, &pmu_lock)) {
120 pdev = ERR_PTR(-EBUSY);
121 } else if (pmu_devices[type] == NULL) {
122 clear_bit_unlock(type, &pmu_lock);
123 pdev = ERR_PTR(-ENODEV);
124 } else {
125 pdev = pmu_devices[type];
126 }
127
128 return pdev;
129} 28}
130EXPORT_SYMBOL_GPL(reserve_pmu); 29EXPORT_SYMBOL_GPL(reserve_pmu);
131 30
132int 31void
133release_pmu(enum arm_pmu_type type) 32release_pmu(enum arm_pmu_type type)
134{ 33{
135 if (WARN_ON(!pmu_devices[type])) 34 clear_bit_unlock(type, pmu_lock);
136 return -EINVAL;
137 clear_bit_unlock(type, &pmu_lock);
138 return 0;
139}
140EXPORT_SYMBOL_GPL(release_pmu);
141
142static int
143set_irq_affinity(int irq,
144 unsigned int cpu)
145{
146#ifdef CONFIG_SMP
147 int err = irq_set_affinity(irq, cpumask_of(cpu));
148 if (err)
149 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
150 irq, cpu);
151 return err;
152#else
153 return -EINVAL;
154#endif
155}
156
157static int
158init_cpu_pmu(void)
159{
160 int i, irqs, err = 0;
161 struct platform_device *pdev = pmu_devices[ARM_PMU_DEVICE_CPU];
162
163 if (!pdev)
164 return -ENODEV;
165
166 irqs = pdev->num_resources;
167
168 /*
169 * If we have a single PMU interrupt that we can't shift, assume that
170 * we're running on a uniprocessor machine and continue.
171 */
172 if (irqs == 1 && !irq_can_set_affinity(platform_get_irq(pdev, 0)))
173 return 0;
174
175 for (i = 0; i < irqs; ++i) {
176 err = set_irq_affinity(platform_get_irq(pdev, i), i);
177 if (err)
178 break;
179 }
180
181 return err;
182}
183
184int
185init_pmu(enum arm_pmu_type type)
186{
187 int err = 0;
188
189 switch (type) {
190 case ARM_PMU_DEVICE_CPU:
191 err = init_cpu_pmu();
192 break;
193 default:
194 pr_warning("attempt to initialise PMU of unknown "
195 "type %d\n", type);
196 err = -EINVAL;
197 }
198
199 return err;
200} 35}
201EXPORT_SYMBOL_GPL(init_pmu);
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 3fe93f75b55a..bda0a218f4a5 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -849,25 +849,8 @@ static struct machine_desc * __init setup_machine_tags(unsigned int nr)
849 849
850 if (__atags_pointer) 850 if (__atags_pointer)
851 tags = phys_to_virt(__atags_pointer); 851 tags = phys_to_virt(__atags_pointer);
852 else if (mdesc->boot_params) { 852 else if (mdesc->atag_offset)
853#ifdef CONFIG_MMU 853 tags = (void *)(PAGE_OFFSET + mdesc->atag_offset);
854 /*
855 * We still are executing with a minimal MMU mapping created
856 * with the presumption that the machine default for this
857 * is located in the first MB of RAM. Anything else will
858 * fault and silently hang the kernel at this point.
859 */
860 if (mdesc->boot_params < PHYS_OFFSET ||
861 mdesc->boot_params >= PHYS_OFFSET + SZ_1M) {
862 printk(KERN_WARNING
863 "Default boot params at physical 0x%08lx out of reach\n",
864 mdesc->boot_params);
865 } else
866#endif
867 {
868 tags = phys_to_virt(mdesc->boot_params);
869 }
870 }
871 854
872#if defined(CONFIG_DEPRECATED_PARAM_STRUCT) 855#if defined(CONFIG_DEPRECATED_PARAM_STRUCT)
873 /* 856 /*
diff --git a/arch/arm/kernel/sleep.S b/arch/arm/kernel/sleep.S
index dc902f2c6845..020e99c845e7 100644
--- a/arch/arm/kernel/sleep.S
+++ b/arch/arm/kernel/sleep.S
@@ -8,92 +8,61 @@
8 .text 8 .text
9 9
10/* 10/*
11 * Save CPU state for a suspend 11 * Save CPU state for a suspend. This saves the CPU general purpose
12 * r1 = v:p offset 12 * registers, and allocates space on the kernel stack to save the CPU
13 * r2 = suspend function arg0 13 * specific registers and some other data for resume.
14 * r3 = suspend function 14 * r0 = suspend function arg0
15 * r1 = suspend function
15 */ 16 */
16ENTRY(__cpu_suspend) 17ENTRY(__cpu_suspend)
17 stmfd sp!, {r4 - r11, lr} 18 stmfd sp!, {r4 - r11, lr}
18#ifdef MULTI_CPU 19#ifdef MULTI_CPU
19 ldr r10, =processor 20 ldr r10, =processor
20 ldr r5, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state 21 ldr r4, [r10, #CPU_SLEEP_SIZE] @ size of CPU sleep state
21 ldr ip, [r10, #CPU_DO_RESUME] @ virtual resume function
22#else 22#else
23 ldr r5, =cpu_suspend_size 23 ldr r4, =cpu_suspend_size
24 ldr ip, =cpu_do_resume
25#endif 24#endif
26 mov r6, sp @ current virtual SP 25 mov r5, sp @ current virtual SP
27 sub sp, sp, r5 @ allocate CPU state on stack 26 add r4, r4, #12 @ Space for pgd, virt sp, phys resume fn
28 mov r0, sp @ save pointer to CPU save block 27 sub sp, sp, r4 @ allocate CPU state on stack
29 add ip, ip, r1 @ convert resume fn to phys 28 stmfd sp!, {r0, r1} @ save suspend func arg and pointer
30 stmfd sp!, {r1, r6, ip} @ save v:p, virt SP, phys resume fn 29 add r0, sp, #8 @ save pointer to save block
31 ldr r5, =sleep_save_sp 30 mov r1, r4 @ size of save block
32 add r6, sp, r1 @ convert SP to phys 31 mov r2, r5 @ virtual SP
33 stmfd sp!, {r2, r3} @ save suspend func arg and pointer 32 ldr r3, =sleep_save_sp
34#ifdef CONFIG_SMP 33#ifdef CONFIG_SMP
35 ALT_SMP(mrc p15, 0, lr, c0, c0, 5) 34 ALT_SMP(mrc p15, 0, lr, c0, c0, 5)
36 ALT_UP(mov lr, #0) 35 ALT_UP(mov lr, #0)
37 and lr, lr, #15 36 and lr, lr, #15
38 str r6, [r5, lr, lsl #2] @ save phys SP 37 add r3, r3, lr, lsl #2
39#else
40 str r6, [r5] @ save phys SP
41#endif
42#ifdef MULTI_CPU
43 mov lr, pc
44 ldr pc, [r10, #CPU_DO_SUSPEND] @ save CPU state
45#else
46 bl cpu_do_suspend
47#endif
48
49 @ flush data cache
50#ifdef MULTI_CACHE
51 ldr r10, =cpu_cache
52 mov lr, pc
53 ldr pc, [r10, #CACHE_FLUSH_KERN_ALL]
54#else
55 bl __cpuc_flush_kern_all
56#endif 38#endif
39 bl __cpu_suspend_save
57 adr lr, BSYM(cpu_suspend_abort) 40 adr lr, BSYM(cpu_suspend_abort)
58 ldmfd sp!, {r0, pc} @ call suspend fn 41 ldmfd sp!, {r0, pc} @ call suspend fn
59ENDPROC(__cpu_suspend) 42ENDPROC(__cpu_suspend)
60 .ltorg 43 .ltorg
61 44
62cpu_suspend_abort: 45cpu_suspend_abort:
63 ldmia sp!, {r1 - r3} @ pop v:p, virt SP, phys resume fn 46 ldmia sp!, {r1 - r3} @ pop phys pgd, virt SP, phys resume fn
47 teq r0, #0
48 moveq r0, #1 @ force non-zero value
64 mov sp, r2 49 mov sp, r2
65 ldmfd sp!, {r4 - r11, pc} 50 ldmfd sp!, {r4 - r11, pc}
66ENDPROC(cpu_suspend_abort) 51ENDPROC(cpu_suspend_abort)
67 52
68/* 53/*
69 * r0 = control register value 54 * r0 = control register value
70 * r1 = v:p offset (preserved by cpu_do_resume)
71 * r2 = phys page table base
72 * r3 = L1 section flags
73 */ 55 */
56 .align 5
74ENTRY(cpu_resume_mmu) 57ENTRY(cpu_resume_mmu)
75 adr r4, cpu_resume_turn_mmu_on
76 mov r4, r4, lsr #20
77 orr r3, r3, r4, lsl #20
78 ldr r5, [r2, r4, lsl #2] @ save old mapping
79 str r3, [r2, r4, lsl #2] @ setup 1:1 mapping for mmu code
80 sub r2, r2, r1
81 ldr r3, =cpu_resume_after_mmu 58 ldr r3, =cpu_resume_after_mmu
82 bic r1, r0, #CR_C @ ensure D-cache is disabled 59 mcr p15, 0, r0, c1, c0, 0 @ turn on MMU, I-cache, etc
83 b cpu_resume_turn_mmu_on 60 mrc p15, 0, r0, c0, c0, 0 @ read id reg
84ENDPROC(cpu_resume_mmu) 61 mov r0, r0
85 .ltorg 62 mov r0, r0
86 .align 5
87cpu_resume_turn_mmu_on:
88 mcr p15, 0, r1, c1, c0, 0 @ turn on MMU, I-cache, etc
89 mrc p15, 0, r1, c0, c0, 0 @ read id reg
90 mov r1, r1
91 mov r1, r1
92 mov pc, r3 @ jump to virtual address 63 mov pc, r3 @ jump to virtual address
93ENDPROC(cpu_resume_turn_mmu_on) 64ENDPROC(cpu_resume_mmu)
94cpu_resume_after_mmu: 65cpu_resume_after_mmu:
95 str r5, [r2, r4, lsl #2] @ restore old mapping
96 mcr p15, 0, r0, c1, c0, 0 @ turn on D-cache
97 bl cpu_init @ restore the und/abt/irq banked regs 66 bl cpu_init @ restore the und/abt/irq banked regs
98 mov r0, #0 @ return zero on success 67 mov r0, #0 @ return zero on success
99 ldmfd sp!, {r4 - r11, pc} 68 ldmfd sp!, {r4 - r11, pc}
@@ -119,7 +88,7 @@ ENTRY(cpu_resume)
119 ldr r0, sleep_save_sp @ stack phys addr 88 ldr r0, sleep_save_sp @ stack phys addr
120#endif 89#endif
121 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off 90 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set SVC, irqs off
122 @ load v:p, stack, resume fn 91 @ load phys pgd, stack, resume fn
123 ARM( ldmia r0!, {r1, sp, pc} ) 92 ARM( ldmia r0!, {r1, sp, pc} )
124THUMB( ldmia r0!, {r1, r2, r3} ) 93THUMB( ldmia r0!, {r1, r2, r3} )
125THUMB( mov sp, r2 ) 94THUMB( mov sp, r2 )
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 94f34a6c8610..ef5640b9e218 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -460,10 +460,6 @@ u64 smp_irq_stat_cpu(unsigned int cpu)
460 for (i = 0; i < NR_IPI; i++) 460 for (i = 0; i < NR_IPI; i++)
461 sum += __get_irq_stat(cpu, ipi_irqs[i]); 461 sum += __get_irq_stat(cpu, ipi_irqs[i]);
462 462
463#ifdef CONFIG_LOCAL_TIMERS
464 sum += __get_irq_stat(cpu, local_timer_irqs);
465#endif
466
467 return sum; 463 return sum;
468} 464}
469 465
@@ -480,38 +476,6 @@ static void ipi_timer(void)
480 irq_exit(); 476 irq_exit();
481} 477}
482 478
483#ifdef CONFIG_LOCAL_TIMERS
484asmlinkage void __exception_irq_entry do_local_timer(struct pt_regs *regs)
485{
486 handle_local_timer(regs);
487}
488
489void handle_local_timer(struct pt_regs *regs)
490{
491 struct pt_regs *old_regs = set_irq_regs(regs);
492 int cpu = smp_processor_id();
493
494 if (local_timer_ack()) {
495 __inc_irq_stat(cpu, local_timer_irqs);
496 ipi_timer();
497 }
498
499 set_irq_regs(old_regs);
500}
501
502void show_local_irqs(struct seq_file *p, int prec)
503{
504 unsigned int cpu;
505
506 seq_printf(p, "%*s: ", prec, "LOC");
507
508 for_each_present_cpu(cpu)
509 seq_printf(p, "%10u ", __get_irq_stat(cpu, local_timer_irqs));
510
511 seq_printf(p, " Local timer interrupts\n");
512}
513#endif
514
515#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST 479#ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
516static void smp_timer_broadcast(const struct cpumask *mask) 480static void smp_timer_broadcast(const struct cpumask *mask)
517{ 481{
@@ -562,7 +526,7 @@ static void percpu_timer_stop(void)
562 unsigned int cpu = smp_processor_id(); 526 unsigned int cpu = smp_processor_id();
563 struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu); 527 struct clock_event_device *evt = &per_cpu(percpu_clockevent, cpu);
564 528
565 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); 529 local_timer_stop(evt);
566} 530}
567#endif 531#endif
568 532
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 01c186222f3b..a8a6682d6b52 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -19,6 +19,7 @@
19#include <linux/io.h> 19#include <linux/io.h>
20 20
21#include <asm/smp_twd.h> 21#include <asm/smp_twd.h>
22#include <asm/localtimer.h>
22#include <asm/hardware/gic.h> 23#include <asm/hardware/gic.h>
23 24
24/* set up by the platform code */ 25/* set up by the platform code */
@@ -26,6 +27,8 @@ void __iomem *twd_base;
26 27
27static unsigned long twd_timer_rate; 28static unsigned long twd_timer_rate;
28 29
30static struct clock_event_device __percpu **twd_evt;
31
29static void twd_set_mode(enum clock_event_mode mode, 32static void twd_set_mode(enum clock_event_mode mode,
30 struct clock_event_device *clk) 33 struct clock_event_device *clk)
31{ 34{
@@ -80,6 +83,12 @@ int twd_timer_ack(void)
80 return 0; 83 return 0;
81} 84}
82 85
86void twd_timer_stop(struct clock_event_device *clk)
87{
88 twd_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
89 disable_percpu_irq(clk->irq);
90}
91
83static void __cpuinit twd_calibrate_rate(void) 92static void __cpuinit twd_calibrate_rate(void)
84{ 93{
85 unsigned long count; 94 unsigned long count;
@@ -119,11 +128,43 @@ static void __cpuinit twd_calibrate_rate(void)
119 } 128 }
120} 129}
121 130
131static irqreturn_t twd_handler(int irq, void *dev_id)
132{
133 struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
134
135 if (twd_timer_ack()) {
136 evt->event_handler(evt);
137 return IRQ_HANDLED;
138 }
139
140 return IRQ_NONE;
141}
142
122/* 143/*
123 * Setup the local clock events for a CPU. 144 * Setup the local clock events for a CPU.
124 */ 145 */
125void __cpuinit twd_timer_setup(struct clock_event_device *clk) 146void __cpuinit twd_timer_setup(struct clock_event_device *clk)
126{ 147{
148 struct clock_event_device **this_cpu_clk;
149
150 if (!twd_evt) {
151 int err;
152
153 twd_evt = alloc_percpu(struct clock_event_device *);
154 if (!twd_evt) {
155 pr_err("twd: can't allocate memory\n");
156 return;
157 }
158
159 err = request_percpu_irq(clk->irq, twd_handler,
160 "twd", twd_evt);
161 if (err) {
162 pr_err("twd: can't register interrupt %d (%d)\n",
163 clk->irq, err);
164 return;
165 }
166 }
167
127 twd_calibrate_rate(); 168 twd_calibrate_rate();
128 169
129 clk->name = "local_timer"; 170 clk->name = "local_timer";
@@ -137,8 +178,10 @@ void __cpuinit twd_timer_setup(struct clock_event_device *clk)
137 clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk); 178 clk->max_delta_ns = clockevent_delta2ns(0xffffffff, clk);
138 clk->min_delta_ns = clockevent_delta2ns(0xf, clk); 179 clk->min_delta_ns = clockevent_delta2ns(0xf, clk);
139 180
181 this_cpu_clk = __this_cpu_ptr(twd_evt);
182 *this_cpu_clk = clk;
183
140 clockevents_register_device(clk); 184 clockevents_register_device(clk);
141 185
142 /* Make sure our local interrupt controller has this enabled */ 186 enable_percpu_irq(clk->irq, 0);
143 gic_enable_ppi(clk->irq);
144} 187}
diff --git a/arch/arm/kernel/suspend.c b/arch/arm/kernel/suspend.c
new file mode 100644
index 000000000000..93a22d282c16
--- /dev/null
+++ b/arch/arm/kernel/suspend.c
@@ -0,0 +1,72 @@
1#include <linux/init.h>
2
3#include <asm/pgalloc.h>
4#include <asm/pgtable.h>
5#include <asm/memory.h>
6#include <asm/suspend.h>
7#include <asm/tlbflush.h>
8
9static pgd_t *suspend_pgd;
10
11extern int __cpu_suspend(unsigned long, int (*)(unsigned long));
12extern void cpu_resume_mmu(void);
13
14/*
15 * This is called by __cpu_suspend() to save the state, and do whatever
16 * flushing is required to ensure that when the CPU goes to sleep we have
17 * the necessary data available when the caches are not searched.
18 */
19void __cpu_suspend_save(u32 *ptr, u32 ptrsz, u32 sp, u32 *save_ptr)
20{
21 *save_ptr = virt_to_phys(ptr);
22
23 /* This must correspond to the LDM in cpu_resume() assembly */
24 *ptr++ = virt_to_phys(suspend_pgd);
25 *ptr++ = sp;
26 *ptr++ = virt_to_phys(cpu_do_resume);
27
28 cpu_do_suspend(ptr);
29
30 flush_cache_all();
31 outer_clean_range(*save_ptr, *save_ptr + ptrsz);
32 outer_clean_range(virt_to_phys(save_ptr),
33 virt_to_phys(save_ptr) + sizeof(*save_ptr));
34}
35
36/*
37 * Hide the first two arguments to __cpu_suspend - these are an implementation
38 * detail which platform code shouldn't have to know about.
39 */
40int cpu_suspend(unsigned long arg, int (*fn)(unsigned long))
41{
42 struct mm_struct *mm = current->active_mm;
43 int ret;
44
45 if (!suspend_pgd)
46 return -EINVAL;
47
48 /*
49 * Provide a temporary page table with an identity mapping for
50 * the MMU-enable code, required for resuming. On successful
51 * resume (indicated by a zero return code), we need to switch
52 * back to the correct page tables.
53 */
54 ret = __cpu_suspend(arg, fn);
55 if (ret == 0) {
56 cpu_switch_mm(mm->pgd, mm);
57 local_flush_tlb_all();
58 }
59
60 return ret;
61}
62
63static int __init cpu_suspend_init(void)
64{
65 suspend_pgd = pgd_alloc(&init_mm);
66 if (suspend_pgd) {
67 unsigned long addr = virt_to_phys(cpu_resume_mmu);
68 identity_mapping_add(suspend_pgd, addr, addr + SECTION_SIZE);
69 }
70 return suspend_pgd ? 0 : -ENOMEM;
71}
72core_initcall(cpu_suspend_init);
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index e04c5fb6f1ee..1532b508c814 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -12,6 +12,7 @@
12 12
13#include <linux/module.h> 13#include <linux/module.h>
14#include <linux/pm.h> 14#include <linux/pm.h>
15#include <linux/dma-mapping.h>
15 16
16#include <asm/irq.h> 17#include <asm/irq.h>
17#include <asm/mach/arch.h> 18#include <asm/mach/arch.h>
@@ -319,6 +320,7 @@ static void at91sam9g45_poweroff(void)
319static void __init at91sam9g45_map_io(void) 320static void __init at91sam9g45_map_io(void)
320{ 321{
321 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE); 322 at91_init_sram(0, AT91SAM9G45_SRAM_BASE, AT91SAM9G45_SRAM_SIZE);
323 init_consistent_dma_size(SZ_4M);
322} 324}
323 325
324static void __init at91sam9g45_initialize(void) 326static void __init at91sam9g45_initialize(void)
diff --git a/arch/arm/mach-at91/include/mach/at91sam9g45.h b/arch/arm/mach-at91/include/mach/at91sam9g45.h
index 2c611b9a0138..406bb6496805 100644
--- a/arch/arm/mach-at91/include/mach/at91sam9g45.h
+++ b/arch/arm/mach-at91/include/mach/at91sam9g45.h
@@ -128,8 +128,6 @@
128#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */ 128#define AT91SAM9G45_EHCI_BASE 0x00800000 /* USB Host controller (EHCI) */
129#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */ 129#define AT91SAM9G45_VDEC_BASE 0x00900000 /* Video Decoder Controller */
130 130
131#define CONSISTENT_DMA_SIZE SZ_4M
132
133/* 131/*
134 * DMA peripheral identifiers 132 * DMA peripheral identifiers
135 * for hardware handshaking interface 133 * for hardware handshaking interface
diff --git a/arch/arm/mach-at91/include/mach/debug-macro.S b/arch/arm/mach-at91/include/mach/debug-macro.S
index bc1e0b2e2f4f..0ed8648c6452 100644
--- a/arch/arm/mach-at91/include/mach/debug-macro.S
+++ b/arch/arm/mach-at91/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/at91_dbgu.h> 15#include <mach/at91_dbgu.h>
16 16
17 .macro addruart, rp, rv 17 .macro addruart, rp, rv, tmp
18 ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address) 18 ldr \rp, =(AT91_BASE_SYS + AT91_DBGU) @ System peripherals (phys address)
19 ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address) 19 ldr \rv, =(AT91_VA_BASE_SYS + AT91_DBGU) @ System peripherals (virt address)
20 .endm 20 .endm
diff --git a/arch/arm/mach-bcmring/include/mach/hardware.h b/arch/arm/mach-bcmring/include/mach/hardware.h
index ed78aabb8e9f..6ae20a649a97 100644
--- a/arch/arm/mach-bcmring/include/mach/hardware.h
+++ b/arch/arm/mach-bcmring/include/mach/hardware.h
@@ -22,7 +22,6 @@
22#define __ASM_ARCH_HARDWARE_H 22#define __ASM_ARCH_HARDWARE_H
23 23
24#include <asm/sizes.h> 24#include <asm/sizes.h>
25#include <mach/memory.h>
26#include <cfg_global.h> 25#include <cfg_global.h>
27#include <mach/csp/mm_io.h> 26#include <mach/csp/mm_io.h>
28 27
@@ -31,7 +30,7 @@
31 * *_SIZE is the size of the region 30 * *_SIZE is the size of the region
32 * *_BASE is the virtual address 31 * *_BASE is the virtual address
33 */ 32 */
34#define RAM_START PLAT_PHYS_OFFSET 33#define RAM_START PHYS_OFFSET
35 34
36#define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED) 35#define RAM_SIZE (CFG_GLOBAL_RAM_SIZE-CFG_GLOBAL_RAM_SIZE_RESERVED)
37#define RAM_BASE PAGE_OFFSET 36#define RAM_BASE PAGE_OFFSET
diff --git a/arch/arm/mach-bcmring/include/mach/memory.h b/arch/arm/mach-bcmring/include/mach/memory.h
deleted file mode 100644
index 15162e4c75f9..000000000000
--- a/arch/arm/mach-bcmring/include/mach/memory.h
+++ /dev/null
@@ -1,33 +0,0 @@
1/*****************************************************************************
2* Copyright 2005 - 2008 Broadcom Corporation. All rights reserved.
3*
4* Unless you and Broadcom execute a separate written software license
5* agreement governing use of this software, this software is licensed to you
6* under the terms of the GNU General Public License version 2, available at
7* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
8*
9* Notwithstanding the above, under no circumstances may you combine this
10* software in any way with any other Broadcom software provided under a
11* license other than the GPL, without Broadcom's express prior written
12* consent.
13*****************************************************************************/
14
15#ifndef __ASM_ARCH_MEMORY_H
16#define __ASM_ARCH_MEMORY_H
17
18#include <cfg_global.h>
19
20/*
21 * Physical vs virtual RAM address space conversion. These are
22 * private definitions which should NOT be used outside memory.h
23 * files. Use virt_to_phys/phys_to_virt/__pa/__va instead.
24 */
25
26#define PLAT_PHYS_OFFSET CFG_GLOBAL_RAM_BASE
27
28/*
29 * Maximum DMA memory allowed is 14M
30 */
31#define CONSISTENT_DMA_SIZE (SZ_16M - SZ_2M)
32
33#endif
diff --git a/arch/arm/mach-bcmring/mm.c b/arch/arm/mach-bcmring/mm.c
index 0f1c37e4523a..8616876abb9f 100644
--- a/arch/arm/mach-bcmring/mm.c
+++ b/arch/arm/mach-bcmring/mm.c
@@ -13,6 +13,7 @@
13*****************************************************************************/ 13*****************************************************************************/
14 14
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/dma-mapping.h>
16#include <asm/mach/map.h> 17#include <asm/mach/map.h>
17 18
18#include <mach/hardware.h> 19#include <mach/hardware.h>
@@ -53,4 +54,6 @@ void __init bcmring_map_io(void)
53{ 54{
54 55
55 iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc)); 56 iotable_init(bcmring_io_desc, ARRAY_SIZE(bcmring_io_desc));
57 /* Maximum DMA memory allowed is 14M */
58 init_consistent_dma_size(14 << 20);
56} 59}
diff --git a/arch/arm/mach-clps711x/autcpu12.c b/arch/arm/mach-clps711x/autcpu12.c
index 4a74b2c959bd..0276091b7f86 100644
--- a/arch/arm/mach-clps711x/autcpu12.c
+++ b/arch/arm/mach-clps711x/autcpu12.c
@@ -64,7 +64,7 @@ void __init autcpu12_map_io(void)
64 64
65MACHINE_START(AUTCPU12, "autronix autcpu12") 65MACHINE_START(AUTCPU12, "autronix autcpu12")
66 /* Maintainer: Thomas Gleixner */ 66 /* Maintainer: Thomas Gleixner */
67 .boot_params = 0xc0020000, 67 .atag_offset = 0x20000,
68 .map_io = autcpu12_map_io, 68 .map_io = autcpu12_map_io,
69 .init_irq = clps711x_init_irq, 69 .init_irq = clps711x_init_irq,
70 .timer = &clps711x_timer, 70 .timer = &clps711x_timer,
diff --git a/arch/arm/mach-clps711x/cdb89712.c b/arch/arm/mach-clps711x/cdb89712.c
index 5a1689d48793..25b3bfd0e85a 100644
--- a/arch/arm/mach-clps711x/cdb89712.c
+++ b/arch/arm/mach-clps711x/cdb89712.c
@@ -55,7 +55,7 @@ static void __init cdb89712_map_io(void)
55 55
56MACHINE_START(CDB89712, "Cirrus-CDB89712") 56MACHINE_START(CDB89712, "Cirrus-CDB89712")
57 /* Maintainer: Ray Lehtiniemi */ 57 /* Maintainer: Ray Lehtiniemi */
58 .boot_params = 0xc0000100, 58 .atag_offset = 0x100,
59 .map_io = cdb89712_map_io, 59 .map_io = cdb89712_map_io,
60 .init_irq = clps711x_init_irq, 60 .init_irq = clps711x_init_irq,
61 .timer = &clps711x_timer, 61 .timer = &clps711x_timer,
diff --git a/arch/arm/mach-clps711x/ceiva.c b/arch/arm/mach-clps711x/ceiva.c
index 16481cf3e931..1df9ec67aa92 100644
--- a/arch/arm/mach-clps711x/ceiva.c
+++ b/arch/arm/mach-clps711x/ceiva.c
@@ -56,7 +56,7 @@ static void __init ceiva_map_io(void)
56 56
57MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame") 57MACHINE_START(CEIVA, "CEIVA/Polaroid Photo MAX Digital Picture Frame")
58 /* Maintainer: Rob Scott */ 58 /* Maintainer: Rob Scott */
59 .boot_params = 0xc0000100, 59 .atag_offset = 0x100,
60 .map_io = ceiva_map_io, 60 .map_io = ceiva_map_io,
61 .init_irq = clps711x_init_irq, 61 .init_irq = clps711x_init_irq,
62 .timer = &clps711x_timer, 62 .timer = &clps711x_timer,
diff --git a/arch/arm/mach-clps711x/clep7312.c b/arch/arm/mach-clps711x/clep7312.c
index 0a2e74feb24a..80496c09ac59 100644
--- a/arch/arm/mach-clps711x/clep7312.c
+++ b/arch/arm/mach-clps711x/clep7312.c
@@ -36,7 +36,7 @@ fixup_clep7312(struct tag *tags, char **cmdline, struct meminfo *mi)
36 36
37MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312") 37MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312")
38 /* Maintainer: Nobody */ 38 /* Maintainer: Nobody */
39 .boot_params = 0xc0000100, 39 .atag_offset = 0x0100,
40 .fixup = fixup_clep7312, 40 .fixup = fixup_clep7312,
41 .map_io = clps711x_map_io, 41 .map_io = clps711x_map_io,
42 .init_irq = clps711x_init_irq, 42 .init_irq = clps711x_init_irq,
diff --git a/arch/arm/mach-clps711x/edb7211-arch.c b/arch/arm/mach-clps711x/edb7211-arch.c
index 725a7a54ba42..9721f6111dc0 100644
--- a/arch/arm/mach-clps711x/edb7211-arch.c
+++ b/arch/arm/mach-clps711x/edb7211-arch.c
@@ -56,7 +56,7 @@ fixup_edb7211(struct tag *tags, char **cmdline, struct meminfo *mi)
56 56
57MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") 57MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)")
58 /* Maintainer: Jon McClintock */ 58 /* Maintainer: Jon McClintock */
59 .boot_params = 0xc0020100, /* 0xc0000000 - 0xc001ffff can be video RAM */ 59 .atag_offset = 0x20100, /* 0xc0000000 - 0xc001ffff can be video RAM */
60 .fixup = fixup_edb7211, 60 .fixup = fixup_edb7211,
61 .map_io = edb7211_map_io, 61 .map_io = edb7211_map_io,
62 .reserve = edb7211_reserve, 62 .reserve = edb7211_reserve,
diff --git a/arch/arm/mach-clps711x/fortunet.c b/arch/arm/mach-clps711x/fortunet.c
index 1947b30f9b8c..d99256687298 100644
--- a/arch/arm/mach-clps711x/fortunet.c
+++ b/arch/arm/mach-clps711x/fortunet.c
@@ -74,7 +74,6 @@ fortunet_fixup(struct tag *tags, char **cmdline, struct meminfo *mi)
74 74
75MACHINE_START(FORTUNET, "ARM-FortuNet") 75MACHINE_START(FORTUNET, "ARM-FortuNet")
76 /* Maintainer: FortuNet Inc. */ 76 /* Maintainer: FortuNet Inc. */
77 .boot_params = 0x00000000,
78 .fixup = fortunet_fixup, 77 .fixup = fortunet_fixup,
79 .map_io = clps711x_map_io, 78 .map_io = clps711x_map_io,
80 .init_irq = clps711x_init_irq, 79 .init_irq = clps711x_init_irq,
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S
index 507c6873b7ee..b802e8a51831 100644
--- a/arch/arm/mach-clps711x/include/mach/debug-macro.S
+++ b/arch/arm/mach-clps711x/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <asm/hardware/clps7111.h> 15#include <asm/hardware/clps7111.h>
16 16
17 .macro addruart, rp, rv 17 .macro addruart, rp, rv, tmp
18#ifndef CONFIG_DEBUG_CLPS711X_UART2 18#ifndef CONFIG_DEBUG_CLPS711X_UART2
19 mov \rp, #0x0000 @ UART1 19 mov \rp, #0x0000 @ UART1
20#else 20#else
diff --git a/arch/arm/mach-clps711x/p720t.c b/arch/arm/mach-clps711x/p720t.c
index 3f796e0d3284..6ecea95f38b2 100644
--- a/arch/arm/mach-clps711x/p720t.c
+++ b/arch/arm/mach-clps711x/p720t.c
@@ -88,7 +88,7 @@ static void __init p720t_map_io(void)
88 88
89MACHINE_START(P720T, "ARM-Prospector720T") 89MACHINE_START(P720T, "ARM-Prospector720T")
90 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 90 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
91 .boot_params = 0xc0000100, 91 .atag_offset = 0x100,
92 .fixup = fixup_p720t, 92 .fixup = fixup_p720t,
93 .map_io = p720t_map_io, 93 .map_io = p720t_map_io,
94 .init_irq = clps711x_init_irq, 94 .init_irq = clps711x_init_irq,
diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c
index 3e7d1496cb47..55f7b4b08ab9 100644
--- a/arch/arm/mach-cns3xxx/cns3420vb.c
+++ b/arch/arm/mach-cns3xxx/cns3420vb.c
@@ -197,7 +197,7 @@ static void __init cns3420_map_io(void)
197} 197}
198 198
199MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") 199MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board")
200 .boot_params = 0x00000100, 200 .atag_offset = 0x100,
201 .map_io = cns3420_map_io, 201 .map_io = cns3420_map_io,
202 .init_irq = cns3xxx_init_irq, 202 .init_irq = cns3xxx_init_irq,
203 .timer = &cns3xxx_timer, 203 .timer = &cns3xxx_timer,
diff --git a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
index 56d828634db5..d04c150baa1c 100644
--- a/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
+++ b/arch/arm/mach-cns3xxx/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 */ 11 */
12 12
13 .macro addruart,rp,rv 13 .macro addruart,rp,rv,tmp
14 mov \rp, #0x00009000 14 mov \rp, #0x00009000
15 orr \rv, \rp, #0xf0000000 @ virtual base 15 orr \rv, \rp, #0xf0000000 @ virtual base
16 orr \rp, \rp, #0x10000000 16 orr \rp, \rp, #0x10000000
diff --git a/arch/arm/mach-cns3xxx/include/mach/memory.h b/arch/arm/mach-cns3xxx/include/mach/memory.h
deleted file mode 100644
index dc16c5c5d86b..000000000000
--- a/arch/arm/mach-cns3xxx/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright 2003 ARM Limited
3 * Copyright 2008 Cavium Networks
4 *
5 * This file is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License, Version 2, as
7 * published by the Free Software Foundation.
8 */
9
10#ifndef __MACH_MEMORY_H
11#define __MACH_MEMORY_H
12
13/*
14 * Physical DRAM offset.
15 */
16#define PLAT_PHYS_OFFSET UL(0x00000000)
17
18#define __phys_to_bus(x) ((x) + PHYS_OFFSET)
19#define __bus_to_phys(x) ((x) - PHYS_OFFSET)
20
21#define __virt_to_bus(v) __phys_to_bus(__virt_to_phys(v))
22#define __bus_to_virt(b) __phys_to_virt(__bus_to_phys(b))
23#define __pfn_to_bus(p) __phys_to_bus(__pfn_to_phys(p))
24#define __bus_to_pfn(b) __phys_to_pfn(__bus_to_phys(b))
25
26#endif
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index 84fd78684868..26d94c0b555c 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -676,7 +676,7 @@ static void __init da830_evm_map_io(void)
676} 676}
677 677
678MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") 678MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
679 .boot_params = (DA8XX_DDR_BASE + 0x100), 679 .atag_offset = 0x100,
680 .map_io = da830_evm_map_io, 680 .map_io = da830_evm_map_io,
681 .init_irq = cp_intc_init, 681 .init_irq = cp_intc_init,
682 .timer = &davinci_timer, 682 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 008d51407cd7..6e41cb5baeb4 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1291,7 +1291,7 @@ static void __init da850_evm_map_io(void)
1291} 1291}
1292 1292
1293MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") 1293MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
1294 .boot_params = (DA8XX_DDR_BASE + 0x100), 1294 .atag_offset = 0x100,
1295 .map_io = da850_evm_map_io, 1295 .map_io = da850_evm_map_io,
1296 .init_irq = cp_intc_init, 1296 .init_irq = cp_intc_init,
1297 .timer = &davinci_timer, 1297 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index 241a6bd67408..65566280b7c9 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -351,7 +351,7 @@ static __init void dm355_evm_init(void)
351} 351}
352 352
353MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") 353MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
354 .boot_params = (0x80000100), 354 .atag_offset = 0x100,
355 .map_io = dm355_evm_map_io, 355 .map_io = dm355_evm_map_io,
356 .init_irq = davinci_irq_init, 356 .init_irq = davinci_irq_init,
357 .timer = &davinci_timer, 357 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index bee284ca7fd6..b307470b071d 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -270,7 +270,7 @@ static __init void dm355_leopard_init(void)
270} 270}
271 271
272MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") 272MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
273 .boot_params = (0x80000100), 273 .atag_offset = 0x100,
274 .map_io = dm355_leopard_map_io, 274 .map_io = dm355_leopard_map_io,
275 .init_irq = davinci_irq_init, 275 .init_irq = davinci_irq_init,
276 .timer = &davinci_timer, 276 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 9818f214d4f0..04c43abcca66 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -612,7 +612,7 @@ static __init void dm365_evm_init(void)
612} 612}
613 613
614MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") 614MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
615 .boot_params = (0x80000100), 615 .atag_offset = 0x100,
616 .map_io = dm365_evm_map_io, 616 .map_io = dm365_evm_map_io,
617 .init_irq = davinci_irq_init, 617 .init_irq = davinci_irq_init,
618 .timer = &davinci_timer, 618 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 95607a191e03..a005e7691ddd 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -712,7 +712,7 @@ static __init void davinci_evm_init(void)
712 712
713MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM") 713MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
714 /* Maintainer: MontaVista Software <source@mvista.com> */ 714 /* Maintainer: MontaVista Software <source@mvista.com> */
715 .boot_params = (DAVINCI_DDR_BASE + 0x100), 715 .atag_offset = 0x100,
716 .map_io = davinci_evm_map_io, 716 .map_io = davinci_evm_map_io,
717 .init_irq = davinci_irq_init, 717 .init_irq = davinci_irq_init,
718 .timer = &davinci_timer, 718 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 993a3146fd35..337c45e3e44d 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -792,7 +792,7 @@ static __init void evm_init(void)
792} 792}
793 793
794MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM") 794MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
795 .boot_params = (0x80000100), 795 .atag_offset = 0x100,
796 .map_io = davinci_map_io, 796 .map_io = davinci_map_io,
797 .init_irq = davinci_irq_init, 797 .init_irq = davinci_irq_init,
798 .timer = &davinci_timer, 798 .timer = &davinci_timer,
@@ -801,7 +801,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
801MACHINE_END 801MACHINE_END
802 802
803MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM") 803MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
804 .boot_params = (0x80000100), 804 .atag_offset = 0x100,
805 .map_io = davinci_map_io, 805 .map_io = davinci_map_io,
806 .init_irq = davinci_irq_init, 806 .init_irq = davinci_irq_init,
807 .timer = &davinci_timer, 807 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index c278226627ad..6efc84cceca0 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -566,7 +566,7 @@ static void __init mityomapl138_map_io(void)
566} 566}
567 567
568MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") 568MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
569 .boot_params = (DA8XX_DDR_BASE + 0x100), 569 .atag_offset = 0x100,
570 .map_io = mityomapl138_map_io, 570 .map_io = mityomapl138_map_io,
571 .init_irq = cp_intc_init, 571 .init_irq = cp_intc_init,
572 .timer = &davinci_timer, 572 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index d60a80028ba3..38d6f644d8b9 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -272,7 +272,7 @@ static __init void davinci_ntosd2_init(void)
272 272
273MACHINE_START(NEUROS_OSD2, "Neuros OSD2") 273MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
274 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */ 274 /* Maintainer: Neuros Technologies <neuros@groups.google.com> */
275 .boot_params = (DAVINCI_DDR_BASE + 0x100), 275 .atag_offset = 0x100,
276 .map_io = davinci_ntosd2_map_io, 276 .map_io = davinci_ntosd2_map_io,
277 .init_irq = davinci_irq_init, 277 .init_irq = davinci_irq_init,
278 .timer = &davinci_timer, 278 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 237332a11421..c6701e4a795c 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -338,7 +338,7 @@ static void __init omapl138_hawk_map_io(void)
338} 338}
339 339
340MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard") 340MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
341 .boot_params = (DA8XX_DDR_BASE + 0x100), 341 .atag_offset = 0x100,
342 .map_io = omapl138_hawk_map_io, 342 .map_io = omapl138_hawk_map_io,
343 .init_irq = cp_intc_init, 343 .init_irq = cp_intc_init,
344 .timer = &davinci_timer, 344 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 5f4385c0a089..5dd4da9d2308 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -151,7 +151,7 @@ static __init void davinci_sffsdr_init(void)
151 151
152MACHINE_START(SFFSDR, "Lyrtech SFFSDR") 152MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
153 /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */ 153 /* Maintainer: Hugo Villeneuve hugo.villeneuve@lyrtech.com */
154 .boot_params = (DAVINCI_DDR_BASE + 0x100), 154 .atag_offset = 0x100,
155 .map_io = davinci_sffsdr_map_io, 155 .map_io = davinci_sffsdr_map_io,
156 .init_irq = davinci_irq_init, 156 .init_irq = davinci_irq_init,
157 .timer = &davinci_timer, 157 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/board-tnetv107x-evm.c b/arch/arm/mach-davinci/board-tnetv107x-evm.c
index 782892065682..90ee7b5aabdc 100644
--- a/arch/arm/mach-davinci/board-tnetv107x-evm.c
+++ b/arch/arm/mach-davinci/board-tnetv107x-evm.c
@@ -277,7 +277,7 @@ console_initcall(tnetv107x_evm_console_init);
277#endif 277#endif
278 278
279MACHINE_START(TNETV107X, "TNETV107X EVM") 279MACHINE_START(TNETV107X, "TNETV107X EVM")
280 .boot_params = (TNETV107X_DDR_BASE + 0x100), 280 .atag_offset = 0x100,
281 .map_io = tnetv107x_init, 281 .map_io = tnetv107x_init,
282 .init_irq = cp_intc_init, 282 .init_irq = cp_intc_init,
283 .timer = &davinci_timer, 283 .timer = &davinci_timer,
diff --git a/arch/arm/mach-davinci/common.c b/arch/arm/mach-davinci/common.c
index 1d2557394235..865ffe5899ac 100644
--- a/arch/arm/mach-davinci/common.c
+++ b/arch/arm/mach-davinci/common.c
@@ -12,6 +12,7 @@
12#include <linux/io.h> 12#include <linux/io.h>
13#include <linux/etherdevice.h> 13#include <linux/etherdevice.h>
14#include <linux/davinci_emac.h> 14#include <linux/davinci_emac.h>
15#include <linux/dma-mapping.h>
15 16
16#include <asm/tlb.h> 17#include <asm/tlb.h>
17#include <asm/mach/map.h> 18#include <asm/mach/map.h>
@@ -86,6 +87,8 @@ void __init davinci_common_init(struct davinci_soc_info *soc_info)
86 iotable_init(davinci_soc_info.io_desc, 87 iotable_init(davinci_soc_info.io_desc,
87 davinci_soc_info.io_desc_num); 88 davinci_soc_info.io_desc_num);
88 89
90 init_consistent_dma_size(14 << 20);
91
89 /* 92 /*
90 * Normally devicemaps_init() would flush caches and tlb after 93 * Normally devicemaps_init() would flush caches and tlb after
91 * mdesc->map_io(), but we must also do it here because of the CPU 94 * mdesc->map_io(), but we must also do it here because of the CPU
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index bd59f31b8a95..0b314bf16f7f 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -19,7 +19,7 @@
19#include <asm/proc-fns.h> 19#include <asm/proc-fns.h>
20 20
21#include <mach/cpuidle.h> 21#include <mach/cpuidle.h>
22#include <mach/memory.h> 22#include <mach/ddr2.h>
23 23
24#define DAVINCI_CPUIDLE_MAX_STATES 2 24#define DAVINCI_CPUIDLE_MAX_STATES 2
25 25
diff --git a/arch/arm/mach-davinci/include/mach/ddr2.h b/arch/arm/mach-davinci/include/mach/ddr2.h
new file mode 100644
index 000000000000..c19e047d0e6a
--- /dev/null
+++ b/arch/arm/mach-davinci/include/mach/ddr2.h
@@ -0,0 +1,4 @@
1#define DDR2_SDRCR_OFFSET 0xc
2#define DDR2_SRPD_BIT (1 << 23)
3#define DDR2_MCLKSTOPEN_BIT (1 << 30)
4#define DDR2_LPMODEN_BIT (1 << 31)
diff --git a/arch/arm/mach-davinci/include/mach/debug-macro.S b/arch/arm/mach-davinci/include/mach/debug-macro.S
index f8b7ea4f6235..cf94552d5274 100644
--- a/arch/arm/mach-davinci/include/mach/debug-macro.S
+++ b/arch/arm/mach-davinci/include/mach/debug-macro.S
@@ -18,56 +18,50 @@
18 18
19#include <linux/serial_reg.h> 19#include <linux/serial_reg.h>
20 20
21#include <asm/memory.h>
22
23#include <mach/serial.h> 21#include <mach/serial.h>
24 22
25#define UART_SHIFT 2 23#define UART_SHIFT 2
26 24
27#define davinci_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
28#define davinci_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET)
29
30 .pushsection .data 25 .pushsection .data
31davinci_uart_phys: .word 0 26davinci_uart_phys: .word 0
32davinci_uart_virt: .word 0 27davinci_uart_virt: .word 0
33 .popsection 28 .popsection
34 29
35 .macro addruart, rp, rv 30 .macro addruart, rp, rv, tmp
36 31
37 /* Use davinci_uart_phys/virt if already configured */ 32 /* Use davinci_uart_phys/virt if already configured */
3810: mrc p15, 0, \rp, c1, c0 3310: adr \rp, 99f @ get effective addr of 99f
39 tst \rp, #1 @ MMU enabled? 34 ldr \rv, [\rp] @ get absolute addr of 99f
40 ldreq \rp, =davinci_uart_v2p(davinci_uart_phys) 35 sub \rv, \rv, \rp @ offset between the two
41 ldrne \rp, =davinci_uart_phys 36 ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
42 add \rv, \rp, #4 @ davinci_uart_virt 37 sub \tmp, \rp, \rv @ make it effective
43 ldr \rp, [\rp, #0] 38 ldr \rp, [\tmp, #0] @ davinci_uart_phys
44 ldr \rv, [\rv, #0] 39 ldr \rv, [\tmp, #4] @ davinci_uart_virt
45 cmp \rp, #0 @ is port configured? 40 cmp \rp, #0 @ is port configured?
46 cmpne \rv, #0 41 cmpne \rv, #0
47 bne 99f @ already configured 42 bne 100f @ already configured
48 43
49 /* Check the debug UART address set in uncompress.h */ 44 /* Check the debug UART address set in uncompress.h */
50 mrc p15, 0, \rp, c1, c0 45 and \rp, pc, #0xff000000
51 tst \rp, #1 @ MMU enabled? 46 ldr \rv, =DAVINCI_UART_INFO_OFS
47 add \rp, \rp, \rv
52 48
53 /* Copy uart phys address from decompressor uart info */ 49 /* Copy uart phys address from decompressor uart info */
54 ldreq \rv, =davinci_uart_v2p(davinci_uart_phys) 50 ldr \rv, [\rp, #0]
55 ldrne \rv, =davinci_uart_phys 51 str \rv, [\tmp, #0]
56 ldreq \rp, =DAVINCI_UART_INFO
57 ldrne \rp, =davinci_uart_p2v(DAVINCI_UART_INFO)
58 ldr \rp, [\rp, #0]
59 str \rp, [\rv]
60 52
61 /* Copy uart virt address from decompressor uart info */ 53 /* Copy uart virt address from decompressor uart info */
62 ldreq \rv, =davinci_uart_v2p(davinci_uart_virt) 54 ldr \rv, [\rp, #4]
63 ldrne \rv, =davinci_uart_virt 55 str \rv, [\tmp, #4]
64 ldreq \rp, =DAVINCI_UART_INFO
65 ldrne \rp, =davinci_uart_p2v(DAVINCI_UART_INFO)
66 ldr \rp, [\rp, #4]
67 str \rp, [\rv]
68 56
69 b 10b 57 b 10b
7099: 58
59 .align
6099: .word .
61 .word davinci_uart_phys
62 .ltorg
63
64100:
71 .endm 65 .endm
72 66
73 .macro senduart,rd,rx 67 .macro senduart,rd,rx
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
deleted file mode 100644
index 78731944a70c..000000000000
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ /dev/null
@@ -1,44 +0,0 @@
1/*
2 * DaVinci memory space definitions
3 *
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
5 *
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
9 * or implied.
10 */
11#ifndef __ASM_ARCH_MEMORY_H
12#define __ASM_ARCH_MEMORY_H
13
14/**************************************************************************
15 * Included Files
16 **************************************************************************/
17#include <asm/page.h>
18#include <asm/sizes.h>
19
20/**************************************************************************
21 * Definitions
22 **************************************************************************/
23#define DAVINCI_DDR_BASE 0x80000000
24#define DA8XX_DDR_BASE 0xc0000000
25
26#if defined(CONFIG_ARCH_DAVINCI_DA8XX) && defined(CONFIG_ARCH_DAVINCI_DMx)
27#error Cannot enable DaVinci and DA8XX platforms concurrently
28#elif defined(CONFIG_ARCH_DAVINCI_DA8XX)
29#define PLAT_PHYS_OFFSET DA8XX_DDR_BASE
30#else
31#define PLAT_PHYS_OFFSET DAVINCI_DDR_BASE
32#endif
33
34#define DDR2_SDRCR_OFFSET 0xc
35#define DDR2_SRPD_BIT BIT(23)
36#define DDR2_MCLKSTOPEN_BIT BIT(30)
37#define DDR2_LPMODEN_BIT BIT(31)
38
39/*
40 * Increase size of DMA-consistent memory region
41 */
42#define CONSISTENT_DMA_SIZE (14<<20)
43
44#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-davinci/include/mach/serial.h b/arch/arm/mach-davinci/include/mach/serial.h
index c9e6ce185a66..e347d88fef91 100644
--- a/arch/arm/mach-davinci/include/mach/serial.h
+++ b/arch/arm/mach-davinci/include/mach/serial.h
@@ -21,8 +21,9 @@
21 * macros in debug-macro.S. 21 * macros in debug-macro.S.
22 * 22 *
23 * This area sits just below the page tables (see arch/arm/kernel/head.S). 23 * This area sits just below the page tables (see arch/arm/kernel/head.S).
24 * We define it as a relative offset from start of usable RAM.
24 */ 25 */
25#define DAVINCI_UART_INFO (PLAT_PHYS_OFFSET + 0x3ff8) 26#define DAVINCI_UART_INFO_OFS 0x3ff8
26 27
27#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000) 28#define DAVINCI_UART0_BASE (IO_PHYS + 0x20000)
28#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400) 29#define DAVINCI_UART1_BASE (IO_PHYS + 0x20400)
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 78d80683cdc2..9dc7cf9664fe 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -43,7 +43,12 @@ static inline void flush(void)
43 43
44static inline void set_uart_info(u32 phys, void * __iomem virt) 44static inline void set_uart_info(u32 phys, void * __iomem virt)
45{ 45{
46 u32 *uart_info = (u32 *)(DAVINCI_UART_INFO); 46 /*
47 * Get address of some.bss variable and round it down
48 * a la CONFIG_AUTO_ZRELADDR.
49 */
50 u32 ram_start = (u32)&uart & 0xf8000000;
51 u32 *uart_info = (u32 *)(ram_start + DAVINCI_UART_INFO_OFS);
47 52
48 uart = (u32 *)phys; 53 uart = (u32 *)phys;
49 uart_info[0] = phys; 54 uart_info[0] = phys;
diff --git a/arch/arm/mach-davinci/sleep.S b/arch/arm/mach-davinci/sleep.S
index 5f1e045a3ad1..d4e9316ecacb 100644
--- a/arch/arm/mach-davinci/sleep.S
+++ b/arch/arm/mach-davinci/sleep.S
@@ -22,7 +22,7 @@
22#include <linux/linkage.h> 22#include <linux/linkage.h>
23#include <asm/assembler.h> 23#include <asm/assembler.h>
24#include <mach/psc.h> 24#include <mach/psc.h>
25#include <mach/memory.h> 25#include <mach/ddr2.h>
26 26
27#include "clock.h" 27#include "clock.h"
28 28
diff --git a/arch/arm/mach-dove/cm-a510.c b/arch/arm/mach-dove/cm-a510.c
index 03e11f9dca97..c8a406f7e946 100644
--- a/arch/arm/mach-dove/cm-a510.c
+++ b/arch/arm/mach-dove/cm-a510.c
@@ -87,7 +87,7 @@ static void __init cm_a510_init(void)
87} 87}
88 88
89MACHINE_START(CM_A510, "Compulab CM-A510 Board") 89MACHINE_START(CM_A510, "Compulab CM-A510 Board")
90 .boot_params = 0x00000100, 90 .atag_offset = 0x100,
91 .init_machine = cm_a510_init, 91 .init_machine = cm_a510_init,
92 .map_io = dove_map_io, 92 .map_io = dove_map_io,
93 .init_early = dove_init_early, 93 .init_early = dove_init_early,
diff --git a/arch/arm/mach-dove/dove-db-setup.c b/arch/arm/mach-dove/dove-db-setup.c
index 2ac34ecfa745..11ea34e4fc76 100644
--- a/arch/arm/mach-dove/dove-db-setup.c
+++ b/arch/arm/mach-dove/dove-db-setup.c
@@ -94,7 +94,7 @@ static void __init dove_db_init(void)
94} 94}
95 95
96MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board") 96MACHINE_START(DOVE_DB, "Marvell DB-MV88AP510-BP Development Board")
97 .boot_params = 0x00000100, 97 .atag_offset = 0x100,
98 .init_machine = dove_db_init, 98 .init_machine = dove_db_init,
99 .map_io = dove_map_io, 99 .map_io = dove_map_io,
100 .init_early = dove_init_early, 100 .init_early = dove_init_early,
diff --git a/arch/arm/mach-dove/include/mach/debug-macro.S b/arch/arm/mach-dove/include/mach/debug-macro.S
index da8bf2bad3b1..5929cbc59161 100644
--- a/arch/arm/mach-dove/include/mach/debug-macro.S
+++ b/arch/arm/mach-dove/include/mach/debug-macro.S
@@ -8,7 +8,7 @@
8 8
9#include <mach/bridge-regs.h> 9#include <mach/bridge-regs.h>
10 10
11 .macro addruart, rp, rv 11 .macro addruart, rp, rv, tmp
12 ldr \rp, =DOVE_SB_REGS_PHYS_BASE 12 ldr \rp, =DOVE_SB_REGS_PHYS_BASE
13 ldr \rv, =DOVE_SB_REGS_VIRT_BASE 13 ldr \rv, =DOVE_SB_REGS_VIRT_BASE
14 orr \rp, \rp, #0x00012000 14 orr \rp, \rp, #0x00012000
diff --git a/arch/arm/mach-dove/include/mach/memory.h b/arch/arm/mach-dove/include/mach/memory.h
deleted file mode 100644
index bbc93fee6c75..000000000000
--- a/arch/arm/mach-dove/include/mach/memory.h
+++ /dev/null
@@ -1,10 +0,0 @@
1/*
2 * arch/arm/mach-dove/include/mach/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PLAT_PHYS_OFFSET UL(0x00000000)
9
10#endif
diff --git a/arch/arm/mach-ebsa110/core.c b/arch/arm/mach-ebsa110/core.c
index 087bc771ac23..d0ce8abdd4b6 100644
--- a/arch/arm/mach-ebsa110/core.c
+++ b/arch/arm/mach-ebsa110/core.c
@@ -280,7 +280,7 @@ arch_initcall(ebsa110_init);
280 280
281MACHINE_START(EBSA110, "EBSA110") 281MACHINE_START(EBSA110, "EBSA110")
282 /* Maintainer: Russell King */ 282 /* Maintainer: Russell King */
283 .boot_params = 0x00000400, 283 .atag_offset = 0x400,
284 .reserve_lp0 = 1, 284 .reserve_lp0 = 1,
285 .reserve_lp2 = 1, 285 .reserve_lp2 = 1,
286 .soft_reboot = 1, 286 .soft_reboot = 1,
diff --git a/arch/arm/mach-ebsa110/include/mach/debug-macro.S b/arch/arm/mach-ebsa110/include/mach/debug-macro.S
index 7ef5690fd08c..bb02c05e6812 100644
--- a/arch/arm/mach-ebsa110/include/mach/debug-macro.S
+++ b/arch/arm/mach-ebsa110/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * 11 *
12**/ 12**/
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0xf0000000 15 mov \rp, #0xf0000000
16 orr \rp, \rp, #0x00000be0 16 orr \rp, \rp, #0x00000be0
17 mov \rp, \rv 17 mov \rp, \rv
diff --git a/arch/arm/mach-ep93xx/adssphere.c b/arch/arm/mach-ep93xx/adssphere.c
index 61b98ce4b673..0713448206a5 100644
--- a/arch/arm/mach-ep93xx/adssphere.c
+++ b/arch/arm/mach-ep93xx/adssphere.c
@@ -33,7 +33,7 @@ static void __init adssphere_init_machine(void)
33 33
34MACHINE_START(ADSSPHERE, "ADS Sphere board") 34MACHINE_START(ADSSPHERE, "ADS Sphere board")
35 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 35 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
36 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 36 .atag_offset = 0x100,
37 .map_io = ep93xx_map_io, 37 .map_io = ep93xx_map_io,
38 .init_irq = ep93xx_init_irq, 38 .init_irq = ep93xx_init_irq,
39 .timer = &ep93xx_timer, 39 .timer = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/edb93xx.c b/arch/arm/mach-ep93xx/edb93xx.c
index 3f320c6477bf..c63a5ec1a8e3 100644
--- a/arch/arm/mach-ep93xx/edb93xx.c
+++ b/arch/arm/mach-ep93xx/edb93xx.c
@@ -241,7 +241,7 @@ static void __init edb93xx_init_machine(void)
241#ifdef CONFIG_MACH_EDB9301 241#ifdef CONFIG_MACH_EDB9301
242MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board") 242MACHINE_START(EDB9301, "Cirrus Logic EDB9301 Evaluation Board")
243 /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */ 243 /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
244 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 244 .atag_offset = 0x100,
245 .map_io = ep93xx_map_io, 245 .map_io = ep93xx_map_io,
246 .init_irq = ep93xx_init_irq, 246 .init_irq = ep93xx_init_irq,
247 .timer = &ep93xx_timer, 247 .timer = &ep93xx_timer,
@@ -252,7 +252,7 @@ MACHINE_END
252#ifdef CONFIG_MACH_EDB9302 252#ifdef CONFIG_MACH_EDB9302
253MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board") 253MACHINE_START(EDB9302, "Cirrus Logic EDB9302 Evaluation Board")
254 /* Maintainer: George Kashperko <george@chas.com.ua> */ 254 /* Maintainer: George Kashperko <george@chas.com.ua> */
255 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 255 .atag_offset = 0x100,
256 .map_io = ep93xx_map_io, 256 .map_io = ep93xx_map_io,
257 .init_irq = ep93xx_init_irq, 257 .init_irq = ep93xx_init_irq,
258 .timer = &ep93xx_timer, 258 .timer = &ep93xx_timer,
@@ -263,7 +263,7 @@ MACHINE_END
263#ifdef CONFIG_MACH_EDB9302A 263#ifdef CONFIG_MACH_EDB9302A
264MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board") 264MACHINE_START(EDB9302A, "Cirrus Logic EDB9302A Evaluation Board")
265 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 265 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
266 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 266 .atag_offset = 0x100,
267 .map_io = ep93xx_map_io, 267 .map_io = ep93xx_map_io,
268 .init_irq = ep93xx_init_irq, 268 .init_irq = ep93xx_init_irq,
269 .timer = &ep93xx_timer, 269 .timer = &ep93xx_timer,
@@ -274,7 +274,7 @@ MACHINE_END
274#ifdef CONFIG_MACH_EDB9307 274#ifdef CONFIG_MACH_EDB9307
275MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board") 275MACHINE_START(EDB9307, "Cirrus Logic EDB9307 Evaluation Board")
276 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ 276 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
277 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 277 .atag_offset = 0x100,
278 .map_io = ep93xx_map_io, 278 .map_io = ep93xx_map_io,
279 .init_irq = ep93xx_init_irq, 279 .init_irq = ep93xx_init_irq,
280 .timer = &ep93xx_timer, 280 .timer = &ep93xx_timer,
@@ -285,7 +285,7 @@ MACHINE_END
285#ifdef CONFIG_MACH_EDB9307A 285#ifdef CONFIG_MACH_EDB9307A
286MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board") 286MACHINE_START(EDB9307A, "Cirrus Logic EDB9307A Evaluation Board")
287 /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */ 287 /* Maintainer: H Hartley Sweeten <hsweeten@visionengravers.com> */
288 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 288 .atag_offset = 0x100,
289 .map_io = ep93xx_map_io, 289 .map_io = ep93xx_map_io,
290 .init_irq = ep93xx_init_irq, 290 .init_irq = ep93xx_init_irq,
291 .timer = &ep93xx_timer, 291 .timer = &ep93xx_timer,
@@ -296,7 +296,7 @@ MACHINE_END
296#ifdef CONFIG_MACH_EDB9312 296#ifdef CONFIG_MACH_EDB9312
297MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board") 297MACHINE_START(EDB9312, "Cirrus Logic EDB9312 Evaluation Board")
298 /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */ 298 /* Maintainer: Toufeeq Hussain <toufeeq_hussain@infosys.com> */
299 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 299 .atag_offset = 0x100,
300 .map_io = ep93xx_map_io, 300 .map_io = ep93xx_map_io,
301 .init_irq = ep93xx_init_irq, 301 .init_irq = ep93xx_init_irq,
302 .timer = &ep93xx_timer, 302 .timer = &ep93xx_timer,
@@ -307,7 +307,7 @@ MACHINE_END
307#ifdef CONFIG_MACH_EDB9315 307#ifdef CONFIG_MACH_EDB9315
308MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board") 308MACHINE_START(EDB9315, "Cirrus Logic EDB9315 Evaluation Board")
309 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 309 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
310 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 310 .atag_offset = 0x100,
311 .map_io = ep93xx_map_io, 311 .map_io = ep93xx_map_io,
312 .init_irq = ep93xx_init_irq, 312 .init_irq = ep93xx_init_irq,
313 .timer = &ep93xx_timer, 313 .timer = &ep93xx_timer,
@@ -318,7 +318,7 @@ MACHINE_END
318#ifdef CONFIG_MACH_EDB9315A 318#ifdef CONFIG_MACH_EDB9315A
319MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board") 319MACHINE_START(EDB9315A, "Cirrus Logic EDB9315A Evaluation Board")
320 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 320 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
321 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 321 .atag_offset = 0x100,
322 .map_io = ep93xx_map_io, 322 .map_io = ep93xx_map_io,
323 .init_irq = ep93xx_init_irq, 323 .init_irq = ep93xx_init_irq,
324 .timer = &ep93xx_timer, 324 .timer = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/gesbc9312.c b/arch/arm/mach-ep93xx/gesbc9312.c
index 9bd3152bff9a..45ee205856f8 100644
--- a/arch/arm/mach-ep93xx/gesbc9312.c
+++ b/arch/arm/mach-ep93xx/gesbc9312.c
@@ -33,7 +33,7 @@ static void __init gesbc9312_init_machine(void)
33 33
34MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx") 34MACHINE_START(GESBC9312, "Glomation GESBC-9312-sx")
35 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 35 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
36 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 36 .atag_offset = 0x100,
37 .map_io = ep93xx_map_io, 37 .map_io = ep93xx_map_io,
38 .init_irq = ep93xx_init_irq, 38 .init_irq = ep93xx_init_irq,
39 .timer = &ep93xx_timer, 39 .timer = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/include/mach/debug-macro.S b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
index b25bc9076367..af54e43132cf 100644
--- a/arch/arm/mach-ep93xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ep93xx/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 */ 11 */
12#include <mach/ep93xx-regs.h> 12#include <mach/ep93xx-regs.h>
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 ldr \rp, =EP93XX_APB_PHYS_BASE @ Physical base 15 ldr \rp, =EP93XX_APB_PHYS_BASE @ Physical base
16 ldr \rv, =EP93XX_APB_VIRT_BASE @ virtual base 16 ldr \rv, =EP93XX_APB_VIRT_BASE @ virtual base
17 orr \rp, \rp, #0x000c0000 17 orr \rp, \rp, #0x000c0000
diff --git a/arch/arm/mach-ep93xx/micro9.c b/arch/arm/mach-ep93xx/micro9.c
index 7adea6258efe..e72f7368876e 100644
--- a/arch/arm/mach-ep93xx/micro9.c
+++ b/arch/arm/mach-ep93xx/micro9.c
@@ -77,7 +77,7 @@ static void __init micro9_init_machine(void)
77#ifdef CONFIG_MACH_MICRO9H 77#ifdef CONFIG_MACH_MICRO9H
78MACHINE_START(MICRO9, "Contec Micro9-High") 78MACHINE_START(MICRO9, "Contec Micro9-High")
79 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ 79 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
80 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 80 .atag_offset = 0x100,
81 .map_io = ep93xx_map_io, 81 .map_io = ep93xx_map_io,
82 .init_irq = ep93xx_init_irq, 82 .init_irq = ep93xx_init_irq,
83 .timer = &ep93xx_timer, 83 .timer = &ep93xx_timer,
@@ -88,7 +88,7 @@ MACHINE_END
88#ifdef CONFIG_MACH_MICRO9M 88#ifdef CONFIG_MACH_MICRO9M
89MACHINE_START(MICRO9M, "Contec Micro9-Mid") 89MACHINE_START(MICRO9M, "Contec Micro9-Mid")
90 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ 90 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
91 .boot_params = EP93XX_SDCE3_PHYS_BASE_ASYNC + 0x100, 91 .atag_offset = 0x100,
92 .map_io = ep93xx_map_io, 92 .map_io = ep93xx_map_io,
93 .init_irq = ep93xx_init_irq, 93 .init_irq = ep93xx_init_irq,
94 .timer = &ep93xx_timer, 94 .timer = &ep93xx_timer,
@@ -99,7 +99,7 @@ MACHINE_END
99#ifdef CONFIG_MACH_MICRO9L 99#ifdef CONFIG_MACH_MICRO9L
100MACHINE_START(MICRO9L, "Contec Micro9-Lite") 100MACHINE_START(MICRO9L, "Contec Micro9-Lite")
101 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ 101 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
102 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 102 .atag_offset = 0x100,
103 .map_io = ep93xx_map_io, 103 .map_io = ep93xx_map_io,
104 .init_irq = ep93xx_init_irq, 104 .init_irq = ep93xx_init_irq,
105 .timer = &ep93xx_timer, 105 .timer = &ep93xx_timer,
@@ -110,7 +110,7 @@ MACHINE_END
110#ifdef CONFIG_MACH_MICRO9S 110#ifdef CONFIG_MACH_MICRO9S
111MACHINE_START(MICRO9S, "Contec Micro9-Slim") 111MACHINE_START(MICRO9S, "Contec Micro9-Slim")
112 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */ 112 /* Maintainer: Hubert Feurstein <hubert.feurstein@contec.at> */
113 .boot_params = EP93XX_SDCE3_PHYS_BASE_ASYNC + 0x100, 113 .atag_offset = 0x100,
114 .map_io = ep93xx_map_io, 114 .map_io = ep93xx_map_io,
115 .init_irq = ep93xx_init_irq, 115 .init_irq = ep93xx_init_irq,
116 .timer = &ep93xx_timer, 116 .timer = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/simone.c b/arch/arm/mach-ep93xx/simone.c
index 1a472ff12cce..d6f286b4db9c 100644
--- a/arch/arm/mach-ep93xx/simone.c
+++ b/arch/arm/mach-ep93xx/simone.c
@@ -65,8 +65,8 @@ static void __init simone_init_machine(void)
65} 65}
66 66
67MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board") 67MACHINE_START(SIM_ONE, "Simplemachines Sim.One Board")
68/* Maintainer: Ryan Mallon */ 68 /* Maintainer: Ryan Mallon */
69 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 69 .atag_offset = 0x100,
70 .map_io = ep93xx_map_io, 70 .map_io = ep93xx_map_io,
71 .init_irq = ep93xx_init_irq, 71 .init_irq = ep93xx_init_irq,
72 .timer = &ep93xx_timer, 72 .timer = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/snappercl15.c b/arch/arm/mach-ep93xx/snappercl15.c
index 4f4b0b2c4c31..2b4d4b0201df 100644
--- a/arch/arm/mach-ep93xx/snappercl15.c
+++ b/arch/arm/mach-ep93xx/snappercl15.c
@@ -163,7 +163,7 @@ static void __init snappercl15_init_machine(void)
163 163
164MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15") 164MACHINE_START(SNAPPER_CL15, "Bluewater Systems Snapper CL15")
165 /* Maintainer: Ryan Mallon */ 165 /* Maintainer: Ryan Mallon */
166 .boot_params = EP93XX_SDCE0_PHYS_BASE + 0x100, 166 .atag_offset = 0x100,
167 .map_io = ep93xx_map_io, 167 .map_io = ep93xx_map_io,
168 .init_irq = ep93xx_init_irq, 168 .init_irq = ep93xx_init_irq,
169 .timer = &ep93xx_timer, 169 .timer = &ep93xx_timer,
diff --git a/arch/arm/mach-ep93xx/ts72xx.c b/arch/arm/mach-ep93xx/ts72xx.c
index c2d2cf40ead9..1ade3c340507 100644
--- a/arch/arm/mach-ep93xx/ts72xx.c
+++ b/arch/arm/mach-ep93xx/ts72xx.c
@@ -257,7 +257,7 @@ static void __init ts72xx_init_machine(void)
257 257
258MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC") 258MACHINE_START(TS72XX, "Technologic Systems TS-72xx SBC")
259 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 259 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
260 .boot_params = EP93XX_SDCE3_PHYS_BASE_SYNC + 0x100, 260 .atag_offset = 0x100,
261 .map_io = ts72xx_map_io, 261 .map_io = ts72xx_map_io,
262 .init_irq = ep93xx_init_irq, 262 .init_irq = ep93xx_init_irq,
263 .timer = &ep93xx_timer, 263 .timer = &ep93xx_timer,
diff --git a/arch/arm/mach-exynos4/include/mach/debug-macro.S b/arch/arm/mach-exynos4/include/mach/debug-macro.S
index a442ef861167..6cacf16a67a6 100644
--- a/arch/arm/mach-exynos4/include/mach/debug-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/debug-macro.S
@@ -20,7 +20,7 @@
20 * aligned and add in the offset when we load the value here. 20 * aligned and add in the offset when we load the value here.
21 */ 21 */
22 22
23 .macro addruart, rp, rv 23 .macro addruart, rp, rv, tmp
24 ldr \rp, = S3C_PA_UART 24 ldr \rp, = S3C_PA_UART
25 ldr \rv, = S3C_VA_UART 25 ldr \rv, = S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0 26#if CONFIG_DEBUG_S3C_UART != 0
diff --git a/arch/arm/mach-exynos4/include/mach/entry-macro.S b/arch/arm/mach-exynos4/include/mach/entry-macro.S
index d7a1e281ce7a..006a4f4c65c6 100644
--- a/arch/arm/mach-exynos4/include/mach/entry-macro.S
+++ b/arch/arm/mach-exynos4/include/mach/entry-macro.S
@@ -55,7 +55,7 @@
55 55
56 bic \irqnr, \irqstat, #0x1c00 56 bic \irqnr, \irqstat, #0x1c00
57 57
58 cmp \irqnr, #29 58 cmp \irqnr, #15
59 cmpcc \irqnr, \irqnr 59 cmpcc \irqnr, \irqnr
60 cmpne \irqnr, \tmp 60 cmpne \irqnr, \tmp
61 cmpcs \irqnr, \irqnr 61 cmpcs \irqnr, \irqnr
@@ -76,8 +76,3 @@
76 strcc \irqstat, [\base, #GIC_CPU_EOI] 76 strcc \irqstat, [\base, #GIC_CPU_EOI]
77 cmpcs \irqnr, \irqnr 77 cmpcs \irqnr, \irqnr
78 .endm 78 .endm
79
80 /* As above, this assumes that irqstat and base are preserved.. */
81
82 .macro test_for_ltirq, irqnr, irqstat, base, tmp
83 .endm
diff --git a/arch/arm/mach-exynos4/mach-armlex4210.c b/arch/arm/mach-exynos4/mach-armlex4210.c
index b482c6285fc4..f0ca6c157d29 100644
--- a/arch/arm/mach-exynos4/mach-armlex4210.c
+++ b/arch/arm/mach-exynos4/mach-armlex4210.c
@@ -207,7 +207,7 @@ static void __init armlex4210_machine_init(void)
207 207
208MACHINE_START(ARMLEX4210, "ARMLEX4210") 208MACHINE_START(ARMLEX4210, "ARMLEX4210")
209 /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */ 209 /* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
210 .boot_params = S5P_PA_SDRAM + 0x100, 210 .atag_offset = 0x100,
211 .init_irq = exynos4_init_irq, 211 .init_irq = exynos4_init_irq,
212 .map_io = armlex4210_map_io, 212 .map_io = armlex4210_map_io,
213 .init_machine = armlex4210_machine_init, 213 .init_machine = armlex4210_machine_init,
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index 43be71b799cb..6e0536818bf5 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -1152,7 +1152,7 @@ static void __init nuri_machine_init(void)
1152 1152
1153MACHINE_START(NURI, "NURI") 1153MACHINE_START(NURI, "NURI")
1154 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ 1154 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
1155 .boot_params = S5P_PA_SDRAM + 0x100, 1155 .atag_offset = 0x100,
1156 .init_irq = exynos4_init_irq, 1156 .init_irq = exynos4_init_irq,
1157 .map_io = nuri_map_io, 1157 .map_io = nuri_map_io,
1158 .init_machine = nuri_machine_init, 1158 .init_machine = nuri_machine_init,
diff --git a/arch/arm/mach-exynos4/mach-smdkc210.c b/arch/arm/mach-exynos4/mach-smdkc210.c
index a7c65e05c1eb..b24ddd7ad8fe 100644
--- a/arch/arm/mach-exynos4/mach-smdkc210.c
+++ b/arch/arm/mach-exynos4/mach-smdkc210.c
@@ -301,7 +301,7 @@ static void __init smdkc210_machine_init(void)
301 301
302MACHINE_START(SMDKC210, "SMDKC210") 302MACHINE_START(SMDKC210, "SMDKC210")
303 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 303 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
304 .boot_params = S5P_PA_SDRAM + 0x100, 304 .atag_offset = 0x100,
305 .init_irq = exynos4_init_irq, 305 .init_irq = exynos4_init_irq,
306 .map_io = smdkc210_map_io, 306 .map_io = smdkc210_map_io,
307 .init_machine = smdkc210_machine_init, 307 .init_machine = smdkc210_machine_init,
diff --git a/arch/arm/mach-exynos4/mach-smdkv310.c b/arch/arm/mach-exynos4/mach-smdkv310.c
index ea4149556860..d90fcddbee1f 100644
--- a/arch/arm/mach-exynos4/mach-smdkv310.c
+++ b/arch/arm/mach-exynos4/mach-smdkv310.c
@@ -255,7 +255,7 @@ static void __init smdkv310_machine_init(void)
255MACHINE_START(SMDKV310, "SMDKV310") 255MACHINE_START(SMDKV310, "SMDKV310")
256 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 256 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
257 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */ 257 /* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
258 .boot_params = S5P_PA_SDRAM + 0x100, 258 .atag_offset = 0x100,
259 .init_irq = exynos4_init_irq, 259 .init_irq = exynos4_init_irq,
260 .map_io = smdkv310_map_io, 260 .map_io = smdkv310_map_io,
261 .init_machine = smdkv310_machine_init, 261 .init_machine = smdkv310_machine_init,
diff --git a/arch/arm/mach-exynos4/mach-universal_c210.c b/arch/arm/mach-exynos4/mach-universal_c210.c
index b3b5d8911004..2aac6f755c8e 100644
--- a/arch/arm/mach-exynos4/mach-universal_c210.c
+++ b/arch/arm/mach-exynos4/mach-universal_c210.c
@@ -762,7 +762,7 @@ static void __init universal_machine_init(void)
762 762
763MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210") 763MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
764 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ 764 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
765 .boot_params = S5P_PA_SDRAM + 0x100, 765 .atag_offset = 0x100,
766 .init_irq = exynos4_init_irq, 766 .init_irq = exynos4_init_irq,
767 .map_io = universal_map_io, 767 .map_io = universal_map_io,
768 .init_machine = universal_machine_init, 768 .init_machine = universal_machine_init,
diff --git a/arch/arm/mach-exynos4/mct.c b/arch/arm/mach-exynos4/mct.c
index ddd86864fb83..582b874aab0e 100644
--- a/arch/arm/mach-exynos4/mct.c
+++ b/arch/arm/mach-exynos4/mct.c
@@ -386,9 +386,11 @@ static void exynos4_mct_tick_init(struct clock_event_device *evt)
386 386
387 if (cpu == 0) { 387 if (cpu == 0) {
388 mct_tick0_event_irq.dev_id = &mct_tick[cpu]; 388 mct_tick0_event_irq.dev_id = &mct_tick[cpu];
389 evt->irq = IRQ_MCT_L0;
389 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); 390 setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
390 } else { 391 } else {
391 mct_tick1_event_irq.dev_id = &mct_tick[cpu]; 392 mct_tick1_event_irq.dev_id = &mct_tick[cpu];
393 evt->irq = IRQ_MCT_L1;
392 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); 394 setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
393 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); 395 irq_set_affinity(IRQ_MCT_L1, cpumask_of(1));
394 } 396 }
@@ -402,9 +404,10 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
402 return 0; 404 return 0;
403} 405}
404 406
405int local_timer_ack(void) 407void local_timer_stop(struct clock_event_device *evt)
406{ 408{
407 return 0; 409 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
410 disable_irq(evt->irq);
408} 411}
409 412
410#endif /* CONFIG_LOCAL_TIMERS */ 413#endif /* CONFIG_LOCAL_TIMERS */
diff --git a/arch/arm/mach-footbridge/cats-hw.c b/arch/arm/mach-footbridge/cats-hw.c
index 206ff2f39d6c..d5f178540928 100644
--- a/arch/arm/mach-footbridge/cats-hw.c
+++ b/arch/arm/mach-footbridge/cats-hw.c
@@ -85,7 +85,7 @@ fixup_cats(struct tag *tags, char **cmdline, struct meminfo *mi)
85 85
86MACHINE_START(CATS, "Chalice-CATS") 86MACHINE_START(CATS, "Chalice-CATS")
87 /* Maintainer: Philip Blundell */ 87 /* Maintainer: Philip Blundell */
88 .boot_params = 0x00000100, 88 .atag_offset = 0x100,
89 .soft_reboot = 1, 89 .soft_reboot = 1,
90 .fixup = fixup_cats, 90 .fixup = fixup_cats,
91 .map_io = footbridge_map_io, 91 .map_io = footbridge_map_io,
diff --git a/arch/arm/mach-footbridge/ebsa285.c b/arch/arm/mach-footbridge/ebsa285.c
index 2ef69ff44ba8..012210cf7d16 100644
--- a/arch/arm/mach-footbridge/ebsa285.c
+++ b/arch/arm/mach-footbridge/ebsa285.c
@@ -15,7 +15,7 @@
15 15
16MACHINE_START(EBSA285, "EBSA285") 16MACHINE_START(EBSA285, "EBSA285")
17 /* Maintainer: Russell King */ 17 /* Maintainer: Russell King */
18 .boot_params = 0x00000100, 18 .atag_offset = 0x100,
19 .video_start = 0x000a0000, 19 .video_start = 0x000a0000,
20 .video_end = 0x000bffff, 20 .video_end = 0x000bffff,
21 .map_io = footbridge_map_io, 21 .map_io = footbridge_map_io,
diff --git a/arch/arm/mach-footbridge/include/mach/debug-macro.S b/arch/arm/mach-footbridge/include/mach/debug-macro.S
index 1be2eeb7a0a0..e5acde25ffc5 100644
--- a/arch/arm/mach-footbridge/include/mach/debug-macro.S
+++ b/arch/arm/mach-footbridge/include/mach/debug-macro.S
@@ -15,7 +15,7 @@
15 15
16#ifndef CONFIG_DEBUG_DC21285_PORT 16#ifndef CONFIG_DEBUG_DC21285_PORT
17 /* For NetWinder debugging */ 17 /* For NetWinder debugging */
18 .macro addruart, rp, rv 18 .macro addruart, rp, rv, tmp
19 mov \rp, #0x000003f8 19 mov \rp, #0x000003f8
20 orr \rv, \rp, #0xff000000 @ virtual 20 orr \rv, \rp, #0xff000000 @ virtual
21 orr \rp, \rp, #0x7c000000 @ physical 21 orr \rp, \rp, #0x7c000000 @ physical
@@ -31,7 +31,7 @@
31 .equ dc21285_high, ARMCSR_BASE & 0xff000000 31 .equ dc21285_high, ARMCSR_BASE & 0xff000000
32 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff 32 .equ dc21285_low, ARMCSR_BASE & 0x00ffffff
33 33
34 .macro addruart, rp, rv 34 .macro addruart, rp, rv, tmp
35 .if dc21285_low 35 .if dc21285_low
36 mov \rp, #dc21285_low 36 mov \rp, #dc21285_low
37 .else 37 .else
diff --git a/arch/arm/mach-footbridge/netwinder-hw.c b/arch/arm/mach-footbridge/netwinder-hw.c
index 0f7aeff486c9..0d3846f3b60d 100644
--- a/arch/arm/mach-footbridge/netwinder-hw.c
+++ b/arch/arm/mach-footbridge/netwinder-hw.c
@@ -647,7 +647,7 @@ fixup_netwinder(struct tag *tags, char **cmdline, struct meminfo *mi)
647 647
648MACHINE_START(NETWINDER, "Rebel-NetWinder") 648MACHINE_START(NETWINDER, "Rebel-NetWinder")
649 /* Maintainer: Russell King/Rebel.com */ 649 /* Maintainer: Russell King/Rebel.com */
650 .boot_params = 0x00000100, 650 .atag_offset = 0x100,
651 .video_start = 0x000a0000, 651 .video_start = 0x000a0000,
652 .video_end = 0x000bffff, 652 .video_end = 0x000bffff,
653 .reserve_lp0 = 1, 653 .reserve_lp0 = 1,
diff --git a/arch/arm/mach-footbridge/personal.c b/arch/arm/mach-footbridge/personal.c
index 3285e91ca8c1..f41dba39b327 100644
--- a/arch/arm/mach-footbridge/personal.c
+++ b/arch/arm/mach-footbridge/personal.c
@@ -15,7 +15,7 @@
15 15
16MACHINE_START(PERSONAL_SERVER, "Compaq-PersonalServer") 16MACHINE_START(PERSONAL_SERVER, "Compaq-PersonalServer")
17 /* Maintainer: Jamey Hicks / George France */ 17 /* Maintainer: Jamey Hicks / George France */
18 .boot_params = 0x00000100, 18 .atag_offset = 0x100,
19 .map_io = footbridge_map_io, 19 .map_io = footbridge_map_io,
20 .init_irq = footbridge_init_irq, 20 .init_irq = footbridge_init_irq,
21 .timer = &footbridge_timer, 21 .timer = &footbridge_timer,
diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c
index 0cf7a07c3f3f..5927d3c253aa 100644
--- a/arch/arm/mach-gemini/board-nas4220b.c
+++ b/arch/arm/mach-gemini/board-nas4220b.c
@@ -102,7 +102,7 @@ static void __init ib4220b_init(void)
102} 102}
103 103
104MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B") 104MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
105 .boot_params = 0x100, 105 .atag_offset = 0x100,
106 .map_io = gemini_map_io, 106 .map_io = gemini_map_io,
107 .init_irq = gemini_init_irq, 107 .init_irq = gemini_init_irq,
108 .timer = &ib4220b_timer, 108 .timer = &ib4220b_timer,
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c
index 4fa09af99495..cd7437a1cea0 100644
--- a/arch/arm/mach-gemini/board-rut1xx.c
+++ b/arch/arm/mach-gemini/board-rut1xx.c
@@ -86,7 +86,7 @@ static void __init rut1xx_init(void)
86} 86}
87 87
88MACHINE_START(RUT100, "Teltonika RUT100") 88MACHINE_START(RUT100, "Teltonika RUT100")
89 .boot_params = 0x100, 89 .atag_offset = 0x100,
90 .map_io = gemini_map_io, 90 .map_io = gemini_map_io,
91 .init_irq = gemini_init_irq, 91 .init_irq = gemini_init_irq,
92 .timer = &rut1xx_timer, 92 .timer = &rut1xx_timer,
diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c
index 88cc422ee444..a367880368f1 100644
--- a/arch/arm/mach-gemini/board-wbd111.c
+++ b/arch/arm/mach-gemini/board-wbd111.c
@@ -129,7 +129,7 @@ static void __init wbd111_init(void)
129} 129}
130 130
131MACHINE_START(WBD111, "Wiliboard WBD-111") 131MACHINE_START(WBD111, "Wiliboard WBD-111")
132 .boot_params = 0x100, 132 .atag_offset = 0x100,
133 .map_io = gemini_map_io, 133 .map_io = gemini_map_io,
134 .init_irq = gemini_init_irq, 134 .init_irq = gemini_init_irq,
135 .timer = &wbd111_timer, 135 .timer = &wbd111_timer,
diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c
index 3a220347bc88..f382811c1319 100644
--- a/arch/arm/mach-gemini/board-wbd222.c
+++ b/arch/arm/mach-gemini/board-wbd222.c
@@ -129,7 +129,7 @@ static void __init wbd222_init(void)
129} 129}
130 130
131MACHINE_START(WBD222, "Wiliboard WBD-222") 131MACHINE_START(WBD222, "Wiliboard WBD-222")
132 .boot_params = 0x100, 132 .atag_offset = 0x100,
133 .map_io = gemini_map_io, 133 .map_io = gemini_map_io,
134 .init_irq = gemini_init_irq, 134 .init_irq = gemini_init_irq,
135 .timer = &wbd222_timer, 135 .timer = &wbd222_timer,
diff --git a/arch/arm/mach-gemini/include/mach/debug-macro.S b/arch/arm/mach-gemini/include/mach/debug-macro.S
index f40e006d296e..837670763b85 100644
--- a/arch/arm/mach-gemini/include/mach/debug-macro.S
+++ b/arch/arm/mach-gemini/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 */ 11 */
12#include <mach/hardware.h> 12#include <mach/hardware.h>
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 ldr \rp, =GEMINI_UART_BASE @ physical 15 ldr \rp, =GEMINI_UART_BASE @ physical
16 ldr \rv, =IO_ADDRESS(GEMINI_UART_BASE) @ virtual 16 ldr \rv, =IO_ADDRESS(GEMINI_UART_BASE) @ virtual
17 .endm 17 .endm
diff --git a/arch/arm/mach-gemini/include/mach/memory.h b/arch/arm/mach-gemini/include/mach/memory.h
deleted file mode 100644
index a50915f764d8..000000000000
--- a/arch/arm/mach-gemini/include/mach/memory.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * Copyright (C) 2001-2006 Storlink, Corp.
3 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 */
10#ifndef __MACH_MEMORY_H
11#define __MACH_MEMORY_H
12
13#ifdef CONFIG_GEMINI_MEM_SWAP
14# define PLAT_PHYS_OFFSET UL(0x00000000)
15#else
16# define PLAT_PHYS_OFFSET UL(0x10000000)
17#endif
18
19#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
index 65f1bea958e5..9886f19805f4 100644
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ b/arch/arm/mach-h720x/h7201-eval.c
@@ -29,7 +29,7 @@
29 29
30MACHINE_START(H7201, "Hynix GMS30C7201") 30MACHINE_START(H7201, "Hynix GMS30C7201")
31 /* Maintainer: Robert Schwebel, Pengutronix */ 31 /* Maintainer: Robert Schwebel, Pengutronix */
32 .boot_params = 0xc0001000, 32 .atag_offset = 0x1000,
33 .map_io = h720x_map_io, 33 .map_io = h720x_map_io,
34 .init_irq = h720x_init_irq, 34 .init_irq = h720x_init_irq,
35 .timer = &h7201_timer, 35 .timer = &h7201_timer,
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
index 884584a09752..284a134819e1 100644
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ b/arch/arm/mach-h720x/h7202-eval.c
@@ -71,7 +71,7 @@ static void __init init_eval_h7202(void)
71 71
72MACHINE_START(H7202, "Hynix HMS30C7202") 72MACHINE_START(H7202, "Hynix HMS30C7202")
73 /* Maintainer: Robert Schwebel, Pengutronix */ 73 /* Maintainer: Robert Schwebel, Pengutronix */
74 .boot_params = 0x40000100, 74 .atag_offset = 0x100,
75 .map_io = h720x_map_io, 75 .map_io = h720x_map_io,
76 .init_irq = h7202_init_irq, 76 .init_irq = h7202_init_irq,
77 .timer = &h7202_timer, 77 .timer = &h7202_timer,
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
index c2093e835720..8a46157b0582 100644
--- a/arch/arm/mach-h720x/include/mach/debug-macro.S
+++ b/arch/arm/mach-h720x/include/mach/debug-macro.S
@@ -16,7 +16,7 @@
16 .equ io_virt, IO_VIRT 16 .equ io_virt, IO_VIRT
17 .equ io_phys, IO_PHYS 17 .equ io_phys, IO_PHYS
18 18
19 .macro addruart, rp, rv 19 .macro addruart, rp, rv, tmp
20 mov \rp, #0x00020000 @ UART1 20 mov \rp, #0x00020000 @ UART1
21 add \rv, \rp, #io_virt @ virtual address 21 add \rv, \rp, #io_virt @ virtual address
22 add \rp, \rp, #io_phys @ physical base address 22 add \rp, \rp, #io_phys @ physical base address
diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h
deleted file mode 100644
index 96dcf50c51d3..000000000000
--- a/arch/arm/mach-h720x/include/mach/memory.h
+++ /dev/null
@@ -1,11 +0,0 @@
1/*
2 * arch/arm/mach-h720x/include/mach/memory.h
3 *
4 * Copyright (c) 2000 Jungjun Kim
5 *
6 */
7#ifndef __ASM_ARCH_MEMORY_H
8#define __ASM_ARCH_MEMORY_H
9
10#define PLAT_PHYS_OFFSET UL(0x40000000)
11#endif
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
index ede2710f8b76..215259083945 100644
--- a/arch/arm/mach-imx/mach-armadillo5x0.c
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -558,7 +558,7 @@ static struct sys_timer armadillo5x0_timer = {
558 558
559MACHINE_START(ARMADILLO5X0, "Armadillo-500") 559MACHINE_START(ARMADILLO5X0, "Armadillo-500")
560 /* Maintainer: Alberto Panizzo */ 560 /* Maintainer: Alberto Panizzo */
561 .boot_params = MX3x_PHYS_OFFSET + 0x100, 561 .atag_offset = 0x100,
562 .map_io = mx31_map_io, 562 .map_io = mx31_map_io,
563 .init_early = imx31_init_early, 563 .init_early = imx31_init_early,
564 .init_irq = mx31_init_irq, 564 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index f851fe903687..b1ec2cf53bb0 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -311,7 +311,7 @@ static struct sys_timer eukrea_cpuimx27_timer = {
311}; 311};
312 312
313MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27") 313MACHINE_START(EUKREA_CPUIMX27, "EUKREA CPUIMX27")
314 .boot_params = MX27_PHYS_OFFSET + 0x100, 314 .atag_offset = 0x100,
315 .map_io = mx27_map_io, 315 .map_io = mx27_map_io,
316 .init_early = imx27_init_early, 316 .init_early = imx27_init_early,
317 .init_irq = mx27_init_irq, 317 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
index 4bd083ba9af2..470b654b0e6e 100644
--- a/arch/arm/mach-imx/mach-cpuimx35.c
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -194,7 +194,7 @@ struct sys_timer eukrea_cpuimx35_timer = {
194 194
195MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35") 195MACHINE_START(EUKREA_CPUIMX35SD, "Eukrea CPUIMX35")
196 /* Maintainer: Eukrea Electromatique */ 196 /* Maintainer: Eukrea Electromatique */
197 .boot_params = MX3x_PHYS_OFFSET + 0x100, 197 .atag_offset = 0x100,
198 .map_io = mx35_map_io, 198 .map_io = mx35_map_io,
199 .init_early = imx35_init_early, 199 .init_early = imx35_init_early,
200 .init_irq = mx35_init_irq, 200 .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 2442d5da883d..9163318e95a2 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -163,7 +163,7 @@ static struct sys_timer eukrea_cpuimx25_timer = {
163 163
164MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25") 164MACHINE_START(EUKREA_CPUIMX25SD, "Eukrea CPUIMX25")
165 /* Maintainer: Eukrea Electromatique */ 165 /* Maintainer: Eukrea Electromatique */
166 .boot_params = MX25_PHYS_OFFSET + 0x100, 166 .atag_offset = 0x100,
167 .map_io = mx25_map_io, 167 .map_io = mx25_map_io,
168 .init_early = imx25_init_early, 168 .init_early = imx25_init_early,
169 .init_irq = mx25_init_irq, 169 .init_irq = mx25_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 6778f8193bc6..22306ce28658 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -275,7 +275,7 @@ static struct sys_timer visstrim_m10_timer = {
275}; 275};
276 276
277MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10") 277MACHINE_START(IMX27_VISSTRIM_M10, "Vista Silicon Visstrim_M10")
278 .boot_params = MX27_PHYS_OFFSET + 0x100, 278 .atag_offset = 0x100,
279 .map_io = mx27_map_io, 279 .map_io = mx27_map_io,
280 .init_early = imx27_init_early, 280 .init_early = imx27_init_early,
281 .init_irq = mx27_init_irq, 281 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx27ipcam.c b/arch/arm/mach-imx/mach-imx27ipcam.c
index 272f793e9247..8da48b33fc53 100644
--- a/arch/arm/mach-imx/mach-imx27ipcam.c
+++ b/arch/arm/mach-imx/mach-imx27ipcam.c
@@ -71,7 +71,7 @@ static struct sys_timer mx27ipcam_timer = {
71 71
72MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM") 72MACHINE_START(IMX27IPCAM, "Freescale IMX27IPCAM")
73 /* maintainer: Freescale Semiconductor, Inc. */ 73 /* maintainer: Freescale Semiconductor, Inc. */
74 .boot_params = MX27_PHYS_OFFSET + 0x100, 74 .atag_offset = 0x100,
75 .map_io = mx27_map_io, 75 .map_io = mx27_map_io,
76 .init_early = imx27_init_early, 76 .init_early = imx27_init_early,
77 .init_irq = mx27_init_irq, 77 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index d81a769fe895..21a14a20e2c3 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -77,7 +77,7 @@ static struct sys_timer mx27lite_timer = {
77}; 77};
78 78
79MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE") 79MACHINE_START(IMX27LITE, "LogicPD i.MX27LITE")
80 .boot_params = MX27_PHYS_OFFSET + 0x100, 80 .atag_offset = 0x100,
81 .map_io = mx27_map_io, 81 .map_io = mx27_map_io,
82 .init_early = imx27_init_early, 82 .init_early = imx27_init_early,
83 .init_irq = mx27_init_irq, 83 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
index e472a1d88058..7c20e9e58006 100644
--- a/arch/arm/mach-imx/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -271,7 +271,7 @@ static struct sys_timer kzm_timer = {
271}; 271};
272 272
273MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01") 273MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
274 .boot_params = MX3x_PHYS_OFFSET + 0x100, 274 .atag_offset = 0x100,
275 .map_io = kzm_map_io, 275 .map_io = kzm_map_io,
276 .init_early = imx31_init_early, 276 .init_early = imx31_init_early,
277 .init_irq = mx31_init_irq, 277 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 5cd8bee46960..530ea08dbafd 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -145,7 +145,7 @@ struct sys_timer mx1ads_timer = {
145 145
146MACHINE_START(MX1ADS, "Freescale MX1ADS") 146MACHINE_START(MX1ADS, "Freescale MX1ADS")
147 /* Maintainer: Sascha Hauer, Pengutronix */ 147 /* Maintainer: Sascha Hauer, Pengutronix */
148 .boot_params = MX1_PHYS_OFFSET + 0x100, 148 .atag_offset = 0x100,
149 .map_io = mx1_map_io, 149 .map_io = mx1_map_io,
150 .init_early = imx1_init_early, 150 .init_early = imx1_init_early,
151 .init_irq = mx1_init_irq, 151 .init_irq = mx1_init_irq,
@@ -154,7 +154,7 @@ MACHINE_START(MX1ADS, "Freescale MX1ADS")
154MACHINE_END 154MACHINE_END
155 155
156MACHINE_START(MXLADS, "Freescale MXLADS") 156MACHINE_START(MXLADS, "Freescale MXLADS")
157 .boot_params = MX1_PHYS_OFFSET + 0x100, 157 .atag_offset = 0x100,
158 .map_io = mx1_map_io, 158 .map_io = mx1_map_io,
159 .init_early = imx1_init_early, 159 .init_early = imx1_init_early,
160 .init_irq = mx1_init_irq, 160 .init_irq = mx1_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index d389ecf9b5a8..e56828da26b2 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -305,7 +305,7 @@ static struct sys_timer mx21ads_timer = {
305 305
306MACHINE_START(MX21ADS, "Freescale i.MX21ADS") 306MACHINE_START(MX21ADS, "Freescale i.MX21ADS")
307 /* maintainer: Freescale Semiconductor, Inc. */ 307 /* maintainer: Freescale Semiconductor, Inc. */
308 .boot_params = MX21_PHYS_OFFSET + 0x100, 308 .atag_offset = 0x100,
309 .map_io = mx21ads_map_io, 309 .map_io = mx21ads_map_io,
310 .init_early = imx21_init_early, 310 .init_early = imx21_init_early,
311 .init_irq = mx21_init_irq, 311 .init_irq = mx21_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 7f66a91df361..dd25ee82e70a 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -253,7 +253,7 @@ static struct sys_timer mx25pdk_timer = {
253 253
254MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)") 254MACHINE_START(MX25_3DS, "Freescale MX25PDK (3DS)")
255 /* Maintainer: Freescale Semiconductor, Inc. */ 255 /* Maintainer: Freescale Semiconductor, Inc. */
256 .boot_params = MX25_PHYS_OFFSET + 0x100, 256 .atag_offset = 0x100,
257 .map_io = mx25_map_io, 257 .map_io = mx25_map_io,
258 .init_early = imx25_init_early, 258 .init_early = imx25_init_early,
259 .init_irq = mx25_init_irq, 259 .init_irq = mx25_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 6fa6934ab150..2eafbac2c763 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -421,7 +421,7 @@ static struct sys_timer mx27pdk_timer = {
421 421
422MACHINE_START(MX27_3DS, "Freescale MX27PDK") 422MACHINE_START(MX27_3DS, "Freescale MX27PDK")
423 /* maintainer: Freescale Semiconductor, Inc. */ 423 /* maintainer: Freescale Semiconductor, Inc. */
424 .boot_params = MX27_PHYS_OFFSET + 0x100, 424 .atag_offset = 0x100,
425 .map_io = mx27_map_io, 425 .map_io = mx27_map_io,
426 .init_early = imx27_init_early, 426 .init_early = imx27_init_early,
427 .init_irq = mx27_init_irq, 427 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index e1addc1a5813..635b0509068b 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -344,7 +344,7 @@ static void __init mx27ads_map_io(void)
344 344
345MACHINE_START(MX27ADS, "Freescale i.MX27ADS") 345MACHINE_START(MX27ADS, "Freescale i.MX27ADS")
346 /* maintainer: Freescale Semiconductor, Inc. */ 346 /* maintainer: Freescale Semiconductor, Inc. */
347 .boot_params = MX27_PHYS_OFFSET + 0x100, 347 .atag_offset = 0x100,
348 .map_io = mx27ads_map_io, 348 .map_io = mx27ads_map_io,
349 .init_early = imx27_init_early, 349 .init_early = imx27_init_early,
350 .init_irq = mx27_init_irq, 350 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
index c20be7530927..589066fb3316 100644
--- a/arch/arm/mach-imx/mach-mx31_3ds.c
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -764,7 +764,7 @@ static void __init mx31_3ds_reserve(void)
764 764
765MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)") 765MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
766 /* Maintainer: Freescale Semiconductor, Inc. */ 766 /* Maintainer: Freescale Semiconductor, Inc. */
767 .boot_params = MX3x_PHYS_OFFSET + 0x100, 767 .atag_offset = 0x100,
768 .map_io = mx31_map_io, 768 .map_io = mx31_map_io,
769 .init_early = imx31_init_early, 769 .init_early = imx31_init_early,
770 .init_irq = mx31_init_irq, 770 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
index 29ca8907a780..910c4561d35f 100644
--- a/arch/arm/mach-imx/mach-mx31ads.c
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -535,7 +535,7 @@ static struct sys_timer mx31ads_timer = {
535 535
536MACHINE_START(MX31ADS, "Freescale MX31ADS") 536MACHINE_START(MX31ADS, "Freescale MX31ADS")
537 /* Maintainer: Freescale Semiconductor, Inc. */ 537 /* Maintainer: Freescale Semiconductor, Inc. */
538 .boot_params = MX3x_PHYS_OFFSET + 0x100, 538 .atag_offset = 0x100,
539 .map_io = mx31ads_map_io, 539 .map_io = mx31ads_map_io,
540 .init_early = imx31_init_early, 540 .init_early = imx31_init_early,
541 .init_irq = mx31ads_init_irq, 541 .init_irq = mx31ads_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
index 126913ad106a..e92eaf91a7be 100644
--- a/arch/arm/mach-imx/mach-mx31lilly.c
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -295,7 +295,7 @@ static struct sys_timer mx31lilly_timer = {
295}; 295};
296 296
297MACHINE_START(LILLY1131, "INCO startec LILLY-1131") 297MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
298 .boot_params = MX3x_PHYS_OFFSET + 0x100, 298 .atag_offset = 0x100,
299 .map_io = mx31_map_io, 299 .map_io = mx31_map_io,
300 .init_early = imx31_init_early, 300 .init_early = imx31_init_early,
301 .init_irq = mx31_init_irq, 301 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
index 4b47fd9fdd89..5242cb78b563 100644
--- a/arch/arm/mach-imx/mach-mx31lite.c
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -280,7 +280,7 @@ struct sys_timer mx31lite_timer = {
280 280
281MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM") 281MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
282 /* Maintainer: Freescale Semiconductor, Inc. */ 282 /* Maintainer: Freescale Semiconductor, Inc. */
283 .boot_params = MX3x_PHYS_OFFSET + 0x100, 283 .atag_offset = 0x100,
284 .map_io = mx31lite_map_io, 284 .map_io = mx31lite_map_io,
285 .init_early = imx31_init_early, 285 .init_early = imx31_init_early,
286 .init_irq = mx31_init_irq, 286 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
index b358383120e7..1d01ef28f25d 100644
--- a/arch/arm/mach-imx/mach-mx31moboard.c
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -567,7 +567,7 @@ static void __init mx31moboard_reserve(void)
567 567
568MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard") 568MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
569 /* Maintainer: Valentin Longchamp, EPFL Mobots group */ 569 /* Maintainer: Valentin Longchamp, EPFL Mobots group */
570 .boot_params = MX3x_PHYS_OFFSET + 0x100, 570 .atag_offset = 0x100,
571 .reserve = mx31moboard_reserve, 571 .reserve = mx31moboard_reserve,
572 .map_io = mx31_map_io, 572 .map_io = mx31_map_io,
573 .init_early = imx31_init_early, 573 .init_early = imx31_init_early,
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
index b3b9bd8ac2a3..f2a873dc08ce 100644
--- a/arch/arm/mach-imx/mach-mx35_3ds.c
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -217,7 +217,7 @@ struct sys_timer mx35pdk_timer = {
217 217
218MACHINE_START(MX35_3DS, "Freescale MX35PDK") 218MACHINE_START(MX35_3DS, "Freescale MX35PDK")
219 /* Maintainer: Freescale Semiconductor, Inc */ 219 /* Maintainer: Freescale Semiconductor, Inc */
220 .boot_params = MX3x_PHYS_OFFSET + 0x100, 220 .atag_offset = 0x100,
221 .map_io = mx35_map_io, 221 .map_io = mx35_map_io,
222 .init_early = imx35_init_early, 222 .init_early = imx35_init_early,
223 .init_irq = mx35_init_irq, 223 .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index c85876fed663..5ec3989704fd 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -267,7 +267,7 @@ static struct sys_timer mxt_td60_timer = {
267 267
268MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60") 268MACHINE_START(MXT_TD60, "Maxtrack i-MXT TD60")
269 /* maintainer: Maxtrack Industrial */ 269 /* maintainer: Maxtrack Industrial */
270 .boot_params = MX27_PHYS_OFFSET + 0x100, 270 .atag_offset = 0x100,
271 .map_io = mx27_map_io, 271 .map_io = mx27_map_io,
272 .init_early = imx27_init_early, 272 .init_early = imx27_init_early,
273 .init_irq = mx27_init_irq, 273 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 71083aa16038..0f6bd1199038 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -435,7 +435,7 @@ static struct sys_timer pca100_timer = {
435}; 435};
436 436
437MACHINE_START(PCA100, "phyCARD-i.MX27") 437MACHINE_START(PCA100, "phyCARD-i.MX27")
438 .boot_params = MX27_PHYS_OFFSET + 0x100, 438 .atag_offset = 0x100,
439 .map_io = mx27_map_io, 439 .map_io = mx27_map_io,
440 .init_early = imx27_init_early, 440 .init_early = imx27_init_early,
441 .init_irq = mx27_init_irq, 441 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
index f45b7cd72c8a..186d4eb90796 100644
--- a/arch/arm/mach-imx/mach-pcm037.c
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -688,7 +688,7 @@ static void __init pcm037_reserve(void)
688 688
689MACHINE_START(PCM037, "Phytec Phycore pcm037") 689MACHINE_START(PCM037, "Phytec Phycore pcm037")
690 /* Maintainer: Pengutronix */ 690 /* Maintainer: Pengutronix */
691 .boot_params = MX3x_PHYS_OFFSET + 0x100, 691 .atag_offset = 0x100,
692 .reserve = pcm037_reserve, 692 .reserve = pcm037_reserve,
693 .map_io = mx31_map_io, 693 .map_io = mx31_map_io,
694 .init_early = imx31_init_early, 694 .init_early = imx31_init_early,
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 2d6a64bbac44..091bcf87e1a0 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -349,7 +349,7 @@ static struct sys_timer pcm038_timer = {
349}; 349};
350 350
351MACHINE_START(PCM038, "phyCORE-i.MX27") 351MACHINE_START(PCM038, "phyCORE-i.MX27")
352 .boot_params = MX27_PHYS_OFFSET + 0x100, 352 .atag_offset = 0x100,
353 .map_io = mx27_map_io, 353 .map_io = mx27_map_io,
354 .init_early = imx27_init_early, 354 .init_early = imx27_init_early,
355 .init_irq = mx27_init_irq, 355 .init_irq = mx27_init_irq,
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
index 660ec3e80cf8..0a4d31de7738 100644
--- a/arch/arm/mach-imx/mach-pcm043.c
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -418,7 +418,7 @@ struct sys_timer pcm043_timer = {
418 418
419MACHINE_START(PCM043, "Phytec Phycore pcm043") 419MACHINE_START(PCM043, "Phytec Phycore pcm043")
420 /* Maintainer: Pengutronix */ 420 /* Maintainer: Pengutronix */
421 .boot_params = MX3x_PHYS_OFFSET + 0x100, 421 .atag_offset = 0x100,
422 .map_io = mx35_map_io, 422 .map_io = mx35_map_io,
423 .init_early = imx35_init_early, 423 .init_early = imx35_init_early,
424 .init_irq = mx35_init_irq, 424 .init_irq = mx35_init_irq,
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
index 3626f486498a..9e11359c324c 100644
--- a/arch/arm/mach-imx/mach-qong.c
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -262,7 +262,7 @@ static struct sys_timer qong_timer = {
262 262
263MACHINE_START(QONG, "Dave/DENX QongEVB-LITE") 263MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
264 /* Maintainer: DENX Software Engineering GmbH */ 264 /* Maintainer: DENX Software Engineering GmbH */
265 .boot_params = MX3x_PHYS_OFFSET + 0x100, 265 .atag_offset = 0x100,
266 .map_io = mx31_map_io, 266 .map_io = mx31_map_io,
267 .init_early = imx31_init_early, 267 .init_early = imx31_init_early,
268 .init_irq = mx31_init_irq, 268 .init_irq = mx31_init_irq,
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index db2d60470e15..85d32845ee1e 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -137,7 +137,7 @@ static struct sys_timer scb9328_timer = {
137 137
138MACHINE_START(SCB9328, "Synertronixx scb9328") 138MACHINE_START(SCB9328, "Synertronixx scb9328")
139 /* Sascha Hauer */ 139 /* Sascha Hauer */
140 .boot_params = 0x08000100, 140 .atag_offset = 100,
141 .map_io = mx1_map_io, 141 .map_io = mx1_map_io,
142 .init_early = imx1_init_early, 142 .init_early = imx1_init_early,
143 .init_irq = mx1_init_irq, 143 .init_irq = mx1_init_irq,
diff --git a/arch/arm/mach-integrator/include/mach/debug-macro.S b/arch/arm/mach-integrator/include/mach/debug-macro.S
index a1f598fd3a56..411b116077e4 100644
--- a/arch/arm/mach-integrator/include/mach/debug-macro.S
+++ b/arch/arm/mach-integrator/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0x16000000 @ physical base address 15 mov \rp, #0x16000000 @ physical base address
16 mov \rv, #0xf0000000 @ virtual base 16 mov \rv, #0xf0000000 @ virtual base
17 add \rv, \rv, #0x16000000 >> 4 17 add \rv, \rv, #0x16000000 >> 4
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index f2119908a0b3..a1769f35a86e 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -465,7 +465,7 @@ static struct sys_timer ap_timer = {
465 465
466MACHINE_START(INTEGRATOR, "ARM-Integrator") 466MACHINE_START(INTEGRATOR, "ARM-Integrator")
467 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 467 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
468 .boot_params = 0x00000100, 468 .atag_offset = 0x100,
469 .reserve = integrator_reserve, 469 .reserve = integrator_reserve,
470 .map_io = ap_map_io, 470 .map_io = ap_map_io,
471 .init_early = integrator_init_early, 471 .init_early = integrator_init_early,
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 4eb03ab5cb46..5de49c33e4d4 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -492,7 +492,7 @@ static struct sys_timer cp_timer = {
492 492
493MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP") 493MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
494 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 494 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
495 .boot_params = 0x00000100, 495 .atag_offset = 0x100,
496 .reserve = integrator_reserve, 496 .reserve = integrator_reserve,
497 .map_io = intcp_map_io, 497 .map_io = intcp_map_io,
498 .init_early = intcp_init_early, 498 .init_early = intcp_init_early,
diff --git a/arch/arm/mach-iop13xx/include/mach/debug-macro.S b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
index e664466d51bf..d869a6f67e5c 100644
--- a/arch/arm/mach-iop13xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop13xx/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0x00002300 15 mov \rp, #0x00002300
16 orr \rp, \rp, #0x00000040 16 orr \rp, \rp, #0x00000040
17 orr \rv, \rp, #0xfe000000 @ virtual 17 orr \rv, \rp, #0xfe000000 @ virtual
diff --git a/arch/arm/mach-iop13xx/iq81340mc.c b/arch/arm/mach-iop13xx/iq81340mc.c
index 23dfaffc586c..4cf2cc477eae 100644
--- a/arch/arm/mach-iop13xx/iq81340mc.c
+++ b/arch/arm/mach-iop13xx/iq81340mc.c
@@ -91,7 +91,7 @@ static struct sys_timer iq81340mc_timer = {
91 91
92MACHINE_START(IQ81340MC, "Intel IQ81340MC") 92MACHINE_START(IQ81340MC, "Intel IQ81340MC")
93 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ 93 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
94 .boot_params = 0x00000100, 94 .atag_offset = 0x100,
95 .map_io = iop13xx_map_io, 95 .map_io = iop13xx_map_io,
96 .init_irq = iop13xx_init_irq, 96 .init_irq = iop13xx_init_irq,
97 .timer = &iq81340mc_timer, 97 .timer = &iq81340mc_timer,
diff --git a/arch/arm/mach-iop13xx/iq81340sc.c b/arch/arm/mach-iop13xx/iq81340sc.c
index df3492a9c280..cd9e27499a1e 100644
--- a/arch/arm/mach-iop13xx/iq81340sc.c
+++ b/arch/arm/mach-iop13xx/iq81340sc.c
@@ -93,7 +93,7 @@ static struct sys_timer iq81340sc_timer = {
93 93
94MACHINE_START(IQ81340SC, "Intel IQ81340SC") 94MACHINE_START(IQ81340SC, "Intel IQ81340SC")
95 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */ 95 /* Maintainer: Dan Williams <dan.j.williams@intel.com> */
96 .boot_params = 0x00000100, 96 .atag_offset = 0x100,
97 .map_io = iop13xx_map_io, 97 .map_io = iop13xx_map_io,
98 .init_irq = iop13xx_init_irq, 98 .init_irq = iop13xx_init_irq,
99 .timer = &iq81340sc_timer, 99 .timer = &iq81340sc_timer,
diff --git a/arch/arm/mach-iop32x/em7210.c b/arch/arm/mach-iop32x/em7210.c
index 6cbffbfc2bba..4325055d4e19 100644
--- a/arch/arm/mach-iop32x/em7210.c
+++ b/arch/arm/mach-iop32x/em7210.c
@@ -203,7 +203,7 @@ static void __init em7210_init_machine(void)
203} 203}
204 204
205MACHINE_START(EM7210, "Lanner EM7210") 205MACHINE_START(EM7210, "Lanner EM7210")
206 .boot_params = 0xa0000100, 206 .atag_offset = 0x100,
207 .map_io = em7210_map_io, 207 .map_io = em7210_map_io,
208 .init_irq = iop32x_init_irq, 208 .init_irq = iop32x_init_irq,
209 .timer = &em7210_timer, 209 .timer = &em7210_timer,
diff --git a/arch/arm/mach-iop32x/glantank.c b/arch/arm/mach-iop32x/glantank.c
index ceef5d4dce1a..0edc88020577 100644
--- a/arch/arm/mach-iop32x/glantank.c
+++ b/arch/arm/mach-iop32x/glantank.c
@@ -207,7 +207,7 @@ static void __init glantank_init_machine(void)
207 207
208MACHINE_START(GLANTANK, "GLAN Tank") 208MACHINE_START(GLANTANK, "GLAN Tank")
209 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 209 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
210 .boot_params = 0xa0000100, 210 .atag_offset = 0x100,
211 .map_io = glantank_map_io, 211 .map_io = glantank_map_io,
212 .init_irq = iop32x_init_irq, 212 .init_irq = iop32x_init_irq,
213 .timer = &glantank_timer, 213 .timer = &glantank_timer,
diff --git a/arch/arm/mach-iop32x/include/mach/debug-macro.S b/arch/arm/mach-iop32x/include/mach/debug-macro.S
index ff9e76c09f35..363bdf90b34d 100644
--- a/arch/arm/mach-iop32x/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop32x/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0xfe000000 @ physical as well as virtual 15 mov \rp, #0xfe000000 @ physical as well as virtual
16 orr \rp, \rp, #0x00800000 @ location of the UART 16 orr \rp, \rp, #0x00800000 @ location of the UART
17 mov \rv, \rp 17 mov \rv, \rp
diff --git a/arch/arm/mach-iop32x/include/mach/memory.h b/arch/arm/mach-iop32x/include/mach/memory.h
deleted file mode 100644
index 169cc239f76c..000000000000
--- a/arch/arm/mach-iop32x/include/mach/memory.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-iop32x/include/mach/memory.h
3 */
4
5#ifndef __MEMORY_H
6#define __MEMORY_H
7
8/*
9 * Physical DRAM offset.
10 */
11#define PLAT_PHYS_OFFSET UL(0xa0000000)
12
13#endif
diff --git a/arch/arm/mach-iop32x/iq31244.c b/arch/arm/mach-iop32x/iq31244.c
index 3a62514dae7c..9e7aaccfeba0 100644
--- a/arch/arm/mach-iop32x/iq31244.c
+++ b/arch/arm/mach-iop32x/iq31244.c
@@ -313,7 +313,7 @@ __setup("force_ep80219", force_ep80219_setup);
313 313
314MACHINE_START(IQ31244, "Intel IQ31244") 314MACHINE_START(IQ31244, "Intel IQ31244")
315 /* Maintainer: Intel Corp. */ 315 /* Maintainer: Intel Corp. */
316 .boot_params = 0xa0000100, 316 .atag_offset = 0x100,
317 .map_io = iq31244_map_io, 317 .map_io = iq31244_map_io,
318 .init_irq = iop32x_init_irq, 318 .init_irq = iop32x_init_irq,
319 .timer = &iq31244_timer, 319 .timer = &iq31244_timer,
@@ -327,7 +327,7 @@ MACHINE_END
327 */ 327 */
328MACHINE_START(EP80219, "Intel EP80219") 328MACHINE_START(EP80219, "Intel EP80219")
329 /* Maintainer: Intel Corp. */ 329 /* Maintainer: Intel Corp. */
330 .boot_params = 0xa0000100, 330 .atag_offset = 0x100,
331 .map_io = iq31244_map_io, 331 .map_io = iq31244_map_io,
332 .init_irq = iop32x_init_irq, 332 .init_irq = iop32x_init_irq,
333 .timer = &iq31244_timer, 333 .timer = &iq31244_timer,
diff --git a/arch/arm/mach-iop32x/iq80321.c b/arch/arm/mach-iop32x/iq80321.c
index 35b7e6914d3b..53ea86f649dd 100644
--- a/arch/arm/mach-iop32x/iq80321.c
+++ b/arch/arm/mach-iop32x/iq80321.c
@@ -186,7 +186,7 @@ static void __init iq80321_init_machine(void)
186 186
187MACHINE_START(IQ80321, "Intel IQ80321") 187MACHINE_START(IQ80321, "Intel IQ80321")
188 /* Maintainer: Intel Corp. */ 188 /* Maintainer: Intel Corp. */
189 .boot_params = 0xa0000100, 189 .atag_offset = 0x100,
190 .map_io = iq80321_map_io, 190 .map_io = iq80321_map_io,
191 .init_irq = iop32x_init_irq, 191 .init_irq = iop32x_init_irq,
192 .timer = &iq80321_timer, 192 .timer = &iq80321_timer,
diff --git a/arch/arm/mach-iop32x/n2100.c b/arch/arm/mach-iop32x/n2100.c
index 1a374eab6007..d7269279968c 100644
--- a/arch/arm/mach-iop32x/n2100.c
+++ b/arch/arm/mach-iop32x/n2100.c
@@ -327,7 +327,7 @@ static void __init n2100_init_machine(void)
327 327
328MACHINE_START(N2100, "Thecus N2100") 328MACHINE_START(N2100, "Thecus N2100")
329 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 329 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
330 .boot_params = 0xa0000100, 330 .atag_offset = 0x100,
331 .map_io = n2100_map_io, 331 .map_io = n2100_map_io,
332 .init_irq = iop32x_init_irq, 332 .init_irq = iop32x_init_irq,
333 .timer = &n2100_timer, 333 .timer = &n2100_timer,
diff --git a/arch/arm/mach-iop33x/include/mach/debug-macro.S b/arch/arm/mach-iop33x/include/mach/debug-macro.S
index 40c500dd1fac..361be1f6026e 100644
--- a/arch/arm/mach-iop33x/include/mach/debug-macro.S
+++ b/arch/arm/mach-iop33x/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * published by the Free Software Foundation. 11 * published by the Free Software Foundation.
12 */ 12 */
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0x00ff0000 15 mov \rp, #0x00ff0000
16 orr \rp, \rp, #0x0000f700 16 orr \rp, \rp, #0x0000f700
17 orr \rv, #0xfe000000 @ virtual 17 orr \rv, #0xfe000000 @ virtual
diff --git a/arch/arm/mach-iop33x/include/mach/memory.h b/arch/arm/mach-iop33x/include/mach/memory.h
deleted file mode 100644
index 8e1daf7006b6..000000000000
--- a/arch/arm/mach-iop33x/include/mach/memory.h
+++ /dev/null
@@ -1,13 +0,0 @@
1/*
2 * arch/arm/mach-iop33x/include/mach/memory.h
3 */
4
5#ifndef __MEMORY_H
6#define __MEMORY_H
7
8/*
9 * Physical DRAM offset.
10 */
11#define PLAT_PHYS_OFFSET UL(0x00000000)
12
13#endif
diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 637c0272d5e0..9e14ccc56f8e 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -141,7 +141,7 @@ static void __init iq80331_init_machine(void)
141 141
142MACHINE_START(IQ80331, "Intel IQ80331") 142MACHINE_START(IQ80331, "Intel IQ80331")
143 /* Maintainer: Intel Corp. */ 143 /* Maintainer: Intel Corp. */
144 .boot_params = 0x00000100, 144 .atag_offset = 0x100,
145 .map_io = iop3xx_map_io, 145 .map_io = iop3xx_map_io,
146 .init_irq = iop33x_init_irq, 146 .init_irq = iop33x_init_irq,
147 .timer = &iq80331_timer, 147 .timer = &iq80331_timer,
diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 90a0436d7255..09c899a2523f 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -141,7 +141,7 @@ static void __init iq80332_init_machine(void)
141 141
142MACHINE_START(IQ80332, "Intel IQ80332") 142MACHINE_START(IQ80332, "Intel IQ80332")
143 /* Maintainer: Intel Corp. */ 143 /* Maintainer: Intel Corp. */
144 .boot_params = 0x00000100, 144 .atag_offset = 0x100,
145 .map_io = iop3xx_map_io, 145 .map_io = iop3xx_map_io,
146 .init_irq = iop33x_init_irq, 146 .init_irq = iop33x_init_irq,
147 .timer = &iq80332_timer, 147 .timer = &iq80332_timer,
diff --git a/arch/arm/mach-ixp2000/enp2611.c b/arch/arm/mach-ixp2000/enp2611.c
index 62c60ade5274..af9994537e01 100644
--- a/arch/arm/mach-ixp2000/enp2611.c
+++ b/arch/arm/mach-ixp2000/enp2611.c
@@ -254,7 +254,7 @@ static void __init enp2611_init_machine(void)
254 254
255MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board") 255MACHINE_START(ENP2611, "Radisys ENP-2611 PCI network processor board")
256 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */ 256 /* Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> */
257 .boot_params = 0x00000100, 257 .atag_offset = 0x100,
258 .map_io = enp2611_map_io, 258 .map_io = enp2611_map_io,
259 .init_irq = ixp2000_init_irq, 259 .init_irq = ixp2000_init_irq,
260 .timer = &enp2611_timer, 260 .timer = &enp2611_timer,
diff --git a/arch/arm/mach-ixp2000/include/mach/debug-macro.S b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
index 0ef533b20972..bdd3ccdc2890 100644
--- a/arch/arm/mach-ixp2000/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp2000/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0x00030000 15 mov \rp, #0x00030000
16#ifdef __ARMEB__ 16#ifdef __ARMEB__
17 orr \rp, \rp, #0x00000003 17 orr \rp, \rp, #0x00000003
diff --git a/arch/arm/mach-ixp2000/ixdp2400.c b/arch/arm/mach-ixp2000/ixdp2400.c
index 5bad1a8419b7..f7dfd9700141 100644
--- a/arch/arm/mach-ixp2000/ixdp2400.c
+++ b/arch/arm/mach-ixp2000/ixdp2400.c
@@ -171,7 +171,7 @@ void __init ixdp2400_init_irq(void)
171 171
172MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform") 172MACHINE_START(IXDP2400, "Intel IXDP2400 Development Platform")
173 /* Maintainer: MontaVista Software, Inc. */ 173 /* Maintainer: MontaVista Software, Inc. */
174 .boot_params = 0x00000100, 174 .atag_offset = 0x100,
175 .map_io = ixdp2x00_map_io, 175 .map_io = ixdp2x00_map_io,
176 .init_irq = ixdp2400_init_irq, 176 .init_irq = ixdp2400_init_irq,
177 .timer = &ixdp2400_timer, 177 .timer = &ixdp2400_timer,
diff --git a/arch/arm/mach-ixp2000/ixdp2800.c b/arch/arm/mach-ixp2000/ixdp2800.c
index 3d3cef876467..d33bcac1ec92 100644
--- a/arch/arm/mach-ixp2000/ixdp2800.c
+++ b/arch/arm/mach-ixp2000/ixdp2800.c
@@ -286,7 +286,7 @@ void __init ixdp2800_init_irq(void)
286 286
287MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform") 287MACHINE_START(IXDP2800, "Intel IXDP2800 Development Platform")
288 /* Maintainer: MontaVista Software, Inc. */ 288 /* Maintainer: MontaVista Software, Inc. */
289 .boot_params = 0x00000100, 289 .atag_offset = 0x100,
290 .map_io = ixdp2x00_map_io, 290 .map_io = ixdp2x00_map_io,
291 .init_irq = ixdp2800_init_irq, 291 .init_irq = ixdp2800_init_irq,
292 .timer = &ixdp2800_timer, 292 .timer = &ixdp2800_timer,
diff --git a/arch/arm/mach-ixp2000/ixdp2x01.c b/arch/arm/mach-ixp2000/ixdp2x01.c
index be2a254f1374..61a28676b5be 100644
--- a/arch/arm/mach-ixp2000/ixdp2x01.c
+++ b/arch/arm/mach-ixp2000/ixdp2x01.c
@@ -417,7 +417,7 @@ static void __init ixdp2x01_init_machine(void)
417#ifdef CONFIG_ARCH_IXDP2401 417#ifdef CONFIG_ARCH_IXDP2401
418MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform") 418MACHINE_START(IXDP2401, "Intel IXDP2401 Development Platform")
419 /* Maintainer: MontaVista Software, Inc. */ 419 /* Maintainer: MontaVista Software, Inc. */
420 .boot_params = 0x00000100, 420 .atag_offset = 0x100,
421 .map_io = ixdp2x01_map_io, 421 .map_io = ixdp2x01_map_io,
422 .init_irq = ixdp2x01_init_irq, 422 .init_irq = ixdp2x01_init_irq,
423 .timer = &ixdp2x01_timer, 423 .timer = &ixdp2x01_timer,
@@ -428,7 +428,7 @@ MACHINE_END
428#ifdef CONFIG_ARCH_IXDP2801 428#ifdef CONFIG_ARCH_IXDP2801
429MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform") 429MACHINE_START(IXDP2801, "Intel IXDP2801 Development Platform")
430 /* Maintainer: MontaVista Software, Inc. */ 430 /* Maintainer: MontaVista Software, Inc. */
431 .boot_params = 0x00000100, 431 .atag_offset = 0x100,
432 .map_io = ixdp2x01_map_io, 432 .map_io = ixdp2x01_map_io,
433 .init_irq = ixdp2x01_init_irq, 433 .init_irq = ixdp2x01_init_irq,
434 .timer = &ixdp2x01_timer, 434 .timer = &ixdp2x01_timer,
@@ -441,7 +441,7 @@ MACHINE_END
441 */ 441 */
442MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform") 442MACHINE_START(IXDP28X5, "Intel IXDP2805/2855 Development Platform")
443 /* Maintainer: MontaVista Software, Inc. */ 443 /* Maintainer: MontaVista Software, Inc. */
444 .boot_params = 0x00000100, 444 .atag_offset = 0x100,
445 .map_io = ixdp2x01_map_io, 445 .map_io = ixdp2x01_map_io,
446 .init_irq = ixdp2x01_init_irq, 446 .init_irq = ixdp2x01_init_irq,
447 .timer = &ixdp2x01_timer, 447 .timer = &ixdp2x01_timer,
diff --git a/arch/arm/mach-ixp23xx/espresso.c b/arch/arm/mach-ixp23xx/espresso.c
index e25e5fe183ba..30dd31652e9d 100644
--- a/arch/arm/mach-ixp23xx/espresso.c
+++ b/arch/arm/mach-ixp23xx/espresso.c
@@ -88,6 +88,6 @@ MACHINE_START(ESPRESSO, "IP Fabrics Double Espresso")
88 .map_io = ixp23xx_map_io, 88 .map_io = ixp23xx_map_io,
89 .init_irq = ixp23xx_init_irq, 89 .init_irq = ixp23xx_init_irq,
90 .timer = &ixp23xx_timer, 90 .timer = &ixp23xx_timer,
91 .boot_params = 0x00000100, 91 .atag_offset = 0x100,
92 .init_machine = espresso_init, 92 .init_machine = espresso_init,
93MACHINE_END 93MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
index f7c6eef7fa22..5ff524c13744 100644
--- a/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp23xx/include/mach/debug-macro.S
@@ -12,7 +12,7 @@
12 */ 12 */
13#include <mach/ixp23xx.h> 13#include <mach/ixp23xx.h>
14 14
15 .macro addruart, rp, rv 15 .macro addruart, rp, rv, tmp
16 ldr \rp, =IXP23XX_PERIPHERAL_PHYS @ physical 16 ldr \rp, =IXP23XX_PERIPHERAL_PHYS @ physical
17 ldr \rv, =IXP23XX_PERIPHERAL_VIRT @ virtual 17 ldr \rv, =IXP23XX_PERIPHERAL_VIRT @ virtual
18#ifdef __ARMEB__ 18#ifdef __ARMEB__
diff --git a/arch/arm/mach-ixp23xx/ixdp2351.c b/arch/arm/mach-ixp23xx/ixdp2351.c
index ec028e35f401..b3a57e0f3419 100644
--- a/arch/arm/mach-ixp23xx/ixdp2351.c
+++ b/arch/arm/mach-ixp23xx/ixdp2351.c
@@ -331,6 +331,6 @@ MACHINE_START(IXDP2351, "Intel IXDP2351 Development Platform")
331 .map_io = ixdp2351_map_io, 331 .map_io = ixdp2351_map_io,
332 .init_irq = ixdp2351_init_irq, 332 .init_irq = ixdp2351_init_irq,
333 .timer = &ixp23xx_timer, 333 .timer = &ixp23xx_timer,
334 .boot_params = 0x00000100, 334 .atag_offset = 0x100,
335 .init_machine = ixdp2351_init, 335 .init_machine = ixdp2351_init,
336MACHINE_END 336MACHINE_END
diff --git a/arch/arm/mach-ixp23xx/roadrunner.c b/arch/arm/mach-ixp23xx/roadrunner.c
index 844551d2368b..8f4dcbba9025 100644
--- a/arch/arm/mach-ixp23xx/roadrunner.c
+++ b/arch/arm/mach-ixp23xx/roadrunner.c
@@ -175,6 +175,6 @@ MACHINE_START(ROADRUNNER, "ADI Engineering RoadRunner Development Platform")
175 .map_io = ixp23xx_map_io, 175 .map_io = ixp23xx_map_io,
176 .init_irq = ixp23xx_init_irq, 176 .init_irq = ixp23xx_init_irq,
177 .timer = &ixp23xx_timer, 177 .timer = &ixp23xx_timer,
178 .boot_params = 0x00000100, 178 .atag_offset = 0x100,
179 .init_machine = roadrunner_init, 179 .init_machine = roadrunner_init,
180MACHINE_END 180MACHINE_END
diff --git a/arch/arm/mach-ixp4xx/avila-setup.c b/arch/arm/mach-ixp4xx/avila-setup.c
index ee19c1d383aa..37609a22c450 100644
--- a/arch/arm/mach-ixp4xx/avila-setup.c
+++ b/arch/arm/mach-ixp4xx/avila-setup.c
@@ -167,7 +167,7 @@ MACHINE_START(AVILA, "Gateworks Avila Network Platform")
167 .map_io = ixp4xx_map_io, 167 .map_io = ixp4xx_map_io,
168 .init_irq = ixp4xx_init_irq, 168 .init_irq = ixp4xx_init_irq,
169 .timer = &ixp4xx_timer, 169 .timer = &ixp4xx_timer,
170 .boot_params = 0x0100, 170 .atag_offset = 0x100,
171 .init_machine = avila_init, 171 .init_machine = avila_init,
172#if defined(CONFIG_PCI) 172#if defined(CONFIG_PCI)
173 .dma_zone_size = SZ_64M, 173 .dma_zone_size = SZ_64M,
@@ -185,7 +185,7 @@ MACHINE_START(LOFT, "Giant Shoulder Inc Loft board")
185 .map_io = ixp4xx_map_io, 185 .map_io = ixp4xx_map_io,
186 .init_irq = ixp4xx_init_irq, 186 .init_irq = ixp4xx_init_irq,
187 .timer = &ixp4xx_timer, 187 .timer = &ixp4xx_timer,
188 .boot_params = 0x0100, 188 .atag_offset = 0x100,
189 .init_machine = avila_init, 189 .init_machine = avila_init,
190#if defined(CONFIG_PCI) 190#if defined(CONFIG_PCI)
191 .dma_zone_size = SZ_64M, 191 .dma_zone_size = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/coyote-setup.c b/arch/arm/mach-ixp4xx/coyote-setup.c
index e24564b5d935..81dfec31842b 100644
--- a/arch/arm/mach-ixp4xx/coyote-setup.c
+++ b/arch/arm/mach-ixp4xx/coyote-setup.c
@@ -112,7 +112,7 @@ MACHINE_START(ADI_COYOTE, "ADI Engineering Coyote")
112 .map_io = ixp4xx_map_io, 112 .map_io = ixp4xx_map_io,
113 .init_irq = ixp4xx_init_irq, 113 .init_irq = ixp4xx_init_irq,
114 .timer = &ixp4xx_timer, 114 .timer = &ixp4xx_timer,
115 .boot_params = 0x0100, 115 .atag_offset = 0x100,
116 .init_machine = coyote_init, 116 .init_machine = coyote_init,
117#if defined(CONFIG_PCI) 117#if defined(CONFIG_PCI)
118 .dma_zone_size = SZ_64M, 118 .dma_zone_size = SZ_64M,
@@ -130,7 +130,7 @@ MACHINE_START(IXDPG425, "Intel IXDPG425")
130 .map_io = ixp4xx_map_io, 130 .map_io = ixp4xx_map_io,
131 .init_irq = ixp4xx_init_irq, 131 .init_irq = ixp4xx_init_irq,
132 .timer = &ixp4xx_timer, 132 .timer = &ixp4xx_timer,
133 .boot_params = 0x0100, 133 .atag_offset = 0x100,
134 .init_machine = coyote_init, 134 .init_machine = coyote_init,
135MACHINE_END 135MACHINE_END
136#endif 136#endif
diff --git a/arch/arm/mach-ixp4xx/dsmg600-setup.c b/arch/arm/mach-ixp4xx/dsmg600-setup.c
index 96e378345801..8837fbca27ce 100644
--- a/arch/arm/mach-ixp4xx/dsmg600-setup.c
+++ b/arch/arm/mach-ixp4xx/dsmg600-setup.c
@@ -278,7 +278,7 @@ static void __init dsmg600_init(void)
278 278
279MACHINE_START(DSMG600, "D-Link DSM-G600 RevA") 279MACHINE_START(DSMG600, "D-Link DSM-G600 RevA")
280 /* Maintainer: www.nslu2-linux.org */ 280 /* Maintainer: www.nslu2-linux.org */
281 .boot_params = 0x00000100, 281 .atag_offset = 0x100,
282 .map_io = ixp4xx_map_io, 282 .map_io = ixp4xx_map_io,
283 .init_irq = ixp4xx_init_irq, 283 .init_irq = ixp4xx_init_irq,
284 .timer = &dsmg600_timer, 284 .timer = &dsmg600_timer,
diff --git a/arch/arm/mach-ixp4xx/fsg-setup.c b/arch/arm/mach-ixp4xx/fsg-setup.c
index 72333a039431..2887c3578c17 100644
--- a/arch/arm/mach-ixp4xx/fsg-setup.c
+++ b/arch/arm/mach-ixp4xx/fsg-setup.c
@@ -272,7 +272,7 @@ MACHINE_START(FSG, "Freecom FSG-3")
272 .map_io = ixp4xx_map_io, 272 .map_io = ixp4xx_map_io,
273 .init_irq = ixp4xx_init_irq, 273 .init_irq = ixp4xx_init_irq,
274 .timer = &ixp4xx_timer, 274 .timer = &ixp4xx_timer,
275 .boot_params = 0x0100, 275 .atag_offset = 0x100,
276 .init_machine = fsg_init, 276 .init_machine = fsg_init,
277#if defined(CONFIG_PCI) 277#if defined(CONFIG_PCI)
278 .dma_zone_size = SZ_64M, 278 .dma_zone_size = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/gateway7001-setup.c b/arch/arm/mach-ixp4xx/gateway7001-setup.c
index d4f851bdd9a4..d69d1b053bb7 100644
--- a/arch/arm/mach-ixp4xx/gateway7001-setup.c
+++ b/arch/arm/mach-ixp4xx/gateway7001-setup.c
@@ -99,7 +99,7 @@ MACHINE_START(GATEWAY7001, "Gateway 7001 AP")
99 .map_io = ixp4xx_map_io, 99 .map_io = ixp4xx_map_io,
100 .init_irq = ixp4xx_init_irq, 100 .init_irq = ixp4xx_init_irq,
101 .timer = &ixp4xx_timer, 101 .timer = &ixp4xx_timer,
102 .boot_params = 0x0100, 102 .atag_offset = 0x100,
103 .init_machine = gateway7001_init, 103 .init_machine = gateway7001_init,
104#if defined(CONFIG_PCI) 104#if defined(CONFIG_PCI)
105 .dma_zone_size = SZ_64M, 105 .dma_zone_size = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/goramo_mlr.c b/arch/arm/mach-ixp4xx/goramo_mlr.c
index 7548d9a2efe2..bf6678d1a929 100644
--- a/arch/arm/mach-ixp4xx/goramo_mlr.c
+++ b/arch/arm/mach-ixp4xx/goramo_mlr.c
@@ -499,7 +499,7 @@ MACHINE_START(GORAMO_MLR, "MultiLink")
499 .map_io = ixp4xx_map_io, 499 .map_io = ixp4xx_map_io,
500 .init_irq = ixp4xx_init_irq, 500 .init_irq = ixp4xx_init_irq,
501 .timer = &ixp4xx_timer, 501 .timer = &ixp4xx_timer,
502 .boot_params = 0x0100, 502 .atag_offset = 0x100,
503 .init_machine = gmlr_init, 503 .init_machine = gmlr_init,
504#if defined(CONFIG_PCI) 504#if defined(CONFIG_PCI)
505 .dma_zone_size = SZ_64M, 505 .dma_zone_size = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/gtwx5715-setup.c b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
index 3790dffd3c30..aa029fc19140 100644
--- a/arch/arm/mach-ixp4xx/gtwx5715-setup.c
+++ b/arch/arm/mach-ixp4xx/gtwx5715-setup.c
@@ -167,7 +167,7 @@ MACHINE_START(GTWX5715, "Gemtek GTWX5715 (Linksys WRV54G)")
167 .map_io = ixp4xx_map_io, 167 .map_io = ixp4xx_map_io,
168 .init_irq = ixp4xx_init_irq, 168 .init_irq = ixp4xx_init_irq,
169 .timer = &ixp4xx_timer, 169 .timer = &ixp4xx_timer,
170 .boot_params = 0x0100, 170 .atag_offset = 0x100,
171 .init_machine = gtwx5715_init, 171 .init_machine = gtwx5715_init,
172#if defined(CONFIG_PCI) 172#if defined(CONFIG_PCI)
173 .dma_zone_size = SZ_64M, 173 .dma_zone_size = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
index b974a49c0aff..8c9f8d564492 100644
--- a/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-ixp4xx/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11*/ 11*/
12 12
13 .macro addruart, rp, rv 13 .macro addruart, rp, rv, tmp
14#ifdef __ARMEB__ 14#ifdef __ARMEB__
15 mov \rp, #3 @ Uart regs are at off set of 3 if 15 mov \rp, #3 @ Uart regs are at off set of 3 if
16 @ byte writes used - Big Endian. 16 @ byte writes used - Big Endian.
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
deleted file mode 100644
index 4caf1761f1e2..000000000000
--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
+++ /dev/null
@@ -1,17 +0,0 @@
1/*
2 * arch/arm/mach-ixp4xx/include/mach/memory.h
3 *
4 * Copyright (c) 2001-2004 MontaVista Software, Inc.
5 */
6
7#ifndef __ASM_ARCH_MEMORY_H
8#define __ASM_ARCH_MEMORY_H
9
10#include <asm/sizes.h>
11
12/*
13 * Physical DRAM offset.
14 */
15#define PLAT_PHYS_OFFSET UL(0x00000000)
16
17#endif
diff --git a/arch/arm/mach-ixp4xx/ixdp425-setup.c b/arch/arm/mach-ixp4xx/ixdp425-setup.c
index 6a2927956bf6..f235f829dfa6 100644
--- a/arch/arm/mach-ixp4xx/ixdp425-setup.c
+++ b/arch/arm/mach-ixp4xx/ixdp425-setup.c
@@ -256,7 +256,7 @@ MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")
256 .map_io = ixp4xx_map_io, 256 .map_io = ixp4xx_map_io,
257 .init_irq = ixp4xx_init_irq, 257 .init_irq = ixp4xx_init_irq,
258 .timer = &ixp4xx_timer, 258 .timer = &ixp4xx_timer,
259 .boot_params = 0x0100, 259 .atag_offset = 0x100,
260 .init_machine = ixdp425_init, 260 .init_machine = ixdp425_init,
261#if defined(CONFIG_PCI) 261#if defined(CONFIG_PCI)
262 .dma_zone_size = SZ_64M, 262 .dma_zone_size = SZ_64M,
@@ -270,7 +270,7 @@ MACHINE_START(IXDP465, "Intel IXDP465 Development Platform")
270 .map_io = ixp4xx_map_io, 270 .map_io = ixp4xx_map_io,
271 .init_irq = ixp4xx_init_irq, 271 .init_irq = ixp4xx_init_irq,
272 .timer = &ixp4xx_timer, 272 .timer = &ixp4xx_timer,
273 .boot_params = 0x0100, 273 .atag_offset = 0x100,
274 .init_machine = ixdp425_init, 274 .init_machine = ixdp425_init,
275#if defined(CONFIG_PCI) 275#if defined(CONFIG_PCI)
276 .dma_zone_size = SZ_64M, 276 .dma_zone_size = SZ_64M,
@@ -284,7 +284,7 @@ MACHINE_START(IXCDP1100, "Intel IXCDP1100 Development Platform")
284 .map_io = ixp4xx_map_io, 284 .map_io = ixp4xx_map_io,
285 .init_irq = ixp4xx_init_irq, 285 .init_irq = ixp4xx_init_irq,
286 .timer = &ixp4xx_timer, 286 .timer = &ixp4xx_timer,
287 .boot_params = 0x0100, 287 .atag_offset = 0x100,
288 .init_machine = ixdp425_init, 288 .init_machine = ixdp425_init,
289#if defined(CONFIG_PCI) 289#if defined(CONFIG_PCI)
290 .dma_zone_size = SZ_64M, 290 .dma_zone_size = SZ_64M,
@@ -298,7 +298,7 @@ MACHINE_START(KIXRP435, "Intel KIXRP435 Reference Platform")
298 .map_io = ixp4xx_map_io, 298 .map_io = ixp4xx_map_io,
299 .init_irq = ixp4xx_init_irq, 299 .init_irq = ixp4xx_init_irq,
300 .timer = &ixp4xx_timer, 300 .timer = &ixp4xx_timer,
301 .boot_params = 0x0100, 301 .atag_offset = 0x100,
302 .init_machine = ixdp425_init, 302 .init_machine = ixdp425_init,
303#if defined(CONFIG_PCI) 303#if defined(CONFIG_PCI)
304 .dma_zone_size = SZ_64M, 304 .dma_zone_size = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/nas100d-setup.c b/arch/arm/mach-ixp4xx/nas100d-setup.c
index b752fa4d6927..de716fa1aab6 100644
--- a/arch/arm/mach-ixp4xx/nas100d-setup.c
+++ b/arch/arm/mach-ixp4xx/nas100d-setup.c
@@ -313,7 +313,7 @@ static void __init nas100d_init(void)
313 313
314MACHINE_START(NAS100D, "Iomega NAS 100d") 314MACHINE_START(NAS100D, "Iomega NAS 100d")
315 /* Maintainer: www.nslu2-linux.org */ 315 /* Maintainer: www.nslu2-linux.org */
316 .boot_params = 0x00000100, 316 .atag_offset = 0x100,
317 .map_io = ixp4xx_map_io, 317 .map_io = ixp4xx_map_io,
318 .init_irq = ixp4xx_init_irq, 318 .init_irq = ixp4xx_init_irq,
319 .timer = &ixp4xx_timer, 319 .timer = &ixp4xx_timer,
diff --git a/arch/arm/mach-ixp4xx/nslu2-setup.c b/arch/arm/mach-ixp4xx/nslu2-setup.c
index 0411a0a01071..ac81ccb26bfe 100644
--- a/arch/arm/mach-ixp4xx/nslu2-setup.c
+++ b/arch/arm/mach-ixp4xx/nslu2-setup.c
@@ -299,7 +299,7 @@ static void __init nslu2_init(void)
299 299
300MACHINE_START(NSLU2, "Linksys NSLU2") 300MACHINE_START(NSLU2, "Linksys NSLU2")
301 /* Maintainer: www.nslu2-linux.org */ 301 /* Maintainer: www.nslu2-linux.org */
302 .boot_params = 0x00000100, 302 .atag_offset = 0x100,
303 .map_io = ixp4xx_map_io, 303 .map_io = ixp4xx_map_io,
304 .init_irq = ixp4xx_init_irq, 304 .init_irq = ixp4xx_init_irq,
305 .timer = &nslu2_timer, 305 .timer = &nslu2_timer,
diff --git a/arch/arm/mach-ixp4xx/vulcan-setup.c b/arch/arm/mach-ixp4xx/vulcan-setup.c
index 045336c833af..27e469ef4523 100644
--- a/arch/arm/mach-ixp4xx/vulcan-setup.c
+++ b/arch/arm/mach-ixp4xx/vulcan-setup.c
@@ -239,7 +239,7 @@ MACHINE_START(ARCOM_VULCAN, "Arcom/Eurotech Vulcan")
239 .map_io = ixp4xx_map_io, 239 .map_io = ixp4xx_map_io,
240 .init_irq = ixp4xx_init_irq, 240 .init_irq = ixp4xx_init_irq,
241 .timer = &ixp4xx_timer, 241 .timer = &ixp4xx_timer,
242 .boot_params = 0x0100, 242 .atag_offset = 0x100,
243 .init_machine = vulcan_init, 243 .init_machine = vulcan_init,
244#if defined(CONFIG_PCI) 244#if defined(CONFIG_PCI)
245 .dma_zone_size = SZ_64M, 245 .dma_zone_size = SZ_64M,
diff --git a/arch/arm/mach-ixp4xx/wg302v2-setup.c b/arch/arm/mach-ixp4xx/wg302v2-setup.c
index 40b9fad800b8..b14144b967a7 100644
--- a/arch/arm/mach-ixp4xx/wg302v2-setup.c
+++ b/arch/arm/mach-ixp4xx/wg302v2-setup.c
@@ -100,7 +100,7 @@ MACHINE_START(WG302V2, "Netgear WG302 v2 / WAG302 v2")
100 .map_io = ixp4xx_map_io, 100 .map_io = ixp4xx_map_io,
101 .init_irq = ixp4xx_init_irq, 101 .init_irq = ixp4xx_init_irq,
102 .timer = &ixp4xx_timer, 102 .timer = &ixp4xx_timer,
103 .boot_params = 0x0100, 103 .atag_offset = 0x100,
104 .init_machine = wg302v2_init, 104 .init_machine = wg302v2_init,
105#if defined(CONFIG_PCI) 105#if defined(CONFIG_PCI)
106 .dma_zone_size = SZ_64M, 106 .dma_zone_size = SZ_64M,
diff --git a/arch/arm/mach-kirkwood/d2net_v2-setup.c b/arch/arm/mach-kirkwood/d2net_v2-setup.c
index 043cfd5e140b..f457e07a65f0 100644
--- a/arch/arm/mach-kirkwood/d2net_v2-setup.c
+++ b/arch/arm/mach-kirkwood/d2net_v2-setup.c
@@ -221,7 +221,7 @@ static void __init d2net_v2_init(void)
221} 221}
222 222
223MACHINE_START(D2NET_V2, "LaCie d2 Network v2") 223MACHINE_START(D2NET_V2, "LaCie d2 Network v2")
224 .boot_params = 0x00000100, 224 .atag_offset = 0x100,
225 .init_machine = d2net_v2_init, 225 .init_machine = d2net_v2_init,
226 .map_io = kirkwood_map_io, 226 .map_io = kirkwood_map_io,
227 .init_early = kirkwood_init_early, 227 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
index bff04e04d679..ff4c21c1f923 100644
--- a/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
+++ b/arch/arm/mach-kirkwood/db88f6281-bp-setup.c
@@ -97,7 +97,7 @@ subsys_initcall(db88f6281_pci_init);
97 97
98MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board") 98MACHINE_START(DB88F6281_BP, "Marvell DB-88F6281-BP Development Board")
99 /* Maintainer: Saeed Bishara <saeed@marvell.com> */ 99 /* Maintainer: Saeed Bishara <saeed@marvell.com> */
100 .boot_params = 0x00000100, 100 .atag_offset = 0x100,
101 .init_machine = db88f6281_init, 101 .init_machine = db88f6281_init,
102 .map_io = kirkwood_map_io, 102 .map_io = kirkwood_map_io,
103 .init_early = kirkwood_init_early, 103 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/dockstar-setup.c b/arch/arm/mach-kirkwood/dockstar-setup.c
index f14dfb8508c5..e4d199b2b1e8 100644
--- a/arch/arm/mach-kirkwood/dockstar-setup.c
+++ b/arch/arm/mach-kirkwood/dockstar-setup.c
@@ -102,7 +102,7 @@ static void __init dockstar_init(void)
102} 102}
103 103
104MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar") 104MACHINE_START(DOCKSTAR, "Seagate FreeAgent DockStar")
105 .boot_params = 0x00000100, 105 .atag_offset = 0x100,
106 .init_machine = dockstar_init, 106 .init_machine = dockstar_init,
107 .map_io = kirkwood_map_io, 107 .map_io = kirkwood_map_io,
108 .init_early = kirkwood_init_early, 108 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/guruplug-setup.c b/arch/arm/mach-kirkwood/guruplug-setup.c
index 41d1b40696a3..6c40f784b516 100644
--- a/arch/arm/mach-kirkwood/guruplug-setup.c
+++ b/arch/arm/mach-kirkwood/guruplug-setup.c
@@ -121,7 +121,7 @@ static void __init guruplug_init(void)
121 121
122MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board") 122MACHINE_START(GURUPLUG, "Marvell GuruPlug Reference Board")
123 /* Maintainer: Siddarth Gore <gores@marvell.com> */ 123 /* Maintainer: Siddarth Gore <gores@marvell.com> */
124 .boot_params = 0x00000100, 124 .atag_offset = 0x100,
125 .init_machine = guruplug_init, 125 .init_machine = guruplug_init,
126 .map_io = kirkwood_map_io, 126 .map_io = kirkwood_map_io,
127 .init_early = kirkwood_init_early, 127 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/include/mach/debug-macro.S b/arch/arm/mach-kirkwood/include/mach/debug-macro.S
index db06ae437d08..f785d401a607 100644
--- a/arch/arm/mach-kirkwood/include/mach/debug-macro.S
+++ b/arch/arm/mach-kirkwood/include/mach/debug-macro.S
@@ -8,7 +8,7 @@
8 8
9#include <mach/bridge-regs.h> 9#include <mach/bridge-regs.h>
10 10
11 .macro addruart, rp, rv 11 .macro addruart, rp, rv, tmp
12 ldr \rp, =KIRKWOOD_REGS_PHYS_BASE 12 ldr \rp, =KIRKWOOD_REGS_PHYS_BASE
13 ldr \rv, =KIRKWOOD_REGS_VIRT_BASE 13 ldr \rv, =KIRKWOOD_REGS_VIRT_BASE
14 orr \rp, \rp, #0x00012000 14 orr \rp, \rp, #0x00012000
diff --git a/arch/arm/mach-kirkwood/include/mach/memory.h b/arch/arm/mach-kirkwood/include/mach/memory.h
deleted file mode 100644
index 4600b44e3ad3..000000000000
--- a/arch/arm/mach-kirkwood/include/mach/memory.h
+++ /dev/null
@@ -1,10 +0,0 @@
1/*
2 * arch/arm/mach-kirkwood/include/mach/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PLAT_PHYS_OFFSET UL(0x00000000)
9
10#endif
diff --git a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
index 00cca22eca6f..9a1e917352f7 100644
--- a/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
+++ b/arch/arm/mach-kirkwood/mv88f6281gtw_ge-setup.c
@@ -163,7 +163,7 @@ subsys_initcall(mv88f6281gtw_ge_pci_init);
163 163
164MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board") 164MACHINE_START(MV88F6281GTW_GE, "Marvell 88F6281 GTW GE Board")
165 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 165 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
166 .boot_params = 0x00000100, 166 .atag_offset = 0x100,
167 .init_machine = mv88f6281gtw_ge_init, 167 .init_machine = mv88f6281gtw_ge_init,
168 .map_io = kirkwood_map_io, 168 .map_io = kirkwood_map_io,
169 .init_early = kirkwood_init_early, 169 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/netspace_v2-setup.c b/arch/arm/mach-kirkwood/netspace_v2-setup.c
index 7cdab5776452..8849bcc7328e 100644
--- a/arch/arm/mach-kirkwood/netspace_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netspace_v2-setup.c
@@ -258,7 +258,7 @@ static void __init netspace_v2_init(void)
258 258
259#ifdef CONFIG_MACH_NETSPACE_V2 259#ifdef CONFIG_MACH_NETSPACE_V2
260MACHINE_START(NETSPACE_V2, "LaCie Network Space v2") 260MACHINE_START(NETSPACE_V2, "LaCie Network Space v2")
261 .boot_params = 0x00000100, 261 .atag_offset = 0x100,
262 .init_machine = netspace_v2_init, 262 .init_machine = netspace_v2_init,
263 .map_io = kirkwood_map_io, 263 .map_io = kirkwood_map_io,
264 .init_early = kirkwood_init_early, 264 .init_early = kirkwood_init_early,
@@ -269,7 +269,7 @@ MACHINE_END
269 269
270#ifdef CONFIG_MACH_INETSPACE_V2 270#ifdef CONFIG_MACH_INETSPACE_V2
271MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2") 271MACHINE_START(INETSPACE_V2, "LaCie Internet Space v2")
272 .boot_params = 0x00000100, 272 .atag_offset = 0x100,
273 .init_machine = netspace_v2_init, 273 .init_machine = netspace_v2_init,
274 .map_io = kirkwood_map_io, 274 .map_io = kirkwood_map_io,
275 .init_early = kirkwood_init_early, 275 .init_early = kirkwood_init_early,
@@ -280,7 +280,7 @@ MACHINE_END
280 280
281#ifdef CONFIG_MACH_NETSPACE_MAX_V2 281#ifdef CONFIG_MACH_NETSPACE_MAX_V2
282MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2") 282MACHINE_START(NETSPACE_MAX_V2, "LaCie Network Space Max v2")
283 .boot_params = 0x00000100, 283 .atag_offset = 0x100,
284 .init_machine = netspace_v2_init, 284 .init_machine = netspace_v2_init,
285 .map_io = kirkwood_map_io, 285 .map_io = kirkwood_map_io,
286 .init_early = kirkwood_init_early, 286 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/netxbig_v2-setup.c b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
index 6be627deb0fc..1ba12c4dff8f 100644
--- a/arch/arm/mach-kirkwood/netxbig_v2-setup.c
+++ b/arch/arm/mach-kirkwood/netxbig_v2-setup.c
@@ -399,7 +399,7 @@ static void __init netxbig_v2_init(void)
399 399
400#ifdef CONFIG_MACH_NET2BIG_V2 400#ifdef CONFIG_MACH_NET2BIG_V2
401MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2") 401MACHINE_START(NET2BIG_V2, "LaCie 2Big Network v2")
402 .boot_params = 0x00000100, 402 .atag_offset = 0x100,
403 .init_machine = netxbig_v2_init, 403 .init_machine = netxbig_v2_init,
404 .map_io = kirkwood_map_io, 404 .map_io = kirkwood_map_io,
405 .init_early = kirkwood_init_early, 405 .init_early = kirkwood_init_early,
@@ -410,7 +410,7 @@ MACHINE_END
410 410
411#ifdef CONFIG_MACH_NET5BIG_V2 411#ifdef CONFIG_MACH_NET5BIG_V2
412MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2") 412MACHINE_START(NET5BIG_V2, "LaCie 5Big Network v2")
413 .boot_params = 0x00000100, 413 .atag_offset = 0x100,
414 .init_machine = netxbig_v2_init, 414 .init_machine = netxbig_v2_init,
415 .map_io = kirkwood_map_io, 415 .map_io = kirkwood_map_io,
416 .init_early = kirkwood_init_early, 416 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/openrd-setup.c b/arch/arm/mach-kirkwood/openrd-setup.c
index f69beeff4450..5660ca6c3d88 100644
--- a/arch/arm/mach-kirkwood/openrd-setup.c
+++ b/arch/arm/mach-kirkwood/openrd-setup.c
@@ -214,7 +214,7 @@ subsys_initcall(openrd_pci_init);
214#ifdef CONFIG_MACH_OPENRD_BASE 214#ifdef CONFIG_MACH_OPENRD_BASE
215MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board") 215MACHINE_START(OPENRD_BASE, "Marvell OpenRD Base Board")
216 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */ 216 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
217 .boot_params = 0x00000100, 217 .atag_offset = 0x100,
218 .init_machine = openrd_init, 218 .init_machine = openrd_init,
219 .map_io = kirkwood_map_io, 219 .map_io = kirkwood_map_io,
220 .init_early = kirkwood_init_early, 220 .init_early = kirkwood_init_early,
@@ -226,7 +226,7 @@ MACHINE_END
226#ifdef CONFIG_MACH_OPENRD_CLIENT 226#ifdef CONFIG_MACH_OPENRD_CLIENT
227MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board") 227MACHINE_START(OPENRD_CLIENT, "Marvell OpenRD Client Board")
228 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */ 228 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
229 .boot_params = 0x00000100, 229 .atag_offset = 0x100,
230 .init_machine = openrd_init, 230 .init_machine = openrd_init,
231 .map_io = kirkwood_map_io, 231 .map_io = kirkwood_map_io,
232 .init_early = kirkwood_init_early, 232 .init_early = kirkwood_init_early,
@@ -238,7 +238,7 @@ MACHINE_END
238#ifdef CONFIG_MACH_OPENRD_ULTIMATE 238#ifdef CONFIG_MACH_OPENRD_ULTIMATE
239MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board") 239MACHINE_START(OPENRD_ULTIMATE, "Marvell OpenRD Ultimate Board")
240 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */ 240 /* Maintainer: Dhaval Vasa <dhaval.vasa@einfochips.com> */
241 .boot_params = 0x00000100, 241 .atag_offset = 0x100,
242 .init_machine = openrd_init, 242 .init_machine = openrd_init,
243 .map_io = kirkwood_map_io, 243 .map_io = kirkwood_map_io,
244 .init_early = kirkwood_init_early, 244 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
index 75c6601b8d87..6663869773ab 100644
--- a/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6192-nas-setup.c
@@ -79,7 +79,7 @@ subsys_initcall(rd88f6192_pci_init);
79 79
80MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board") 80MACHINE_START(RD88F6192_NAS, "Marvell RD-88F6192-NAS Development Board")
81 /* Maintainer: Saeed Bishara <saeed@marvell.com> */ 81 /* Maintainer: Saeed Bishara <saeed@marvell.com> */
82 .boot_params = 0x00000100, 82 .atag_offset = 0x100,
83 .init_machine = rd88f6192_init, 83 .init_machine = rd88f6192_init,
84 .map_io = kirkwood_map_io, 84 .map_io = kirkwood_map_io,
85 .init_early = kirkwood_init_early, 85 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/rd88f6281-setup.c b/arch/arm/mach-kirkwood/rd88f6281-setup.c
index 0f75494d5902..66b3c05e37a6 100644
--- a/arch/arm/mach-kirkwood/rd88f6281-setup.c
+++ b/arch/arm/mach-kirkwood/rd88f6281-setup.c
@@ -115,7 +115,7 @@ subsys_initcall(rd88f6281_pci_init);
115 115
116MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board") 116MACHINE_START(RD88F6281, "Marvell RD-88F6281 Reference Board")
117 /* Maintainer: Saeed Bishara <saeed@marvell.com> */ 117 /* Maintainer: Saeed Bishara <saeed@marvell.com> */
118 .boot_params = 0x00000100, 118 .atag_offset = 0x100,
119 .init_machine = rd88f6281_init, 119 .init_machine = rd88f6281_init,
120 .map_io = kirkwood_map_io, 120 .map_io = kirkwood_map_io,
121 .init_early = kirkwood_init_early, 121 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/sheevaplug-setup.c b/arch/arm/mach-kirkwood/sheevaplug-setup.c
index 17de0bf53c08..8b102d62e82c 100644
--- a/arch/arm/mach-kirkwood/sheevaplug-setup.c
+++ b/arch/arm/mach-kirkwood/sheevaplug-setup.c
@@ -138,7 +138,7 @@ static void __init sheevaplug_init(void)
138#ifdef CONFIG_MACH_SHEEVAPLUG 138#ifdef CONFIG_MACH_SHEEVAPLUG
139MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board") 139MACHINE_START(SHEEVAPLUG, "Marvell SheevaPlug Reference Board")
140 /* Maintainer: shadi Ammouri <shadi@marvell.com> */ 140 /* Maintainer: shadi Ammouri <shadi@marvell.com> */
141 .boot_params = 0x00000100, 141 .atag_offset = 0x100,
142 .init_machine = sheevaplug_init, 142 .init_machine = sheevaplug_init,
143 .map_io = kirkwood_map_io, 143 .map_io = kirkwood_map_io,
144 .init_early = kirkwood_init_early, 144 .init_early = kirkwood_init_early,
@@ -149,7 +149,7 @@ MACHINE_END
149 149
150#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG 150#ifdef CONFIG_MACH_ESATA_SHEEVAPLUG
151MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board") 151MACHINE_START(ESATA_SHEEVAPLUG, "Marvell eSATA SheevaPlug Reference Board")
152 .boot_params = 0x00000100, 152 .atag_offset = 0x100,
153 .init_machine = sheevaplug_init, 153 .init_machine = sheevaplug_init,
154 .map_io = kirkwood_map_io, 154 .map_io = kirkwood_map_io,
155 .init_early = kirkwood_init_early, 155 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/t5325-setup.c b/arch/arm/mach-kirkwood/t5325-setup.c
index e6b9b1b22a35..ea104fb5ec3d 100644
--- a/arch/arm/mach-kirkwood/t5325-setup.c
+++ b/arch/arm/mach-kirkwood/t5325-setup.c
@@ -201,7 +201,7 @@ subsys_initcall(hp_t5325_pci_init);
201 201
202MACHINE_START(T5325, "HP t5325 Thin Client") 202MACHINE_START(T5325, "HP t5325 Thin Client")
203 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ 203 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
204 .boot_params = 0x00000100, 204 .atag_offset = 0x100,
205 .init_machine = hp_t5325_init, 205 .init_machine = hp_t5325_init,
206 .map_io = kirkwood_map_io, 206 .map_io = kirkwood_map_io,
207 .init_early = kirkwood_init_early, 207 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/ts219-setup.c b/arch/arm/mach-kirkwood/ts219-setup.c
index 68f32f2bf552..262c034836d4 100644
--- a/arch/arm/mach-kirkwood/ts219-setup.c
+++ b/arch/arm/mach-kirkwood/ts219-setup.c
@@ -132,7 +132,7 @@ subsys_initcall(ts219_pci_init);
132 132
133MACHINE_START(TS219, "QNAP TS-119/TS-219") 133MACHINE_START(TS219, "QNAP TS-119/TS-219")
134 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ 134 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
135 .boot_params = 0x00000100, 135 .atag_offset = 0x100,
136 .init_machine = qnap_ts219_init, 136 .init_machine = qnap_ts219_init,
137 .map_io = kirkwood_map_io, 137 .map_io = kirkwood_map_io,
138 .init_early = kirkwood_init_early, 138 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index d5d009970705..b68f5b4a9ec8 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -176,7 +176,7 @@ subsys_initcall(ts41x_pci_init);
176 176
177MACHINE_START(TS41X, "QNAP TS-41x") 177MACHINE_START(TS41X, "QNAP TS-41x")
178 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ 178 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
179 .boot_params = 0x00000100, 179 .atag_offset = 0x100,
180 .init_machine = qnap_ts41x_init, 180 .init_machine = qnap_ts41x_init,
181 .map_io = kirkwood_map_io, 181 .map_io = kirkwood_map_io,
182 .init_early = kirkwood_init_early, 182 .init_early = kirkwood_init_early,
diff --git a/arch/arm/mach-ks8695/board-acs5k.c b/arch/arm/mach-ks8695/board-acs5k.c
index 3d7d11436aa5..a91f99d265aa 100644
--- a/arch/arm/mach-ks8695/board-acs5k.c
+++ b/arch/arm/mach-ks8695/board-acs5k.c
@@ -223,7 +223,7 @@ static void __init acs5k_init(void)
223 223
224MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board") 224MACHINE_START(ACS5K, "Brivo Systems LLC ACS-5000 Master board")
225 /* Maintainer: Simtec Electronics. */ 225 /* Maintainer: Simtec Electronics. */
226 .boot_params = KS8695_SDRAM_PA + 0x100, 226 .atag_offset = 0x100,
227 .map_io = ks8695_map_io, 227 .map_io = ks8695_map_io,
228 .init_irq = ks8695_init_irq, 228 .init_irq = ks8695_init_irq,
229 .init_machine = acs5k_init, 229 .init_machine = acs5k_init,
diff --git a/arch/arm/mach-ks8695/board-dsm320.c b/arch/arm/mach-ks8695/board-dsm320.c
index c3c867ac4155..d24bcef2e2dd 100644
--- a/arch/arm/mach-ks8695/board-dsm320.c
+++ b/arch/arm/mach-ks8695/board-dsm320.c
@@ -121,7 +121,7 @@ static void __init dsm320_init(void)
121 121
122MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player") 122MACHINE_START(DSM320, "D-Link DSM-320 Wireless Media Player")
123 /* Maintainer: Simtec Electronics. */ 123 /* Maintainer: Simtec Electronics. */
124 .boot_params = KS8695_SDRAM_PA + 0x100, 124 .atag_offset = 0x100,
125 .map_io = ks8695_map_io, 125 .map_io = ks8695_map_io,
126 .init_irq = ks8695_init_irq, 126 .init_irq = ks8695_init_irq,
127 .init_machine = dsm320_init, 127 .init_machine = dsm320_init,
diff --git a/arch/arm/mach-ks8695/board-micrel.c b/arch/arm/mach-ks8695/board-micrel.c
index 9b9c47cc6471..16c95657f8fd 100644
--- a/arch/arm/mach-ks8695/board-micrel.c
+++ b/arch/arm/mach-ks8695/board-micrel.c
@@ -53,7 +53,7 @@ static void __init micrel_init(void)
53 53
54MACHINE_START(KS8695, "KS8695 Centaur Development Board") 54MACHINE_START(KS8695, "KS8695 Centaur Development Board")
55 /* Maintainer: Micrel Semiconductor Inc. */ 55 /* Maintainer: Micrel Semiconductor Inc. */
56 .boot_params = KS8695_SDRAM_PA + 0x100, 56 .atag_offset = 0x100,
57 .map_io = ks8695_map_io, 57 .map_io = ks8695_map_io,
58 .init_irq = ks8695_init_irq, 58 .init_irq = ks8695_init_irq,
59 .init_machine = micrel_init, 59 .init_machine = micrel_init,
diff --git a/arch/arm/mach-ks8695/include/mach/debug-macro.S b/arch/arm/mach-ks8695/include/mach/debug-macro.S
index bf516adf1925..a79e48981202 100644
--- a/arch/arm/mach-ks8695/include/mach/debug-macro.S
+++ b/arch/arm/mach-ks8695/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
14#include <mach/hardware.h> 14#include <mach/hardware.h>
15#include <mach/regs-uart.h> 15#include <mach/regs-uart.h>
16 16
17 .macro addruart, rp, rv 17 .macro addruart, rp, rv, tmp
18 ldr \rp, =KS8695_UART_PA @ physical base address 18 ldr \rp, =KS8695_UART_PA @ physical base address
19 ldr \rv, =KS8695_UART_VA @ virtual base address 19 ldr \rv, =KS8695_UART_VA @ virtual base address
20 .endm 20 .endm
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
index b0a2db77d392..0b4e760159b9 100644
--- a/arch/arm/mach-l7200/include/mach/debug-macro.S
+++ b/arch/arm/mach-l7200/include/mach/debug-macro.S
@@ -14,7 +14,7 @@
14 .equ io_virt, IO_BASE 14 .equ io_virt, IO_BASE
15 .equ io_phys, IO_START 15 .equ io_phys, IO_START
16 16
17 .macro addruart, rp, rv 17 .macro addruart, rp, rv, tmp
18 mov \rp, #0x00044000 @ UART1 18 mov \rp, #0x00044000 @ UART1
19@ mov \rp, #0x00045000 @ UART2 19@ mov \rp, #0x00045000 @ UART2
20 add \rv, \rp, #io_virt @ virtual address 20 add \rv, \rp, #io_virt @ virtual address
diff --git a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
index 629e744aeb9e..351bd6c84909 100644
--- a/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-lpc32xx/include/mach/debug-macro.S
@@ -20,7 +20,7 @@
20 * Debug output is hardcoded to standard UART 5 20 * Debug output is hardcoded to standard UART 5
21*/ 21*/
22 22
23 .macro addruart, rp, rv 23 .macro addruart, rp, rv, tmp
24 ldreq \rp, =0x40090000 24 ldreq \rp, =0x40090000
25 ldrne \rv, =0xF4090000 25 ldrne \rv, =0xF4090000
26 .endm 26 .endm
diff --git a/arch/arm/mach-lpc32xx/include/mach/memory.h b/arch/arm/mach-lpc32xx/include/mach/memory.h
deleted file mode 100644
index a647dd624afa..000000000000
--- a/arch/arm/mach-lpc32xx/include/mach/memory.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * arch/arm/mach-lpc32xx/include/mach/memory.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_MEMORY_H
20#define __ASM_ARCH_MEMORY_H
21
22/*
23 * Physical DRAM offset of bank 0
24 */
25#define PLAT_PHYS_OFFSET UL(0x80000000)
26
27#endif
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index c3a22fd736aa..6d2f0d1b9373 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -383,7 +383,7 @@ arch_initcall(lpc32xx_display_uid);
383 383
384MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller") 384MACHINE_START(PHY3250, "Phytec 3250 board with the LPC3250 Microcontroller")
385 /* Maintainer: Kevin Wells, NXP Semiconductors */ 385 /* Maintainer: Kevin Wells, NXP Semiconductors */
386 .boot_params = 0x80000100, 386 .atag_offset = 0x100,
387 .map_io = lpc32xx_map_io, 387 .map_io = lpc32xx_map_io,
388 .init_irq = lpc32xx_init_irq, 388 .init_irq = lpc32xx_init_irq,
389 .timer = &lpc32xx_timer, 389 .timer = &lpc32xx_timer,
diff --git a/arch/arm/mach-mmp/include/mach/debug-macro.S b/arch/arm/mach-mmp/include/mach/debug-macro.S
index 7e2ebd3efc7c..b6f14d203c25 100644
--- a/arch/arm/mach-mmp/include/mach/debug-macro.S
+++ b/arch/arm/mach-mmp/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 11
12#include <mach/addr-map.h> 12#include <mach/addr-map.h>
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 ldr \rp, =APB_PHYS_BASE @ physical 15 ldr \rp, =APB_PHYS_BASE @ physical
16 ldr \rv, =APB_VIRT_BASE @ virtual 16 ldr \rv, =APB_VIRT_BASE @ virtual
17 orr \rp, \rp, #0x00017000 17 orr \rp, \rp, #0x00017000
diff --git a/arch/arm/mach-mmp/include/mach/memory.h b/arch/arm/mach-mmp/include/mach/memory.h
deleted file mode 100644
index d68b50a2d6a0..000000000000
--- a/arch/arm/mach-mmp/include/mach/memory.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/*
2 * linux/arch/arm/mach-mmp/include/mach/memory.h
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef __ASM_MACH_MEMORY_H
10#define __ASM_MACH_MEMORY_H
11
12#define PLAT_PHYS_OFFSET UL(0x00000000)
13
14#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index f81ef1f9d46f..a60ab6d04ec5 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -93,7 +93,7 @@ static void __init halibut_map_io(void)
93} 93}
94 94
95MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)") 95MACHINE_START(HALIBUT, "Halibut Board (QCT SURF7200A)")
96 .boot_params = 0x10000100, 96 .atag_offset = 0x100,
97 .fixup = halibut_fixup, 97 .fixup = halibut_fixup,
98 .map_io = halibut_map_io, 98 .map_io = halibut_map_io,
99 .init_irq = halibut_init_irq, 99 .init_irq = halibut_init_irq,
diff --git a/arch/arm/mach-msm/board-mahimahi.c b/arch/arm/mach-msm/board-mahimahi.c
index 1df15aa3c66d..5a4882fc6f7a 100644
--- a/arch/arm/mach-msm/board-mahimahi.c
+++ b/arch/arm/mach-msm/board-mahimahi.c
@@ -74,7 +74,7 @@ static void __init mahimahi_map_io(void)
74extern struct sys_timer msm_timer; 74extern struct sys_timer msm_timer;
75 75
76MACHINE_START(MAHIMAHI, "mahimahi") 76MACHINE_START(MAHIMAHI, "mahimahi")
77 .boot_params = 0x20000100, 77 .atag_offset = 0x100,
78 .fixup = mahimahi_fixup, 78 .fixup = mahimahi_fixup,
79 .map_io = mahimahi_map_io, 79 .map_io = mahimahi_map_io,
80 .init_irq = msm_init_irq, 80 .init_irq = msm_init_irq,
diff --git a/arch/arm/mach-msm/board-msm7x27.c b/arch/arm/mach-msm/board-msm7x27.c
index 1a313e10c68a..6d84ee740df4 100644
--- a/arch/arm/mach-msm/board-msm7x27.c
+++ b/arch/arm/mach-msm/board-msm7x27.c
@@ -129,7 +129,7 @@ static void __init msm7x2x_map_io(void)
129} 129}
130 130
131MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF") 131MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
132 .boot_params = PLAT_PHYS_OFFSET + 0x100, 132 .atag_offset = 0x100,
133 .map_io = msm7x2x_map_io, 133 .map_io = msm7x2x_map_io,
134 .init_irq = msm7x2x_init_irq, 134 .init_irq = msm7x2x_init_irq,
135 .init_machine = msm7x2x_init, 135 .init_machine = msm7x2x_init,
@@ -137,7 +137,7 @@ MACHINE_START(MSM7X27_SURF, "QCT MSM7x27 SURF")
137MACHINE_END 137MACHINE_END
138 138
139MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA") 139MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
140 .boot_params = PLAT_PHYS_OFFSET + 0x100, 140 .atag_offset = 0x100,
141 .map_io = msm7x2x_map_io, 141 .map_io = msm7x2x_map_io,
142 .init_irq = msm7x2x_init_irq, 142 .init_irq = msm7x2x_init_irq,
143 .init_machine = msm7x2x_init, 143 .init_machine = msm7x2x_init,
@@ -145,7 +145,7 @@ MACHINE_START(MSM7X27_FFA, "QCT MSM7x27 FFA")
145MACHINE_END 145MACHINE_END
146 146
147MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF") 147MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
148 .boot_params = PLAT_PHYS_OFFSET + 0x100, 148 .atag_offset = 0x100,
149 .map_io = msm7x2x_map_io, 149 .map_io = msm7x2x_map_io,
150 .init_irq = msm7x2x_init_irq, 150 .init_irq = msm7x2x_init_irq,
151 .init_machine = msm7x2x_init, 151 .init_machine = msm7x2x_init,
@@ -153,7 +153,7 @@ MACHINE_START(MSM7X25_SURF, "QCT MSM7x25 SURF")
153MACHINE_END 153MACHINE_END
154 154
155MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA") 155MACHINE_START(MSM7X25_FFA, "QCT MSM7x25 FFA")
156 .boot_params = PLAT_PHYS_OFFSET + 0x100, 156 .atag_offset = 0x100,
157 .map_io = msm7x2x_map_io, 157 .map_io = msm7x2x_map_io,
158 .init_irq = msm7x2x_init_irq, 158 .init_irq = msm7x2x_init_irq,
159 .init_machine = msm7x2x_init, 159 .init_machine = msm7x2x_init,
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 9043417ea52f..71de5062c71e 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -121,7 +121,7 @@ static void __init msm7x30_map_io(void)
121} 121}
122 122
123MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF") 123MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
124 .boot_params = PLAT_PHYS_OFFSET + 0x100, 124 .atag_offset = 0x100,
125 .fixup = msm7x30_fixup, 125 .fixup = msm7x30_fixup,
126 .reserve = msm7x30_reserve, 126 .reserve = msm7x30_reserve,
127 .map_io = msm7x30_map_io, 127 .map_io = msm7x30_map_io,
@@ -131,7 +131,7 @@ MACHINE_START(MSM7X30_SURF, "QCT MSM7X30 SURF")
131MACHINE_END 131MACHINE_END
132 132
133MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA") 133MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
134 .boot_params = PLAT_PHYS_OFFSET + 0x100, 134 .atag_offset = 0x100,
135 .fixup = msm7x30_fixup, 135 .fixup = msm7x30_fixup,
136 .reserve = msm7x30_reserve, 136 .reserve = msm7x30_reserve,
137 .map_io = msm7x30_map_io, 137 .map_io = msm7x30_map_io,
@@ -141,7 +141,7 @@ MACHINE_START(MSM7X30_FFA, "QCT MSM7X30 FFA")
141MACHINE_END 141MACHINE_END
142 142
143MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID") 143MACHINE_START(MSM7X30_FLUID, "QCT MSM7X30 FLUID")
144 .boot_params = PLAT_PHYS_OFFSET + 0x100, 144 .atag_offset = 0x100,
145 .fixup = msm7x30_fixup, 145 .fixup = msm7x30_fixup,
146 .reserve = msm7x30_reserve, 146 .reserve = msm7x30_reserve,
147 .map_io = msm7x30_map_io, 147 .map_io = msm7x30_map_io,
diff --git a/arch/arm/mach-msm/board-msm8x60.c b/arch/arm/mach-msm/board-msm8x60.c
index 9221f54778be..106170fb1844 100644
--- a/arch/arm/mach-msm/board-msm8x60.c
+++ b/arch/arm/mach-msm/board-msm8x60.c
@@ -53,8 +53,6 @@ static void __init msm8x60_map_io(void)
53 53
54static void __init msm8x60_init_irq(void) 54static void __init msm8x60_init_irq(void)
55{ 55{
56 unsigned int i;
57
58 gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, 56 gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
59 (void *)MSM_QGIC_CPU_BASE); 57 (void *)MSM_QGIC_CPU_BASE);
60 58
@@ -66,15 +64,6 @@ static void __init msm8x60_init_irq(void)
66 */ 64 */
67 if (!machine_is_msm8x60_sim()) 65 if (!machine_is_msm8x60_sim())
68 writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET); 66 writel(0x0000FFFF, MSM_QGIC_DIST_BASE + GIC_DIST_ENABLE_SET);
69
70 /* FIXME: Not installing AVS_SVICINT and AVS_SVICINTSWDONE yet
71 * as they are configured as level, which does not play nice with
72 * handle_percpu_irq.
73 */
74 for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
75 if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
76 irq_set_handler(i, handle_percpu_irq);
77 }
78} 67}
79 68
80static void __init msm8x60_init(void) 69static void __init msm8x60_init(void)
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 24e9b89738ef..7e8909c978c3 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -192,7 +192,7 @@ static void __init qsd8x50_init(void)
192} 192}
193 193
194MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF") 194MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
195 .boot_params = PLAT_PHYS_OFFSET + 0x100, 195 .atag_offset = 0x100,
196 .map_io = qsd8x50_map_io, 196 .map_io = qsd8x50_map_io,
197 .init_irq = qsd8x50_init_irq, 197 .init_irq = qsd8x50_init_irq,
198 .init_machine = qsd8x50_init, 198 .init_machine = qsd8x50_init,
@@ -200,7 +200,7 @@ MACHINE_START(QSD8X50_SURF, "QCT QSD8X50 SURF")
200MACHINE_END 200MACHINE_END
201 201
202MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5") 202MACHINE_START(QSD8X50A_ST1_5, "QCT QSD8X50A ST1.5")
203 .boot_params = PLAT_PHYS_OFFSET + 0x100, 203 .atag_offset = 0x100,
204 .map_io = qsd8x50_map_io, 204 .map_io = qsd8x50_map_io,
205 .init_irq = qsd8x50_init_irq, 205 .init_irq = qsd8x50_init_irq,
206 .init_machine = qsd8x50_init, 206 .init_machine = qsd8x50_init,
diff --git a/arch/arm/mach-msm/board-sapphire.c b/arch/arm/mach-msm/board-sapphire.c
index 11c1e75ebb1b..32b465763dbd 100644
--- a/arch/arm/mach-msm/board-sapphire.c
+++ b/arch/arm/mach-msm/board-sapphire.c
@@ -104,7 +104,7 @@ static void __init sapphire_map_io(void)
104 104
105MACHINE_START(SAPPHIRE, "sapphire") 105MACHINE_START(SAPPHIRE, "sapphire")
106/* Maintainer: Brian Swetland <swetland@google.com> */ 106/* Maintainer: Brian Swetland <swetland@google.com> */
107 .boot_params = PLAT_PHYS_OFFSET + 0x100, 107 .atag_offset = 0x100,
108 .fixup = sapphire_fixup, 108 .fixup = sapphire_fixup,
109 .map_io = sapphire_map_io, 109 .map_io = sapphire_map_io,
110 .init_irq = sapphire_init_irq, 110 .init_irq = sapphire_init_irq,
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 7acd2021ada9..6b9b227c87c5 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -93,7 +93,7 @@ static void __init trout_map_io(void)
93} 93}
94 94
95MACHINE_START(TROUT, "HTC Dream") 95MACHINE_START(TROUT, "HTC Dream")
96 .boot_params = 0x10000100, 96 .atag_offset = 0x100,
97 .fixup = trout_fixup, 97 .fixup = trout_fixup,
98 .map_io = trout_map_io, 98 .map_io = trout_map_io,
99 .init_irq = trout_init_irq, 99 .init_irq = trout_init_irq,
diff --git a/arch/arm/mach-msm/include/mach/debug-macro.S b/arch/arm/mach-msm/include/mach/debug-macro.S
index 646b99ebc773..2dc73ccddb11 100644
--- a/arch/arm/mach-msm/include/mach/debug-macro.S
+++ b/arch/arm/mach-msm/include/mach/debug-macro.S
@@ -20,7 +20,7 @@
20#include <mach/msm_iomap.h> 20#include <mach/msm_iomap.h>
21 21
22#if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE) 22#if defined(CONFIG_HAS_MSM_DEBUG_UART_PHYS) && !defined(CONFIG_MSM_DEBUG_UART_NONE)
23 .macro addruart, rp, rv 23 .macro addruart, rp, rv, tmp
24 ldr \rp, =MSM_DEBUG_UART_PHYS 24 ldr \rp, =MSM_DEBUG_UART_PHYS
25 ldr \rv, =MSM_DEBUG_UART_BASE 25 ldr \rv, =MSM_DEBUG_UART_BASE
26 .endm 26 .endm
@@ -37,7 +37,7 @@
37 beq 1001b 37 beq 1001b
38 .endm 38 .endm
39#else 39#else
40 .macro addruart, rp, rv 40 .macro addruart, rp, rv, tmp
41 mov \rv, #0xff000000 41 mov \rv, #0xff000000
42 orr \rv, \rv, #0x00f00000 42 orr \rv, \rv, #0x00f00000
43 .endm 43 .endm
diff --git a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
index 12467157afb9..717076f3ca73 100644
--- a/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
+++ b/arch/arm/mach-msm/include/mach/entry-macro-qgic.S
@@ -8,81 +8,10 @@
8 * warranty of any kind, whether express or implied. 8 * warranty of any kind, whether express or implied.
9 */ 9 */
10 10
11#include <mach/hardware.h> 11#include <asm/hardware/entry-macro-gic.S>
12#include <asm/hardware/gic.h>
13 12
14 .macro disable_fiq 13 .macro disable_fiq
15 .endm 14 .endm
16 15
17 .macro get_irqnr_preamble, base, tmp
18 ldr \base, =gic_cpu_base_addr
19 ldr \base, [\base]
20 .endm
21
22 .macro arch_ret_to_user, tmp1, tmp2 16 .macro arch_ret_to_user, tmp1, tmp2
23 .endm 17 .endm
24
25 /*
26 * The interrupt numbering scheme is defined in the
27 * interrupt controller spec. To wit:
28 *
29 * Migrated the code from ARM MP port to be more consistent
30 * with interrupt processing , the following still holds true
31 * however, all interrupts are treated the same regardless of
32 * if they are local IPI or PPI
33 *
34 * Interrupts 0-15 are IPI
35 * 16-31 are PPI
36 * (16-18 are the timers)
37 * 32-1020 are global
38 * 1021-1022 are reserved
39 * 1023 is "spurious" (no interrupt)
40 *
41 * A simple read from the controller will tell us the number of the
42 * highest priority enabled interrupt. We then just need to check
43 * whether it is in the valid range for an IRQ (0-1020 inclusive).
44 *
45 * Base ARM code assumes that the local (private) peripheral interrupts
46 * are not valid, we treat them differently, in that the privates are
47 * handled like normal shared interrupts with the exception that only
48 * one processor can register the interrupt and the handler must be
49 * the same for all processors.
50 */
51
52 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
53
54 ldr \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 =srcCPU,
55 9-0 =int # */
56
57 bic \irqnr, \irqstat, #0x1c00 @mask src
58 cmp \irqnr, #15
59 ldr \tmp, =1021
60 cmpcc \irqnr, \irqnr
61 cmpne \irqnr, \tmp
62 cmpcs \irqnr, \irqnr
63
64 .endm
65
66 /* We assume that irqstat (the raw value of the IRQ acknowledge
67 * register) is preserved from the macro above.
68 * If there is an IPI, we immediately signal end of interrupt on the
69 * controller, since this requires the original irqstat value which
70 * we won't easily be able to recreate later.
71 */
72 .macro test_for_ipi, irqnr, irqstat, base, tmp
73 bic \irqnr, \irqstat, #0x1c00
74 cmp \irqnr, #16
75 strcc \irqstat, [\base, #GIC_CPU_EOI]
76 cmpcs \irqnr, \irqnr
77 .endm
78
79 /* As above, this assumes that irqstat and base are preserved.. */
80
81 .macro test_for_ltirq, irqnr, irqstat, base, tmp
82 bic \irqnr, \irqstat, #0x1c00
83 mov \tmp, #0
84 cmp \irqnr, #16
85 moveq \tmp, #1
86 streq \irqstat, [\base, #GIC_CPU_EOI]
87 cmp \tmp, #0
88 .endm
diff --git a/arch/arm/mach-msm/include/mach/memory.h b/arch/arm/mach-msm/include/mach/memory.h
deleted file mode 100644
index 58d5e7eec431..000000000000
--- a/arch/arm/mach-msm/include/mach/memory.h
+++ /dev/null
@@ -1,35 +0,0 @@
1/* arch/arm/mach-msm/include/mach/memory.h
2 *
3 * Copyright (C) 2007 Google, Inc.
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16#ifndef __ASM_ARCH_MEMORY_H
17#define __ASM_ARCH_MEMORY_H
18
19/* physical offset of RAM */
20#if defined(CONFIG_ARCH_QSD8X50) && defined(CONFIG_MSM_SOC_REV_A)
21#define PLAT_PHYS_OFFSET UL(0x00000000)
22#elif defined(CONFIG_ARCH_QSD8X50)
23#define PLAT_PHYS_OFFSET UL(0x20000000)
24#elif defined(CONFIG_ARCH_MSM7X30)
25#define PLAT_PHYS_OFFSET UL(0x00000000)
26#elif defined(CONFIG_ARCH_MSM8X60)
27#define PLAT_PHYS_OFFSET UL(0x40000000)
28#elif defined(CONFIG_ARCH_MSM8960)
29#define PLAT_PHYS_OFFSET UL(0x40000000)
30#else
31#define PLAT_PHYS_OFFSET UL(0x10000000)
32#endif
33
34#endif
35
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 63621f152c98..afeeca52fc66 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -71,12 +71,16 @@ enum timer_location {
71struct msm_clock { 71struct msm_clock {
72 struct clock_event_device clockevent; 72 struct clock_event_device clockevent;
73 struct clocksource clocksource; 73 struct clocksource clocksource;
74 struct irqaction irq; 74 unsigned int irq;
75 void __iomem *regbase; 75 void __iomem *regbase;
76 uint32_t freq; 76 uint32_t freq;
77 uint32_t shift; 77 uint32_t shift;
78 void __iomem *global_counter; 78 void __iomem *global_counter;
79 void __iomem *local_counter; 79 void __iomem *local_counter;
80 union {
81 struct clock_event_device *evt;
82 struct clock_event_device __percpu **percpu_evt;
83 };
80}; 84};
81 85
82enum { 86enum {
@@ -87,13 +91,10 @@ enum {
87 91
88 92
89static struct msm_clock msm_clocks[]; 93static struct msm_clock msm_clocks[];
90static struct clock_event_device *local_clock_event;
91 94
92static irqreturn_t msm_timer_interrupt(int irq, void *dev_id) 95static irqreturn_t msm_timer_interrupt(int irq, void *dev_id)
93{ 96{
94 struct clock_event_device *evt = dev_id; 97 struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
95 if (smp_processor_id() != 0)
96 evt = local_clock_event;
97 if (evt->event_handler == NULL) 98 if (evt->event_handler == NULL)
98 return IRQ_HANDLED; 99 return IRQ_HANDLED;
99 evt->event_handler(evt); 100 evt->event_handler(evt);
@@ -171,13 +172,7 @@ static struct msm_clock msm_clocks[] = {
171 .mask = CLOCKSOURCE_MASK(32), 172 .mask = CLOCKSOURCE_MASK(32),
172 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 173 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
173 }, 174 },
174 .irq = { 175 .irq = INT_GP_TIMER_EXP,
175 .name = "gp_timer",
176 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
177 .handler = msm_timer_interrupt,
178 .dev_id = &msm_clocks[0].clockevent,
179 .irq = INT_GP_TIMER_EXP
180 },
181 .freq = GPT_HZ, 176 .freq = GPT_HZ,
182 }, 177 },
183 [MSM_CLOCK_DGT] = { 178 [MSM_CLOCK_DGT] = {
@@ -196,13 +191,7 @@ static struct msm_clock msm_clocks[] = {
196 .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)), 191 .mask = CLOCKSOURCE_MASK((32 - MSM_DGT_SHIFT)),
197 .flags = CLOCK_SOURCE_IS_CONTINUOUS, 192 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
198 }, 193 },
199 .irq = { 194 .irq = INT_DEBUG_TIMER_EXP,
200 .name = "dg_timer",
201 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_RISING,
202 .handler = msm_timer_interrupt,
203 .dev_id = &msm_clocks[1].clockevent,
204 .irq = INT_DEBUG_TIMER_EXP
205 },
206 .freq = DGT_HZ >> MSM_DGT_SHIFT, 195 .freq = DGT_HZ >> MSM_DGT_SHIFT,
207 .shift = MSM_DGT_SHIFT, 196 .shift = MSM_DGT_SHIFT,
208 } 197 }
@@ -261,10 +250,30 @@ static void __init msm_timer_init(void)
261 printk(KERN_ERR "msm_timer_init: clocksource_register " 250 printk(KERN_ERR "msm_timer_init: clocksource_register "
262 "failed for %s\n", cs->name); 251 "failed for %s\n", cs->name);
263 252
264 res = setup_irq(clock->irq.irq, &clock->irq); 253 ce->irq = clock->irq;
254 if (cpu_is_msm8x60() || cpu_is_msm8960()) {
255 clock->percpu_evt = alloc_percpu(struct clock_event_device *);
256 if (!clock->percpu_evt) {
257 pr_err("msm_timer_init: memory allocation "
258 "failed for %s\n", ce->name);
259 continue;
260 }
261
262 *__this_cpu_ptr(clock->percpu_evt) = ce;
263 res = request_percpu_irq(ce->irq, msm_timer_interrupt,
264 ce->name, clock->percpu_evt);
265 if (!res)
266 enable_percpu_irq(ce->irq, 0);
267 } else {
268 clock->evt = ce;
269 res = request_irq(ce->irq, msm_timer_interrupt,
270 IRQF_TIMER | IRQF_NOBALANCING | IRQF_TRIGGER_RISING,
271 ce->name, &clock->evt);
272 }
273
265 if (res) 274 if (res)
266 printk(KERN_ERR "msm_timer_init: setup_irq " 275 pr_err("msm_timer_init: request_irq failed for %s\n",
267 "failed for %s\n", cs->name); 276 ce->name);
268 277
269 clockevents_register_device(ce); 278 clockevents_register_device(ce);
270 } 279 }
@@ -273,6 +282,7 @@ static void __init msm_timer_init(void)
273#ifdef CONFIG_SMP 282#ifdef CONFIG_SMP
274int __cpuinit local_timer_setup(struct clock_event_device *evt) 283int __cpuinit local_timer_setup(struct clock_event_device *evt)
275{ 284{
285 static bool local_timer_inited;
276 struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER]; 286 struct msm_clock *clock = &msm_clocks[MSM_GLOBAL_TIMER];
277 287
278 /* Use existing clock_event for cpu 0 */ 288 /* Use existing clock_event for cpu 0 */
@@ -281,12 +291,13 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
281 291
282 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL); 292 writel(DGT_CLK_CTL_DIV_4, MSM_TMR_BASE + DGT_CLK_CTL);
283 293
284 if (!local_clock_event) { 294 if (!local_timer_inited) {
285 writel(0, clock->regbase + TIMER_ENABLE); 295 writel(0, clock->regbase + TIMER_ENABLE);
286 writel(0, clock->regbase + TIMER_CLEAR); 296 writel(0, clock->regbase + TIMER_CLEAR);
287 writel(~0, clock->regbase + TIMER_MATCH_VAL); 297 writel(~0, clock->regbase + TIMER_MATCH_VAL);
298 local_timer_inited = true;
288 } 299 }
289 evt->irq = clock->irq.irq; 300 evt->irq = clock->irq;
290 evt->name = "local_timer"; 301 evt->name = "local_timer";
291 evt->features = CLOCK_EVT_FEAT_ONESHOT; 302 evt->features = CLOCK_EVT_FEAT_ONESHOT;
292 evt->rating = clock->clockevent.rating; 303 evt->rating = clock->clockevent.rating;
@@ -298,17 +309,17 @@ int __cpuinit local_timer_setup(struct clock_event_device *evt)
298 clockevent_delta2ns(0xf0000000 >> clock->shift, evt); 309 clockevent_delta2ns(0xf0000000 >> clock->shift, evt);
299 evt->min_delta_ns = clockevent_delta2ns(4, evt); 310 evt->min_delta_ns = clockevent_delta2ns(4, evt);
300 311
301 local_clock_event = evt; 312 *__this_cpu_ptr(clock->percpu_evt) = evt;
302 313 enable_percpu_irq(evt->irq, 0);
303 gic_enable_ppi(clock->irq.irq);
304 314
305 clockevents_register_device(evt); 315 clockevents_register_device(evt);
306 return 0; 316 return 0;
307} 317}
308 318
309inline int local_timer_ack(void) 319void local_timer_stop(struct clock_event_device *evt)
310{ 320{
311 return 1; 321 evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt);
322 disable_percpu_irq(evt->irq);
312} 323}
313 324
314#endif 325#endif
diff --git a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
index 20f3f125ed2b..0e94268d6e6f 100644
--- a/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
+++ b/arch/arm/mach-mv78xx0/buffalo-wxl-setup.c
@@ -145,7 +145,7 @@ subsys_initcall(wxl_pci_init);
145 145
146MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL") 146MACHINE_START(TERASTATION_WXL, "Buffalo Nas WXL")
147 /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */ 147 /* Maintainer: Sebastien Requiem <sebastien@requiem.fr> */
148 .boot_params = 0x00000100, 148 .atag_offset = 0x100,
149 .init_machine = wxl_init, 149 .init_machine = wxl_init,
150 .map_io = mv78xx0_map_io, 150 .map_io = mv78xx0_map_io,
151 .init_early = mv78xx0_init_early, 151 .init_early = mv78xx0_init_early,
diff --git a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
index df5aebe5b0fa..50b85ae2da52 100644
--- a/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
+++ b/arch/arm/mach-mv78xx0/db78x00-bp-setup.c
@@ -93,7 +93,7 @@ subsys_initcall(db78x00_pci_init);
93 93
94MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board") 94MACHINE_START(DB78X00_BP, "Marvell DB-78x00-BP Development Board")
95 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 95 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
96 .boot_params = 0x00000100, 96 .atag_offset = 0x100,
97 .init_machine = db78x00_init, 97 .init_machine = db78x00_init,
98 .map_io = mv78xx0_map_io, 98 .map_io = mv78xx0_map_io,
99 .init_early = mv78xx0_init_early, 99 .init_early = mv78xx0_init_early,
diff --git a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
index 04891428e48b..a7df02b049b7 100644
--- a/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
+++ b/arch/arm/mach-mv78xx0/include/mach/debug-macro.S
@@ -8,7 +8,7 @@
8 8
9#include <mach/mv78xx0.h> 9#include <mach/mv78xx0.h>
10 10
11 .macro addruart, rp, rv 11 .macro addruart, rp, rv, tmp
12 ldr \rp, =MV78XX0_REGS_PHYS_BASE 12 ldr \rp, =MV78XX0_REGS_PHYS_BASE
13 ldr \rv, =MV78XX0_REGS_VIRT_BASE 13 ldr \rv, =MV78XX0_REGS_VIRT_BASE
14 orr \rp, \rp, #0x00012000 14 orr \rp, \rp, #0x00012000
diff --git a/arch/arm/mach-mv78xx0/include/mach/memory.h b/arch/arm/mach-mv78xx0/include/mach/memory.h
deleted file mode 100644
index a648c51f2e42..000000000000
--- a/arch/arm/mach-mv78xx0/include/mach/memory.h
+++ /dev/null
@@ -1,10 +0,0 @@
1/*
2 * arch/arm/mach-mv78xx0/include/mach/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PLAT_PHYS_OFFSET UL(0x00000000)
9
10#endif
diff --git a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
index d927f14c6810..e85222e53578 100644
--- a/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
+++ b/arch/arm/mach-mv78xx0/rd78x00-masa-setup.c
@@ -78,7 +78,7 @@ subsys_initcall(rd78x00_pci_init);
78 78
79MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board") 79MACHINE_START(RD78X00_MASA, "Marvell RD-78x00-MASA Development Board")
80 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 80 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
81 .boot_params = 0x00000100, 81 .atag_offset = 0x100,
82 .init_machine = rd78x00_masa_init, 82 .init_machine = rd78x00_masa_init,
83 .map_io = mv78xx0_map_io, 83 .map_io = mv78xx0_map_io,
84 .init_early = mv78xx0_init_early, 84 .init_early = mv78xx0_init_early,
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 68934ea8725a..e01af948e043 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -293,7 +293,7 @@ static struct sys_timer mxc_timer = {
293 293
294MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") 294MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
295 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 295 /* Maintainer: Eric Bénard <eric@eukrea.com> */
296 .boot_params = MX51_PHYS_OFFSET + 0x100, 296 .atag_offset = 0x100,
297 .map_io = mx51_map_io, 297 .map_io = mx51_map_io,
298 .init_early = imx51_init_early, 298 .init_early = imx51_init_early,
299 .init_irq = mx51_init_irq, 299 .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index ff096d587299..b41fc274a425 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -331,7 +331,7 @@ static struct sys_timer mxc_timer = {
331 331
332MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") 332MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
333 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 333 /* Maintainer: Eric Bénard <eric@eukrea.com> */
334 .boot_params = MX51_PHYS_OFFSET + 0x100, 334 .atag_offset = 0x100,
335 .map_io = mx51_map_io, 335 .map_io = mx51_map_io,
336 .init_early = imx51_init_early, 336 .init_early = imx51_init_early,
337 .init_irq = mx51_init_irq, 337 .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 07a38154da21..a50174e69e2f 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -169,7 +169,7 @@ static struct sys_timer mx51_3ds_timer = {
169 169
170MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") 170MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
171 /* Maintainer: Freescale Semiconductor, Inc. */ 171 /* Maintainer: Freescale Semiconductor, Inc. */
172 .boot_params = MX51_PHYS_OFFSET + 0x100, 172 .atag_offset = 0x100,
173 .map_io = mx51_map_io, 173 .map_io = mx51_map_io,
174 .init_early = imx51_init_early, 174 .init_early = imx51_init_early,
175 .init_irq = mx51_init_irq, 175 .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 11b0ff67f89d..468926a48fe0 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -416,7 +416,7 @@ static struct sys_timer mx51_babbage_timer = {
416 416
417MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board") 417MACHINE_START(MX51_BABBAGE, "Freescale MX51 Babbage Board")
418 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */ 418 /* Maintainer: Amit Kucheria <amit.kucheria@canonical.com> */
419 .boot_params = MX51_PHYS_OFFSET + 0x100, 419 .atag_offset = 0x100,
420 .map_io = mx51_map_io, 420 .map_io = mx51_map_io,
421 .init_early = imx51_init_early, 421 .init_early = imx51_init_early,
422 .init_irq = mx51_init_irq, 422 .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index 551daf85ff8c..c36880da03f0 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -280,7 +280,7 @@ static struct sys_timer mx51_efikamx_timer = {
280 280
281MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop") 281MACHINE_START(MX51_EFIKAMX, "Genesi EfikaMX nettop")
282 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */ 282 /* Maintainer: Amit Kucheria <amit.kucheria@linaro.org> */
283 .boot_params = MX51_PHYS_OFFSET + 0x100, 283 .atag_offset = 0x100,
284 .map_io = mx51_map_io, 284 .map_io = mx51_map_io,
285 .init_early = imx51_init_early, 285 .init_early = imx51_init_early,
286 .init_irq = mx51_init_irq, 286 .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
index 8a9bca22beb5..ba5436a9fb1a 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -266,7 +266,7 @@ static struct sys_timer mx51_efikasb_timer = {
266}; 266};
267 267
268MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook") 268MACHINE_START(MX51_EFIKASB, "Genesi Efika Smartbook")
269 .boot_params = MX51_PHYS_OFFSET + 0x100, 269 .atag_offset = 0x100,
270 .map_io = mx51_map_io, 270 .map_io = mx51_map_io,
271 .init_early = imx51_init_early, 271 .init_early = imx51_init_early,
272 .init_irq = mx51_init_irq, 272 .init_irq = mx51_init_irq,
diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S
index 79650a1ad78d..714570d83668 100644
--- a/arch/arm/mach-mxs/include/mach/debug-macro.S
+++ b/arch/arm/mach-mxs/include/mach/debug-macro.S
@@ -30,7 +30,7 @@
30 30
31#define UART_VADDR MXS_IO_ADDRESS(UART_PADDR) 31#define UART_VADDR MXS_IO_ADDRESS(UART_PADDR)
32 32
33 .macro addruart, rp, rv 33 .macro addruart, rp, rv, tmp
34 ldr \rp, =UART_PADDR @ physical 34 ldr \rp, =UART_PADDR @ physical
35 ldr \rv, =UART_VADDR @ virtual 35 ldr \rv, =UART_VADDR @ virtual
36 .endm 36 .endm
diff --git a/arch/arm/mach-mxs/include/mach/memory.h b/arch/arm/mach-mxs/include/mach/memory.h
deleted file mode 100644
index b5420a5c2d4b..000000000000
--- a/arch/arm/mach-mxs/include/mach/memory.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_MXS_MEMORY_H__
20#define __MACH_MXS_MEMORY_H__
21
22#define PHYS_OFFSET UL(0x40000000)
23
24#endif /* __MACH_MXS_MEMORY_H__ */
diff --git a/arch/arm/mach-netx/include/mach/debug-macro.S b/arch/arm/mach-netx/include/mach/debug-macro.S
index 56a915228180..247781e096e2 100644
--- a/arch/arm/mach-netx/include/mach/debug-macro.S
+++ b/arch/arm/mach-netx/include/mach/debug-macro.S
@@ -13,7 +13,7 @@
13 13
14#include "hardware.h" 14#include "hardware.h"
15 15
16 .macro addruart, rp, rv 16 .macro addruart, rp, rv, tmp
17 mov \rp, #0x00000a00 17 mov \rp, #0x00000a00
18 orr \rv, \rp, #io_p2v(0x00100000) @ virtual 18 orr \rv, \rp, #io_p2v(0x00100000) @ virtual
19 orr \rp, \rp, #0x00100000 @ physical 19 orr \rp, \rp, #0x00100000 @ physical
diff --git a/arch/arm/mach-netx/include/mach/memory.h b/arch/arm/mach-netx/include/mach/memory.h
deleted file mode 100644
index 59561496c36e..000000000000
--- a/arch/arm/mach-netx/include/mach/memory.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * arch/arm/mach-netx/include/mach/memory.h
3 *
4 * Copyright (C) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20#ifndef __ASM_ARCH_MEMORY_H
21#define __ASM_ARCH_MEMORY_H
22
23#define PLAT_PHYS_OFFSET UL(0x80000000)
24
25#endif
26
diff --git a/arch/arm/mach-netx/nxdb500.c b/arch/arm/mach-netx/nxdb500.c
index ca8b203a3c99..90903dd44cbc 100644
--- a/arch/arm/mach-netx/nxdb500.c
+++ b/arch/arm/mach-netx/nxdb500.c
@@ -200,7 +200,7 @@ static void __init nxdb500_init(void)
200} 200}
201 201
202MACHINE_START(NXDB500, "Hilscher nxdb500") 202MACHINE_START(NXDB500, "Hilscher nxdb500")
203 .boot_params = 0x80000100, 203 .atag_offset = 0x100,
204 .map_io = netx_map_io, 204 .map_io = netx_map_io,
205 .init_irq = netx_init_irq, 205 .init_irq = netx_init_irq,
206 .timer = &netx_timer, 206 .timer = &netx_timer,
diff --git a/arch/arm/mach-netx/nxdkn.c b/arch/arm/mach-netx/nxdkn.c
index d775cbe07278..c63384aba500 100644
--- a/arch/arm/mach-netx/nxdkn.c
+++ b/arch/arm/mach-netx/nxdkn.c
@@ -93,7 +93,7 @@ static void __init nxdkn_init(void)
93} 93}
94 94
95MACHINE_START(NXDKN, "Hilscher nxdkn") 95MACHINE_START(NXDKN, "Hilscher nxdkn")
96 .boot_params = 0x80000100, 96 .atag_offset = 0x100,
97 .map_io = netx_map_io, 97 .map_io = netx_map_io,
98 .init_irq = netx_init_irq, 98 .init_irq = netx_init_irq,
99 .timer = &netx_timer, 99 .timer = &netx_timer,
diff --git a/arch/arm/mach-netx/nxeb500hmi.c b/arch/arm/mach-netx/nxeb500hmi.c
index de369cd1dcbe..8f548ec83ad2 100644
--- a/arch/arm/mach-netx/nxeb500hmi.c
+++ b/arch/arm/mach-netx/nxeb500hmi.c
@@ -177,7 +177,7 @@ static void __init nxeb500hmi_init(void)
177} 177}
178 178
179MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi") 179MACHINE_START(NXEB500HMI, "Hilscher nxeb500hmi")
180 .boot_params = 0x80000100, 180 .atag_offset = 0x100,
181 .map_io = netx_map_io, 181 .map_io = netx_map_io,
182 .init_irq = netx_init_irq, 182 .init_irq = netx_init_irq,
183 .timer = &netx_timer, 183 .timer = &netx_timer,
diff --git a/arch/arm/mach-nomadik/board-nhk8815.c b/arch/arm/mach-nomadik/board-nhk8815.c
index 97d7186484ca..0cbb74c96ef7 100644
--- a/arch/arm/mach-nomadik/board-nhk8815.c
+++ b/arch/arm/mach-nomadik/board-nhk8815.c
@@ -277,7 +277,7 @@ static void __init nhk8815_platform_init(void)
277 277
278MACHINE_START(NOMADIK, "NHK8815") 278MACHINE_START(NOMADIK, "NHK8815")
279 /* Maintainer: ST MicroElectronics */ 279 /* Maintainer: ST MicroElectronics */
280 .boot_params = 0x100, 280 .atag_offset = 0x100,
281 .map_io = cpu8815_map_io, 281 .map_io = cpu8815_map_io,
282 .init_irq = cpu8815_init_irq, 282 .init_irq = cpu8815_init_irq,
283 .timer = &nomadik_timer, 283 .timer = &nomadik_timer,
diff --git a/arch/arm/mach-nomadik/include/mach/debug-macro.S b/arch/arm/mach-nomadik/include/mach/debug-macro.S
index e7151b4b8889..735417922ce2 100644
--- a/arch/arm/mach-nomadik/include/mach/debug-macro.S
+++ b/arch/arm/mach-nomadik/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
10 * 10 *
11*/ 11*/
12 12
13 .macro addruart, rp, rv 13 .macro addruart, rp, rv, tmp
14 mov \rp, #0x00100000 14 mov \rp, #0x00100000
15 add \rp, \rp, #0x000fb000 15 add \rp, \rp, #0x000fb000
16 add \rv, \rp, #0xf0000000 @ virtual base 16 add \rv, \rp, #0xf0000000 @ virtual base
diff --git a/arch/arm/mach-nomadik/include/mach/memory.h b/arch/arm/mach-nomadik/include/mach/memory.h
deleted file mode 100644
index d3325211ba6a..000000000000
--- a/arch/arm/mach-nomadik/include/mach/memory.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * mach-nomadik/include/mach/memory.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_MEMORY_H
21#define __ASM_ARCH_MEMORY_H
22
23/*
24 * Physical DRAM offset.
25 */
26#define PLAT_PHYS_OFFSET UL(0x00000000)
27
28#endif
diff --git a/arch/arm/mach-nuc93x/include/mach/memory.h b/arch/arm/mach-nuc93x/include/mach/memory.h
deleted file mode 100644
index ef9864b002a6..000000000000
--- a/arch/arm/mach-nuc93x/include/mach/memory.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-nuc93x/include/mach/memory.h
3 *
4 * Copyright (c) 2008 Nuvoton technology corporation
5 * All rights reserved.
6 *
7 * Wan ZongShun <mcuos.com@gmail.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#ifndef __ASM_ARCH_MEMORY_H
17#define __ASM_ARCH_MEMORY_H
18
19#define PLAT_PHYS_OFFSET UL(0x00000000)
20
21#endif
diff --git a/arch/arm/mach-nuc93x/mach-nuc932evb.c b/arch/arm/mach-nuc93x/mach-nuc932evb.c
index d70257042480..1f741b1c1604 100644
--- a/arch/arm/mach-nuc93x/mach-nuc932evb.c
+++ b/arch/arm/mach-nuc93x/mach-nuc932evb.c
@@ -35,7 +35,6 @@ static void __init nuc932evb_init(void)
35 35
36MACHINE_START(NUC932EVB, "NUC932EVB") 36MACHINE_START(NUC932EVB, "NUC932EVB")
37 /* Maintainer: Wan ZongShun */ 37 /* Maintainer: Wan ZongShun */
38 .boot_params = 0,
39 .map_io = nuc932evb_map_io, 38 .map_io = nuc932evb_map_io,
40 .init_irq = nuc93x_init_irq, 39 .init_irq = nuc93x_init_irq,
41 .init_machine = nuc932evb_init, 40 .init_machine = nuc932evb_init,
diff --git a/arch/arm/mach-omap1/board-ams-delta.c b/arch/arm/mach-omap1/board-ams-delta.c
index d86e9af2822b..4ea60e2038ea 100644
--- a/arch/arm/mach-omap1/board-ams-delta.c
+++ b/arch/arm/mach-omap1/board-ams-delta.c
@@ -385,7 +385,7 @@ static void __init ams_delta_map_io(void)
385 385
386MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)") 386MACHINE_START(AMS_DELTA, "Amstrad E3 (Delta)")
387 /* Maintainer: Jonathan McDowell <noodles@earth.li> */ 387 /* Maintainer: Jonathan McDowell <noodles@earth.li> */
388 .boot_params = 0x10000100, 388 .atag_offset = 0x100,
389 .map_io = ams_delta_map_io, 389 .map_io = ams_delta_map_io,
390 .reserve = omap_reserve, 390 .reserve = omap_reserve,
391 .init_irq = ams_delta_init_irq, 391 .init_irq = ams_delta_init_irq,
diff --git a/arch/arm/mach-omap1/board-fsample.c b/arch/arm/mach-omap1/board-fsample.c
index dd814b33cdd5..31e089b6f03f 100644
--- a/arch/arm/mach-omap1/board-fsample.c
+++ b/arch/arm/mach-omap1/board-fsample.c
@@ -388,7 +388,7 @@ static void __init omap_fsample_map_io(void)
388 388
389MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample") 389MACHINE_START(OMAP_FSAMPLE, "OMAP730 F-Sample")
390/* Maintainer: Brian Swetland <swetland@google.com> */ 390/* Maintainer: Brian Swetland <swetland@google.com> */
391 .boot_params = 0x10000100, 391 .atag_offset = 0x100,
392 .map_io = omap_fsample_map_io, 392 .map_io = omap_fsample_map_io,
393 .reserve = omap_reserve, 393 .reserve = omap_reserve,
394 .init_irq = omap_fsample_init_irq, 394 .init_irq = omap_fsample_init_irq,
diff --git a/arch/arm/mach-omap1/board-generic.c b/arch/arm/mach-omap1/board-generic.c
index 8f7d11581482..05c6e9d858f3 100644
--- a/arch/arm/mach-omap1/board-generic.c
+++ b/arch/arm/mach-omap1/board-generic.c
@@ -93,7 +93,7 @@ static void __init omap_generic_map_io(void)
93 93
94MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710") 94MACHINE_START(OMAP_GENERIC, "Generic OMAP1510/1610/1710")
95 /* Maintainer: Tony Lindgren <tony@atomide.com> */ 95 /* Maintainer: Tony Lindgren <tony@atomide.com> */
96 .boot_params = 0x10000100, 96 .atag_offset = 0x100,
97 .map_io = omap_generic_map_io, 97 .map_io = omap_generic_map_io,
98 .reserve = omap_reserve, 98 .reserve = omap_reserve,
99 .init_irq = omap_generic_init_irq, 99 .init_irq = omap_generic_init_irq,
diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
index 0796ad7e24b5..c2e279173d42 100644
--- a/arch/arm/mach-omap1/board-h2.c
+++ b/arch/arm/mach-omap1/board-h2.c
@@ -460,7 +460,7 @@ static void __init h2_map_io(void)
460 460
461MACHINE_START(OMAP_H2, "TI-H2") 461MACHINE_START(OMAP_H2, "TI-H2")
462 /* Maintainer: Imre Deak <imre.deak@nokia.com> */ 462 /* Maintainer: Imre Deak <imre.deak@nokia.com> */
463 .boot_params = 0x10000100, 463 .atag_offset = 0x100,
464 .map_io = h2_map_io, 464 .map_io = h2_map_io,
465 .reserve = omap_reserve, 465 .reserve = omap_reserve,
466 .init_irq = h2_init_irq, 466 .init_irq = h2_init_irq,
diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
index fe1814c5e748..8f5b6af7ed59 100644
--- a/arch/arm/mach-omap1/board-h3.c
+++ b/arch/arm/mach-omap1/board-h3.c
@@ -448,7 +448,7 @@ static void __init h3_map_io(void)
448 448
449MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board") 449MACHINE_START(OMAP_H3, "TI OMAP1710 H3 board")
450 /* Maintainer: Texas Instruments, Inc. */ 450 /* Maintainer: Texas Instruments, Inc. */
451 .boot_params = 0x10000100, 451 .atag_offset = 0x100,
452 .map_io = h3_map_io, 452 .map_io = h3_map_io,
453 .reserve = omap_reserve, 453 .reserve = omap_reserve,
454 .init_irq = h3_init_irq, 454 .init_irq = h3_init_irq,
diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
index 4af7bfa40e4a..fcd1a3c31896 100644
--- a/arch/arm/mach-omap1/board-htcherald.c
+++ b/arch/arm/mach-omap1/board-htcherald.c
@@ -610,7 +610,7 @@ static void __init htcherald_init_irq(void)
610MACHINE_START(HERALD, "HTC Herald") 610MACHINE_START(HERALD, "HTC Herald")
611 /* Maintainer: Cory Maccarrone <darkstar6262@gmail.com> */ 611 /* Maintainer: Cory Maccarrone <darkstar6262@gmail.com> */
612 /* Maintainer: wing-linux.sourceforge.net */ 612 /* Maintainer: wing-linux.sourceforge.net */
613 .boot_params = 0x10000100, 613 .atag_offset = 0x100,
614 .map_io = htcherald_map_io, 614 .map_io = htcherald_map_io,
615 .reserve = omap_reserve, 615 .reserve = omap_reserve,
616 .init_irq = htcherald_init_irq, 616 .init_irq = htcherald_init_irq,
diff --git a/arch/arm/mach-omap1/board-innovator.c b/arch/arm/mach-omap1/board-innovator.c
index e603e5eb32a8..c2234caf8a7a 100644
--- a/arch/arm/mach-omap1/board-innovator.c
+++ b/arch/arm/mach-omap1/board-innovator.c
@@ -458,7 +458,7 @@ static void __init innovator_map_io(void)
458 458
459MACHINE_START(OMAP_INNOVATOR, "TI-Innovator") 459MACHINE_START(OMAP_INNOVATOR, "TI-Innovator")
460 /* Maintainer: MontaVista Software, Inc. */ 460 /* Maintainer: MontaVista Software, Inc. */
461 .boot_params = 0x10000100, 461 .atag_offset = 0x100,
462 .map_io = innovator_map_io, 462 .map_io = innovator_map_io,
463 .reserve = omap_reserve, 463 .reserve = omap_reserve,
464 .init_irq = innovator_init_irq, 464 .init_irq = innovator_init_irq,
diff --git a/arch/arm/mach-omap1/board-nokia770.c b/arch/arm/mach-omap1/board-nokia770.c
index 8420535fe51d..02789c5d3703 100644
--- a/arch/arm/mach-omap1/board-nokia770.c
+++ b/arch/arm/mach-omap1/board-nokia770.c
@@ -263,7 +263,7 @@ static void __init omap_nokia770_map_io(void)
263} 263}
264 264
265MACHINE_START(NOKIA770, "Nokia 770") 265MACHINE_START(NOKIA770, "Nokia 770")
266 .boot_params = 0x10000100, 266 .atag_offset = 0x100,
267 .map_io = omap_nokia770_map_io, 267 .map_io = omap_nokia770_map_io,
268 .reserve = omap_reserve, 268 .reserve = omap_reserve,
269 .init_irq = omap_nokia770_init_irq, 269 .init_irq = omap_nokia770_init_irq,
diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
index bf1ebe5b2442..e4dca1deebb4 100644
--- a/arch/arm/mach-omap1/board-osk.c
+++ b/arch/arm/mach-omap1/board-osk.c
@@ -582,7 +582,7 @@ static void __init osk_map_io(void)
582 582
583MACHINE_START(OMAP_OSK, "TI-OSK") 583MACHINE_START(OMAP_OSK, "TI-OSK")
584 /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */ 584 /* Maintainer: Dirk Behme <dirk.behme@de.bosch.com> */
585 .boot_params = 0x10000100, 585 .atag_offset = 0x100,
586 .map_io = osk_map_io, 586 .map_io = osk_map_io,
587 .reserve = omap_reserve, 587 .reserve = omap_reserve,
588 .init_irq = osk_init_irq, 588 .init_irq = osk_init_irq,
diff --git a/arch/arm/mach-omap1/board-palmte.c b/arch/arm/mach-omap1/board-palmte.c
index 45596b5acf09..50c4e398bcc8 100644
--- a/arch/arm/mach-omap1/board-palmte.c
+++ b/arch/arm/mach-omap1/board-palmte.c
@@ -274,7 +274,7 @@ static void __init omap_palmte_map_io(void)
274} 274}
275 275
276MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E") 276MACHINE_START(OMAP_PALMTE, "OMAP310 based Palm Tungsten E")
277 .boot_params = 0x10000100, 277 .atag_offset = 0x100,
278 .map_io = omap_palmte_map_io, 278 .map_io = omap_palmte_map_io,
279 .reserve = omap_reserve, 279 .reserve = omap_reserve,
280 .init_irq = omap_palmte_init_irq, 280 .init_irq = omap_palmte_init_irq,
diff --git a/arch/arm/mach-omap1/board-palmtt.c b/arch/arm/mach-omap1/board-palmtt.c
index f942221f6e71..273771cb1b61 100644
--- a/arch/arm/mach-omap1/board-palmtt.c
+++ b/arch/arm/mach-omap1/board-palmtt.c
@@ -321,7 +321,7 @@ static void __init omap_palmtt_map_io(void)
321} 321}
322 322
323MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T") 323MACHINE_START(OMAP_PALMTT, "OMAP1510 based Palm Tungsten|T")
324 .boot_params = 0x10000100, 324 .atag_offset = 0x100,
325 .map_io = omap_palmtt_map_io, 325 .map_io = omap_palmtt_map_io,
326 .reserve = omap_reserve, 326 .reserve = omap_reserve,
327 .init_irq = omap_palmtt_init_irq, 327 .init_irq = omap_palmtt_init_irq,
diff --git a/arch/arm/mach-omap1/board-palmz71.c b/arch/arm/mach-omap1/board-palmz71.c
index 2b912d46ceec..de36ade38ef7 100644
--- a/arch/arm/mach-omap1/board-palmz71.c
+++ b/arch/arm/mach-omap1/board-palmz71.c
@@ -341,7 +341,7 @@ omap_palmz71_map_io(void)
341} 341}
342 342
343MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71") 343MACHINE_START(OMAP_PALMZ71, "OMAP310 based Palm Zire71")
344 .boot_params = 0x10000100, 344 .atag_offset = 0x100,
345 .map_io = omap_palmz71_map_io, 345 .map_io = omap_palmz71_map_io,
346 .reserve = omap_reserve, 346 .reserve = omap_reserve,
347 .init_irq = omap_palmz71_init_irq, 347 .init_irq = omap_palmz71_init_irq,
diff --git a/arch/arm/mach-omap1/board-perseus2.c b/arch/arm/mach-omap1/board-perseus2.c
index 7e2efe52cc35..04b1befaced6 100644
--- a/arch/arm/mach-omap1/board-perseus2.c
+++ b/arch/arm/mach-omap1/board-perseus2.c
@@ -349,7 +349,7 @@ static void __init omap_perseus2_map_io(void)
349 349
350MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2") 350MACHINE_START(OMAP_PERSEUS2, "OMAP730 Perseus2")
351 /* Maintainer: Kevin Hilman <kjh@hilman.org> */ 351 /* Maintainer: Kevin Hilman <kjh@hilman.org> */
352 .boot_params = 0x10000100, 352 .atag_offset = 0x100,
353 .map_io = omap_perseus2_map_io, 353 .map_io = omap_perseus2_map_io,
354 .reserve = omap_reserve, 354 .reserve = omap_reserve,
355 .init_irq = omap_perseus2_init_irq, 355 .init_irq = omap_perseus2_init_irq,
diff --git a/arch/arm/mach-omap1/board-sx1.c b/arch/arm/mach-omap1/board-sx1.c
index 172a28f9a344..2bea941741d5 100644
--- a/arch/arm/mach-omap1/board-sx1.c
+++ b/arch/arm/mach-omap1/board-sx1.c
@@ -420,7 +420,7 @@ static void __init omap_sx1_map_io(void)
420} 420}
421 421
422MACHINE_START(SX1, "OMAP310 based Siemens SX1") 422MACHINE_START(SX1, "OMAP310 based Siemens SX1")
423 .boot_params = 0x10000100, 423 .atag_offset = 0x100,
424 .map_io = omap_sx1_map_io, 424 .map_io = omap_sx1_map_io,
425 .reserve = omap_reserve, 425 .reserve = omap_reserve,
426 .init_irq = omap_sx1_init_irq, 426 .init_irq = omap_sx1_init_irq,
diff --git a/arch/arm/mach-omap1/board-voiceblue.c b/arch/arm/mach-omap1/board-voiceblue.c
index 236b7ded0cf8..940faed82be2 100644
--- a/arch/arm/mach-omap1/board-voiceblue.c
+++ b/arch/arm/mach-omap1/board-voiceblue.c
@@ -301,7 +301,7 @@ static void __init voiceblue_init(void)
301 301
302MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910") 302MACHINE_START(VOICEBLUE, "VoiceBlue OMAP5910")
303 /* Maintainer: Ladislav Michl <michl@2n.cz> */ 303 /* Maintainer: Ladislav Michl <michl@2n.cz> */
304 .boot_params = 0x10000100, 304 .atag_offset = 0x100,
305 .map_io = voiceblue_map_io, 305 .map_io = voiceblue_map_io,
306 .reserve = omap_reserve, 306 .reserve = omap_reserve,
307 .init_irq = voiceblue_init_irq, 307 .init_irq = voiceblue_init_irq,
diff --git a/arch/arm/mach-omap1/include/mach/debug-macro.S b/arch/arm/mach-omap1/include/mach/debug-macro.S
index 62856044eb63..2b36a281dc84 100644
--- a/arch/arm/mach-omap1/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap1/include/mach/debug-macro.S
@@ -13,13 +13,8 @@
13 13
14#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
15 15
16#include <asm/memory.h>
17
18#include <plat/serial.h> 16#include <plat/serial.h>
19 17
20#define omap_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
21#define omap_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET)
22
23 .pushsection .data 18 .pushsection .data
24omap_uart_phys: .word 0x0 19omap_uart_phys: .word 0x0
25omap_uart_virt: .word 0x0 20omap_uart_virt: .word 0x0
@@ -31,26 +26,24 @@ omap_uart_virt: .word 0x0
31 * the desired UART phys and virt addresses temporarily into 26 * the desired UART phys and virt addresses temporarily into
32 * the omap_uart_phys and omap_uart_virt above. 27 * the omap_uart_phys and omap_uart_virt above.
33 */ 28 */
34 .macro addruart, rp, rv 29 .macro addruart, rp, rv, tmp
35 30
36 /* Use omap_uart_phys/virt if already configured */ 31 /* Use omap_uart_phys/virt if already configured */
379: mrc p15, 0, \rp, c1, c0 329: adr \rp, 99f @ get effective addr of 99f
38 tst \rp, #1 @ MMU enabled? 33 ldr \rv, [\rp] @ get absolute addr of 99f
39 ldreq \rp, =omap_uart_v2p(omap_uart_phys) @ MMU disabled 34 sub \rv, \rv, \rp @ offset between the two
40 ldrne \rp, =omap_uart_phys @ MMU enabled 35 ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
41 add \rv, \rp, #4 @ omap_uart_virt 36 sub \tmp, \rp, \rv @ make it effective
42 ldr \rp, [\rp, #0] 37 ldr \rp, [\tmp, #0] @ omap_uart_phys
43 ldr \rv, [\rv, #0] 38 ldr \rv, [\tmp, #4] @ omap_uart_virt
44 cmp \rp, #0 @ is port configured? 39 cmp \rp, #0 @ is port configured?
45 cmpne \rv, #0 40 cmpne \rv, #0
46 bne 99f @ already configured 41 bne 100f @ already configured
47 42
48 /* Check the debug UART configuration set in uncompress.h */ 43 /* Check the debug UART configuration set in uncompress.h */
49 mrc p15, 0, \rp, c1, c0 44 and \rp, pc, #0xff000000
50 tst \rp, #1 @ MMU enabled? 45 ldr \rv, =OMAP_UART_INFO_OFS
51 ldreq \rp, =OMAP_UART_INFO @ MMU not enabled 46 ldr \rp, [\rp, \rv]
52 ldrne \rp, =omap_uart_p2v(OMAP_UART_INFO) @ MMU enabled
53 ldr \rp, [\rp, #0]
54 47
55 /* Select the UART to use based on the UART1 scratchpad value */ 48 /* Select the UART to use based on the UART1 scratchpad value */
5610: cmp \rp, #0 @ no port configured? 4910: cmp \rp, #0 @ no port configured?
@@ -74,17 +67,18 @@ omap_uart_virt: .word 0x0
74 67
75 /* Store both phys and virt address for the uart */ 68 /* Store both phys and virt address for the uart */
7698: add \rp, \rp, #0xff000000 @ phys base 6998: add \rp, \rp, #0xff000000 @ phys base
77 mrc p15, 0, \rv, c1, c0 70 str \rp, [\tmp, #0] @ omap_uart_phys
78 tst \rv, #1 @ MMU enabled?
79 ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled
80 ldrne \rv, =omap_uart_phys @ MMU enabled
81 str \rp, [\rv, #0]
82 sub \rp, \rp, #0xff000000 @ phys base 71 sub \rp, \rp, #0xff000000 @ phys base
83 add \rp, \rp, #0xfe000000 @ virt base 72 add \rp, \rp, #0xfe000000 @ virt base
84 add \rv, \rv, #4 @ omap_uart_lsr 73 str \rp, [\tmp, #4] @ omap_uart_virt
85 str \rp, [\rv, #0]
86 b 9b 74 b 9b
8799: 75
76 .align
7799: .word .
78 .word omap_uart_phys
79 .ltorg
80
81100:
88 .endm 82 .endm
89 83
90 .macro senduart,rd,rx 84 .macro senduart,rd,rx
diff --git a/arch/arm/mach-omap1/include/mach/memory.h b/arch/arm/mach-omap1/include/mach/memory.h
index e9b600c113ef..c6337645ba8a 100644
--- a/arch/arm/mach-omap1/include/mach/memory.h
+++ b/arch/arm/mach-omap1/include/mach/memory.h
@@ -2,4 +2,55 @@
2 * arch/arm/mach-omap1/include/mach/memory.h 2 * arch/arm/mach-omap1/include/mach/memory.h
3 */ 3 */
4 4
5#include <plat/memory.h> 5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8/*
9 * Physical DRAM offset.
10 */
11#define PLAT_PHYS_OFFSET UL(0x10000000)
12
13/*
14 * Bus address is physical address, except for OMAP-1510 Local Bus.
15 * OMAP-1510 bus address is translated into a Local Bus address if the
16 * OMAP bus type is lbus. We do the address translation based on the
17 * device overriding the defaults used in the dma-mapping API.
18 * Note that the is_lbus_device() test is not very efficient on 1510
19 * because of the strncmp().
20 */
21#ifdef CONFIG_ARCH_OMAP15XX
22
23/*
24 * OMAP-1510 Local Bus address offset
25 */
26#define OMAP1510_LB_OFFSET UL(0x30000000)
27
28#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
29#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
30#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
31
32#define __arch_pfn_to_dma(dev, pfn) \
33 ({ dma_addr_t __dma = __pfn_to_phys(pfn); \
34 if (is_lbus_device(dev)) \
35 __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
36 __dma; })
37
38#define __arch_dma_to_pfn(dev, addr) \
39 ({ dma_addr_t __dma = addr; \
40 if (is_lbus_device(dev)) \
41 __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \
42 __phys_to_pfn(__dma); \
43 })
44
45#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
46 lbus_to_virt(addr) : \
47 __phys_to_virt(addr)); })
48
49#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
50 (dma_addr_t) (is_lbus_device(dev) ? \
51 virt_to_lbus(__addr) : \
52 __virt_to_phys(__addr)); })
53
54#endif /* CONFIG_ARCH_OMAP15XX */
55
56#endif
diff --git a/arch/arm/mach-omap1/io.c b/arch/arm/mach-omap1/io.c
index 870886a29594..1cfa1b6bb62b 100644
--- a/arch/arm/mach-omap1/io.c
+++ b/arch/arm/mach-omap1/io.c
@@ -121,6 +121,7 @@ void __init omap1_map_common_io(void)
121#endif 121#endif
122 122
123 omap_sram_init(); 123 omap_sram_init();
124 omap_init_consistent_dma_size();
124} 125}
125 126
126/* 127/*
diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c
index f79b7d2a8ed4..87f43ade4405 100644
--- a/arch/arm/mach-omap2/board-2430sdp.c
+++ b/arch/arm/mach-omap2/board-2430sdp.c
@@ -257,7 +257,7 @@ static void __init omap_2430sdp_map_io(void)
257 257
258MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board") 258MACHINE_START(OMAP_2430SDP, "OMAP2430 sdp2430 board")
259 /* Maintainer: Syed Khasim - Texas Instruments Inc */ 259 /* Maintainer: Syed Khasim - Texas Instruments Inc */
260 .boot_params = 0x80000100, 260 .atag_offset = 0x100,
261 .reserve = omap_reserve, 261 .reserve = omap_reserve,
262 .map_io = omap_2430sdp_map_io, 262 .map_io = omap_2430sdp_map_io,
263 .init_early = omap_2430sdp_init_early, 263 .init_early = omap_2430sdp_init_early,
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index bd600cfb7f80..2430531b2239 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -729,7 +729,7 @@ static void __init omap_3430sdp_init(void)
729 729
730MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board") 730MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
731 /* Maintainer: Syed Khasim - Texas Instruments Inc */ 731 /* Maintainer: Syed Khasim - Texas Instruments Inc */
732 .boot_params = 0x80000100, 732 .atag_offset = 0x100,
733 .reserve = omap_reserve, 733 .reserve = omap_reserve,
734 .map_io = omap3_map_io, 734 .map_io = omap3_map_io,
735 .init_early = omap_3430sdp_init_early, 735 .init_early = omap_3430sdp_init_early,
diff --git a/arch/arm/mach-omap2/board-3630sdp.c b/arch/arm/mach-omap2/board-3630sdp.c
index e4f37b57a0c4..8b5b5aa751ed 100644
--- a/arch/arm/mach-omap2/board-3630sdp.c
+++ b/arch/arm/mach-omap2/board-3630sdp.c
@@ -215,7 +215,7 @@ static void __init omap_sdp_init(void)
215} 215}
216 216
217MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board") 217MACHINE_START(OMAP_3630SDP, "OMAP 3630SDP board")
218 .boot_params = 0x80000100, 218 .atag_offset = 0x100,
219 .reserve = omap_reserve, 219 .reserve = omap_reserve,
220 .map_io = omap3_map_io, 220 .map_io = omap3_map_io,
221 .init_early = omap_sdp_init_early, 221 .init_early = omap_sdp_init_early,
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index c7cef44c75d4..be931105d681 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -838,7 +838,7 @@ static void __init omap_4430sdp_map_io(void)
838 838
839MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board") 839MACHINE_START(OMAP_4430SDP, "OMAP4430 4430SDP board")
840 /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */ 840 /* Maintainer: Santosh Shilimkar - Texas Instruments Inc */
841 .boot_params = 0x80000100, 841 .atag_offset = 0x100,
842 .reserve = omap_reserve, 842 .reserve = omap_reserve,
843 .map_io = omap_4430sdp_map_io, 843 .map_io = omap_4430sdp_map_io,
844 .init_early = omap_4430sdp_init_early, 844 .init_early = omap_4430sdp_init_early,
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 933e9353cb37..db110fdb8b2c 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -98,7 +98,7 @@ static void __init am3517_crane_init(void)
98} 98}
99 99
100MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD") 100MACHINE_START(CRANEBOARD, "AM3517/05 CRANEBOARD")
101 .boot_params = 0x80000100, 101 .atag_offset = 0x100,
102 .reserve = omap_reserve, 102 .reserve = omap_reserve,
103 .map_io = omap3_map_io, 103 .map_io = omap3_map_io,
104 .init_early = am3517_crane_init_early, 104 .init_early = am3517_crane_init_early,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index f3006c304150..1325085e453d 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -490,7 +490,7 @@ static void __init am3517_evm_init(void)
490} 490}
491 491
492MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM") 492MACHINE_START(OMAP3517EVM, "OMAP3517/AM3517 EVM")
493 .boot_params = 0x80000100, 493 .atag_offset = 0x100,
494 .reserve = omap_reserve, 494 .reserve = omap_reserve,
495 .map_io = omap3_map_io, 495 .map_io = omap3_map_io,
496 .init_early = am3517_evm_init_early, 496 .init_early = am3517_evm_init_early,
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 70211703ff9f..67800e647d7a 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -350,7 +350,7 @@ static void __init omap_apollon_map_io(void)
350 350
351MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon") 351MACHINE_START(OMAP_APOLLON, "OMAP24xx Apollon")
352 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */ 352 /* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
353 .boot_params = 0x80000100, 353 .atag_offset = 0x100,
354 .reserve = omap_reserve, 354 .reserve = omap_reserve,
355 .map_io = omap_apollon_map_io, 355 .map_io = omap_apollon_map_io,
356 .init_early = omap_apollon_init_early, 356 .init_early = omap_apollon_init_early,
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 3af8aab435b5..38179c175503 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -634,7 +634,7 @@ static void __init cm_t3730_init(void)
634} 634}
635 635
636MACHINE_START(CM_T35, "Compulab CM-T35") 636MACHINE_START(CM_T35, "Compulab CM-T35")
637 .boot_params = 0x80000100, 637 .atag_offset = 0x100,
638 .reserve = omap_reserve, 638 .reserve = omap_reserve,
639 .map_io = omap3_map_io, 639 .map_io = omap3_map_io,
640 .init_early = cm_t35_init_early, 640 .init_early = cm_t35_init_early,
@@ -644,7 +644,7 @@ MACHINE_START(CM_T35, "Compulab CM-T35")
644MACHINE_END 644MACHINE_END
645 645
646MACHINE_START(CM_T3730, "Compulab CM-T3730") 646MACHINE_START(CM_T3730, "Compulab CM-T3730")
647 .boot_params = 0x80000100, 647 .atag_offset = 0x100,
648 .reserve = omap_reserve, 648 .reserve = omap_reserve,
649 .map_io = omap3_map_io, 649 .map_io = omap3_map_io,
650 .init_early = cm_t35_init_early, 650 .init_early = cm_t35_init_early,
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 05c72f4c1b57..aed9c29f9fae 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -299,7 +299,7 @@ static void __init cm_t3517_init(void)
299} 299}
300 300
301MACHINE_START(CM_T3517, "Compulab CM-T3517") 301MACHINE_START(CM_T3517, "Compulab CM-T3517")
302 .boot_params = 0x80000100, 302 .atag_offset = 0x100,
303 .reserve = omap_reserve, 303 .reserve = omap_reserve,
304 .map_io = omap3_map_io, 304 .map_io = omap3_map_io,
305 .init_early = cm_t3517_init_early, 305 .init_early = cm_t3517_init_early,
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index b6002ec31c6a..99a42432ac93 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -667,7 +667,7 @@ static void __init devkit8000_init(void)
667} 667}
668 668
669MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000") 669MACHINE_START(DEVKIT8000, "OMAP3 Devkit8000")
670 .boot_params = 0x80000100, 670 .atag_offset = 0x100,
671 .reserve = omap_reserve, 671 .reserve = omap_reserve,
672 .map_io = omap3_map_io, 672 .map_io = omap3_map_io,
673 .init_early = devkit8000_init_early, 673 .init_early = devkit8000_init_early,
diff --git a/arch/arm/mach-omap2/board-generic.c b/arch/arm/mach-omap2/board-generic.c
index bb4af05c7f0a..4431ad364565 100644
--- a/arch/arm/mach-omap2/board-generic.c
+++ b/arch/arm/mach-omap2/board-generic.c
@@ -65,7 +65,7 @@ static void __init omap_generic_map_io(void)
65/* XXX This machine entry name should be updated */ 65/* XXX This machine entry name should be updated */
66MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx") 66MACHINE_START(OMAP_GENERIC, "Generic OMAP24xx")
67 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ 67 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
68 .boot_params = 0x80000100, 68 .atag_offset = 0x100,
69 .reserve = omap_reserve, 69 .reserve = omap_reserve,
70 .map_io = omap_generic_map_io, 70 .map_io = omap_generic_map_io,
71 .init_early = omap_generic_init_early, 71 .init_early = omap_generic_init_early,
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index 95319e761802..82421a4cfa92 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -381,7 +381,7 @@ static void __init omap_h4_map_io(void)
381 381
382MACHINE_START(OMAP_H4, "OMAP2420 H4 board") 382MACHINE_START(OMAP_H4, "OMAP2420 H4 board")
383 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */ 383 /* Maintainer: Paul Mundt <paul.mundt@nokia.com> */
384 .boot_params = 0x80000100, 384 .atag_offset = 0x100,
385 .reserve = omap_reserve, 385 .reserve = omap_reserve,
386 .map_io = omap_h4_map_io, 386 .map_io = omap_h4_map_io,
387 .init_early = omap_h4_init_early, 387 .init_early = omap_h4_init_early,
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 35be778caf1b..7040352b16b4 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -672,7 +672,7 @@ static void __init igep_init(void)
672} 672}
673 673
674MACHINE_START(IGEP0020, "IGEP v2 board") 674MACHINE_START(IGEP0020, "IGEP v2 board")
675 .boot_params = 0x80000100, 675 .atag_offset = 0x100,
676 .reserve = omap_reserve, 676 .reserve = omap_reserve,
677 .map_io = omap3_map_io, 677 .map_io = omap3_map_io,
678 .init_early = igep_init_early, 678 .init_early = igep_init_early,
@@ -682,7 +682,7 @@ MACHINE_START(IGEP0020, "IGEP v2 board")
682MACHINE_END 682MACHINE_END
683 683
684MACHINE_START(IGEP0030, "IGEP OMAP3 module") 684MACHINE_START(IGEP0030, "IGEP OMAP3 module")
685 .boot_params = 0x80000100, 685 .atag_offset = 0x100,
686 .reserve = omap_reserve, 686 .reserve = omap_reserve,
687 .map_io = omap3_map_io, 687 .map_io = omap3_map_io,
688 .init_early = igep_init_early, 688 .init_early = igep_init_early,
diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c
index ddff45c1688c..abe8c7e496a2 100644
--- a/arch/arm/mach-omap2/board-ldp.c
+++ b/arch/arm/mach-omap2/board-ldp.c
@@ -332,7 +332,7 @@ static void __init omap_ldp_init(void)
332} 332}
333 333
334MACHINE_START(OMAP_LDP, "OMAP LDP board") 334MACHINE_START(OMAP_LDP, "OMAP LDP board")
335 .boot_params = 0x80000100, 335 .atag_offset = 0x100,
336 .reserve = omap_reserve, 336 .reserve = omap_reserve,
337 .map_io = omap3_map_io, 337 .map_io = omap3_map_io,
338 .init_early = omap_ldp_init_early, 338 .init_early = omap_ldp_init_early,
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index e11f0c5d608a..6ce748154f24 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -695,7 +695,7 @@ static void __init n8x0_init_machine(void)
695} 695}
696 696
697MACHINE_START(NOKIA_N800, "Nokia N800") 697MACHINE_START(NOKIA_N800, "Nokia N800")
698 .boot_params = 0x80000100, 698 .atag_offset = 0x100,
699 .reserve = omap_reserve, 699 .reserve = omap_reserve,
700 .map_io = n8x0_map_io, 700 .map_io = n8x0_map_io,
701 .init_early = n8x0_init_early, 701 .init_early = n8x0_init_early,
@@ -705,7 +705,7 @@ MACHINE_START(NOKIA_N800, "Nokia N800")
705MACHINE_END 705MACHINE_END
706 706
707MACHINE_START(NOKIA_N810, "Nokia N810") 707MACHINE_START(NOKIA_N810, "Nokia N810")
708 .boot_params = 0x80000100, 708 .atag_offset = 0x100,
709 .reserve = omap_reserve, 709 .reserve = omap_reserve,
710 .map_io = n8x0_map_io, 710 .map_io = n8x0_map_io,
711 .init_early = n8x0_init_early, 711 .init_early = n8x0_init_early,
@@ -715,7 +715,7 @@ MACHINE_START(NOKIA_N810, "Nokia N810")
715MACHINE_END 715MACHINE_END
716 716
717MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX") 717MACHINE_START(NOKIA_N810_WIMAX, "Nokia N810 WiMAX")
718 .boot_params = 0x80000100, 718 .atag_offset = 0x100,
719 .reserve = omap_reserve, 719 .reserve = omap_reserve,
720 .map_io = n8x0_map_io, 720 .map_io = n8x0_map_io,
721 .init_early = n8x0_init_early, 721 .init_early = n8x0_init_early,
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 3ae16b4e3f52..1fde8a0474bb 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -557,7 +557,7 @@ static void __init omap3_beagle_init(void)
557 557
558MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board") 558MACHINE_START(OMAP3_BEAGLE, "OMAP3 Beagle Board")
559 /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */ 559 /* Maintainer: Syed Mohammed Khasim - http://beagleboard.org */
560 .boot_params = 0x80000100, 560 .atag_offset = 0x100,
561 .reserve = omap_reserve, 561 .reserve = omap_reserve,
562 .map_io = omap3_map_io, 562 .map_io = omap3_map_io,
563 .init_early = omap3_beagle_init_early, 563 .init_early = omap3_beagle_init_early,
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index c452b3f3331a..15c69a0c1ce5 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -681,7 +681,7 @@ static void __init omap3_evm_init(void)
681 681
682MACHINE_START(OMAP3EVM, "OMAP3 EVM") 682MACHINE_START(OMAP3EVM, "OMAP3 EVM")
683 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */ 683 /* Maintainer: Syed Mohammed Khasim - Texas Instruments */
684 .boot_params = 0x80000100, 684 .atag_offset = 0x100,
685 .reserve = omap_reserve, 685 .reserve = omap_reserve,
686 .map_io = omap3_map_io, 686 .map_io = omap3_map_io,
687 .init_early = omap3_evm_init_early, 687 .init_early = omap3_evm_init_early,
diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c
index 703aeb5b8fd4..01354a214caf 100644
--- a/arch/arm/mach-omap2/board-omap3logic.c
+++ b/arch/arm/mach-omap2/board-omap3logic.c
@@ -209,7 +209,7 @@ static void __init omap3logic_init(void)
209} 209}
210 210
211MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board") 211MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
212 .boot_params = 0x80000100, 212 .atag_offset = 0x100,
213 .map_io = omap3_map_io, 213 .map_io = omap3_map_io,
214 .init_early = omap3logic_init_early, 214 .init_early = omap3logic_init_early,
215 .init_irq = omap3_init_irq, 215 .init_irq = omap3_init_irq,
@@ -218,7 +218,7 @@ MACHINE_START(OMAP3_TORPEDO, "Logic OMAP3 Torpedo board")
218MACHINE_END 218MACHINE_END
219 219
220MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board") 220MACHINE_START(OMAP3530_LV_SOM, "OMAP Logic 3530 LV SOM board")
221 .boot_params = 0x80000100, 221 .atag_offset = 0x100,
222 .map_io = omap3_map_io, 222 .map_io = omap3_map_io,
223 .init_early = omap3logic_init_early, 223 .init_early = omap3logic_init_early,
224 .init_irq = omap3_init_irq, 224 .init_irq = omap3_init_irq,
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 080d7bd6795e..ace56938dd3b 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -606,7 +606,7 @@ static void __init omap3pandora_init(void)
606} 606}
607 607
608MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console") 608MACHINE_START(OMAP3_PANDORA, "Pandora Handheld Console")
609 .boot_params = 0x80000100, 609 .atag_offset = 0x100,
610 .reserve = omap_reserve, 610 .reserve = omap_reserve,
611 .map_io = omap3_map_io, 611 .map_io = omap3_map_io,
612 .init_early = omap3pandora_init_early, 612 .init_early = omap3pandora_init_early,
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index 8e104980ea26..ba13e1d5d0ab 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -494,7 +494,7 @@ static void __init omap3_stalker_init(void)
494 494
495MACHINE_START(SBC3530, "OMAP3 STALKER") 495MACHINE_START(SBC3530, "OMAP3 STALKER")
496 /* Maintainer: Jason Lam -lzg@ema-tech.com */ 496 /* Maintainer: Jason Lam -lzg@ema-tech.com */
497 .boot_params = 0x80000100, 497 .atag_offset = 0x100,
498 .map_io = omap3_map_io, 498 .map_io = omap3_map_io,
499 .init_early = omap3_stalker_init_early, 499 .init_early = omap3_stalker_init_early,
500 .init_irq = omap3_stalker_init_irq, 500 .init_irq = omap3_stalker_init_irq,
diff --git a/arch/arm/mach-omap2/board-omap3touchbook.c b/arch/arm/mach-omap2/board-omap3touchbook.c
index 852ea0464057..49e4bd207cb6 100644
--- a/arch/arm/mach-omap2/board-omap3touchbook.c
+++ b/arch/arm/mach-omap2/board-omap3touchbook.c
@@ -404,7 +404,7 @@ static void __init omap3_touchbook_init(void)
404 404
405MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board") 405MACHINE_START(TOUCHBOOK, "OMAP3 touchbook Board")
406 /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */ 406 /* Maintainer: Gregoire Gentil - http://www.alwaysinnovating.com */
407 .boot_params = 0x80000100, 407 .atag_offset = 0x100,
408 .reserve = omap_reserve, 408 .reserve = omap_reserve,
409 .map_io = omap3_map_io, 409 .map_io = omap3_map_io,
410 .init_early = omap3_touchbook_init_early, 410 .init_early = omap3_touchbook_init_early,
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index 9aaa96057666..683bede73d54 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -583,7 +583,7 @@ static void __init omap4_panda_map_io(void)
583 583
584MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board") 584MACHINE_START(OMAP4_PANDA, "OMAP4 Panda board")
585 /* Maintainer: David Anders - Texas Instruments Inc */ 585 /* Maintainer: David Anders - Texas Instruments Inc */
586 .boot_params = 0x80000100, 586 .atag_offset = 0x100,
587 .reserve = omap_reserve, 587 .reserve = omap_reserve,
588 .map_io = omap4_panda_map_io, 588 .map_io = omap4_panda_map_io,
589 .init_early = omap4_panda_init_early, 589 .init_early = omap4_panda_init_early,
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index f949a9954d76..e592fb134c4e 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -561,7 +561,7 @@ static void __init overo_init(void)
561} 561}
562 562
563MACHINE_START(OVERO, "Gumstix Overo") 563MACHINE_START(OVERO, "Gumstix Overo")
564 .boot_params = 0x80000100, 564 .atag_offset = 0x100,
565 .reserve = omap_reserve, 565 .reserve = omap_reserve,
566 .map_io = omap3_map_io, 566 .map_io = omap3_map_io,
567 .init_early = overo_init_early, 567 .init_early = overo_init_early,
diff --git a/arch/arm/mach-omap2/board-rm680.c b/arch/arm/mach-omap2/board-rm680.c
index 7dfed24ee12e..9a8ce239ba9e 100644
--- a/arch/arm/mach-omap2/board-rm680.c
+++ b/arch/arm/mach-omap2/board-rm680.c
@@ -153,7 +153,7 @@ static void __init rm680_map_io(void)
153} 153}
154 154
155MACHINE_START(NOKIA_RM680, "Nokia RM-680 board") 155MACHINE_START(NOKIA_RM680, "Nokia RM-680 board")
156 .boot_params = 0x80000100, 156 .atag_offset = 0x100,
157 .reserve = omap_reserve, 157 .reserve = omap_reserve,
158 .map_io = rm680_map_io, 158 .map_io = rm680_map_io,
159 .init_early = rm680_init_early, 159 .init_early = rm680_init_early,
diff --git a/arch/arm/mach-omap2/board-rx51.c b/arch/arm/mach-omap2/board-rx51.c
index 5ea142f9bc97..a6c473bbb3d6 100644
--- a/arch/arm/mach-omap2/board-rx51.c
+++ b/arch/arm/mach-omap2/board-rx51.c
@@ -156,7 +156,7 @@ static void __init rx51_reserve(void)
156 156
157MACHINE_START(NOKIA_RX51, "Nokia RX-51 board") 157MACHINE_START(NOKIA_RX51, "Nokia RX-51 board")
158 /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */ 158 /* Maintainer: Lauri Leukkunen <lauri.leukkunen@nokia.com> */
159 .boot_params = 0x80000100, 159 .atag_offset = 0x100,
160 .reserve = rx51_reserve, 160 .reserve = rx51_reserve,
161 .map_io = rx51_map_io, 161 .map_io = rx51_map_io,
162 .init_early = rx51_init_early, 162 .init_early = rx51_init_early,
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
index a85d5b0b11da..e41958acb6b6 100644
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ b/arch/arm/mach-omap2/board-ti8168evm.c
@@ -48,7 +48,7 @@ static void __init ti8168_evm_map_io(void)
48 48
49MACHINE_START(TI8168EVM, "ti8168evm") 49MACHINE_START(TI8168EVM, "ti8168evm")
50 /* Maintainer: Texas Instruments */ 50 /* Maintainer: Texas Instruments */
51 .boot_params = 0x80000100, 51 .atag_offset = 0x100,
52 .map_io = ti8168_evm_map_io, 52 .map_io = ti8168_evm_map_io,
53 .init_early = ti8168_init_early, 53 .init_early = ti8168_init_early,
54 .init_irq = ti816x_init_irq, 54 .init_irq = ti816x_init_irq,
diff --git a/arch/arm/mach-omap2/board-zoom.c b/arch/arm/mach-omap2/board-zoom.c
index 8a98c3c303fc..72f1db4863e5 100644
--- a/arch/arm/mach-omap2/board-zoom.c
+++ b/arch/arm/mach-omap2/board-zoom.c
@@ -133,7 +133,7 @@ static void __init omap_zoom_init(void)
133} 133}
134 134
135MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board") 135MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
136 .boot_params = 0x80000100, 136 .atag_offset = 0x100,
137 .reserve = omap_reserve, 137 .reserve = omap_reserve,
138 .map_io = omap3_map_io, 138 .map_io = omap3_map_io,
139 .init_early = omap_zoom_init_early, 139 .init_early = omap_zoom_init_early,
@@ -143,7 +143,7 @@ MACHINE_START(OMAP_ZOOM2, "OMAP Zoom2 board")
143MACHINE_END 143MACHINE_END
144 144
145MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board") 145MACHINE_START(OMAP_ZOOM3, "OMAP Zoom3 board")
146 .boot_params = 0x80000100, 146 .atag_offset = 0x100,
147 .reserve = omap_reserve, 147 .reserve = omap_reserve,
148 .map_io = omap3_map_io, 148 .map_io = omap3_map_io,
149 .init_early = omap_zoom_init_early, 149 .init_early = omap_zoom_init_early,
diff --git a/arch/arm/mach-omap2/include/mach/debug-macro.S b/arch/arm/mach-omap2/include/mach/debug-macro.S
index 48adfe9fe4f3..13f98e59cfef 100644
--- a/arch/arm/mach-omap2/include/mach/debug-macro.S
+++ b/arch/arm/mach-omap2/include/mach/debug-macro.S
@@ -13,15 +13,10 @@
13 13
14#include <linux/serial_reg.h> 14#include <linux/serial_reg.h>
15 15
16#include <asm/memory.h>
17
18#include <plat/serial.h> 16#include <plat/serial.h>
19 17
20#define UART_OFFSET(addr) ((addr) & 0x00ffffff) 18#define UART_OFFSET(addr) ((addr) & 0x00ffffff)
21 19
22#define omap_uart_v2p(x) ((x) - PAGE_OFFSET + PLAT_PHYS_OFFSET)
23#define omap_uart_p2v(x) ((x) - PLAT_PHYS_OFFSET + PAGE_OFFSET)
24
25 .pushsection .data 20 .pushsection .data
26omap_uart_phys: .word 0 21omap_uart_phys: .word 0
27omap_uart_virt: .word 0 22omap_uart_virt: .word 0
@@ -34,26 +29,25 @@ omap_uart_lsr: .word 0
34 * the desired UART phys and virt addresses temporarily into 29 * the desired UART phys and virt addresses temporarily into
35 * the omap_uart_phys and omap_uart_virt above. 30 * the omap_uart_phys and omap_uart_virt above.
36 */ 31 */
37 .macro addruart, rp, rv 32 .macro addruart, rp, rv, tmp
38 33
39 /* Use omap_uart_phys/virt if already configured */ 34 /* Use omap_uart_phys/virt if already configured */
4010: mrc p15, 0, \rp, c1, c0 3510: adr \rp, 99f @ get effective addr of 99f
41 tst \rp, #1 @ MMU enabled? 36 ldr \rv, [\rp] @ get absolute addr of 99f
42 ldreq \rp, =omap_uart_v2p(omap_uart_phys) @ MMU disabled 37 sub \rv, \rv, \rp @ offset between the two
43 ldrne \rp, =omap_uart_phys @ MMU enabled 38 ldr \rp, [\rp, #4] @ abs addr of omap_uart_phys
44 add \rv, \rp, #4 @ omap_uart_virt 39 sub \tmp, \rp, \rv @ make it effective
45 ldr \rp, [\rp, #0] 40 ldr \rp, [\tmp, #0] @ omap_uart_phys
46 ldr \rv, [\rv, #0] 41 ldr \rv, [\tmp, #4] @ omap_uart_virt
47 cmp \rp, #0 @ is port configured? 42 cmp \rp, #0 @ is port configured?
48 cmpne \rv, #0 43 cmpne \rv, #0
49 bne 99f @ already configured 44 bne 100f @ already configured
50 45
51 /* Check the debug UART configuration set in uncompress.h */ 46 /* Check the debug UART configuration set in uncompress.h */
52 mrc p15, 0, \rp, c1, c0 47 mov \rp, pc
53 tst \rp, #1 @ MMU enabled? 48 ldr \rv, =OMAP_UART_INFO_OFS
54 ldreq \rp, =OMAP_UART_INFO @ MMU not enabled 49 and \rp, \rp, #0xff000000
55 ldrne \rp, =omap_uart_p2v(OMAP_UART_INFO) @ MMU enabled 50 ldr \rp, [\rp, \rv]
56 ldr \rp, [\rp, #0]
57 51
58 /* Select the UART to use based on the UART1 scratchpad value */ 52 /* Select the UART to use based on the UART1 scratchpad value */
59 cmp \rp, #0 @ no port configured? 53 cmp \rp, #0 @ no port configured?
@@ -106,50 +100,47 @@ omap_uart_lsr: .word 0
106 b 98f 100 b 98f
10783: mov \rp, #UART_OFFSET(TI816X_UART3_BASE) 10183: mov \rp, #UART_OFFSET(TI816X_UART3_BASE)
108 b 98f 102 b 98f
103
10995: ldr \rp, =ZOOM_UART_BASE 10495: ldr \rp, =ZOOM_UART_BASE
110 mrc p15, 0, \rv, c1, c0 105 str \rp, [\tmp, #0] @ omap_uart_phys
111 tst \rv, #1 @ MMU enabled?
112 ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled
113 ldrne \rv, =omap_uart_phys @ MMU enabled
114 str \rp, [\rv, #0]
115 ldr \rp, =ZOOM_UART_VIRT 106 ldr \rp, =ZOOM_UART_VIRT
116 add \rv, \rv, #4 @ omap_uart_virt 107 str \rp, [\tmp, #4] @ omap_uart_virt
117 str \rp, [\rv, #0]
118 mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT) 108 mov \rp, #(UART_LSR << ZOOM_PORT_SHIFT)
119 add \rv, \rv, #4 @ omap_uart_lsr 109 str \rp, [\tmp, #8] @ omap_uart_lsr
120 str \rp, [\rv, #0]
121 b 10b 110 b 10b
122 111
123 /* Store both phys and virt address for the uart */ 112 /* Store both phys and virt address for the uart */
12498: add \rp, \rp, #0x48000000 @ phys base 11398: add \rp, \rp, #0x48000000 @ phys base
125 mrc p15, 0, \rv, c1, c0 114 str \rp, [\tmp, #0] @ omap_uart_phys
126 tst \rv, #1 @ MMU enabled?
127 ldreq \rv, =omap_uart_v2p(omap_uart_phys) @ MMU disabled
128 ldrne \rv, =omap_uart_phys @ MMU enabled
129 str \rp, [\rv, #0]
130 sub \rp, \rp, #0x48000000 @ phys base 115 sub \rp, \rp, #0x48000000 @ phys base
131 add \rp, \rp, #0xfa000000 @ virt base 116 add \rp, \rp, #0xfa000000 @ virt base
132 add \rv, \rv, #4 @ omap_uart_virt 117 str \rp, [\tmp, #4] @ omap_uart_virt
133 str \rp, [\rv, #0]
134 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT) 118 mov \rp, #(UART_LSR << OMAP_PORT_SHIFT)
135 add \rv, \rv, #4 @ omap_uart_lsr 119 str \rp, [\tmp, #8] @ omap_uart_lsr
136 str \rp, [\rv, #0]
137 120
138 b 10b 121 b 10b
13999: 122
123 .align
12499: .word .
125 .word omap_uart_phys
126 .ltorg
127
128100: /* Pass the UART_LSR reg address */
129 ldr \tmp, [\tmp, #8] @ omap_uart_lsr
130 add \rp, \rp, \tmp
131 add \rv, \rv, \tmp
140 .endm 132 .endm
141 133
142 .macro senduart,rd,rx 134 .macro senduart,rd,rx
143 strb \rd, [\rx] 135 orr \rd, \rd, \rx, lsl #24 @ preserve LSR reg offset
136 bic \rx, \rx, #0xff @ get base (THR) reg address
137 strb \rd, [\rx] @ send lower byte of rd
138 orr \rx, \rx, \rd, lsr #24 @ restore original rx (LSR)
139 bic \rd, \rd, #(0xff << 24) @ restore original rd
144 .endm 140 .endm
145 141
146 .macro busyuart,rd,rx 142 .macro busyuart,rd,rx
1471001: mrc p15, 0, \rd, c1, c0 1431001: ldrb \rd, [\rx] @ rx contains UART_LSR address
148 tst \rd, #1 @ MMU enabled?
149 ldreq \rd, =omap_uart_v2p(omap_uart_lsr) @ MMU disabled
150 ldrne \rd, =omap_uart_lsr @ MMU enabled
151 ldr \rd, [\rd, #0]
152 ldrb \rd, [\rx, \rd]
153 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE) 144 and \rd, \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
154 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE) 145 teq \rd, #(UART_LSR_TEMT | UART_LSR_THRE)
155 bne 1001b 146 bne 1001b
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S
index ceb8b7e593d7..feb90a10945a 100644
--- a/arch/arm/mach-omap2/include/mach/entry-macro.S
+++ b/arch/arm/mach-omap2/include/mach/entry-macro.S
@@ -78,7 +78,7 @@
784401: ldr \irqstat, [\base, #GIC_CPU_INTACK] 784401: ldr \irqstat, [\base, #GIC_CPU_INTACK]
79 ldr \tmp, =1021 79 ldr \tmp, =1021
80 bic \irqnr, \irqstat, #0x1c00 80 bic \irqnr, \irqstat, #0x1c00
81 cmp \irqnr, #29 81 cmp \irqnr, #15
82 cmpcc \irqnr, \irqnr 82 cmpcc \irqnr, \irqnr
83 cmpne \irqnr, \tmp 83 cmpne \irqnr, \tmp
84 cmpcs \irqnr, \irqnr 84 cmpcs \irqnr, \irqnr
@@ -101,18 +101,6 @@
101 it cs 101 it cs
102 cmpcs \irqnr, \irqnr 102 cmpcs \irqnr, \irqnr
103 .endm 103 .endm
104
105 /* As above, this assumes that irqstat and base are preserved */
106
107 .macro test_for_ltirq, irqnr, irqstat, base, tmp
108 bic \irqnr, \irqstat, #0x1c00
109 mov \tmp, #0
110 cmp \irqnr, #29
111 itt eq
112 moveq \tmp, #1
113 streq \irqstat, [\base, #GIC_CPU_EOI]
114 cmp \tmp, #0
115 .endm
116#endif /* CONFIG_SMP */ 104#endif /* CONFIG_SMP */
117 105
118#else /* MULTI_OMAP2 */ 106#else /* MULTI_OMAP2 */
diff --git a/arch/arm/mach-omap2/include/mach/memory.h b/arch/arm/mach-omap2/include/mach/memory.h
deleted file mode 100644
index ca6d32a917dd..000000000000
--- a/arch/arm/mach-omap2/include/mach/memory.h
+++ /dev/null
@@ -1,5 +0,0 @@
1/*
2 * arch/arm/mach-omap2/include/mach/memory.h
3 */
4
5#include <plat/memory.h>
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 2ce1ce6fb4db..d6d01cb7f28a 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -16,7 +16,6 @@
16 * it under the terms of the GNU General Public License version 2 as 16 * it under the terms of the GNU General Public License version 2 as
17 * published by the Free Software Foundation. 17 * published by the Free Software Foundation.
18 */ 18 */
19
20#include <linux/module.h> 19#include <linux/module.h>
21#include <linux/kernel.h> 20#include <linux/kernel.h>
22#include <linux/init.h> 21#include <linux/init.h>
@@ -250,6 +249,7 @@ static void __init _omap2_map_common_io(void)
250 249
251 omap2_check_revision(); 250 omap2_check_revision();
252 omap_sram_init(); 251 omap_sram_init();
252 omap_init_consistent_dma_size();
253} 253}
254 254
255#ifdef CONFIG_SOC_OMAP2420 255#ifdef CONFIG_SOC_OMAP2420
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 19cf5bf99f1b..8c8300951f46 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -336,7 +336,7 @@ static void __init d2net_init(void)
336 336
337#ifdef CONFIG_MACH_D2NET 337#ifdef CONFIG_MACH_D2NET
338MACHINE_START(D2NET, "LaCie d2 Network") 338MACHINE_START(D2NET, "LaCie d2 Network")
339 .boot_params = 0x00000100, 339 .atag_offset = 0x100,
340 .init_machine = d2net_init, 340 .init_machine = d2net_init,
341 .map_io = orion5x_map_io, 341 .map_io = orion5x_map_io,
342 .init_early = orion5x_init_early, 342 .init_early = orion5x_init_early,
@@ -348,7 +348,7 @@ MACHINE_END
348 348
349#ifdef CONFIG_MACH_BIGDISK 349#ifdef CONFIG_MACH_BIGDISK
350MACHINE_START(BIGDISK, "LaCie Big Disk Network") 350MACHINE_START(BIGDISK, "LaCie Big Disk Network")
351 .boot_params = 0x00000100, 351 .atag_offset = 0x100,
352 .init_machine = d2net_init, 352 .init_machine = d2net_init,
353 .map_io = orion5x_map_io, 353 .map_io = orion5x_map_io,
354 .init_early = orion5x_init_early, 354 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index 6d771cbf06a4..4b79a80d5e1f 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -358,7 +358,7 @@ static void __init db88f5281_init(void)
358 358
359MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board") 359MACHINE_START(DB88F5281, "Marvell Orion-2 Development Board")
360 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */ 360 /* Maintainer: Tzachi Perelstein <tzachi@marvell.com> */
361 .boot_params = 0x00000100, 361 .atag_offset = 0x100,
362 .init_machine = db88f5281_init, 362 .init_machine = db88f5281_init,
363 .map_io = orion5x_map_io, 363 .map_io = orion5x_map_io,
364 .init_early = orion5x_init_early, 364 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 6fb4908e998b..343f60e9639f 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -729,7 +729,7 @@ static void __init dns323_init(void)
729/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */ 729/* Warning: D-Link uses a wrong mach-type (=526) in their bootloader */
730MACHINE_START(DNS323, "D-Link DNS-323") 730MACHINE_START(DNS323, "D-Link DNS-323")
731 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */ 731 /* Maintainer: Herbert Valerio Riedel <hvr@gnu.org> */
732 .boot_params = 0x00000100, 732 .atag_offset = 0x100,
733 .init_machine = dns323_init, 733 .init_machine = dns323_init,
734 .map_io = orion5x_map_io, 734 .map_io = orion5x_map_io,
735 .init_early = orion5x_init_early, 735 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index b67cff0d4cfe..70a4e9265f06 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -251,7 +251,7 @@ static void __init edmini_v2_init(void)
251/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ 251/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
252MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2") 252MACHINE_START(EDMINI_V2, "LaCie Ethernet Disk mini V2")
253 /* Maintainer: Christopher Moore <moore@free.fr> */ 253 /* Maintainer: Christopher Moore <moore@free.fr> */
254 .boot_params = 0x00000100, 254 .atag_offset = 0x100,
255 .init_machine = edmini_v2_init, 255 .init_machine = edmini_v2_init,
256 .map_io = orion5x_map_io, 256 .map_io = orion5x_map_io,
257 .init_early = orion5x_init_early, 257 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/include/mach/debug-macro.S b/arch/arm/mach-orion5x/include/mach/debug-macro.S
index 5e3bf5b68aec..f340ed8f8dd0 100644
--- a/arch/arm/mach-orion5x/include/mach/debug-macro.S
+++ b/arch/arm/mach-orion5x/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
10 10
11#include <mach/orion5x.h> 11#include <mach/orion5x.h>
12 12
13 .macro addruart, rp, rv 13 .macro addruart, rp, rv, tmp
14 ldr \rp, =ORION5X_REGS_PHYS_BASE 14 ldr \rp, =ORION5X_REGS_PHYS_BASE
15 ldr \rv, =ORION5X_REGS_VIRT_BASE 15 ldr \rv, =ORION5X_REGS_VIRT_BASE
16 orr \rp, \rp, #0x00012000 16 orr \rp, \rp, #0x00012000
diff --git a/arch/arm/mach-orion5x/include/mach/memory.h b/arch/arm/mach-orion5x/include/mach/memory.h
deleted file mode 100644
index 6769917882fe..000000000000
--- a/arch/arm/mach-orion5x/include/mach/memory.h
+++ /dev/null
@@ -1,12 +0,0 @@
1/*
2 * arch/arm/mach-orion5x/include/mach/memory.h
3 *
4 * Marvell Orion memory definitions
5 */
6
7#ifndef __ASM_ARCH_MEMORY_H
8#define __ASM_ARCH_MEMORY_H
9
10#define PLAT_PHYS_OFFSET UL(0x00000000)
11
12#endif
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index f88f54bb7562..d3cd3f63258a 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -379,7 +379,7 @@ static void __init kurobox_pro_init(void)
379#ifdef CONFIG_MACH_KUROBOX_PRO 379#ifdef CONFIG_MACH_KUROBOX_PRO
380MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro") 380MACHINE_START(KUROBOX_PRO, "Buffalo/Revogear Kurobox Pro")
381 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 381 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
382 .boot_params = 0x00000100, 382 .atag_offset = 0x100,
383 .init_machine = kurobox_pro_init, 383 .init_machine = kurobox_pro_init,
384 .map_io = orion5x_map_io, 384 .map_io = orion5x_map_io,
385 .init_early = orion5x_init_early, 385 .init_early = orion5x_init_early,
@@ -392,7 +392,7 @@ MACHINE_END
392#ifdef CONFIG_MACH_LINKSTATION_PRO 392#ifdef CONFIG_MACH_LINKSTATION_PRO
393MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live") 393MACHINE_START(LINKSTATION_PRO, "Buffalo Linkstation Pro/Live")
394 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ 394 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
395 .boot_params = 0x00000100, 395 .atag_offset = 0x100,
396 .init_machine = kurobox_pro_init, 396 .init_machine = kurobox_pro_init,
397 .map_io = orion5x_map_io, 397 .map_io = orion5x_map_io,
398 .init_early = orion5x_init_early, 398 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 5065803ca82a..9503fff404e3 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -318,7 +318,7 @@ static void __init lschl_init(void)
318 318
319MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)") 319MACHINE_START(LINKSTATION_LSCHL, "Buffalo Linkstation LiveV3 (LS-CHL)")
320 /* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */ 320 /* Maintainer: Ash Hughes <ashley.hughes@blueyonder.co.uk> */
321 .boot_params = 0x00000100, 321 .atag_offset = 0x100,
322 .init_machine = lschl_init, 322 .init_machine = lschl_init,
323 .map_io = orion5x_map_io, 323 .map_io = orion5x_map_io,
324 .init_early = orion5x_init_early, 324 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 8503d0a42d41..ed6d772f4a24 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -265,7 +265,7 @@ static void __init ls_hgl_init(void)
265 265
266MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL") 266MACHINE_START(LINKSTATION_LS_HGL, "Buffalo Linkstation LS-HGL")
267 /* Maintainer: Zhu Qingsen <zhuqs@cn.fujistu.com> */ 267 /* Maintainer: Zhu Qingsen <zhuqs@cn.fujistu.com> */
268 .boot_params = 0x00000100, 268 .atag_offset = 0x100,
269 .init_machine = ls_hgl_init, 269 .init_machine = ls_hgl_init,
270 .map_io = orion5x_map_io, 270 .map_io = orion5x_map_io,
271 .init_early = orion5x_init_early, 271 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 9c82723c05c0..743f7f1db181 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -267,7 +267,7 @@ static void __init lsmini_init(void)
267#ifdef CONFIG_MACH_LINKSTATION_MINI 267#ifdef CONFIG_MACH_LINKSTATION_MINI
268MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini") 268MACHINE_START(LINKSTATION_MINI, "Buffalo Linkstation Mini")
269 /* Maintainer: Alexey Kopytko <alexey@kopytko.ru> */ 269 /* Maintainer: Alexey Kopytko <alexey@kopytko.ru> */
270 .boot_params = 0x00000100, 270 .atag_offset = 0x100,
271 .init_machine = lsmini_init, 271 .init_machine = lsmini_init,
272 .map_io = orion5x_map_io, 272 .map_io = orion5x_map_io,
273 .init_early = orion5x_init_early, 273 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index ef3bb8e9a4c2..6020e26b1c71 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -261,7 +261,7 @@ static void __init mss2_init(void)
261 261
262MACHINE_START(MSS2, "Maxtor Shared Storage II") 262MACHINE_START(MSS2, "Maxtor Shared Storage II")
263 /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */ 263 /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
264 .boot_params = 0x00000100, 264 .atag_offset = 0x100,
265 .init_machine = mss2_init, 265 .init_machine = mss2_init,
266 .map_io = orion5x_map_io, 266 .map_io = orion5x_map_io,
267 .init_early = orion5x_init_early, 267 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 525eb1286859..201ae3676289 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -228,7 +228,7 @@ static void __init mv2120_init(void)
228/* Warning: HP uses a wrong mach-type (=526) in their bootloader */ 228/* Warning: HP uses a wrong mach-type (=526) in their bootloader */
229MACHINE_START(MV2120, "HP Media Vault mv2120") 229MACHINE_START(MV2120, "HP Media Vault mv2120")
230 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */ 230 /* Maintainer: Martin Michlmayr <tbm@cyrius.com> */
231 .boot_params = 0x00000100, 231 .atag_offset = 0x100,
232 .init_machine = mv2120_init, 232 .init_machine = mv2120_init,
233 .map_io = orion5x_map_io, 233 .map_io = orion5x_map_io,
234 .init_early = orion5x_init_early, 234 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index e43b39cc7fe9..6197c79a2ecb 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -419,7 +419,7 @@ static void __init net2big_init(void)
419 419
420/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */ 420/* Warning: LaCie use a wrong mach-type (0x20e=526) in their bootloader. */
421MACHINE_START(NET2BIG, "LaCie 2Big Network") 421MACHINE_START(NET2BIG, "LaCie 2Big Network")
422 .boot_params = 0x00000100, 422 .atag_offset = 0x100,
423 .init_machine = net2big_init, 423 .init_machine = net2big_init,
424 .map_io = orion5x_map_io, 424 .map_io = orion5x_map_io,
425 .init_early = orion5x_init_early, 425 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 50aae6f571b8..ebd6767d8e88 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -168,7 +168,7 @@ subsys_initcall(rd88f5181l_fxo_pci_init);
168 168
169MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design") 169MACHINE_START(RD88F5181L_FXO, "Marvell Orion-VoIP FXO Reference Design")
170 /* Maintainer: Nicolas Pitre <nico@marvell.com> */ 170 /* Maintainer: Nicolas Pitre <nico@marvell.com> */
171 .boot_params = 0x00000100, 171 .atag_offset = 0x100,
172 .init_machine = rd88f5181l_fxo_init, 172 .init_machine = rd88f5181l_fxo_init,
173 .map_io = orion5x_map_io, 173 .map_io = orion5x_map_io,
174 .init_early = orion5x_init_early, 174 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index 35f106ac593a..05db2d336b08 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -180,7 +180,7 @@ subsys_initcall(rd88f5181l_ge_pci_init);
180 180
181MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design") 181MACHINE_START(RD88F5181L_GE, "Marvell Orion-VoIP GE Reference Design")
182 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 182 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
183 .boot_params = 0x00000100, 183 .atag_offset = 0x100,
184 .init_machine = rd88f5181l_ge_init, 184 .init_machine = rd88f5181l_ge_init,
185 .map_io = orion5x_map_io, 185 .map_io = orion5x_map_io,
186 .init_early = orion5x_init_early, 186 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 9bb2b8bafbfd..e47fa0578ae3 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -305,7 +305,7 @@ static void __init rd88f5182_init(void)
305 305
306MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design") 306MACHINE_START(RD88F5182, "Marvell Orion-NAS Reference Design")
307 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */ 307 /* Maintainer: Ronen Shitrit <rshitrit@marvell.com> */
308 .boot_params = 0x00000100, 308 .atag_offset = 0x100,
309 .init_machine = rd88f5182_init, 309 .init_machine = rd88f5182_init,
310 .map_io = orion5x_map_io, 310 .map_io = orion5x_map_io,
311 .init_early = orion5x_init_early, 311 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index 1d00df9ad464..64317251ec00 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -121,7 +121,7 @@ subsys_initcall(rd88f6183ap_ge_pci_init);
121 121
122MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design") 122MACHINE_START(RD88F6183AP_GE, "Marvell Orion-1-90 AP GE Reference Design")
123 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 123 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
124 .boot_params = 0x00000100, 124 .atag_offset = 0x100,
125 .init_machine = rd88f6183ap_ge_init, 125 .init_machine = rd88f6183ap_ge_init,
126 .map_io = orion5x_map_io, 126 .map_io = orion5x_map_io,
127 .init_early = orion5x_init_early, 127 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index c9dd31d34866..29f1526f7b70 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -357,7 +357,7 @@ static void __init tsp2_init(void)
357 357
358MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live") 358MACHINE_START(TERASTATION_PRO2, "Buffalo Terastation Pro II/Live")
359 /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */ 359 /* Maintainer: Sylver Bruneau <sylver.bruneau@googlemail.com> */
360 .boot_params = 0x00000100, 360 .atag_offset = 0x100,
361 .init_machine = tsp2_init, 361 .init_machine = tsp2_init,
362 .map_io = orion5x_map_io, 362 .map_io = orion5x_map_io,
363 .init_early = orion5x_init_early, 363 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index 764307b8abfc..31e51f9b4b64 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -322,7 +322,7 @@ static void __init qnap_ts209_init(void)
322 322
323MACHINE_START(TS209, "QNAP TS-109/TS-209") 323MACHINE_START(TS209, "QNAP TS-109/TS-209")
324 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */ 324 /* Maintainer: Byron Bradley <byron.bbradley@gmail.com> */
325 .boot_params = 0x00000100, 325 .atag_offset = 0x100,
326 .init_machine = qnap_ts209_init, 326 .init_machine = qnap_ts209_init,
327 .map_io = orion5x_map_io, 327 .map_io = orion5x_map_io,
328 .init_early = orion5x_init_early, 328 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 0572dd1c8aaa..0fbcc14e09d7 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -311,7 +311,7 @@ static void __init qnap_ts409_init(void)
311 311
312MACHINE_START(TS409, "QNAP TS-409") 312MACHINE_START(TS409, "QNAP TS-409")
313 /* Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> */ 313 /* Maintainer: Sylver Bruneau <sylver.bruneau@gmail.com> */
314 .boot_params = 0x00000100, 314 .atag_offset = 0x100,
315 .init_machine = qnap_ts409_init, 315 .init_machine = qnap_ts409_init,
316 .map_io = orion5x_map_io, 316 .map_io = orion5x_map_io,
317 .init_early = orion5x_init_early, 317 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index 6b7b54116f30..6c75cd35c4c8 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -621,7 +621,7 @@ static void __init ts78xx_init(void)
621 621
622MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC") 622MACHINE_START(TS78XX, "Technologic Systems TS-78xx SBC")
623 /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */ 623 /* Maintainer: Alexander Clouter <alex@digriz.org.uk> */
624 .boot_params = 0x00000100, 624 .atag_offset = 0x100,
625 .init_machine = ts78xx_init, 625 .init_machine = ts78xx_init,
626 .map_io = ts78xx_map_io, 626 .map_io = ts78xx_map_io,
627 .init_early = orion5x_init_early, 627 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index cdad50bd4891..b8be7d8d0cf4 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -172,7 +172,7 @@ subsys_initcall(wnr854t_pci_init);
172 172
173MACHINE_START(WNR854T, "Netgear WNR854T") 173MACHINE_START(WNR854T, "Netgear WNR854T")
174 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */ 174 /* Maintainer: Imre Kaloz <kaloz@openwrt.org> */
175 .boot_params = 0x00000100, 175 .atag_offset = 0x100,
176 .init_machine = wnr854t_init, 176 .init_machine = wnr854t_init,
177 .map_io = orion5x_map_io, 177 .map_io = orion5x_map_io,
178 .init_early = orion5x_init_early, 178 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 8f10ffd77ec3..faf81a039360 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -260,7 +260,7 @@ subsys_initcall(wrt350n_v2_pci_init);
260 260
261MACHINE_START(WRT350N_V2, "Linksys WRT350N v2") 261MACHINE_START(WRT350N_V2, "Linksys WRT350N v2")
262 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */ 262 /* Maintainer: Lennert Buytenhek <buytenh@marvell.com> */
263 .boot_params = 0x00000100, 263 .atag_offset = 0x100,
264 .init_machine = wrt350n_v2_init, 264 .init_machine = wrt350n_v2_init,
265 .map_io = orion5x_map_io, 265 .map_io = orion5x_map_io,
266 .init_early = orion5x_init_early, 266 .init_early = orion5x_init_early,
diff --git a/arch/arm/mach-pnx4008/core.c b/arch/arm/mach-pnx4008/core.c
index 63399755f199..cdb95e726f5c 100644
--- a/arch/arm/mach-pnx4008/core.c
+++ b/arch/arm/mach-pnx4008/core.c
@@ -264,7 +264,7 @@ extern struct sys_timer pnx4008_timer;
264 264
265MACHINE_START(PNX4008, "Philips PNX4008") 265MACHINE_START(PNX4008, "Philips PNX4008")
266 /* Maintainer: MontaVista Software Inc. */ 266 /* Maintainer: MontaVista Software Inc. */
267 .boot_params = 0x80000100, 267 .atag_offset = 0x100,
268 .map_io = pnx4008_map_io, 268 .map_io = pnx4008_map_io,
269 .init_irq = pnx4008_init_irq, 269 .init_irq = pnx4008_init_irq,
270 .init_machine = pnx4008_init, 270 .init_machine = pnx4008_init,
diff --git a/arch/arm/mach-pnx4008/include/mach/debug-macro.S b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
index 931afebaf064..469d60d97f5c 100644
--- a/arch/arm/mach-pnx4008/include/mach/debug-macro.S
+++ b/arch/arm/mach-pnx4008/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0x00090000 15 mov \rp, #0x00090000
16 add \rv, \rp, #0xf4000000 @ virtual 16 add \rv, \rp, #0xf4000000 @ virtual
17 add \rp, \rp, #0x40000000 @ physical 17 add \rp, \rp, #0x40000000 @ physical
diff --git a/arch/arm/mach-pnx4008/include/mach/memory.h b/arch/arm/mach-pnx4008/include/mach/memory.h
deleted file mode 100644
index 1275db61cee5..000000000000
--- a/arch/arm/mach-pnx4008/include/mach/memory.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-pnx4008/include/mach/memory.h
3 *
4 * Copyright (c) 2005 Philips Semiconductors
5 * Copyright (c) 2005 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16/*
17 * Physical DRAM offset.
18 */
19#define PLAT_PHYS_OFFSET UL(0x80000000)
20
21#endif
diff --git a/arch/arm/mach-prima2/include/mach/debug-macro.S b/arch/arm/mach-prima2/include/mach/debug-macro.S
index bf75106333ff..cd97492bb075 100644
--- a/arch/arm/mach-prima2/include/mach/debug-macro.S
+++ b/arch/arm/mach-prima2/include/mach/debug-macro.S
@@ -9,7 +9,7 @@
9#include <mach/hardware.h> 9#include <mach/hardware.h>
10#include <mach/uart.h> 10#include <mach/uart.h>
11 11
12 .macro addruart, rp, rv 12 .macro addruart, rp, rv, tmp
13 ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical 13 ldr \rp, =SIRFSOC_UART1_PA_BASE @ physical
14 ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual 14 ldr \rv, =SIRFSOC_UART1_VA_BASE @ virtual
15 .endm 15 .endm
diff --git a/arch/arm/mach-prima2/include/mach/memory.h b/arch/arm/mach-prima2/include/mach/memory.h
deleted file mode 100644
index 368cd5a0601a..000000000000
--- a/arch/arm/mach-prima2/include/mach/memory.h
+++ /dev/null
@@ -1,21 +0,0 @@
1/*
2 * arch/arm/mach-prima2/include/mach/memory.h
3 *
4 * Copyright (c) 2010 – 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
5 *
6 * Licensed under GPLv2 or later.
7 */
8
9#ifndef __ASM_ARCH_MEMORY_H
10#define __ASM_ARCH_MEMORY_H
11
12#define PLAT_PHYS_OFFSET UL(0x00000000)
13
14/*
15 * Restrict DMA-able region to workaround silicon limitation.
16 * The limitation restricts buffers available for DMA to SD/MMC
17 * hardware to be below 256MB
18 */
19#define ARM_DMA_ZONE_SIZE (SZ_256M)
20
21#endif
diff --git a/arch/arm/mach-prima2/l2x0.c b/arch/arm/mach-prima2/l2x0.c
index 9cda2057bcfb..66c6387e5a04 100644
--- a/arch/arm/mach-prima2/l2x0.c
+++ b/arch/arm/mach-prima2/l2x0.c
@@ -13,7 +13,6 @@
13#include <linux/of.h> 13#include <linux/of.h>
14#include <linux/of_address.h> 14#include <linux/of_address.h>
15#include <asm/hardware/cache-l2x0.h> 15#include <asm/hardware/cache-l2x0.h>
16#include <mach/memory.h>
17 16
18#define L2X0_ADDR_FILTERING_START 0xC00 17#define L2X0_ADDR_FILTERING_START 0xC00
19#define L2X0_ADDR_FILTERING_END 0xC04 18#define L2X0_ADDR_FILTERING_END 0xC04
@@ -41,9 +40,9 @@ static int __init sirfsoc_of_l2x_init(void)
41 /* 40 /*
42 * set the physical memory windows L2 cache will cover 41 * set the physical memory windows L2 cache will cover
43 */ 42 */
44 writel_relaxed(PLAT_PHYS_OFFSET + 1024 * 1024 * 1024, 43 writel_relaxed(PHYS_OFFSET + 1024 * 1024 * 1024,
45 sirfsoc_l2x_base + L2X0_ADDR_FILTERING_END); 44 sirfsoc_l2x_base + L2X0_ADDR_FILTERING_END);
46 writel_relaxed(PLAT_PHYS_OFFSET | 0x1, 45 writel_relaxed(PHYS_OFFSET | 0x1,
47 sirfsoc_l2x_base + L2X0_ADDR_FILTERING_START); 46 sirfsoc_l2x_base + L2X0_ADDR_FILTERING_START);
48 47
49 writel_relaxed(0, 48 writel_relaxed(0,
diff --git a/arch/arm/mach-prima2/prima2.c b/arch/arm/mach-prima2/prima2.c
index f57124bdd143..ee33c3d458f5 100644
--- a/arch/arm/mach-prima2/prima2.c
+++ b/arch/arm/mach-prima2/prima2.c
@@ -31,11 +31,12 @@ static const char *prima2cb_dt_match[] __initdata = {
31 31
32MACHINE_START(PRIMA2_EVB, "prima2cb") 32MACHINE_START(PRIMA2_EVB, "prima2cb")
33 /* Maintainer: Barry Song <baohua.song@csr.com> */ 33 /* Maintainer: Barry Song <baohua.song@csr.com> */
34 .boot_params = 0x00000100, 34 .atag_offset = 0x100,
35 .init_early = sirfsoc_of_clk_init, 35 .init_early = sirfsoc_of_clk_init,
36 .map_io = sirfsoc_map_lluart, 36 .map_io = sirfsoc_map_lluart,
37 .init_irq = sirfsoc_of_irq_init, 37 .init_irq = sirfsoc_of_irq_init,
38 .timer = &sirfsoc_timer, 38 .timer = &sirfsoc_timer,
39 .dma_zone_size = SZ_256M,
39 .init_machine = sirfsoc_mach_init, 40 .init_machine = sirfsoc_mach_init,
40 .dt_compat = prima2cb_dt_match, 41 .dt_compat = prima2cb_dt_match,
41MACHINE_END 42MACHINE_END
diff --git a/arch/arm/mach-pxa/balloon3.c b/arch/arm/mach-pxa/balloon3.c
index ef3e8b1e06c1..7765d677adbb 100644
--- a/arch/arm/mach-pxa/balloon3.c
+++ b/arch/arm/mach-pxa/balloon3.c
@@ -828,5 +828,5 @@ MACHINE_START(BALLOON3, "Balloon3")
828 .handle_irq = pxa27x_handle_irq, 828 .handle_irq = pxa27x_handle_irq,
829 .timer = &pxa_timer, 829 .timer = &pxa_timer,
830 .init_machine = balloon3_init, 830 .init_machine = balloon3_init,
831 .boot_params = PLAT_PHYS_OFFSET + 0x100, 831 .atag_offset = 0x100,
832MACHINE_END 832MACHINE_END
diff --git a/arch/arm/mach-pxa/capc7117.c b/arch/arm/mach-pxa/capc7117.c
index 648b0ab2bf77..4efc16d39c79 100644
--- a/arch/arm/mach-pxa/capc7117.c
+++ b/arch/arm/mach-pxa/capc7117.c
@@ -148,7 +148,7 @@ static void __init capc7117_init(void)
148 148
149MACHINE_START(CAPC7117, 149MACHINE_START(CAPC7117,
150 "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM") 150 "Embedian CAPC-7117 evaluation kit based on the MXM-8x10 CoM")
151 .boot_params = 0xa0000100, 151 .atag_offset = 0x100,
152 .map_io = pxa3xx_map_io, 152 .map_io = pxa3xx_map_io,
153 .init_irq = pxa3xx_init_irq, 153 .init_irq = pxa3xx_init_irq,
154 .handle_irq = pxa3xx_handle_irq, 154 .handle_irq = pxa3xx_handle_irq,
diff --git a/arch/arm/mach-pxa/cm-x2xx.c b/arch/arm/mach-pxa/cm-x2xx.c
index 13cf518bbbf8..349896c53abd 100644
--- a/arch/arm/mach-pxa/cm-x2xx.c
+++ b/arch/arm/mach-pxa/cm-x2xx.c
@@ -513,7 +513,7 @@ static void __init cmx2xx_map_io(void)
513#endif 513#endif
514 514
515MACHINE_START(ARMCORE, "Compulab CM-X2XX") 515MACHINE_START(ARMCORE, "Compulab CM-X2XX")
516 .boot_params = 0xa0000100, 516 .atag_offset = 0x100,
517 .map_io = cmx2xx_map_io, 517 .map_io = cmx2xx_map_io,
518 .nr_irqs = CMX2XX_NR_IRQS, 518 .nr_irqs = CMX2XX_NR_IRQS,
519 .init_irq = cmx2xx_init_irq, 519 .init_irq = cmx2xx_init_irq,
diff --git a/arch/arm/mach-pxa/cm-x300.c b/arch/arm/mach-pxa/cm-x300.c
index d940e8a72270..d2da301619f0 100644
--- a/arch/arm/mach-pxa/cm-x300.c
+++ b/arch/arm/mach-pxa/cm-x300.c
@@ -852,7 +852,7 @@ static void __init cm_x300_fixup(struct tag *tags, char **cmdline,
852} 852}
853 853
854MACHINE_START(CM_X300, "CM-X300 module") 854MACHINE_START(CM_X300, "CM-X300 module")
855 .boot_params = 0xa0000100, 855 .atag_offset = 0x100,
856 .map_io = pxa3xx_map_io, 856 .map_io = pxa3xx_map_io,
857 .init_irq = pxa3xx_init_irq, 857 .init_irq = pxa3xx_init_irq,
858 .handle_irq = pxa3xx_handle_irq, 858 .handle_irq = pxa3xx_handle_irq,
diff --git a/arch/arm/mach-pxa/colibri-pxa270.c b/arch/arm/mach-pxa/colibri-pxa270.c
index 870920934ecf..7db66465716f 100644
--- a/arch/arm/mach-pxa/colibri-pxa270.c
+++ b/arch/arm/mach-pxa/colibri-pxa270.c
@@ -306,7 +306,7 @@ static void __init colibri_pxa270_income_init(void)
306} 306}
307 307
308MACHINE_START(COLIBRI, "Toradex Colibri PXA270") 308MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
309 .boot_params = COLIBRI_SDRAM_BASE + 0x100, 309 .atag_offset = 0x100,
310 .init_machine = colibri_pxa270_init, 310 .init_machine = colibri_pxa270_init,
311 .map_io = pxa27x_map_io, 311 .map_io = pxa27x_map_io,
312 .init_irq = pxa27x_init_irq, 312 .init_irq = pxa27x_init_irq,
@@ -315,7 +315,7 @@ MACHINE_START(COLIBRI, "Toradex Colibri PXA270")
315MACHINE_END 315MACHINE_END
316 316
317MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC") 317MACHINE_START(INCOME, "Income s.r.o. SH-Dmaster PXA270 SBC")
318 .boot_params = 0xa0000100, 318 .atag_offset = 0x100,
319 .init_machine = colibri_pxa270_income_init, 319 .init_machine = colibri_pxa270_income_init,
320 .map_io = pxa27x_map_io, 320 .map_io = pxa27x_map_io,
321 .init_irq = pxa27x_init_irq, 321 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/colibri-pxa300.c b/arch/arm/mach-pxa/colibri-pxa300.c
index 60a6781e7a8e..c825e8bf2db1 100644
--- a/arch/arm/mach-pxa/colibri-pxa300.c
+++ b/arch/arm/mach-pxa/colibri-pxa300.c
@@ -183,7 +183,7 @@ void __init colibri_pxa300_init(void)
183} 183}
184 184
185MACHINE_START(COLIBRI300, "Toradex Colibri PXA300") 185MACHINE_START(COLIBRI300, "Toradex Colibri PXA300")
186 .boot_params = COLIBRI_SDRAM_BASE + 0x100, 186 .atag_offset = 0x100,
187 .init_machine = colibri_pxa300_init, 187 .init_machine = colibri_pxa300_init,
188 .map_io = pxa3xx_map_io, 188 .map_io = pxa3xx_map_io,
189 .init_irq = pxa3xx_init_irq, 189 .init_irq = pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/colibri-pxa320.c b/arch/arm/mach-pxa/colibri-pxa320.c
index d2c6631915d4..692e1ffc5586 100644
--- a/arch/arm/mach-pxa/colibri-pxa320.c
+++ b/arch/arm/mach-pxa/colibri-pxa320.c
@@ -253,7 +253,7 @@ void __init colibri_pxa320_init(void)
253} 253}
254 254
255MACHINE_START(COLIBRI320, "Toradex Colibri PXA320") 255MACHINE_START(COLIBRI320, "Toradex Colibri PXA320")
256 .boot_params = COLIBRI_SDRAM_BASE + 0x100, 256 .atag_offset = 0x100,
257 .init_machine = colibri_pxa320_init, 257 .init_machine = colibri_pxa320_init,
258 .map_io = pxa3xx_map_io, 258 .map_io = pxa3xx_map_io,
259 .init_irq = pxa3xx_init_irq, 259 .init_irq = pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/csb726.c b/arch/arm/mach-pxa/csb726.c
index fe812eafb1f1..5e2cf39e9e4c 100644
--- a/arch/arm/mach-pxa/csb726.c
+++ b/arch/arm/mach-pxa/csb726.c
@@ -272,7 +272,7 @@ static void __init csb726_init(void)
272} 272}
273 273
274MACHINE_START(CSB726, "Cogent CSB726") 274MACHINE_START(CSB726, "Cogent CSB726")
275 .boot_params = 0xa0000100, 275 .atag_offset = 0x100,
276 .map_io = pxa27x_map_io, 276 .map_io = pxa27x_map_io,
277 .init_irq = pxa27x_init_irq, 277 .init_irq = pxa27x_init_irq,
278 .handle_irq = pxa27x_handle_irq, 278 .handle_irq = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/em-x270.c b/arch/arm/mach-pxa/em-x270.c
index 2e37ea52b372..94acc0b01dd6 100644
--- a/arch/arm/mach-pxa/em-x270.c
+++ b/arch/arm/mach-pxa/em-x270.c
@@ -1299,7 +1299,7 @@ static void __init em_x270_init(void)
1299} 1299}
1300 1300
1301MACHINE_START(EM_X270, "Compulab EM-X270") 1301MACHINE_START(EM_X270, "Compulab EM-X270")
1302 .boot_params = 0xa0000100, 1302 .atag_offset = 0x100,
1303 .map_io = pxa27x_map_io, 1303 .map_io = pxa27x_map_io,
1304 .init_irq = pxa27x_init_irq, 1304 .init_irq = pxa27x_init_irq,
1305 .handle_irq = pxa27x_handle_irq, 1305 .handle_irq = pxa27x_handle_irq,
@@ -1308,7 +1308,7 @@ MACHINE_START(EM_X270, "Compulab EM-X270")
1308MACHINE_END 1308MACHINE_END
1309 1309
1310MACHINE_START(EXEDA, "Compulab eXeda") 1310MACHINE_START(EXEDA, "Compulab eXeda")
1311 .boot_params = 0xa0000100, 1311 .atag_offset = 0x100,
1312 .map_io = pxa27x_map_io, 1312 .map_io = pxa27x_map_io,
1313 .init_irq = pxa27x_init_irq, 1313 .init_irq = pxa27x_init_irq,
1314 .handle_irq = pxa27x_handle_irq, 1314 .handle_irq = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/eseries.c b/arch/arm/mach-pxa/eseries.c
index e4a1f4dc89ff..8e697dd8accd 100644
--- a/arch/arm/mach-pxa/eseries.c
+++ b/arch/arm/mach-pxa/eseries.c
@@ -188,7 +188,7 @@ static void __init e330_init(void)
188 188
189MACHINE_START(E330, "Toshiba e330") 189MACHINE_START(E330, "Toshiba e330")
190 /* Maintainer: Ian Molton (spyro@f2s.com) */ 190 /* Maintainer: Ian Molton (spyro@f2s.com) */
191 .boot_params = 0xa0000100, 191 .atag_offset = 0x100,
192 .map_io = pxa25x_map_io, 192 .map_io = pxa25x_map_io,
193 .nr_irqs = ESERIES_NR_IRQS, 193 .nr_irqs = ESERIES_NR_IRQS,
194 .init_irq = pxa25x_init_irq, 194 .init_irq = pxa25x_init_irq,
@@ -238,7 +238,7 @@ static void __init e350_init(void)
238 238
239MACHINE_START(E350, "Toshiba e350") 239MACHINE_START(E350, "Toshiba e350")
240 /* Maintainer: Ian Molton (spyro@f2s.com) */ 240 /* Maintainer: Ian Molton (spyro@f2s.com) */
241 .boot_params = 0xa0000100, 241 .atag_offset = 0x100,
242 .map_io = pxa25x_map_io, 242 .map_io = pxa25x_map_io,
243 .nr_irqs = ESERIES_NR_IRQS, 243 .nr_irqs = ESERIES_NR_IRQS,
244 .init_irq = pxa25x_init_irq, 244 .init_irq = pxa25x_init_irq,
@@ -361,7 +361,7 @@ static void __init e400_init(void)
361 361
362MACHINE_START(E400, "Toshiba e400") 362MACHINE_START(E400, "Toshiba e400")
363 /* Maintainer: Ian Molton (spyro@f2s.com) */ 363 /* Maintainer: Ian Molton (spyro@f2s.com) */
364 .boot_params = 0xa0000100, 364 .atag_offset = 0x100,
365 .map_io = pxa25x_map_io, 365 .map_io = pxa25x_map_io,
366 .nr_irqs = ESERIES_NR_IRQS, 366 .nr_irqs = ESERIES_NR_IRQS,
367 .init_irq = pxa25x_init_irq, 367 .init_irq = pxa25x_init_irq,
@@ -550,7 +550,7 @@ static void __init e740_init(void)
550 550
551MACHINE_START(E740, "Toshiba e740") 551MACHINE_START(E740, "Toshiba e740")
552 /* Maintainer: Ian Molton (spyro@f2s.com) */ 552 /* Maintainer: Ian Molton (spyro@f2s.com) */
553 .boot_params = 0xa0000100, 553 .atag_offset = 0x100,
554 .map_io = pxa25x_map_io, 554 .map_io = pxa25x_map_io,
555 .nr_irqs = ESERIES_NR_IRQS, 555 .nr_irqs = ESERIES_NR_IRQS,
556 .init_irq = pxa25x_init_irq, 556 .init_irq = pxa25x_init_irq,
@@ -742,7 +742,7 @@ static void __init e750_init(void)
742 742
743MACHINE_START(E750, "Toshiba e750") 743MACHINE_START(E750, "Toshiba e750")
744 /* Maintainer: Ian Molton (spyro@f2s.com) */ 744 /* Maintainer: Ian Molton (spyro@f2s.com) */
745 .boot_params = 0xa0000100, 745 .atag_offset = 0x100,
746 .map_io = pxa25x_map_io, 746 .map_io = pxa25x_map_io,
747 .nr_irqs = ESERIES_NR_IRQS, 747 .nr_irqs = ESERIES_NR_IRQS,
748 .init_irq = pxa25x_init_irq, 748 .init_irq = pxa25x_init_irq,
@@ -947,7 +947,7 @@ static void __init e800_init(void)
947 947
948MACHINE_START(E800, "Toshiba e800") 948MACHINE_START(E800, "Toshiba e800")
949 /* Maintainer: Ian Molton (spyro@f2s.com) */ 949 /* Maintainer: Ian Molton (spyro@f2s.com) */
950 .boot_params = 0xa0000100, 950 .atag_offset = 0x100,
951 .map_io = pxa25x_map_io, 951 .map_io = pxa25x_map_io,
952 .nr_irqs = ESERIES_NR_IRQS, 952 .nr_irqs = ESERIES_NR_IRQS,
953 .init_irq = pxa25x_init_irq, 953 .init_irq = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/ezx.c b/arch/arm/mach-pxa/ezx.c
index b73eadb9f5dc..8308eee5a924 100644
--- a/arch/arm/mach-pxa/ezx.c
+++ b/arch/arm/mach-pxa/ezx.c
@@ -797,7 +797,7 @@ static void __init a780_init(void)
797} 797}
798 798
799MACHINE_START(EZX_A780, "Motorola EZX A780") 799MACHINE_START(EZX_A780, "Motorola EZX A780")
800 .boot_params = 0xa0000100, 800 .atag_offset = 0x100,
801 .map_io = pxa27x_map_io, 801 .map_io = pxa27x_map_io,
802 .nr_irqs = EZX_NR_IRQS, 802 .nr_irqs = EZX_NR_IRQS,
803 .init_irq = pxa27x_init_irq, 803 .init_irq = pxa27x_init_irq,
@@ -863,7 +863,7 @@ static void __init e680_init(void)
863} 863}
864 864
865MACHINE_START(EZX_E680, "Motorola EZX E680") 865MACHINE_START(EZX_E680, "Motorola EZX E680")
866 .boot_params = 0xa0000100, 866 .atag_offset = 0x100,
867 .map_io = pxa27x_map_io, 867 .map_io = pxa27x_map_io,
868 .nr_irqs = EZX_NR_IRQS, 868 .nr_irqs = EZX_NR_IRQS,
869 .init_irq = pxa27x_init_irq, 869 .init_irq = pxa27x_init_irq,
@@ -929,7 +929,7 @@ static void __init a1200_init(void)
929} 929}
930 930
931MACHINE_START(EZX_A1200, "Motorola EZX A1200") 931MACHINE_START(EZX_A1200, "Motorola EZX A1200")
932 .boot_params = 0xa0000100, 932 .atag_offset = 0x100,
933 .map_io = pxa27x_map_io, 933 .map_io = pxa27x_map_io,
934 .nr_irqs = EZX_NR_IRQS, 934 .nr_irqs = EZX_NR_IRQS,
935 .init_irq = pxa27x_init_irq, 935 .init_irq = pxa27x_init_irq,
@@ -1120,7 +1120,7 @@ static void __init a910_init(void)
1120} 1120}
1121 1121
1122MACHINE_START(EZX_A910, "Motorola EZX A910") 1122MACHINE_START(EZX_A910, "Motorola EZX A910")
1123 .boot_params = 0xa0000100, 1123 .atag_offset = 0x100,
1124 .map_io = pxa27x_map_io, 1124 .map_io = pxa27x_map_io,
1125 .nr_irqs = EZX_NR_IRQS, 1125 .nr_irqs = EZX_NR_IRQS,
1126 .init_irq = pxa27x_init_irq, 1126 .init_irq = pxa27x_init_irq,
@@ -1186,7 +1186,7 @@ static void __init e6_init(void)
1186} 1186}
1187 1187
1188MACHINE_START(EZX_E6, "Motorola EZX E6") 1188MACHINE_START(EZX_E6, "Motorola EZX E6")
1189 .boot_params = 0xa0000100, 1189 .atag_offset = 0x100,
1190 .map_io = pxa27x_map_io, 1190 .map_io = pxa27x_map_io,
1191 .nr_irqs = EZX_NR_IRQS, 1191 .nr_irqs = EZX_NR_IRQS,
1192 .init_irq = pxa27x_init_irq, 1192 .init_irq = pxa27x_init_irq,
@@ -1226,7 +1226,7 @@ static void __init e2_init(void)
1226} 1226}
1227 1227
1228MACHINE_START(EZX_E2, "Motorola EZX E2") 1228MACHINE_START(EZX_E2, "Motorola EZX E2")
1229 .boot_params = 0xa0000100, 1229 .atag_offset = 0x100,
1230 .map_io = pxa27x_map_io, 1230 .map_io = pxa27x_map_io,
1231 .nr_irqs = EZX_NR_IRQS, 1231 .nr_irqs = EZX_NR_IRQS,
1232 .init_irq = pxa27x_init_irq, 1232 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/gumstix.c b/arch/arm/mach-pxa/gumstix.c
index deaa111c91f9..9c8208ca0415 100644
--- a/arch/arm/mach-pxa/gumstix.c
+++ b/arch/arm/mach-pxa/gumstix.c
@@ -233,7 +233,7 @@ static void __init gumstix_init(void)
233} 233}
234 234
235MACHINE_START(GUMSTIX, "Gumstix") 235MACHINE_START(GUMSTIX, "Gumstix")
236 .boot_params = 0xa0000100, /* match u-boot bi_boot_params */ 236 .atag_offset = 0x100, /* match u-boot bi_boot_params */
237 .map_io = pxa25x_map_io, 237 .map_io = pxa25x_map_io,
238 .init_irq = pxa25x_init_irq, 238 .init_irq = pxa25x_init_irq,
239 .handle_irq = pxa25x_handle_irq, 239 .handle_irq = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/h5000.c b/arch/arm/mach-pxa/h5000.c
index 0a235128914d..4b5e110640b1 100644
--- a/arch/arm/mach-pxa/h5000.c
+++ b/arch/arm/mach-pxa/h5000.c
@@ -203,7 +203,7 @@ static void __init h5000_init(void)
203} 203}
204 204
205MACHINE_START(H5400, "HP iPAQ H5000") 205MACHINE_START(H5400, "HP iPAQ H5000")
206 .boot_params = 0xa0000100, 206 .atag_offset = 0x100,
207 .map_io = pxa25x_map_io, 207 .map_io = pxa25x_map_io,
208 .init_irq = pxa25x_init_irq, 208 .init_irq = pxa25x_init_irq,
209 .handle_irq = pxa25x_handle_irq, 209 .handle_irq = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/himalaya.c b/arch/arm/mach-pxa/himalaya.c
index a997d0ab2872..f2c324570844 100644
--- a/arch/arm/mach-pxa/himalaya.c
+++ b/arch/arm/mach-pxa/himalaya.c
@@ -158,7 +158,7 @@ static void __init himalaya_init(void)
158 158
159 159
160MACHINE_START(HIMALAYA, "HTC Himalaya") 160MACHINE_START(HIMALAYA, "HTC Himalaya")
161 .boot_params = 0xa0000100, 161 .atag_offset = 0x100,
162 .map_io = pxa25x_map_io, 162 .map_io = pxa25x_map_io,
163 .init_irq = pxa25x_init_irq, 163 .init_irq = pxa25x_init_irq,
164 .handle_irq = pxa25x_handle_irq, 164 .handle_irq = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index c748a473a2ff..6f6368ece9bd 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -838,7 +838,7 @@ static void __init hx4700_init(void)
838} 838}
839 839
840MACHINE_START(H4700, "HP iPAQ HX4700") 840MACHINE_START(H4700, "HP iPAQ HX4700")
841 .boot_params = 0xa0000100, 841 .atag_offset = 0x100,
842 .map_io = pxa27x_map_io, 842 .map_io = pxa27x_map_io,
843 .nr_irqs = HX4700_NR_IRQS, 843 .nr_irqs = HX4700_NR_IRQS,
844 .init_irq = pxa27x_init_irq, 844 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/icontrol.c b/arch/arm/mach-pxa/icontrol.c
index d427429f1f34..f78d5db758da 100644
--- a/arch/arm/mach-pxa/icontrol.c
+++ b/arch/arm/mach-pxa/icontrol.c
@@ -191,7 +191,7 @@ static void __init icontrol_init(void)
191} 191}
192 192
193MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM") 193MACHINE_START(ICONTROL, "iControl/SafeTcam boards using Embedian MXM-8x10 CoM")
194 .boot_params = 0xa0000100, 194 .atag_offset = 0x100,
195 .map_io = pxa3xx_map_io, 195 .map_io = pxa3xx_map_io,
196 .init_irq = pxa3xx_init_irq, 196 .init_irq = pxa3xx_init_irq,
197 .handle_irq = pxa3xx_handle_irq, 197 .handle_irq = pxa3xx_handle_irq,
diff --git a/arch/arm/mach-pxa/include/mach/debug-macro.S b/arch/arm/mach-pxa/include/mach/debug-macro.S
index 7d5c75125d65..70b112e8ef68 100644
--- a/arch/arm/mach-pxa/include/mach/debug-macro.S
+++ b/arch/arm/mach-pxa/include/mach/debug-macro.S
@@ -13,7 +13,7 @@
13 13
14#include "hardware.h" 14#include "hardware.h"
15 15
16 .macro addruart, rp, rv 16 .macro addruart, rp, rv, tmp
17 mov \rp, #0x00100000 17 mov \rp, #0x00100000
18 orr \rv, \rp, #io_p2v(0x40000000) @ virtual 18 orr \rv, \rp, #io_p2v(0x40000000) @ virtual
19 orr \rp, \rp, #0x40000000 @ physical 19 orr \rp, \rp, #0x40000000 @ physical
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
deleted file mode 100644
index d05a59727d66..000000000000
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * arch/arm/mach-pxa/include/mach/memory.h
3 *
4 * Author: Nicolas Pitre
5 * Copyright: (C) 2001 MontaVista Software Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ASM_ARCH_MEMORY_H
13#define __ASM_ARCH_MEMORY_H
14
15/*
16 * Physical DRAM offset.
17 */
18#define PLAT_PHYS_OFFSET UL(0xa0000000)
19
20#endif
diff --git a/arch/arm/mach-pxa/littleton.c b/arch/arm/mach-pxa/littleton.c
index 8f97e15e86e5..0037e57e0cec 100644
--- a/arch/arm/mach-pxa/littleton.c
+++ b/arch/arm/mach-pxa/littleton.c
@@ -437,7 +437,7 @@ static void __init littleton_init(void)
437} 437}
438 438
439MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)") 439MACHINE_START(LITTLETON, "Marvell Form Factor Development Platform (aka Littleton)")
440 .boot_params = 0xa0000100, 440 .atag_offset = 0x100,
441 .map_io = pxa3xx_map_io, 441 .map_io = pxa3xx_map_io,
442 .nr_irqs = LITTLETON_NR_IRQS, 442 .nr_irqs = LITTLETON_NR_IRQS,
443 .init_irq = pxa3xx_init_irq, 443 .init_irq = pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/lpd270.c b/arch/arm/mach-pxa/lpd270.c
index a3acd968b44d..64540d908958 100644
--- a/arch/arm/mach-pxa/lpd270.c
+++ b/arch/arm/mach-pxa/lpd270.c
@@ -498,7 +498,7 @@ static void __init lpd270_map_io(void)
498 498
499MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine") 499MACHINE_START(LOGICPD_PXA270, "LogicPD PXA270 Card Engine")
500 /* Maintainer: Peter Barada */ 500 /* Maintainer: Peter Barada */
501 .boot_params = 0xa0000100, 501 .atag_offset = 0x100,
502 .map_io = lpd270_map_io, 502 .map_io = lpd270_map_io,
503 .nr_irqs = LPD270_NR_IRQS, 503 .nr_irqs = LPD270_NR_IRQS,
504 .init_irq = lpd270_init_irq, 504 .init_irq = lpd270_init_irq,
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 5fe5bcd7c0a1..4b796c37af3e 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -753,7 +753,7 @@ static void __init magician_init(void)
753 753
754 754
755MACHINE_START(MAGICIAN, "HTC Magician") 755MACHINE_START(MAGICIAN, "HTC Magician")
756 .boot_params = 0xa0000100, 756 .atag_offset = 0x100,
757 .map_io = pxa27x_map_io, 757 .map_io = pxa27x_map_io,
758 .nr_irqs = MAGICIAN_NR_IRQS, 758 .nr_irqs = MAGICIAN_NR_IRQS,
759 .init_irq = pxa27x_init_irq, 759 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/mainstone.c b/arch/arm/mach-pxa/mainstone.c
index 6bc784bb3696..0567d3965fda 100644
--- a/arch/arm/mach-pxa/mainstone.c
+++ b/arch/arm/mach-pxa/mainstone.c
@@ -615,7 +615,7 @@ static void __init mainstone_map_io(void)
615 615
616MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)") 616MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
617 /* Maintainer: MontaVista Software Inc. */ 617 /* Maintainer: MontaVista Software Inc. */
618 .boot_params = 0xa0000100, /* BLOB boot parameter setting */ 618 .atag_offset = 0x100, /* BLOB boot parameter setting */
619 .map_io = mainstone_map_io, 619 .map_io = mainstone_map_io,
620 .nr_irqs = MAINSTONE_NR_IRQS, 620 .nr_irqs = MAINSTONE_NR_IRQS,
621 .init_irq = mainstone_init_irq, 621 .init_irq = mainstone_init_irq,
diff --git a/arch/arm/mach-pxa/mioa701.c b/arch/arm/mach-pxa/mioa701.c
index 64810f908e5b..b938fc2c316a 100644
--- a/arch/arm/mach-pxa/mioa701.c
+++ b/arch/arm/mach-pxa/mioa701.c
@@ -751,7 +751,7 @@ static void mioa701_machine_exit(void)
751} 751}
752 752
753MACHINE_START(MIOA701, "MIO A701") 753MACHINE_START(MIOA701, "MIO A701")
754 .boot_params = 0xa0000100, 754 .atag_offset = 0x100,
755 .map_io = &pxa27x_map_io, 755 .map_io = &pxa27x_map_io,
756 .init_irq = &pxa27x_init_irq, 756 .init_irq = &pxa27x_init_irq,
757 .handle_irq = &pxa27x_handle_irq, 757 .handle_irq = &pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/mp900.c b/arch/arm/mach-pxa/mp900.c
index fb408861dbcf..4af5d513c380 100644
--- a/arch/arm/mach-pxa/mp900.c
+++ b/arch/arm/mach-pxa/mp900.c
@@ -92,7 +92,7 @@ static void __init mp900c_init(void)
92 92
93/* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */ 93/* Maintainer - Michael Petchkovsky <mkpetch@internode.on.net> */
94MACHINE_START(NEC_MP900, "MobilePro900/C") 94MACHINE_START(NEC_MP900, "MobilePro900/C")
95 .boot_params = 0xa0220100, 95 .atag_offset = 0x220100,
96 .timer = &pxa_timer, 96 .timer = &pxa_timer,
97 .map_io = pxa25x_map_io, 97 .map_io = pxa25x_map_io,
98 .init_irq = pxa25x_init_irq, 98 .init_irq = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/palmld.c b/arch/arm/mach-pxa/palmld.c
index 6b77365ed938..3d4a2819cae1 100644
--- a/arch/arm/mach-pxa/palmld.c
+++ b/arch/arm/mach-pxa/palmld.c
@@ -342,7 +342,7 @@ static void __init palmld_init(void)
342} 342}
343 343
344MACHINE_START(PALMLD, "Palm LifeDrive") 344MACHINE_START(PALMLD, "Palm LifeDrive")
345 .boot_params = 0xa0000100, 345 .atag_offset = 0x100,
346 .map_io = palmld_map_io, 346 .map_io = palmld_map_io,
347 .init_irq = pxa27x_init_irq, 347 .init_irq = pxa27x_init_irq,
348 .handle_irq = pxa27x_handle_irq, 348 .handle_irq = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/palmt5.c b/arch/arm/mach-pxa/palmt5.c
index 9bd3e47486fb..99d6bcf1f974 100644
--- a/arch/arm/mach-pxa/palmt5.c
+++ b/arch/arm/mach-pxa/palmt5.c
@@ -202,7 +202,7 @@ static void __init palmt5_init(void)
202} 202}
203 203
204MACHINE_START(PALMT5, "Palm Tungsten|T5") 204MACHINE_START(PALMT5, "Palm Tungsten|T5")
205 .boot_params = 0xa0000100, 205 .atag_offset = 0x100,
206 .map_io = pxa27x_map_io, 206 .map_io = pxa27x_map_io,
207 .reserve = palmt5_reserve, 207 .reserve = palmt5_reserve,
208 .init_irq = pxa27x_init_irq, 208 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/palmtc.c b/arch/arm/mach-pxa/palmtc.c
index 6ad4a6c7bc96..6ec7caefb37c 100644
--- a/arch/arm/mach-pxa/palmtc.c
+++ b/arch/arm/mach-pxa/palmtc.c
@@ -537,7 +537,7 @@ static void __init palmtc_init(void)
537}; 537};
538 538
539MACHINE_START(PALMTC, "Palm Tungsten|C") 539MACHINE_START(PALMTC, "Palm Tungsten|C")
540 .boot_params = 0xa0000100, 540 .atag_offset = 0x100,
541 .map_io = pxa25x_map_io, 541 .map_io = pxa25x_map_io,
542 .init_irq = pxa25x_init_irq, 542 .init_irq = pxa25x_init_irq,
543 .handle_irq = pxa25x_handle_irq, 543 .handle_irq = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/palmte2.c b/arch/arm/mach-pxa/palmte2.c
index 664232f3e62c..9376da06404c 100644
--- a/arch/arm/mach-pxa/palmte2.c
+++ b/arch/arm/mach-pxa/palmte2.c
@@ -356,7 +356,7 @@ static void __init palmte2_init(void)
356} 356}
357 357
358MACHINE_START(PALMTE2, "Palm Tungsten|E2") 358MACHINE_START(PALMTE2, "Palm Tungsten|E2")
359 .boot_params = 0xa0000100, 359 .atag_offset = 0x100,
360 .map_io = pxa25x_map_io, 360 .map_io = pxa25x_map_io,
361 .init_irq = pxa25x_init_irq, 361 .init_irq = pxa25x_init_irq,
362 .handle_irq = pxa25x_handle_irq, 362 .handle_irq = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/palmtreo.c b/arch/arm/mach-pxa/palmtreo.c
index bb27d4b688d8..7346fbfa8101 100644
--- a/arch/arm/mach-pxa/palmtreo.c
+++ b/arch/arm/mach-pxa/palmtreo.c
@@ -440,7 +440,7 @@ static void __init centro_init(void)
440} 440}
441 441
442MACHINE_START(TREO680, "Palm Treo 680") 442MACHINE_START(TREO680, "Palm Treo 680")
443 .boot_params = 0xa0000100, 443 .atag_offset = 0x100,
444 .map_io = pxa27x_map_io, 444 .map_io = pxa27x_map_io,
445 .reserve = treo_reserve, 445 .reserve = treo_reserve,
446 .init_irq = pxa27x_init_irq, 446 .init_irq = pxa27x_init_irq,
@@ -450,7 +450,7 @@ MACHINE_START(TREO680, "Palm Treo 680")
450MACHINE_END 450MACHINE_END
451 451
452MACHINE_START(CENTRO, "Palm Centro 685") 452MACHINE_START(CENTRO, "Palm Centro 685")
453 .boot_params = 0xa0000100, 453 .atag_offset = 0x100,
454 .map_io = pxa27x_map_io, 454 .map_io = pxa27x_map_io,
455 .reserve = treo_reserve, 455 .reserve = treo_reserve,
456 .init_irq = pxa27x_init_irq, 456 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/palmtx.c b/arch/arm/mach-pxa/palmtx.c
index fc4285589c1f..2b9e76fc2c90 100644
--- a/arch/arm/mach-pxa/palmtx.c
+++ b/arch/arm/mach-pxa/palmtx.c
@@ -364,7 +364,7 @@ static void __init palmtx_init(void)
364} 364}
365 365
366MACHINE_START(PALMTX, "Palm T|X") 366MACHINE_START(PALMTX, "Palm T|X")
367 .boot_params = 0xa0000100, 367 .atag_offset = 0x100,
368 .map_io = palmtx_map_io, 368 .map_io = palmtx_map_io,
369 .init_irq = pxa27x_init_irq, 369 .init_irq = pxa27x_init_irq,
370 .handle_irq = pxa27x_handle_irq, 370 .handle_irq = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/palmz72.c b/arch/arm/mach-pxa/palmz72.c
index e61c1cc05519..68e18baf8e07 100644
--- a/arch/arm/mach-pxa/palmz72.c
+++ b/arch/arm/mach-pxa/palmz72.c
@@ -399,7 +399,7 @@ static void __init palmz72_init(void)
399} 399}
400 400
401MACHINE_START(PALMZ72, "Palm Zire72") 401MACHINE_START(PALMZ72, "Palm Zire72")
402 .boot_params = 0xa0000100, 402 .atag_offset = 0x100,
403 .map_io = pxa27x_map_io, 403 .map_io = pxa27x_map_io,
404 .init_irq = pxa27x_init_irq, 404 .init_irq = pxa27x_init_irq,
405 .handle_irq = pxa27x_handle_irq, 405 .handle_irq = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/pcm027.c b/arch/arm/mach-pxa/pcm027.c
index ffa65dfb8c6f..0b825a353537 100644
--- a/arch/arm/mach-pxa/pcm027.c
+++ b/arch/arm/mach-pxa/pcm027.c
@@ -258,7 +258,7 @@ static void __init pcm027_map_io(void)
258 258
259MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270") 259MACHINE_START(PCM027, "Phytec Messtechnik GmbH phyCORE-PXA270")
260 /* Maintainer: Pengutronix */ 260 /* Maintainer: Pengutronix */
261 .boot_params = 0xa0000100, 261 .atag_offset = 0x100,
262 .map_io = pcm027_map_io, 262 .map_io = pcm027_map_io,
263 .nr_irqs = PCM027_NR_IRQS, 263 .nr_irqs = PCM027_NR_IRQS,
264 .init_irq = pxa27x_init_irq, 264 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/raumfeld.c b/arch/arm/mach-pxa/raumfeld.c
index bbcd90562ebe..6810cddec927 100644
--- a/arch/arm/mach-pxa/raumfeld.c
+++ b/arch/arm/mach-pxa/raumfeld.c
@@ -1086,7 +1086,7 @@ static void __init raumfeld_speaker_init(void)
1086 1086
1087#ifdef CONFIG_MACH_RAUMFELD_RC 1087#ifdef CONFIG_MACH_RAUMFELD_RC
1088MACHINE_START(RAUMFELD_RC, "Raumfeld Controller") 1088MACHINE_START(RAUMFELD_RC, "Raumfeld Controller")
1089 .boot_params = RAUMFELD_SDRAM_BASE + 0x100, 1089 .atag_offset = 0x100,
1090 .init_machine = raumfeld_controller_init, 1090 .init_machine = raumfeld_controller_init,
1091 .map_io = pxa3xx_map_io, 1091 .map_io = pxa3xx_map_io,
1092 .init_irq = pxa3xx_init_irq, 1092 .init_irq = pxa3xx_init_irq,
@@ -1097,7 +1097,7 @@ MACHINE_END
1097 1097
1098#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR 1098#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR
1099MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector") 1099MACHINE_START(RAUMFELD_CONNECTOR, "Raumfeld Connector")
1100 .boot_params = RAUMFELD_SDRAM_BASE + 0x100, 1100 .atag_offset = 0x100,
1101 .init_machine = raumfeld_connector_init, 1101 .init_machine = raumfeld_connector_init,
1102 .map_io = pxa3xx_map_io, 1102 .map_io = pxa3xx_map_io,
1103 .init_irq = pxa3xx_init_irq, 1103 .init_irq = pxa3xx_init_irq,
@@ -1108,7 +1108,7 @@ MACHINE_END
1108 1108
1109#ifdef CONFIG_MACH_RAUMFELD_SPEAKER 1109#ifdef CONFIG_MACH_RAUMFELD_SPEAKER
1110MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker") 1110MACHINE_START(RAUMFELD_SPEAKER, "Raumfeld Speaker")
1111 .boot_params = RAUMFELD_SDRAM_BASE + 0x100, 1111 .atag_offset = 0x100,
1112 .init_machine = raumfeld_speaker_init, 1112 .init_machine = raumfeld_speaker_init,
1113 .map_io = pxa3xx_map_io, 1113 .map_io = pxa3xx_map_io,
1114 .init_irq = pxa3xx_init_irq, 1114 .init_irq = pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/saar.c b/arch/arm/mach-pxa/saar.c
index 72001ec6e7b5..fc2c1e05af9c 100644
--- a/arch/arm/mach-pxa/saar.c
+++ b/arch/arm/mach-pxa/saar.c
@@ -596,7 +596,7 @@ static void __init saar_init(void)
596 596
597MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)") 597MACHINE_START(SAAR, "PXA930 Handheld Platform (aka SAAR)")
598 /* Maintainer: Eric Miao <eric.miao@marvell.com> */ 598 /* Maintainer: Eric Miao <eric.miao@marvell.com> */
599 .boot_params = 0xa0000100, 599 .atag_offset = 0x100,
600 .map_io = pxa3xx_map_io, 600 .map_io = pxa3xx_map_io,
601 .init_irq = pxa3xx_init_irq, 601 .init_irq = pxa3xx_init_irq,
602 .handle_irq = pxa3xx_handle_irq, 602 .handle_irq = pxa3xx_handle_irq,
diff --git a/arch/arm/mach-pxa/saarb.c b/arch/arm/mach-pxa/saarb.c
index eb6a10d85b03..3c988b6f718f 100644
--- a/arch/arm/mach-pxa/saarb.c
+++ b/arch/arm/mach-pxa/saarb.c
@@ -103,7 +103,7 @@ static void __init saarb_init(void)
103} 103}
104 104
105MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)") 105MACHINE_START(SAARB, "PXA955 Handheld Platform (aka SAARB)")
106 .boot_params = 0xa0000100, 106 .atag_offset = 0x100,
107 .map_io = pxa3xx_map_io, 107 .map_io = pxa3xx_map_io,
108 .nr_irqs = SAARB_NR_IRQS, 108 .nr_irqs = SAARB_NR_IRQS,
109 .init_irq = pxa95x_init_irq, 109 .init_irq = pxa95x_init_irq,
diff --git a/arch/arm/mach-pxa/stargate2.c b/arch/arm/mach-pxa/stargate2.c
index 3f8d0af9e2f7..4c9a48bef569 100644
--- a/arch/arm/mach-pxa/stargate2.c
+++ b/arch/arm/mach-pxa/stargate2.c
@@ -1004,7 +1004,7 @@ MACHINE_START(INTELMOTE2, "IMOTE 2")
1004 .handle_irq = pxa27x_handle_irq, 1004 .handle_irq = pxa27x_handle_irq,
1005 .timer = &pxa_timer, 1005 .timer = &pxa_timer,
1006 .init_machine = imote2_init, 1006 .init_machine = imote2_init,
1007 .boot_params = 0xA0000100, 1007 .atag_offset = 0x100,
1008MACHINE_END 1008MACHINE_END
1009#endif 1009#endif
1010 1010
@@ -1016,6 +1016,6 @@ MACHINE_START(STARGATE2, "Stargate 2")
1016 .handle_irq = pxa27x_handle_irq, 1016 .handle_irq = pxa27x_handle_irq,
1017 .timer = &pxa_timer, 1017 .timer = &pxa_timer,
1018 .init_machine = stargate2_init, 1018 .init_machine = stargate2_init,
1019 .boot_params = 0xA0000100, 1019 .atag_offset = 0x100,
1020MACHINE_END 1020MACHINE_END
1021#endif 1021#endif
diff --git a/arch/arm/mach-pxa/tavorevb.c b/arch/arm/mach-pxa/tavorevb.c
index 32fb58e01b10..ad47bb98f30d 100644
--- a/arch/arm/mach-pxa/tavorevb.c
+++ b/arch/arm/mach-pxa/tavorevb.c
@@ -489,7 +489,7 @@ static void __init tavorevb_init(void)
489 489
490MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)") 490MACHINE_START(TAVOREVB, "PXA930 Evaluation Board (aka TavorEVB)")
491 /* Maintainer: Eric Miao <eric.miao@marvell.com> */ 491 /* Maintainer: Eric Miao <eric.miao@marvell.com> */
492 .boot_params = 0xa0000100, 492 .atag_offset = 0x100,
493 .map_io = pxa3xx_map_io, 493 .map_io = pxa3xx_map_io,
494 .init_irq = pxa3xx_init_irq, 494 .init_irq = pxa3xx_init_irq,
495 .handle_irq = pxa3xx_handle_irq, 495 .handle_irq = pxa3xx_handle_irq,
diff --git a/arch/arm/mach-pxa/tavorevb3.c b/arch/arm/mach-pxa/tavorevb3.c
index fd5a8eae0a87..fd569167302a 100644
--- a/arch/arm/mach-pxa/tavorevb3.c
+++ b/arch/arm/mach-pxa/tavorevb3.c
@@ -125,7 +125,7 @@ static void __init evb3_init(void)
125} 125}
126 126
127MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)") 127MACHINE_START(TAVOREVB3, "PXA950 Evaluation Board (aka TavorEVB3)")
128 .boot_params = 0xa0000100, 128 .atag_offset = 0x100,
129 .map_io = pxa3xx_map_io, 129 .map_io = pxa3xx_map_io,
130 .nr_irqs = TAVOREVB3_NR_IRQS, 130 .nr_irqs = TAVOREVB3_NR_IRQS,
131 .init_irq = pxa3xx_init_irq, 131 .init_irq = pxa3xx_init_irq,
diff --git a/arch/arm/mach-pxa/trizeps4.c b/arch/arm/mach-pxa/trizeps4.c
index c0417508f39d..35bbf13724b9 100644
--- a/arch/arm/mach-pxa/trizeps4.c
+++ b/arch/arm/mach-pxa/trizeps4.c
@@ -554,7 +554,7 @@ static void __init trizeps4_map_io(void)
554 554
555MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module") 555MACHINE_START(TRIZEPS4, "Keith und Koep Trizeps IV module")
556 /* MAINTAINER("Jürgen Schindele") */ 556 /* MAINTAINER("Jürgen Schindele") */
557 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100, 557 .atag_offset = 0x100,
558 .init_machine = trizeps4_init, 558 .init_machine = trizeps4_init,
559 .map_io = trizeps4_map_io, 559 .map_io = trizeps4_map_io,
560 .init_irq = pxa27x_init_irq, 560 .init_irq = pxa27x_init_irq,
@@ -564,7 +564,7 @@ MACHINE_END
564 564
565MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module") 565MACHINE_START(TRIZEPS4WL, "Keith und Koep Trizeps IV-WL module")
566 /* MAINTAINER("Jürgen Schindele") */ 566 /* MAINTAINER("Jürgen Schindele") */
567 .boot_params = TRIZEPS4_SDRAM_BASE + 0x100, 567 .atag_offset = 0x100,
568 .init_machine = trizeps4_init, 568 .init_machine = trizeps4_init,
569 .map_io = trizeps4_map_io, 569 .map_io = trizeps4_map_io,
570 .init_irq = pxa27x_init_irq, 570 .init_irq = pxa27x_init_irq,
diff --git a/arch/arm/mach-pxa/viper.c b/arch/arm/mach-pxa/viper.c
index d4a3dc74e84a..242ddae332d3 100644
--- a/arch/arm/mach-pxa/viper.c
+++ b/arch/arm/mach-pxa/viper.c
@@ -992,7 +992,7 @@ static void __init viper_map_io(void)
992 992
993MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC") 993MACHINE_START(VIPER, "Arcom/Eurotech VIPER SBC")
994 /* Maintainer: Marc Zyngier <maz@misterjones.org> */ 994 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
995 .boot_params = 0xa0000100, 995 .atag_offset = 0x100,
996 .map_io = viper_map_io, 996 .map_io = viper_map_io,
997 .init_irq = viper_init_irq, 997 .init_irq = viper_init_irq,
998 .handle_irq = pxa25x_handle_irq, 998 .handle_irq = pxa25x_handle_irq,
diff --git a/arch/arm/mach-pxa/vpac270.c b/arch/arm/mach-pxa/vpac270.c
index 5f8490ab07cb..a7539a6ed1ff 100644
--- a/arch/arm/mach-pxa/vpac270.c
+++ b/arch/arm/mach-pxa/vpac270.c
@@ -716,7 +716,7 @@ static void __init vpac270_init(void)
716} 716}
717 717
718MACHINE_START(VPAC270, "Voipac PXA270") 718MACHINE_START(VPAC270, "Voipac PXA270")
719 .boot_params = 0xa0000100, 719 .atag_offset = 0x100,
720 .map_io = pxa27x_map_io, 720 .map_io = pxa27x_map_io,
721 .init_irq = pxa27x_init_irq, 721 .init_irq = pxa27x_init_irq,
722 .handle_irq = pxa27x_handle_irq, 722 .handle_irq = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/xcep.c b/arch/arm/mach-pxa/xcep.c
index 937c42845df9..70e1730ef282 100644
--- a/arch/arm/mach-pxa/xcep.c
+++ b/arch/arm/mach-pxa/xcep.c
@@ -179,7 +179,7 @@ static void __init xcep_init(void)
179} 179}
180 180
181MACHINE_START(XCEP, "Iskratel XCEP") 181MACHINE_START(XCEP, "Iskratel XCEP")
182 .boot_params = 0xa0000100, 182 .atag_offset = 0x100,
183 .init_machine = xcep_init, 183 .init_machine = xcep_init,
184 .map_io = pxa25x_map_io, 184 .map_io = pxa25x_map_io,
185 .init_irq = pxa25x_init_irq, 185 .init_irq = pxa25x_init_irq,
diff --git a/arch/arm/mach-pxa/z2.c b/arch/arm/mach-pxa/z2.c
index 6c9275a20c91..84ed72de53b5 100644
--- a/arch/arm/mach-pxa/z2.c
+++ b/arch/arm/mach-pxa/z2.c
@@ -686,7 +686,7 @@ static void z2_power_off(void)
686 */ 686 */
687 PSPR = 0x0; 687 PSPR = 0x0;
688 local_irq_disable(); 688 local_irq_disable();
689 pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PLAT_PHYS_OFFSET - PAGE_OFFSET); 689 pxa27x_cpu_suspend(PWRMODE_DEEPSLEEP, PHYS_OFFSET - PAGE_OFFSET);
690} 690}
691#else 691#else
692#define z2_power_off NULL 692#define z2_power_off NULL
@@ -718,7 +718,7 @@ static void __init z2_init(void)
718} 718}
719 719
720MACHINE_START(ZIPIT2, "Zipit Z2") 720MACHINE_START(ZIPIT2, "Zipit Z2")
721 .boot_params = 0xa0000100, 721 .atag_offset = 0x100,
722 .map_io = pxa27x_map_io, 722 .map_io = pxa27x_map_io,
723 .init_irq = pxa27x_init_irq, 723 .init_irq = pxa27x_init_irq,
724 .handle_irq = pxa27x_handle_irq, 724 .handle_irq = pxa27x_handle_irq,
diff --git a/arch/arm/mach-pxa/zeus.c b/arch/arm/mach-pxa/zeus.c
index 99c49bcd9f70..c424e7d85ce3 100644
--- a/arch/arm/mach-pxa/zeus.c
+++ b/arch/arm/mach-pxa/zeus.c
@@ -904,7 +904,7 @@ static void __init zeus_map_io(void)
904 904
905MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS") 905MACHINE_START(ARCOM_ZEUS, "Arcom/Eurotech ZEUS")
906 /* Maintainer: Marc Zyngier <maz@misterjones.org> */ 906 /* Maintainer: Marc Zyngier <maz@misterjones.org> */
907 .boot_params = 0xa0000100, 907 .atag_offset = 0x100,
908 .map_io = zeus_map_io, 908 .map_io = zeus_map_io,
909 .nr_irqs = ZEUS_NR_IRQS, 909 .nr_irqs = ZEUS_NR_IRQS,
910 .init_irq = zeus_init_irq, 910 .init_irq = zeus_init_irq,
diff --git a/arch/arm/mach-pxa/zylonite.c b/arch/arm/mach-pxa/zylonite.c
index 15ec66b3471a..31d496891891 100644
--- a/arch/arm/mach-pxa/zylonite.c
+++ b/arch/arm/mach-pxa/zylonite.c
@@ -422,7 +422,7 @@ static void __init zylonite_init(void)
422} 422}
423 423
424MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)") 424MACHINE_START(ZYLONITE, "PXA3xx Platform Development Kit (aka Zylonite)")
425 .boot_params = 0xa0000100, 425 .atag_offset = 0x100,
426 .map_io = pxa3xx_map_io, 426 .map_io = pxa3xx_map_io,
427 .nr_irqs = ZYLONITE_NR_IRQS, 427 .nr_irqs = ZYLONITE_NR_IRQS,
428 .init_irq = pxa3xx_init_irq, 428 .init_irq = pxa3xx_init_irq,
diff --git a/arch/arm/mach-realview/include/mach/debug-macro.S b/arch/arm/mach-realview/include/mach/debug-macro.S
index 90b687cbe04e..fb4901c4ef04 100644
--- a/arch/arm/mach-realview/include/mach/debug-macro.S
+++ b/arch/arm/mach-realview/include/mach/debug-macro.S
@@ -33,7 +33,7 @@
33#error "Unknown RealView platform" 33#error "Unknown RealView platform"
34#endif 34#endif
35 35
36 .macro addruart, rp, rv 36 .macro addruart, rp, rv, tmp
37 mov \rp, #DEBUG_LL_UART_OFFSET 37 mov \rp, #DEBUG_LL_UART_OFFSET
38 orr \rv, \rp, #0xfb000000 @ virtual base 38 orr \rv, \rp, #0xfb000000 @ virtual base
39 orr \rp, \rp, #0x10000000 @ physical base 39 orr \rp, \rp, #0x10000000 @ physical base
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index 7a4e3b18cb3e..026c66ad7ec2 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -463,7 +463,7 @@ static void __init realview_eb_init(void)
463 463
464MACHINE_START(REALVIEW_EB, "ARM-RealView EB") 464MACHINE_START(REALVIEW_EB, "ARM-RealView EB")
465 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 465 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
466 .boot_params = PLAT_PHYS_OFFSET + 0x00000100, 466 .atag_offset = 0x100,
467 .fixup = realview_fixup, 467 .fixup = realview_fixup,
468 .map_io = realview_eb_map_io, 468 .map_io = realview_eb_map_io,
469 .init_early = realview_init_early, 469 .init_early = realview_init_early,
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index 865d440fcf58..c057540ec776 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -386,7 +386,7 @@ static void __init realview_pb1176_init(void)
386 386
387MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176") 387MACHINE_START(REALVIEW_PB1176, "ARM-RealView PB1176")
388 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 388 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
389 .boot_params = PLAT_PHYS_OFFSET + 0x00000100, 389 .atag_offset = 0x100,
390 .fixup = realview_pb1176_fixup, 390 .fixup = realview_pb1176_fixup,
391 .map_io = realview_pb1176_map_io, 391 .map_io = realview_pb1176_map_io,
392 .init_early = realview_init_early, 392 .init_early = realview_init_early,
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index b43644b3685e..671ad6d6ff00 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -360,7 +360,7 @@ static void __init realview_pb11mp_init(void)
360 360
361MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore") 361MACHINE_START(REALVIEW_PB11MP, "ARM-RealView PB11MPCore")
362 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 362 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
363 .boot_params = PLAT_PHYS_OFFSET + 0x00000100, 363 .atag_offset = 0x100,
364 .fixup = realview_fixup, 364 .fixup = realview_fixup,
365 .map_io = realview_pb11mp_map_io, 365 .map_io = realview_pb11mp_map_io,
366 .init_early = realview_init_early, 366 .init_early = realview_init_early,
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 763e8f38c15d..cbf22df4ad5b 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -310,7 +310,7 @@ static void __init realview_pba8_init(void)
310 310
311MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8") 311MACHINE_START(REALVIEW_PBA8, "ARM-RealView PB-A8")
312 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 312 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
313 .boot_params = PLAT_PHYS_OFFSET + 0x00000100, 313 .atag_offset = 0x100,
314 .fixup = realview_fixup, 314 .fixup = realview_fixup,
315 .map_io = realview_pba8_map_io, 315 .map_io = realview_pba8_map_io,
316 .init_early = realview_init_early, 316 .init_early = realview_init_early,
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 3e1eb2eb8132..63c4114afae9 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -393,7 +393,7 @@ static void __init realview_pbx_init(void)
393 393
394MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX") 394MACHINE_START(REALVIEW_PBX, "ARM-RealView PBX")
395 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 395 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
396 .boot_params = PLAT_PHYS_OFFSET + 0x00000100, 396 .atag_offset = 0x100,
397 .fixup = realview_pbx_fixup, 397 .fixup = realview_pbx_fixup,
398 .map_io = realview_pbx_map_io, 398 .map_io = realview_pbx_map_io,
399 .init_early = realview_init_early, 399 .init_early = realview_init_early,
diff --git a/arch/arm/mach-rpc/include/mach/debug-macro.S b/arch/arm/mach-rpc/include/mach/debug-macro.S
index 85effffdc2b2..6d28cc99b124 100644
--- a/arch/arm/mach-rpc/include/mach/debug-macro.S
+++ b/arch/arm/mach-rpc/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0x00010000 15 mov \rp, #0x00010000
16 orr \rp, \rp, #0x00000fe0 16 orr \rp, \rp, #0x00000fe0
17 orr \rv, \rp, #0xe0000000 @ virtual 17 orr \rv, \rp, #0xe0000000 @ virtual
diff --git a/arch/arm/mach-rpc/riscpc.c b/arch/arm/mach-rpc/riscpc.c
index 1e0e60d04622..8559598ab767 100644
--- a/arch/arm/mach-rpc/riscpc.c
+++ b/arch/arm/mach-rpc/riscpc.c
@@ -218,7 +218,7 @@ extern struct sys_timer ioc_timer;
218 218
219MACHINE_START(RISCPC, "Acorn-RiscPC") 219MACHINE_START(RISCPC, "Acorn-RiscPC")
220 /* Maintainer: Russell King */ 220 /* Maintainer: Russell King */
221 .boot_params = 0x10000100, 221 .atag_offset = 0x100,
222 .reserve_lp0 = 1, 222 .reserve_lp0 = 1,
223 .reserve_lp1 = 1, 223 .reserve_lp1 = 1,
224 .map_io = rpc_map_io, 224 .map_io = rpc_map_io,
diff --git a/arch/arm/mach-s3c2400/include/mach/memory.h b/arch/arm/mach-s3c2400/include/mach/memory.h
deleted file mode 100644
index 3f33670dd012..000000000000
--- a/arch/arm/mach-s3c2400/include/mach/memory.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/* arch/arm/mach-s3c2400/include/mach/memory.h
2 * from arch/arm/mach-rpc/include/mach/memory.h
3 *
4 * Copyright 2007 Simtec Electronics
5 * http://armlinux.simtec.co.uk/
6 * Ben Dooks <ben@simtec.co.uk>
7 *
8 * Copyright (C) 1996,1997,1998 Russell King.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_MEMORY_H
16#define __ASM_ARCH_MEMORY_H
17
18#define PLAT_PHYS_OFFSET UL(0x0C000000)
19
20#endif
diff --git a/arch/arm/mach-s3c2410/include/mach/debug-macro.S b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
index 5882deaa56be..4135de87d1f7 100644
--- a/arch/arm/mach-s3c2410/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c2410/include/mach/debug-macro.S
@@ -19,7 +19,7 @@
19#define S3C2410_UART1_OFF (0x4000) 19#define S3C2410_UART1_OFF (0x4000)
20#define SHIFT_2440TXF (14-9) 20#define SHIFT_2440TXF (14-9)
21 21
22 .macro addruart, rp, rv 22 .macro addruart, rp, rv, tmp
23 ldr \rp, = S3C24XX_PA_UART 23 ldr \rp, = S3C24XX_PA_UART
24 ldr \rv, = S3C24XX_VA_UART 24 ldr \rv, = S3C24XX_VA_UART
25#if CONFIG_DEBUG_S3C_UART != 0 25#if CONFIG_DEBUG_S3C_UART != 0
diff --git a/arch/arm/mach-s3c2410/include/mach/memory.h b/arch/arm/mach-s3c2410/include/mach/memory.h
deleted file mode 100644
index f92b97b89c0c..000000000000
--- a/arch/arm/mach-s3c2410/include/mach/memory.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/memory.h
2 * from arch/arm/mach-rpc/include/mach/memory.h
3 *
4 * Copyright (C) 1996,1997,1998 Russell King.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#ifndef __ASM_ARCH_MEMORY_H
12#define __ASM_ARCH_MEMORY_H
13
14#define PLAT_PHYS_OFFSET UL(0x30000000)
15
16#endif
diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index dabc141243f3..79838942b0ac 100644
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -236,7 +236,7 @@ static void __init amlm5900_init(void)
236} 236}
237 237
238MACHINE_START(AML_M5900, "AML_M5900") 238MACHINE_START(AML_M5900, "AML_M5900")
239 .boot_params = S3C2410_SDRAM_PA + 0x100, 239 .atag_offset = 0x100,
240 .map_io = amlm5900_map_io, 240 .map_io = amlm5900_map_io,
241 .init_irq = s3c24xx_init_irq, 241 .init_irq = s3c24xx_init_irq,
242 .init_machine = amlm5900_init, 242 .init_machine = amlm5900_init,
diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 1e2d536adda9..a20ae1ad4062 100644
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -657,7 +657,7 @@ static void __init bast_init(void)
657 657
658MACHINE_START(BAST, "Simtec-BAST") 658MACHINE_START(BAST, "Simtec-BAST")
659 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 659 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
660 .boot_params = S3C2410_SDRAM_PA + 0x100, 660 .atag_offset = 0x100,
661 .map_io = bast_map_io, 661 .map_io = bast_map_io,
662 .init_irq = s3c24xx_init_irq, 662 .init_irq = s3c24xx_init_irq,
663 .init_machine = bast_init, 663 .init_machine = bast_init,
diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 2a2fa0620133..556c535829f0 100644
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -744,7 +744,7 @@ static void __init h1940_init(void)
744 744
745MACHINE_START(H1940, "IPAQ-H1940") 745MACHINE_START(H1940, "IPAQ-H1940")
746 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 746 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
747 .boot_params = S3C2410_SDRAM_PA + 0x100, 747 .atag_offset = 0x100,
748 .map_io = h1940_map_io, 748 .map_io = h1940_map_io,
749 .reserve = h1940_reserve, 749 .reserve = h1940_reserve,
750 .init_irq = h1940_init_irq, 750 .init_irq = h1940_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 079dcaa602d3..1dc3e3234417 100644
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -586,7 +586,7 @@ MACHINE_START(N30, "Acer-N30")
586 /* Maintainer: Christer Weinigel <christer@weinigel.se>, 586 /* Maintainer: Christer Weinigel <christer@weinigel.se>,
587 Ben Dooks <ben-linux@fluff.org> 587 Ben Dooks <ben-linux@fluff.org>
588 */ 588 */
589 .boot_params = S3C2410_SDRAM_PA + 0x100, 589 .atag_offset = 0x100,
590 .timer = &s3c24xx_timer, 590 .timer = &s3c24xx_timer,
591 .init_machine = n30_init, 591 .init_machine = n30_init,
592 .init_irq = s3c24xx_init_irq, 592 .init_irq = s3c24xx_init_irq,
@@ -596,7 +596,7 @@ MACHINE_END
596MACHINE_START(N35, "Acer-N35") 596MACHINE_START(N35, "Acer-N35")
597 /* Maintainer: Christer Weinigel <christer@weinigel.se> 597 /* Maintainer: Christer Weinigel <christer@weinigel.se>
598 */ 598 */
599 .boot_params = S3C2410_SDRAM_PA + 0x100, 599 .atag_offset = 0x100,
600 .timer = &s3c24xx_timer, 600 .timer = &s3c24xx_timer,
601 .init_machine = n30_init, 601 .init_machine = n30_init,
602 .init_irq = s3c24xx_init_irq, 602 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index 0aa16cd5acbc..f03f3fd9cec9 100644
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -116,7 +116,7 @@ static void __init otom11_init(void)
116 116
117MACHINE_START(OTOM, "Nex Vision - Otom 1.1") 117MACHINE_START(OTOM, "Nex Vision - Otom 1.1")
118 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */ 118 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
119 .boot_params = S3C2410_SDRAM_PA + 0x100, 119 .atag_offset = 0x100,
120 .map_io = otom11_map_io, 120 .map_io = otom11_map_io,
121 .init_machine = otom11_init, 121 .init_machine = otom11_init,
122 .init_irq = s3c24xx_init_irq, 122 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index f44f77531b1e..367d376deb96 100644
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -344,7 +344,7 @@ static void __init qt2410_machine_init(void)
344} 344}
345 345
346MACHINE_START(QT2410, "QT2410") 346MACHINE_START(QT2410, "QT2410")
347 .boot_params = S3C2410_SDRAM_PA + 0x100, 347 .atag_offset = 0x100,
348 .map_io = qt2410_map_io, 348 .map_io = qt2410_map_io,
349 .init_irq = s3c24xx_init_irq, 349 .init_irq = s3c24xx_init_irq,
350 .init_machine = qt2410_machine_init, 350 .init_machine = qt2410_machine_init,
diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index e17f03387aba..99c9dfdb71c7 100644
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -111,7 +111,7 @@ static void __init smdk2410_init(void)
111MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch 111MACHINE_START(SMDK2410, "SMDK2410") /* @TODO: request a new identifier and switch
112 * to SMDK2410 */ 112 * to SMDK2410 */
113 /* Maintainer: Jonas Dietsche */ 113 /* Maintainer: Jonas Dietsche */
114 .boot_params = S3C2410_SDRAM_PA + 0x100, 114 .atag_offset = 0x100,
115 .map_io = smdk2410_map_io, 115 .map_io = smdk2410_map_io,
116 .init_irq = s3c24xx_init_irq, 116 .init_irq = s3c24xx_init_irq,
117 .init_machine = smdk2410_init, 117 .init_machine = smdk2410_init,
diff --git a/arch/arm/mach-s3c2410/mach-tct_hammer.c b/arch/arm/mach-s3c2410/mach-tct_hammer.c
index 43c2b831b9e8..e0d0b6fb2800 100644
--- a/arch/arm/mach-s3c2410/mach-tct_hammer.c
+++ b/arch/arm/mach-s3c2410/mach-tct_hammer.c
@@ -146,7 +146,7 @@ static void __init tct_hammer_init(void)
146} 146}
147 147
148MACHINE_START(TCT_HAMMER, "TCT_HAMMER") 148MACHINE_START(TCT_HAMMER, "TCT_HAMMER")
149 .boot_params = S3C2410_SDRAM_PA + 0x100, 149 .atag_offset = 0x100,
150 .map_io = tct_hammer_map_io, 150 .map_io = tct_hammer_map_io,
151 .init_irq = s3c24xx_init_irq, 151 .init_irq = s3c24xx_init_irq,
152 .init_machine = tct_hammer_init, 152 .init_machine = tct_hammer_init,
diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 6ccce5a761b4..df47e8e90065 100644
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -400,7 +400,7 @@ static void __init vr1000_init(void)
400 400
401MACHINE_START(VR1000, "Thorcom-VR1000") 401MACHINE_START(VR1000, "Thorcom-VR1000")
402 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 402 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
403 .boot_params = S3C2410_SDRAM_PA + 0x100, 403 .atag_offset = 0x100,
404 .map_io = vr1000_map_io, 404 .map_io = vr1000_map_io,
405 .init_machine = vr1000_init, 405 .init_machine = vr1000_init,
406 .init_irq = s3c24xx_init_irq, 406 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2412/mach-jive.c b/arch/arm/mach-s3c2412/mach-jive.c
index 5eeb47580b0c..286ef1738c61 100644
--- a/arch/arm/mach-s3c2412/mach-jive.c
+++ b/arch/arm/mach-s3c2412/mach-jive.c
@@ -655,7 +655,7 @@ static void __init jive_machine_init(void)
655 655
656MACHINE_START(JIVE, "JIVE") 656MACHINE_START(JIVE, "JIVE")
657 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 657 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
658 .boot_params = S3C2410_SDRAM_PA + 0x100, 658 .atag_offset = 0x100,
659 659
660 .init_irq = s3c24xx_init_irq, 660 .init_irq = s3c24xx_init_irq,
661 .map_io = jive_map_io, 661 .map_io = jive_map_io,
diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 3391713e0c92..f1eec1b54932 100644
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -127,7 +127,7 @@ static void __init smdk2413_machine_init(void)
127 127
128MACHINE_START(S3C2413, "S3C2413") 128MACHINE_START(S3C2413, "S3C2413")
129 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 129 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
130 .boot_params = S3C2410_SDRAM_PA + 0x100, 130 .atag_offset = 0x100,
131 131
132 .fixup = smdk2413_fixup, 132 .fixup = smdk2413_fixup,
133 .init_irq = s3c24xx_init_irq, 133 .init_irq = s3c24xx_init_irq,
@@ -138,7 +138,7 @@ MACHINE_END
138 138
139MACHINE_START(SMDK2412, "SMDK2412") 139MACHINE_START(SMDK2412, "SMDK2412")
140 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 140 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
141 .boot_params = S3C2410_SDRAM_PA + 0x100, 141 .atag_offset = 0x100,
142 142
143 .fixup = smdk2413_fixup, 143 .fixup = smdk2413_fixup,
144 .init_irq = s3c24xx_init_irq, 144 .init_irq = s3c24xx_init_irq,
@@ -149,7 +149,7 @@ MACHINE_END
149 149
150MACHINE_START(SMDK2413, "SMDK2413") 150MACHINE_START(SMDK2413, "SMDK2413")
151 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 151 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
152 .boot_params = S3C2410_SDRAM_PA + 0x100, 152 .atag_offset = 0x100,
153 153
154 .fixup = smdk2413_fixup, 154 .fixup = smdk2413_fixup,
155 .init_irq = s3c24xx_init_irq, 155 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index b6ed4573553a..1bbb1ef5f4ff 100644
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -155,7 +155,7 @@ static void __init vstms_init(void)
155} 155}
156 156
157MACHINE_START(VSTMS, "VSTMS") 157MACHINE_START(VSTMS, "VSTMS")
158 .boot_params = S3C2410_SDRAM_PA + 0x100, 158 .atag_offset = 0x100,
159 159
160 .fixup = vstms_fixup, 160 .fixup = vstms_fixup,
161 .init_irq = s3c24xx_init_irq, 161 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index ac27ebb31c9b..a9eee531ca76 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -245,7 +245,7 @@ static void __init smdk2416_machine_init(void)
245 245
246MACHINE_START(SMDK2416, "SMDK2416") 246MACHINE_START(SMDK2416, "SMDK2416")
247 /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */ 247 /* Maintainer: Yauhen Kharuzhy <jekhor@gmail.com> */
248 .boot_params = S3C2410_SDRAM_PA + 0x100, 248 .atag_offset = 0x100,
249 249
250 .init_irq = s3c24xx_init_irq, 250 .init_irq = s3c24xx_init_irq,
251 .map_io = smdk2416_map_io, 251 .map_io = smdk2416_map_io,
diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index d7086788b1ff..74f92fc3fd04 100644
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -498,7 +498,7 @@ static void __init anubis_init(void)
498 498
499MACHINE_START(ANUBIS, "Simtec-Anubis") 499MACHINE_START(ANUBIS, "Simtec-Anubis")
500 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 500 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
501 .boot_params = S3C2410_SDRAM_PA + 0x100, 501 .atag_offset = 0x100,
502 .map_io = anubis_map_io, 502 .map_io = anubis_map_io,
503 .init_machine = anubis_init, 503 .init_machine = anubis_init,
504 .init_irq = s3c24xx_init_irq, 504 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-at2440evb.c b/arch/arm/mach-s3c2440/mach-at2440evb.c
index 6c98b789b8c6..38887ee0c784 100644
--- a/arch/arm/mach-s3c2440/mach-at2440evb.c
+++ b/arch/arm/mach-s3c2440/mach-at2440evb.c
@@ -233,7 +233,7 @@ static void __init at2440evb_init(void)
233 233
234 234
235MACHINE_START(AT2440EVB, "AT2440EVB") 235MACHINE_START(AT2440EVB, "AT2440EVB")
236 .boot_params = S3C2410_SDRAM_PA + 0x100, 236 .atag_offset = 0x100,
237 .map_io = at2440evb_map_io, 237 .map_io = at2440evb_map_io,
238 .init_machine = at2440evb_init, 238 .init_machine = at2440evb_init,
239 .init_irq = s3c24xx_init_irq, 239 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-gta02.c b/arch/arm/mach-s3c2440/mach-gta02.c
index c10ddf4ed7f1..de1e0ff46cec 100644
--- a/arch/arm/mach-s3c2440/mach-gta02.c
+++ b/arch/arm/mach-s3c2440/mach-gta02.c
@@ -595,7 +595,7 @@ static void __init gta02_machine_init(void)
595 595
596MACHINE_START(NEO1973_GTA02, "GTA02") 596MACHINE_START(NEO1973_GTA02, "GTA02")
597 /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */ 597 /* Maintainer: Nelson Castillo <arhuaco@freaks-unidos.net> */
598 .boot_params = S3C2410_SDRAM_PA + 0x100, 598 .atag_offset = 0x100,
599 .map_io = gta02_map_io, 599 .map_io = gta02_map_io,
600 .init_irq = s3c24xx_init_irq, 600 .init_irq = s3c24xx_init_irq,
601 .init_machine = gta02_machine_init, 601 .init_machine = gta02_machine_init,
diff --git a/arch/arm/mach-s3c2440/mach-mini2440.c b/arch/arm/mach-s3c2440/mach-mini2440.c
index fc2dc0b3d4fe..91fe0b4c95f1 100644
--- a/arch/arm/mach-s3c2440/mach-mini2440.c
+++ b/arch/arm/mach-s3c2440/mach-mini2440.c
@@ -676,7 +676,7 @@ static void __init mini2440_init(void)
676 676
677MACHINE_START(MINI2440, "MINI2440") 677MACHINE_START(MINI2440, "MINI2440")
678 /* Maintainer: Michel Pollet <buserror@gmail.com> */ 678 /* Maintainer: Michel Pollet <buserror@gmail.com> */
679 .boot_params = S3C2410_SDRAM_PA + 0x100, 679 .atag_offset = 0x100,
680 .map_io = mini2440_map_io, 680 .map_io = mini2440_map_io,
681 .init_machine = mini2440_init, 681 .init_machine = mini2440_init,
682 .init_irq = s3c24xx_init_irq, 682 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 37dd306fb7dc..61c0bf148165 100644
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -151,7 +151,7 @@ static void __init nexcoder_init(void)
151 151
152MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440") 152MACHINE_START(NEXCODER_2440, "NexVision - Nexcoder 2440")
153 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */ 153 /* Maintainer: Guillaume GOURAT <guillaume.gourat@nexvision.tv> */
154 .boot_params = S3C2410_SDRAM_PA + 0x100, 154 .atag_offset = 0x100,
155 .map_io = nexcoder_map_io, 155 .map_io = nexcoder_map_io,
156 .init_machine = nexcoder_init, 156 .init_machine = nexcoder_init,
157 .init_irq = s3c24xx_init_irq, 157 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index d88536393310..dc142ebf8cba 100644
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -447,7 +447,7 @@ static void __init osiris_init(void)
447 447
448MACHINE_START(OSIRIS, "Simtec-OSIRIS") 448MACHINE_START(OSIRIS, "Simtec-OSIRIS")
449 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */ 449 /* Maintainer: Ben Dooks <ben@simtec.co.uk> */
450 .boot_params = S3C2410_SDRAM_PA + 0x100, 450 .atag_offset = 0x100,
451 .map_io = osiris_map_io, 451 .map_io = osiris_map_io,
452 .init_irq = s3c24xx_init_irq, 452 .init_irq = s3c24xx_init_irq,
453 .init_machine = osiris_init, 453 .init_machine = osiris_init,
diff --git a/arch/arm/mach-s3c2440/mach-rx1950.c b/arch/arm/mach-s3c2440/mach-rx1950.c
index 27ea95096fe1..684dbb3567f5 100644
--- a/arch/arm/mach-s3c2440/mach-rx1950.c
+++ b/arch/arm/mach-s3c2440/mach-rx1950.c
@@ -825,7 +825,7 @@ static void __init rx1950_reserve(void)
825 825
826MACHINE_START(RX1950, "HP iPAQ RX1950") 826MACHINE_START(RX1950, "HP iPAQ RX1950")
827 /* Maintainers: Vasily Khoruzhick */ 827 /* Maintainers: Vasily Khoruzhick */
828 .boot_params = S3C2410_SDRAM_PA + 0x100, 828 .atag_offset = 0x100,
829 .map_io = rx1950_map_io, 829 .map_io = rx1950_map_io,
830 .reserve = rx1950_reserve, 830 .reserve = rx1950_reserve,
831 .init_irq = s3c24xx_init_irq, 831 .init_irq = s3c24xx_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 1472b1a5b2fb..e19499c2f909 100644
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -218,7 +218,7 @@ static void __init rx3715_init_machine(void)
218 218
219MACHINE_START(RX3715, "IPAQ-RX3715") 219MACHINE_START(RX3715, "IPAQ-RX3715")
220 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 220 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
221 .boot_params = S3C2410_SDRAM_PA + 0x100, 221 .atag_offset = 0x100,
222 .map_io = rx3715_map_io, 222 .map_io = rx3715_map_io,
223 .reserve = rx3715_reserve, 223 .reserve = rx3715_reserve,
224 .init_irq = rx3715_init_irq, 224 .init_irq = rx3715_init_irq,
diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index eedfe0f11643..36eeb4197a84 100644
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -175,7 +175,7 @@ static void __init smdk2440_machine_init(void)
175 175
176MACHINE_START(S3C2440, "SMDK2440") 176MACHINE_START(S3C2440, "SMDK2440")
177 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 177 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
178 .boot_params = S3C2410_SDRAM_PA + 0x100, 178 .atag_offset = 0x100,
179 179
180 .init_irq = s3c24xx_init_irq, 180 .init_irq = s3c24xx_init_irq,
181 .map_io = smdk2440_map_io, 181 .map_io = smdk2440_map_io,
diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index 514275e43ca0..bec107e00441 100644
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -139,7 +139,7 @@ static void __init smdk2443_machine_init(void)
139 139
140MACHINE_START(SMDK2443, "SMDK2443") 140MACHINE_START(SMDK2443, "SMDK2443")
141 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 141 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
142 .boot_params = S3C2410_SDRAM_PA + 0x100, 142 .atag_offset = 0x100,
143 143
144 .init_irq = s3c24xx_init_irq, 144 .init_irq = s3c24xx_init_irq,
145 .map_io = smdk2443_map_io, 145 .map_io = smdk2443_map_io,
diff --git a/arch/arm/mach-s3c64xx/cpu.c b/arch/arm/mach-s3c64xx/cpu.c
index 374e45e566b8..8dc05763a7eb 100644
--- a/arch/arm/mach-s3c64xx/cpu.c
+++ b/arch/arm/mach-s3c64xx/cpu.c
@@ -20,6 +20,7 @@
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/io.h> 22#include <linux/io.h>
23#include <linux/dma-mapping.h>
23 24
24#include <mach/hardware.h> 25#include <mach/hardware.h>
25#include <mach/map.h> 26#include <mach/map.h>
@@ -145,6 +146,7 @@ void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
145 /* initialise the io descriptors we need for initialisation */ 146 /* initialise the io descriptors we need for initialisation */
146 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc)); 147 iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
147 iotable_init(mach_desc, size); 148 iotable_init(mach_desc, size);
149 init_consistent_dma_size(SZ_8M);
148 150
149 idcode = __raw_readl(S3C_VA_SYS + 0x118); 151 idcode = __raw_readl(S3C_VA_SYS + 0x118);
150 if (!idcode) { 152 if (!idcode) {
diff --git a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
index a29e70550c70..c0c076a90f27 100644
--- a/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
+++ b/arch/arm/mach-s3c64xx/include/mach/debug-macro.S
@@ -21,7 +21,7 @@
21 * aligned and add in the offset when we load the value here. 21 * aligned and add in the offset when we load the value here.
22 */ 22 */
23 23
24 .macro addruart, rp, rv 24 .macro addruart, rp, rv, tmp
25 ldr \rp, = S3C_PA_UART 25 ldr \rp, = S3C_PA_UART
26 ldr \rv, = (S3C_VA_UART + S3C_PA_UART & 0xfffff) 26 ldr \rv, = (S3C_VA_UART + S3C_PA_UART & 0xfffff)
27#if CONFIG_DEBUG_S3C_UART != 0 27#if CONFIG_DEBUG_S3C_UART != 0
diff --git a/arch/arm/mach-s3c64xx/include/mach/memory.h b/arch/arm/mach-s3c64xx/include/mach/memory.h
deleted file mode 100644
index 4760cdae1eb6..000000000000
--- a/arch/arm/mach-s3c64xx/include/mach/memory.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/* arch/arm/mach-s3c6400/include/mach/memory.h
2 *
3 * Copyright 2008 Openmoko, Inc.
4 * Copyright 2008 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 * http://armlinux.simtec.co.uk/
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PLAT_PHYS_OFFSET UL(0x50000000)
17
18#define CONSISTENT_DMA_SIZE SZ_8M
19
20#endif
diff --git a/arch/arm/mach-s3c64xx/mach-anw6410.c b/arch/arm/mach-s3c64xx/mach-anw6410.c
index cb8864327ac4..d164a282bfb4 100644
--- a/arch/arm/mach-s3c64xx/mach-anw6410.c
+++ b/arch/arm/mach-s3c64xx/mach-anw6410.c
@@ -233,7 +233,7 @@ static void __init anw6410_machine_init(void)
233 233
234MACHINE_START(ANW6410, "A&W6410") 234MACHINE_START(ANW6410, "A&W6410")
235 /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */ 235 /* Maintainer: Kwangwoo Lee <kwangwoo.lee@gmail.com> */
236 .boot_params = S3C64XX_PA_SDRAM + 0x100, 236 .atag_offset = 0x100,
237 237
238 .init_irq = s3c6410_init_irq, 238 .init_irq = s3c6410_init_irq,
239 .map_io = anw6410_map_io, 239 .map_io = anw6410_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-crag6410.c b/arch/arm/mach-s3c64xx/mach-crag6410.c
index af0c2fe1ea37..4c76e08423fb 100644
--- a/arch/arm/mach-s3c64xx/mach-crag6410.c
+++ b/arch/arm/mach-s3c64xx/mach-crag6410.c
@@ -766,7 +766,7 @@ static void __init crag6410_machine_init(void)
766 766
767MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410") 767MACHINE_START(WLF_CRAGG_6410, "Wolfson Cragganmore 6410")
768 /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */ 768 /* Maintainer: Mark Brown <broonie@opensource.wolfsonmicro.com> */
769 .boot_params = S3C64XX_PA_SDRAM + 0x100, 769 .atag_offset = 0x100,
770 .init_irq = s3c6410_init_irq, 770 .init_irq = s3c6410_init_irq,
771 .map_io = crag6410_map_io, 771 .map_io = crag6410_map_io,
772 .init_machine = crag6410_machine_init, 772 .init_machine = crag6410_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
index b3d93cc8dde0..19a0887e1c1e 100644
--- a/arch/arm/mach-s3c64xx/mach-hmt.c
+++ b/arch/arm/mach-s3c64xx/mach-hmt.c
@@ -265,7 +265,7 @@ static void __init hmt_machine_init(void)
265 265
266MACHINE_START(HMT, "Airgoo-HMT") 266MACHINE_START(HMT, "Airgoo-HMT")
267 /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */ 267 /* Maintainer: Peter Korsgaard <jacmet@sunsite.dk> */
268 .boot_params = S3C64XX_PA_SDRAM + 0x100, 268 .atag_offset = 0x100,
269 .init_irq = s3c6410_init_irq, 269 .init_irq = s3c6410_init_irq,
270 .map_io = hmt_map_io, 270 .map_io = hmt_map_io,
271 .init_machine = hmt_machine_init, 271 .init_machine = hmt_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-mini6410.c b/arch/arm/mach-s3c64xx/mach-mini6410.c
index 527f49bd1b57..e91f63f7a490 100644
--- a/arch/arm/mach-s3c64xx/mach-mini6410.c
+++ b/arch/arm/mach-s3c64xx/mach-mini6410.c
@@ -349,7 +349,7 @@ static void __init mini6410_machine_init(void)
349 349
350MACHINE_START(MINI6410, "MINI6410") 350MACHINE_START(MINI6410, "MINI6410")
351 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */ 351 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
352 .boot_params = S3C64XX_PA_SDRAM + 0x100, 352 .atag_offset = 0x100,
353 .init_irq = s3c6410_init_irq, 353 .init_irq = s3c6410_init_irq,
354 .map_io = mini6410_map_io, 354 .map_io = mini6410_map_io,
355 .init_machine = mini6410_machine_init, 355 .init_machine = mini6410_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-ncp.c b/arch/arm/mach-s3c64xx/mach-ncp.c
index 01c6857c5b63..c30f2e5e0d85 100644
--- a/arch/arm/mach-s3c64xx/mach-ncp.c
+++ b/arch/arm/mach-s3c64xx/mach-ncp.c
@@ -97,7 +97,7 @@ static void __init ncp_machine_init(void)
97 97
98MACHINE_START(NCP, "NCP") 98MACHINE_START(NCP, "NCP")
99 /* Maintainer: Samsung Electronics */ 99 /* Maintainer: Samsung Electronics */
100 .boot_params = S3C64XX_PA_SDRAM + 0x100, 100 .atag_offset = 0x100,
101 .init_irq = s3c6410_init_irq, 101 .init_irq = s3c6410_init_irq,
102 .map_io = ncp_map_io, 102 .map_io = ncp_map_io,
103 .init_machine = ncp_machine_init, 103 .init_machine = ncp_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-real6410.c b/arch/arm/mach-s3c64xx/mach-real6410.c
index 95b04b1729e3..10870cb5b39e 100644
--- a/arch/arm/mach-s3c64xx/mach-real6410.c
+++ b/arch/arm/mach-s3c64xx/mach-real6410.c
@@ -329,7 +329,7 @@ static void __init real6410_machine_init(void)
329 329
330MACHINE_START(REAL6410, "REAL6410") 330MACHINE_START(REAL6410, "REAL6410")
331 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */ 331 /* Maintainer: Darius Augulis <augulis.darius@gmail.com> */
332 .boot_params = S3C64XX_PA_SDRAM + 0x100, 332 .atag_offset = 0x100,
333 333
334 .init_irq = s3c6410_init_irq, 334 .init_irq = s3c6410_init_irq,
335 .map_io = real6410_map_io, 335 .map_io = real6410_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
index 342e8dfddf8b..cbb57ded3d95 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq5.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
@@ -146,7 +146,7 @@ static void __init smartq5_machine_init(void)
146 146
147MACHINE_START(SMARTQ5, "SmartQ 5") 147MACHINE_START(SMARTQ5, "SmartQ 5")
148 /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ 148 /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
149 .boot_params = S3C64XX_PA_SDRAM + 0x100, 149 .atag_offset = 0x100,
150 .init_irq = s3c6410_init_irq, 150 .init_irq = s3c6410_init_irq,
151 .map_io = smartq_map_io, 151 .map_io = smartq_map_io,
152 .init_machine = smartq5_machine_init, 152 .init_machine = smartq5_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
index 57963977da8e..04f914b85fdf 100644
--- a/arch/arm/mach-s3c64xx/mach-smartq7.c
+++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
@@ -162,7 +162,7 @@ static void __init smartq7_machine_init(void)
162 162
163MACHINE_START(SMARTQ7, "SmartQ 7") 163MACHINE_START(SMARTQ7, "SmartQ 7")
164 /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */ 164 /* Maintainer: Maurus Cuelenaere <mcuelenaere AT gmail DOT com> */
165 .boot_params = S3C64XX_PA_SDRAM + 0x100, 165 .atag_offset = 0x100,
166 .init_irq = s3c6410_init_irq, 166 .init_irq = s3c6410_init_irq,
167 .map_io = smartq_map_io, 167 .map_io = smartq_map_io,
168 .init_machine = smartq7_machine_init, 168 .init_machine = smartq7_machine_init,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6400.c b/arch/arm/mach-s3c64xx/mach-smdk6400.c
index 3cca642f1e6d..6fd5e95f8f75 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6400.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6400.c
@@ -85,7 +85,7 @@ static void __init smdk6400_machine_init(void)
85 85
86MACHINE_START(SMDK6400, "SMDK6400") 86MACHINE_START(SMDK6400, "SMDK6400")
87 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 87 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
88 .boot_params = S3C64XX_PA_SDRAM + 0x100, 88 .atag_offset = 0x100,
89 89
90 .init_irq = s3c6400_init_irq, 90 .init_irq = s3c6400_init_irq,
91 .map_io = smdk6400_map_io, 91 .map_io = smdk6400_map_io,
diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
index a9f3183e0290..7b66ede9fbcd 100644
--- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
+++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
@@ -703,7 +703,7 @@ static void __init smdk6410_machine_init(void)
703 703
704MACHINE_START(SMDK6410, "SMDK6410") 704MACHINE_START(SMDK6410, "SMDK6410")
705 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */ 705 /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
706 .boot_params = S3C64XX_PA_SDRAM + 0x100, 706 .atag_offset = 0x100,
707 707
708 .init_irq = s3c6410_init_irq, 708 .init_irq = s3c6410_init_irq,
709 .map_io = smdk6410_map_io, 709 .map_io = smdk6410_map_io,
diff --git a/arch/arm/mach-s5p64x0/cpu.c b/arch/arm/mach-s5p64x0/cpu.c
index a5c00952ea35..8a938542c54d 100644
--- a/arch/arm/mach-s5p64x0/cpu.c
+++ b/arch/arm/mach-s5p64x0/cpu.c
@@ -20,6 +20,7 @@
20#include <linux/serial_core.h> 20#include <linux/serial_core.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/sched.h> 22#include <linux/sched.h>
23#include <linux/dma-mapping.h>
23 24
24#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 26#include <asm/mach/map.h>
@@ -111,6 +112,7 @@ void __init s5p6440_map_io(void)
111 112
112 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); 113 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
113 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc)); 114 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
115 init_consistent_dma_size(SZ_8M);
114} 116}
115 117
116void __init s5p6450_map_io(void) 118void __init s5p6450_map_io(void)
@@ -120,6 +122,7 @@ void __init s5p6450_map_io(void)
120 122
121 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); 123 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
122 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); 124 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
125 init_consistent_dma_size(SZ_8M);
123} 126}
124 127
125/* 128/*
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
index 79b04e6a6f8e..e80ba3c69814 100644
--- a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
@@ -15,7 +15,7 @@
15 15
16#include <plat/regs-serial.h> 16#include <plat/regs-serial.h>
17 17
18 .macro addruart, rp, rv 18 .macro addruart, rp, rv, tmp
19 mov \rp, #0xE0000000 19 mov \rp, #0xE0000000
20 orr \rp, \rp, #0x00100000 20 orr \rp, \rp, #0x00100000
21 ldr \rp, [\rp, #0x118 ] 21 ldr \rp, [\rp, #0x118 ]
diff --git a/arch/arm/mach-s5p64x0/include/mach/memory.h b/arch/arm/mach-s5p64x0/include/mach/memory.h
deleted file mode 100644
index 365a6eb4b88f..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/memory.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/memory.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Memory definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H __FILE__
15
16#define PLAT_PHYS_OFFSET UL(0x20000000)
17#define CONSISTENT_DMA_SIZE SZ_8M
18
19#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
index 346f8dfa6f35..3b84e9bfd073 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6440.c
@@ -171,7 +171,7 @@ static void __init smdk6440_machine_init(void)
171 171
172MACHINE_START(SMDK6440, "SMDK6440") 172MACHINE_START(SMDK6440, "SMDK6440")
173 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 173 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
174 .boot_params = S5P64X0_PA_SDRAM + 0x100, 174 .atag_offset = 0x100,
175 175
176 .init_irq = s5p6440_init_irq, 176 .init_irq = s5p6440_init_irq,
177 .map_io = smdk6440_map_io, 177 .map_io = smdk6440_map_io,
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
index 33f2adf8f3fe..d99d29b5558e 100644
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ b/arch/arm/mach-s5p64x0/mach-smdk6450.c
@@ -190,7 +190,7 @@ static void __init smdk6450_machine_init(void)
190 190
191MACHINE_START(SMDK6450, "SMDK6450") 191MACHINE_START(SMDK6450, "SMDK6450")
192 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 192 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
193 .boot_params = S5P64X0_PA_SDRAM + 0x100, 193 .atag_offset = 0x100,
194 194
195 .init_irq = s5p6450_init_irq, 195 .init_irq = s5p6450_init_irq,
196 .map_io = smdk6450_map_io, 196 .map_io = smdk6450_map_io,
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
index b2ba95ddf8e0..694f75937000 100644
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
@@ -22,7 +22,7 @@
22 * aligned and add in the offset when we load the value here. 22 * aligned and add in the offset when we load the value here.
23 */ 23 */
24 24
25 .macro addruart, rp, rv 25 .macro addruart, rp, rv, tmp
26 ldr \rp, = S3C_PA_UART 26 ldr \rp, = S3C_PA_UART
27 ldr \rv, = S3C_VA_UART 27 ldr \rv, = S3C_VA_UART
28#if CONFIG_DEBUG_S3C_UART != 0 28#if CONFIG_DEBUG_S3C_UART != 0
diff --git a/arch/arm/mach-s5pc100/include/mach/memory.h b/arch/arm/mach-s5pc100/include/mach/memory.h
deleted file mode 100644
index bda4e79fd5fc..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/memory.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* arch/arm/mach-s5pc100/include/mach/memory.h
2 *
3 * Copyright 2008 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * Based on mach-s3c6400/include/mach/memory.h
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MEMORY_H
14#define __ASM_ARCH_MEMORY_H
15
16#define PLAT_PHYS_OFFSET UL(0x20000000)
17
18#endif
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
index 227d8908aab6..688f45b7cd00 100644
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ b/arch/arm/mach-s5pc100/mach-smdkc100.c
@@ -254,7 +254,7 @@ static void __init smdkc100_machine_init(void)
254 254
255MACHINE_START(SMDKC100, "SMDKC100") 255MACHINE_START(SMDKC100, "SMDKC100")
256 /* Maintainer: Byungho Min <bhmin@samsung.com> */ 256 /* Maintainer: Byungho Min <bhmin@samsung.com> */
257 .boot_params = S5P_PA_SDRAM + 0x100, 257 .atag_offset = 0x100,
258 .init_irq = s5pc100_init_irq, 258 .init_irq = s5pc100_init_irq,
259 .map_io = smdkc100_map_io, 259 .map_io = smdkc100_map_io,
260 .init_machine = smdkc100_machine_init, 260 .init_machine = smdkc100_machine_init,
diff --git a/arch/arm/mach-s5pv210/cpu.c b/arch/arm/mach-s5pv210/cpu.c
index 79907ec78d43..91145720822c 100644
--- a/arch/arm/mach-s5pv210/cpu.c
+++ b/arch/arm/mach-s5pv210/cpu.c
@@ -20,6 +20,7 @@
20#include <linux/sysdev.h> 20#include <linux/sysdev.h>
21#include <linux/platform_device.h> 21#include <linux/platform_device.h>
22#include <linux/sched.h> 22#include <linux/sched.h>
23#include <linux/dma-mapping.h>
23 24
24#include <asm/mach/arch.h> 25#include <asm/mach/arch.h>
25#include <asm/mach/map.h> 26#include <asm/mach/map.h>
@@ -119,6 +120,7 @@ static void s5pv210_sw_reset(void)
119void __init s5pv210_map_io(void) 120void __init s5pv210_map_io(void)
120{ 121{
121 iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc)); 122 iotable_init(s5pv210_iodesc, ARRAY_SIZE(s5pv210_iodesc));
123 init_consistent_dma_size(14 << 20);
122 124
123 /* initialise device information early */ 125 /* initialise device information early */
124 s5pv210_default_sdhci0(); 126 s5pv210_default_sdhci0();
diff --git a/arch/arm/mach-s5pv210/include/mach/debug-macro.S b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
index 169fe654a59e..79e55597ab63 100644
--- a/arch/arm/mach-s5pv210/include/mach/debug-macro.S
+++ b/arch/arm/mach-s5pv210/include/mach/debug-macro.S
@@ -21,7 +21,7 @@
21 * aligned and add in the offset when we load the value here. 21 * aligned and add in the offset when we load the value here.
22 */ 22 */
23 23
24 .macro addruart, rp, rv 24 .macro addruart, rp, rv, tmp
25 ldr \rp, = S3C_PA_UART 25 ldr \rp, = S3C_PA_UART
26 ldr \rv, = S3C_VA_UART 26 ldr \rv, = S3C_VA_UART
27#if CONFIG_DEBUG_S3C_UART != 0 27#if CONFIG_DEBUG_S3C_UART != 0
diff --git a/arch/arm/mach-s5pv210/include/mach/memory.h b/arch/arm/mach-s5pv210/include/mach/memory.h
index 7b5fcf0da0c4..2d3cfa221d5f 100644
--- a/arch/arm/mach-s5pv210/include/mach/memory.h
+++ b/arch/arm/mach-s5pv210/include/mach/memory.h
@@ -14,7 +14,6 @@
14#define __ASM_ARCH_MEMORY_H 14#define __ASM_ARCH_MEMORY_H
15 15
16#define PLAT_PHYS_OFFSET UL(0x20000000) 16#define PLAT_PHYS_OFFSET UL(0x20000000)
17#define CONSISTENT_DMA_SIZE (SZ_8M + SZ_4M + SZ_2M)
18 17
19/* 18/*
20 * Sparsemem support 19 * Sparsemem support
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c
index 509627f25111..5811a96125f0 100644
--- a/arch/arm/mach-s5pv210/mach-aquila.c
+++ b/arch/arm/mach-s5pv210/mach-aquila.c
@@ -678,7 +678,7 @@ MACHINE_START(AQUILA, "Aquila")
678 /* Maintainers: 678 /* Maintainers:
679 Marek Szyprowski <m.szyprowski@samsung.com> 679 Marek Szyprowski <m.szyprowski@samsung.com>
680 Kyungmin Park <kyungmin.park@samsung.com> */ 680 Kyungmin Park <kyungmin.park@samsung.com> */
681 .boot_params = S5P_PA_SDRAM + 0x100, 681 .atag_offset = 0x100,
682 .init_irq = s5pv210_init_irq, 682 .init_irq = s5pv210_init_irq,
683 .map_io = aquila_map_io, 683 .map_io = aquila_map_io,
684 .init_machine = aquila_machine_init, 684 .init_machine = aquila_machine_init,
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c
index 85c2d51a0956..061cc7e4f48c 100644
--- a/arch/arm/mach-s5pv210/mach-goni.c
+++ b/arch/arm/mach-s5pv210/mach-goni.c
@@ -897,7 +897,7 @@ static void __init goni_machine_init(void)
897 897
898MACHINE_START(GONI, "GONI") 898MACHINE_START(GONI, "GONI")
899 /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */ 899 /* Maintainers: Kyungmin Park <kyungmin.park@samsung.com> */
900 .boot_params = S5P_PA_SDRAM + 0x100, 900 .atag_offset = 0x100,
901 .init_irq = s5pv210_init_irq, 901 .init_irq = s5pv210_init_irq,
902 .map_io = goni_map_io, 902 .map_io = goni_map_io,
903 .init_machine = goni_machine_init, 903 .init_machine = goni_machine_init,
diff --git a/arch/arm/mach-s5pv210/mach-smdkc110.c b/arch/arm/mach-s5pv210/mach-smdkc110.c
index 6c412c8ceccc..f7266bb0cac8 100644
--- a/arch/arm/mach-s5pv210/mach-smdkc110.c
+++ b/arch/arm/mach-s5pv210/mach-smdkc110.c
@@ -136,7 +136,7 @@ static void __init smdkc110_machine_init(void)
136 136
137MACHINE_START(SMDKC110, "SMDKC110") 137MACHINE_START(SMDKC110, "SMDKC110")
138 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 138 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
139 .boot_params = S5P_PA_SDRAM + 0x100, 139 .atag_offset = 0x100,
140 .init_irq = s5pv210_init_irq, 140 .init_irq = s5pv210_init_irq,
141 .map_io = smdkc110_map_io, 141 .map_io = smdkc110_map_io,
142 .init_machine = smdkc110_machine_init, 142 .init_machine = smdkc110_machine_init,
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c
index 5e011fc6720d..e73e3b6d41b5 100644
--- a/arch/arm/mach-s5pv210/mach-smdkv210.c
+++ b/arch/arm/mach-s5pv210/mach-smdkv210.c
@@ -319,7 +319,7 @@ static void __init smdkv210_machine_init(void)
319 319
320MACHINE_START(SMDKV210, "SMDKV210") 320MACHINE_START(SMDKV210, "SMDKV210")
321 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ 321 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
322 .boot_params = S5P_PA_SDRAM + 0x100, 322 .atag_offset = 0x100,
323 .init_irq = s5pv210_init_irq, 323 .init_irq = s5pv210_init_irq,
324 .map_io = smdkv210_map_io, 324 .map_io = smdkv210_map_io,
325 .init_machine = smdkv210_machine_init, 325 .init_machine = smdkv210_machine_init,
diff --git a/arch/arm/mach-s5pv210/mach-torbreck.c b/arch/arm/mach-s5pv210/mach-torbreck.c
index 925fc0dc6252..97cc066c5369 100644
--- a/arch/arm/mach-s5pv210/mach-torbreck.c
+++ b/arch/arm/mach-s5pv210/mach-torbreck.c
@@ -125,7 +125,7 @@ static void __init torbreck_machine_init(void)
125 125
126MACHINE_START(TORBRECK, "TORBRECK") 126MACHINE_START(TORBRECK, "TORBRECK")
127 /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */ 127 /* Maintainer: Hyunchul Ko <ghcstop@gmail.com> */
128 .boot_params = S5P_PA_SDRAM + 0x100, 128 .atag_offset = 0x100,
129 .init_irq = s5pv210_init_irq, 129 .init_irq = s5pv210_init_irq,
130 .map_io = torbreck_map_io, 130 .map_io = torbreck_map_io,
131 .init_machine = torbreck_machine_init, 131 .init_machine = torbreck_machine_init,
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index 6290ce28b883..3dd133f18415 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -446,7 +446,7 @@ static void __init assabet_map_io(void)
446 446
447 447
448MACHINE_START(ASSABET, "Intel-Assabet") 448MACHINE_START(ASSABET, "Intel-Assabet")
449 .boot_params = 0xc0000100, 449 .atag_offset = 0x100,
450 .fixup = fixup_assabet, 450 .fixup = fixup_assabet,
451 .map_io = assabet_map_io, 451 .map_io = assabet_map_io,
452 .init_irq = sa1100_init_irq, 452 .init_irq = sa1100_init_irq,
diff --git a/arch/arm/mach-sa1100/badge4.c b/arch/arm/mach-sa1100/badge4.c
index b4311b0a4395..bda83e1ab078 100644
--- a/arch/arm/mach-sa1100/badge4.c
+++ b/arch/arm/mach-sa1100/badge4.c
@@ -302,7 +302,7 @@ static void __init badge4_map_io(void)
302} 302}
303 303
304MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4") 304MACHINE_START(BADGE4, "Hewlett-Packard Laboratories BadgePAD 4")
305 .boot_params = 0xc0000100, 305 .atag_offset = 0x100,
306 .map_io = badge4_map_io, 306 .map_io = badge4_map_io,
307 .init_irq = sa1100_init_irq, 307 .init_irq = sa1100_init_irq,
308 .timer = &sa1100_timer, 308 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/h3100.c b/arch/arm/mach-sa1100/h3100.c
index 03d7376cf8a0..b30733a2b82e 100644
--- a/arch/arm/mach-sa1100/h3100.c
+++ b/arch/arm/mach-sa1100/h3100.c
@@ -84,7 +84,7 @@ static void __init h3100_mach_init(void)
84} 84}
85 85
86MACHINE_START(H3100, "Compaq iPAQ H3100") 86MACHINE_START(H3100, "Compaq iPAQ H3100")
87 .boot_params = 0xc0000100, 87 .atag_offset = 0x100,
88 .map_io = h3100_map_io, 88 .map_io = h3100_map_io,
89 .init_irq = sa1100_init_irq, 89 .init_irq = sa1100_init_irq,
90 .timer = &sa1100_timer, 90 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/h3600.c b/arch/arm/mach-sa1100/h3600.c
index 965f64a836f8..6fd324d92389 100644
--- a/arch/arm/mach-sa1100/h3600.c
+++ b/arch/arm/mach-sa1100/h3600.c
@@ -125,7 +125,7 @@ static void __init h3600_mach_init(void)
125} 125}
126 126
127MACHINE_START(H3600, "Compaq iPAQ H3600") 127MACHINE_START(H3600, "Compaq iPAQ H3600")
128 .boot_params = 0xc0000100, 128 .atag_offset = 0x100,
129 .map_io = h3600_map_io, 129 .map_io = h3600_map_io,
130 .init_irq = sa1100_init_irq, 130 .init_irq = sa1100_init_irq,
131 .timer = &sa1100_timer, 131 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/hackkit.c b/arch/arm/mach-sa1100/hackkit.c
index db5e434a17db..30f4a551b8e5 100644
--- a/arch/arm/mach-sa1100/hackkit.c
+++ b/arch/arm/mach-sa1100/hackkit.c
@@ -195,7 +195,7 @@ static void __init hackkit_init(void)
195 */ 195 */
196 196
197MACHINE_START(HACKKIT, "HackKit Cpu Board") 197MACHINE_START(HACKKIT, "HackKit Cpu Board")
198 .boot_params = 0xc0000100, 198 .atag_offset = 0x100,
199 .map_io = hackkit_map_io, 199 .map_io = hackkit_map_io,
200 .init_irq = sa1100_init_irq, 200 .init_irq = sa1100_init_irq,
201 .timer = &sa1100_timer, 201 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/include/mach/debug-macro.S b/arch/arm/mach-sa1100/include/mach/debug-macro.S
index 0cd0fc9635b6..530772d937ad 100644
--- a/arch/arm/mach-sa1100/include/mach/debug-macro.S
+++ b/arch/arm/mach-sa1100/include/mach/debug-macro.S
@@ -12,7 +12,7 @@
12*/ 12*/
13#include <mach/hardware.h> 13#include <mach/hardware.h>
14 14
15 .macro addruart, rp, rv 15 .macro addruart, rp, rv, tmp
16 mrc p15, 0, \rp, c1, c0 16 mrc p15, 0, \rp, c1, c0
17 tst \rp, #1 @ MMU enabled? 17 tst \rp, #1 @ MMU enabled?
18 moveq \rp, #0x80000000 @ physical base address 18 moveq \rp, #0x80000000 @ physical base address
diff --git a/arch/arm/mach-sa1100/jornada720.c b/arch/arm/mach-sa1100/jornada720.c
index 176c066aec7e..0bb520d48ed0 100644
--- a/arch/arm/mach-sa1100/jornada720.c
+++ b/arch/arm/mach-sa1100/jornada720.c
@@ -364,7 +364,7 @@ static void __init jornada720_mach_init(void)
364 364
365MACHINE_START(JORNADA720, "HP Jornada 720") 365MACHINE_START(JORNADA720, "HP Jornada 720")
366 /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */ 366 /* Maintainer: Kristoffer Ericson <Kristoffer.Ericson@gmail.com> */
367 .boot_params = 0xc0000100, 367 .atag_offset = 0x100,
368 .map_io = jornada720_map_io, 368 .map_io = jornada720_map_io,
369 .init_irq = sa1100_init_irq, 369 .init_irq = sa1100_init_irq,
370 .timer = &sa1100_timer, 370 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/lart.c b/arch/arm/mach-sa1100/lart.c
index 7b9556b59057..5bc59d0947ba 100644
--- a/arch/arm/mach-sa1100/lart.c
+++ b/arch/arm/mach-sa1100/lart.c
@@ -61,7 +61,7 @@ static void __init lart_map_io(void)
61} 61}
62 62
63MACHINE_START(LART, "LART") 63MACHINE_START(LART, "LART")
64 .boot_params = 0xc0000100, 64 .atag_offset = 0x100,
65 .map_io = lart_map_io, 65 .map_io = lart_map_io,
66 .init_irq = sa1100_init_irq, 66 .init_irq = sa1100_init_irq,
67 .init_machine = lart_init, 67 .init_machine = lart_init,
diff --git a/arch/arm/mach-sa1100/nanoengine.c b/arch/arm/mach-sa1100/nanoengine.c
index 72087f0658b7..032f3881d145 100644
--- a/arch/arm/mach-sa1100/nanoengine.c
+++ b/arch/arm/mach-sa1100/nanoengine.c
@@ -111,7 +111,7 @@ static void __init nanoengine_init(void)
111} 111}
112 112
113MACHINE_START(NANOENGINE, "BSE nanoEngine") 113MACHINE_START(NANOENGINE, "BSE nanoEngine")
114 .boot_params = 0xc0000000, 114 .atag_offset = 0x100,
115 .map_io = nanoengine_map_io, 115 .map_io = nanoengine_map_io,
116 .init_irq = sa1100_init_irq, 116 .init_irq = sa1100_init_irq,
117 .timer = &sa1100_timer, 117 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/shannon.c b/arch/arm/mach-sa1100/shannon.c
index 7917b2405579..1cccbf5b9e9a 100644
--- a/arch/arm/mach-sa1100/shannon.c
+++ b/arch/arm/mach-sa1100/shannon.c
@@ -82,7 +82,7 @@ static void __init shannon_map_io(void)
82} 82}
83 83
84MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)") 84MACHINE_START(SHANNON, "Shannon (AKA: Tuxscreen)")
85 .boot_params = 0xc0000100, 85 .atag_offset = 0x100,
86 .map_io = shannon_map_io, 86 .map_io = shannon_map_io,
87 .init_irq = sa1100_init_irq, 87 .init_irq = sa1100_init_irq,
88 .timer = &sa1100_timer, 88 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-sa1100/simpad.c b/arch/arm/mach-sa1100/simpad.c
index 34659f354bef..4790f3f3d008 100644
--- a/arch/arm/mach-sa1100/simpad.c
+++ b/arch/arm/mach-sa1100/simpad.c
@@ -392,7 +392,7 @@ arch_initcall(simpad_init);
392 392
393MACHINE_START(SIMPAD, "Simpad") 393MACHINE_START(SIMPAD, "Simpad")
394 /* Maintainer: Holger Freyther */ 394 /* Maintainer: Holger Freyther */
395 .boot_params = 0xc0000100, 395 .atag_offset = 0x100,
396 .map_io = simpad_map_io, 396 .map_io = simpad_map_io,
397 .init_irq = sa1100_init_irq, 397 .init_irq = sa1100_init_irq,
398 .timer = &sa1100_timer, 398 .timer = &sa1100_timer,
diff --git a/arch/arm/mach-shark/core.c b/arch/arm/mach-shark/core.c
index ac2873c8014b..feda3ca7fc95 100644
--- a/arch/arm/mach-shark/core.c
+++ b/arch/arm/mach-shark/core.c
@@ -152,7 +152,7 @@ static struct sys_timer shark_timer = {
152 152
153MACHINE_START(SHARK, "Shark") 153MACHINE_START(SHARK, "Shark")
154 /* Maintainer: Alexander Schulz */ 154 /* Maintainer: Alexander Schulz */
155 .boot_params = 0x08003000, 155 .atag_offset = 0x3000,
156 .map_io = shark_map_io, 156 .map_io = shark_map_io,
157 .init_irq = shark_init_irq, 157 .init_irq = shark_init_irq,
158 .timer = &shark_timer, 158 .timer = &shark_timer,
diff --git a/arch/arm/mach-shark/include/mach/debug-macro.S b/arch/arm/mach-shark/include/mach/debug-macro.S
index a473f55dc71f..20eb2bf2a42b 100644
--- a/arch/arm/mach-shark/include/mach/debug-macro.S
+++ b/arch/arm/mach-shark/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0xe0000000 15 mov \rp, #0xe0000000
16 orr \rp, \rp, #0x000003f8 16 orr \rp, \rp, #0x000003f8
17 mov \rv, \rp 17 mov \rv, \rp
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index cdfdd624d21d..5fde49da399a 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -37,6 +37,7 @@
37#include <linux/mmc/sh_mobile_sdhi.h> 37#include <linux/mmc/sh_mobile_sdhi.h>
38#include <linux/mfd/tmio.h> 38#include <linux/mfd/tmio.h>
39#include <linux/sh_clk.h> 39#include <linux/sh_clk.h>
40#include <linux/dma-mapping.h>
40#include <video/sh_mobile_lcdc.h> 41#include <video/sh_mobile_lcdc.h>
41#include <video/sh_mipi_dsi.h> 42#include <video/sh_mipi_dsi.h>
42#include <sound/sh_fsi.h> 43#include <sound/sh_fsi.h>
@@ -447,6 +448,8 @@ static struct map_desc ag5evm_io_desc[] __initdata = {
447static void __init ag5evm_map_io(void) 448static void __init ag5evm_map_io(void)
448{ 449{
449 iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc)); 450 iotable_init(ag5evm_io_desc, ARRAY_SIZE(ag5evm_io_desc));
451 /* DMA memory at 0xf6000000 - 0xffdfffff */
452 init_consistent_dma_size(158 << 20);
450 453
451 /* setup early devices and console here as well */ 454 /* setup early devices and console here as well */
452 sh73a0_add_early_devices(); 455 sh73a0_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 7e90d064ebcb..5b7edadf4647 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -43,6 +43,7 @@
43#include <linux/input/sh_keysc.h> 43#include <linux/input/sh_keysc.h>
44#include <linux/usb/r8a66597.h> 44#include <linux/usb/r8a66597.h>
45#include <linux/pm_clock.h> 45#include <linux/pm_clock.h>
46#include <linux/dma-mapping.h>
46 47
47#include <media/sh_mobile_ceu.h> 48#include <media/sh_mobile_ceu.h>
48#include <media/sh_mobile_csi2.h> 49#include <media/sh_mobile_csi2.h>
@@ -1171,6 +1172,8 @@ static struct map_desc ap4evb_io_desc[] __initdata = {
1171static void __init ap4evb_map_io(void) 1172static void __init ap4evb_map_io(void)
1172{ 1173{
1173 iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc)); 1174 iotable_init(ap4evb_io_desc, ARRAY_SIZE(ap4evb_io_desc));
1175 /* DMA memory at 0xf6000000 - 0xffdfffff */
1176 init_consistent_dma_size(158 << 20);
1174 1177
1175 /* setup early devices and console here as well */ 1178 /* setup early devices and console here as well */
1176 sh7372_add_early_devices(); 1179 sh7372_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-g3evm.c b/arch/arm/mach-shmobile/board-g3evm.c
index ef4613b993a2..8b620bf06221 100644
--- a/arch/arm/mach-shmobile/board-g3evm.c
+++ b/arch/arm/mach-shmobile/board-g3evm.c
@@ -32,6 +32,7 @@
32#include <linux/gpio.h> 32#include <linux/gpio.h>
33#include <linux/input.h> 33#include <linux/input.h>
34#include <linux/input/sh_keysc.h> 34#include <linux/input/sh_keysc.h>
35#include <linux/dma-mapping.h>
35#include <mach/sh7367.h> 36#include <mach/sh7367.h>
36#include <mach/common.h> 37#include <mach/common.h>
37#include <asm/mach-types.h> 38#include <asm/mach-types.h>
@@ -260,6 +261,8 @@ static struct map_desc g3evm_io_desc[] __initdata = {
260static void __init g3evm_map_io(void) 261static void __init g3evm_map_io(void)
261{ 262{
262 iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc)); 263 iotable_init(g3evm_io_desc, ARRAY_SIZE(g3evm_io_desc));
264 /* DMA memory at 0xf6000000 - 0xffdfffff */
265 init_consistent_dma_size(158 << 20);
263 266
264 /* setup early devices and console here as well */ 267 /* setup early devices and console here as well */
265 sh7367_add_early_devices(); 268 sh7367_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index 8e3c5559f27f..7719ddc5f591 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -33,6 +33,7 @@
33#include <linux/mmc/host.h> 33#include <linux/mmc/host.h>
34#include <linux/mmc/sh_mobile_sdhi.h> 34#include <linux/mmc/sh_mobile_sdhi.h>
35#include <linux/gpio.h> 35#include <linux/gpio.h>
36#include <linux/dma-mapping.h>
36#include <mach/sh7377.h> 37#include <mach/sh7377.h>
37#include <mach/common.h> 38#include <mach/common.h>
38#include <asm/mach-types.h> 39#include <asm/mach-types.h>
@@ -274,6 +275,8 @@ static struct map_desc g4evm_io_desc[] __initdata = {
274static void __init g4evm_map_io(void) 275static void __init g4evm_map_io(void)
275{ 276{
276 iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc)); 277 iotable_init(g4evm_io_desc, ARRAY_SIZE(g4evm_io_desc));
278 /* DMA memory at 0xf6000000 - 0xffdfffff */
279 init_consistent_dma_size(158 << 20);
277 280
278 /* setup early devices and console here as well */ 281 /* setup early devices and console here as well */
279 sh7377_add_early_devices(); 282 sh7377_add_early_devices();
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 00273dad5bf0..7d073c121941 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -45,6 +45,7 @@
45#include <linux/tca6416_keypad.h> 45#include <linux/tca6416_keypad.h>
46#include <linux/usb/r8a66597.h> 46#include <linux/usb/r8a66597.h>
47#include <linux/usb/renesas_usbhs.h> 47#include <linux/usb/renesas_usbhs.h>
48#include <linux/dma-mapping.h>
48 49
49#include <video/sh_mobile_hdmi.h> 50#include <video/sh_mobile_hdmi.h>
50#include <video/sh_mobile_lcdc.h> 51#include <video/sh_mobile_lcdc.h>
@@ -1382,6 +1383,8 @@ static struct map_desc mackerel_io_desc[] __initdata = {
1382static void __init mackerel_map_io(void) 1383static void __init mackerel_map_io(void)
1383{ 1384{
1384 iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc)); 1385 iotable_init(mackerel_io_desc, ARRAY_SIZE(mackerel_io_desc));
1386 /* DMA memory at 0xf6000000 - 0xffdfffff */
1387 init_consistent_dma_size(158 << 20);
1385 1388
1386 /* setup early devices and console here as well */ 1389 /* setup early devices and console here as well */
1387 sh7372_add_early_devices(); 1390 sh7372_add_early_devices();
diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S
index cac0a7ae2084..1a1c00ca39a2 100644
--- a/arch/arm/mach-shmobile/entry-intc.S
+++ b/arch/arm/mach-shmobile/entry-intc.S
@@ -51,7 +51,4 @@
51 .macro test_for_ipi, irqnr, irqstat, base, tmp 51 .macro test_for_ipi, irqnr, irqstat, base, tmp
52 .endm 52 .endm
53 53
54 .macro test_for_ltirq, irqnr, irqstat, base, tmp
55 .endm
56
57 arch_irq_handler shmobile_handle_irq_intc 54 arch_irq_handler shmobile_handle_irq_intc
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index d791f10eeac7..8d4a416d4285 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -27,8 +27,5 @@
27 .macro test_for_ipi, irqnr, irqstat, base, tmp 27 .macro test_for_ipi, irqnr, irqstat, base, tmp
28 .endm 28 .endm
29 29
30 .macro test_for_ltirq, irqnr, irqstat, base, tmp
31 .endm
32
33 .macro arch_ret_to_user, tmp1, tmp2 30 .macro arch_ret_to_user, tmp1, tmp2
34 .endm 31 .endm
diff --git a/arch/arm/mach-shmobile/include/mach/memory.h b/arch/arm/mach-shmobile/include/mach/memory.h
index ad00c3c258f4..0ffbe8155c76 100644
--- a/arch/arm/mach-shmobile/include/mach/memory.h
+++ b/arch/arm/mach-shmobile/include/mach/memory.h
@@ -4,7 +4,4 @@
4#define PLAT_PHYS_OFFSET UL(CONFIG_MEMORY_START) 4#define PLAT_PHYS_OFFSET UL(CONFIG_MEMORY_START)
5#define MEM_SIZE UL(CONFIG_MEMORY_SIZE) 5#define MEM_SIZE UL(CONFIG_MEMORY_SIZE)
6 6
7/* DMA memory at 0xf6000000 - 0xffdfffff */
8#define CONSISTENT_DMA_SIZE (158 << 20)
9
10#endif /* __ASM_MACH_MEMORY_H */ 7#endif /* __ASM_MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/memory.h b/arch/arm/mach-spear3xx/include/mach/memory.h
deleted file mode 100644
index 51735221ea19..000000000000
--- a/arch/arm/mach-spear3xx/include/mach/memory.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-spear3xx/include/mach/memory.h
3 *
4 * Memory map for SPEAr3xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_MEMORY_H
15#define __MACH_MEMORY_H
16
17#include <plat/memory.h>
18
19#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 69006f694220..a5ff98eed1db 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -64,7 +64,7 @@ static void __init spear300_evb_init(void)
64} 64}
65 65
66MACHINE_START(SPEAR300, "ST-SPEAR300-EVB") 66MACHINE_START(SPEAR300, "ST-SPEAR300-EVB")
67 .boot_params = 0x00000100, 67 .atag_offset = 0x100,
68 .map_io = spear3xx_map_io, 68 .map_io = spear3xx_map_io,
69 .init_irq = spear3xx_init_irq, 69 .init_irq = spear3xx_init_irq,
70 .timer = &spear3xx_timer, 70 .timer = &spear3xx_timer,
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index c8684ce1f9b3..45d180d59362 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -70,7 +70,7 @@ static void __init spear310_evb_init(void)
70} 70}
71 71
72MACHINE_START(SPEAR310, "ST-SPEAR310-EVB") 72MACHINE_START(SPEAR310, "ST-SPEAR310-EVB")
73 .boot_params = 0x00000100, 73 .atag_offset = 0x100,
74 .map_io = spear3xx_map_io, 74 .map_io = spear3xx_map_io,
75 .init_irq = spear3xx_init_irq, 75 .init_irq = spear3xx_init_irq,
76 .timer = &spear3xx_timer, 76 .timer = &spear3xx_timer,
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index a12b353940d6..22879848d73a 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -68,7 +68,7 @@ static void __init spear320_evb_init(void)
68} 68}
69 69
70MACHINE_START(SPEAR320, "ST-SPEAR320-EVB") 70MACHINE_START(SPEAR320, "ST-SPEAR320-EVB")
71 .boot_params = 0x00000100, 71 .atag_offset = 0x100,
72 .map_io = spear3xx_map_io, 72 .map_io = spear3xx_map_io,
73 .init_irq = spear3xx_init_irq, 73 .init_irq = spear3xx_init_irq,
74 .timer = &spear3xx_timer, 74 .timer = &spear3xx_timer,
diff --git a/arch/arm/mach-spear6xx/include/mach/memory.h b/arch/arm/mach-spear6xx/include/mach/memory.h
deleted file mode 100644
index 781f088fc228..000000000000
--- a/arch/arm/mach-spear6xx/include/mach/memory.h
+++ /dev/null
@@ -1,19 +0,0 @@
1/*
2 * arch/arm/mach-spear6xx/include/mach/memory.h
3 *
4 * Memory map for SPEAr6xx machine family
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Rajeev Kumar<rajeev-dlh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __MACH_MEMORY_H
15#define __MACH_MEMORY_H
16
17#include <plat/memory.h>
18
19#endif /* __MACH_MEMORY_H */
diff --git a/arch/arm/mach-spear6xx/spear600_evb.c b/arch/arm/mach-spear6xx/spear600_evb.c
index f19cefe91a2b..8238fe38e713 100644
--- a/arch/arm/mach-spear6xx/spear600_evb.c
+++ b/arch/arm/mach-spear6xx/spear600_evb.c
@@ -43,7 +43,7 @@ static void __init spear600_evb_init(void)
43} 43}
44 44
45MACHINE_START(SPEAR600, "ST-SPEAR600-EVB") 45MACHINE_START(SPEAR600, "ST-SPEAR600-EVB")
46 .boot_params = 0x00000100, 46 .atag_offset = 0x100,
47 .map_io = spear6xx_map_io, 47 .map_io = spear6xx_map_io,
48 .init_irq = spear6xx_init_irq, 48 .init_irq = spear6xx_init_irq,
49 .timer = &spear6xx_timer, 49 .timer = &spear6xx_timer,
diff --git a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
index 4cb3c2dd905c..777a5bb9eed2 100644
--- a/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
+++ b/arch/arm/mach-tcc8k/board-tcc8000-sdk.c
@@ -73,7 +73,7 @@ static void __init tcc8k_map_io(void)
73} 73}
74 74
75MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board") 75MACHINE_START(TCC8000_SDK, "Telechips TCC8000-SDK Demo Board")
76 .boot_params = PLAT_PHYS_OFFSET + 0x00000100, 76 .atag_offset = 0x100,
77 .map_io = tcc8k_map_io, 77 .map_io = tcc8k_map_io,
78 .init_irq = tcc8k_init_irq, 78 .init_irq = tcc8k_init_irq,
79 .init_machine = tcc8k_init, 79 .init_machine = tcc8k_init,
diff --git a/arch/arm/mach-tegra/board-harmony.c b/arch/arm/mach-tegra/board-harmony.c
index c78ce41cca16..93c793f48caf 100644
--- a/arch/arm/mach-tegra/board-harmony.c
+++ b/arch/arm/mach-tegra/board-harmony.c
@@ -179,7 +179,7 @@ static void __init tegra_harmony_init(void)
179} 179}
180 180
181MACHINE_START(HARMONY, "harmony") 181MACHINE_START(HARMONY, "harmony")
182 .boot_params = 0x00000100, 182 .atag_offset = 0x100,
183 .fixup = tegra_harmony_fixup, 183 .fixup = tegra_harmony_fixup,
184 .map_io = tegra_map_common_io, 184 .map_io = tegra_map_common_io,
185 .init_early = tegra_init_early, 185 .init_early = tegra_init_early,
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c
index 5e6bc7719642..fbc9e0ed926e 100644
--- a/arch/arm/mach-tegra/board-paz00.c
+++ b/arch/arm/mach-tegra/board-paz00.c
@@ -127,7 +127,7 @@ static void __init tegra_paz00_init(void)
127} 127}
128 128
129MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ") 129MACHINE_START(PAZ00, "Toshiba AC100 / Dynabook AZ")
130 .boot_params = 0x00000100, 130 .atag_offset = 0x100,
131 .fixup = tegra_paz00_fixup, 131 .fixup = tegra_paz00_fixup,
132 .map_io = tegra_map_common_io, 132 .map_io = tegra_map_common_io,
133 .init_early = tegra_init_early, 133 .init_early = tegra_init_early,
diff --git a/arch/arm/mach-tegra/board-seaboard.c b/arch/arm/mach-tegra/board-seaboard.c
index 56cbabf6aa68..9e98ac706f40 100644
--- a/arch/arm/mach-tegra/board-seaboard.c
+++ b/arch/arm/mach-tegra/board-seaboard.c
@@ -201,7 +201,7 @@ static void __init tegra_wario_init(void)
201 201
202 202
203MACHINE_START(SEABOARD, "seaboard") 203MACHINE_START(SEABOARD, "seaboard")
204 .boot_params = 0x00000100, 204 .atag_offset = 0x100,
205 .map_io = tegra_map_common_io, 205 .map_io = tegra_map_common_io,
206 .init_early = tegra_init_early, 206 .init_early = tegra_init_early,
207 .init_irq = tegra_init_irq, 207 .init_irq = tegra_init_irq,
@@ -210,7 +210,7 @@ MACHINE_START(SEABOARD, "seaboard")
210MACHINE_END 210MACHINE_END
211 211
212MACHINE_START(KAEN, "kaen") 212MACHINE_START(KAEN, "kaen")
213 .boot_params = 0x00000100, 213 .atag_offset = 0x100,
214 .map_io = tegra_map_common_io, 214 .map_io = tegra_map_common_io,
215 .init_early = tegra_init_early, 215 .init_early = tegra_init_early,
216 .init_irq = tegra_init_irq, 216 .init_irq = tegra_init_irq,
@@ -219,7 +219,7 @@ MACHINE_START(KAEN, "kaen")
219MACHINE_END 219MACHINE_END
220 220
221MACHINE_START(WARIO, "wario") 221MACHINE_START(WARIO, "wario")
222 .boot_params = 0x00000100, 222 .atag_offset = 0x100,
223 .map_io = tegra_map_common_io, 223 .map_io = tegra_map_common_io,
224 .init_early = tegra_init_early, 224 .init_early = tegra_init_early,
225 .init_irq = tegra_init_irq, 225 .init_irq = tegra_init_irq,
diff --git a/arch/arm/mach-tegra/board-trimslice.c b/arch/arm/mach-tegra/board-trimslice.c
index 652c3404d0e2..e3d9ec2f0fe1 100644
--- a/arch/arm/mach-tegra/board-trimslice.c
+++ b/arch/arm/mach-tegra/board-trimslice.c
@@ -171,7 +171,7 @@ static void __init tegra_trimslice_init(void)
171} 171}
172 172
173MACHINE_START(TRIMSLICE, "trimslice") 173MACHINE_START(TRIMSLICE, "trimslice")
174 .boot_params = 0x00000100, 174 .atag_offset = 0x100,
175 .fixup = tegra_trimslice_fixup, 175 .fixup = tegra_trimslice_fixup,
176 .map_io = tegra_map_common_io, 176 .map_io = tegra_map_common_io,
177 .init_early = tegra_init_early, 177 .init_early = tegra_init_early,
diff --git a/arch/arm/mach-tegra/include/mach/debug-macro.S b/arch/arm/mach-tegra/include/mach/debug-macro.S
index e0ebe65c1657..619abc63aee8 100644
--- a/arch/arm/mach-tegra/include/mach/debug-macro.S
+++ b/arch/arm/mach-tegra/include/mach/debug-macro.S
@@ -21,7 +21,7 @@
21#include <mach/io.h> 21#include <mach/io.h>
22#include <mach/iomap.h> 22#include <mach/iomap.h>
23 23
24 .macro addruart, rp, rv 24 .macro addruart, rp, rv, tmp
25 ldr \rp, =IO_APB_PHYS @ physical 25 ldr \rp, =IO_APB_PHYS @ physical
26 ldr \rv, =IO_APB_VIRT @ virtual 26 ldr \rv, =IO_APB_VIRT @ virtual
27 orr \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF) 27 orr \rp, \rp, #(TEGRA_DEBUG_UART_BASE & 0xFF)
diff --git a/arch/arm/mach-tegra/include/mach/memory.h b/arch/arm/mach-tegra/include/mach/memory.h
deleted file mode 100644
index 537db3aa81a7..000000000000
--- a/arch/arm/mach-tegra/include/mach/memory.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-tegra/include/mach/memory.h
3 *
4 * Copyright (C) 2010 Google, Inc.
5 *
6 * Author:
7 * Colin Cross <ccross@google.com>
8 * Erik Gilling <konkers@google.com>
9 *
10 * This software is licensed under the terms of the GNU General Public
11 * License version 2, as published by the Free Software Foundation, and
12 * may be copied, distributed, and modified under those terms.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20
21#ifndef __MACH_TEGRA_MEMORY_H
22#define __MACH_TEGRA_MEMORY_H
23
24/* physical offset of RAM */
25#define PLAT_PHYS_OFFSET UL(0)
26
27#endif
28
diff --git a/arch/arm/mach-u300/core.c b/arch/arm/mach-u300/core.c
index 24f3a96aac35..f4ad6d2e26f3 100644
--- a/arch/arm/mach-u300/core.c
+++ b/arch/arm/mach-u300/core.c
@@ -27,6 +27,7 @@
27#include <linux/mtd/fsmc.h> 27#include <linux/mtd/fsmc.h>
28#include <linux/pinctrl/machine.h> 28#include <linux/pinctrl/machine.h>
29#include <linux/pinctrl/pinmux.h> 29#include <linux/pinctrl/pinmux.h>
30#include <linux/dma-mapping.h>
30 31
31#include <asm/types.h> 32#include <asm/types.h>
32#include <asm/setup.h> 33#include <asm/setup.h>
@@ -95,6 +96,8 @@ static struct map_desc u300_io_desc[] __initdata = {
95void __init u300_map_io(void) 96void __init u300_map_io(void)
96{ 97{
97 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc)); 98 iotable_init(u300_io_desc, ARRAY_SIZE(u300_io_desc));
99 /* We enable a real big DMA buffer if need be. */
100 init_consistent_dma_size(SZ_4M);
98} 101}
99 102
100/* 103/*
diff --git a/arch/arm/mach-u300/include/mach/debug-macro.S b/arch/arm/mach-u300/include/mach/debug-macro.S
index df715707bead..8ae8e4ab34b0 100644
--- a/arch/arm/mach-u300/include/mach/debug-macro.S
+++ b/arch/arm/mach-u300/include/mach/debug-macro.S
@@ -10,7 +10,7 @@
10 */ 10 */
11#include <mach/hardware.h> 11#include <mach/hardware.h>
12 12
13 .macro addruart, rp, rv 13 .macro addruart, rp, rv, tmp
14 /* If we move the address using MMU, use this. */ 14 /* If we move the address using MMU, use this. */
15 ldr \rp, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address 15 ldr \rp, = U300_SLOW_PER_PHYS_BASE @ MMU off, physical address
16 ldr \rv, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address 16 ldr \rv, = U300_SLOW_PER_VIRT_BASE @ MMU on, virtual address
diff --git a/arch/arm/mach-u300/include/mach/memory.h b/arch/arm/mach-u300/include/mach/memory.h
index 888e2e351ee1..7034bae95de6 100644
--- a/arch/arm/mach-u300/include/mach/memory.h
+++ b/arch/arm/mach-u300/include/mach/memory.h
@@ -16,7 +16,7 @@
16#ifdef CONFIG_MACH_U300_DUAL_RAM 16#ifdef CONFIG_MACH_U300_DUAL_RAM
17 17
18#define PLAT_PHYS_OFFSET UL(0x48000000) 18#define PLAT_PHYS_OFFSET UL(0x48000000)
19#define BOOT_PARAMS_OFFSET (PHYS_OFFSET + 0x100) 19#define BOOT_PARAMS_OFFSET 0x100
20 20
21#else 21#else
22 22
@@ -24,19 +24,14 @@
24#define PLAT_PHYS_OFFSET (0x28000000 + \ 24#define PLAT_PHYS_OFFSET (0x28000000 + \
25 (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \ 25 (CONFIG_MACH_U300_ACCESS_MEM_SIZE - \
26 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024) 26 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
27#define BOOT_PARAMS_OFFSET (0x100 + \
28 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1)*1024*1024*2)
27#else 29#else
28#define PLAT_PHYS_OFFSET (0x28000000 + \ 30#define PLAT_PHYS_OFFSET (0x28000000 + \
29 (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \ 31 (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \
30 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024) 32 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024)
33#define BOOT_PARAMS_OFFSET 0x100
31#endif 34#endif
32#define BOOT_PARAMS_OFFSET (0x28000000 + \
33 (CONFIG_MACH_U300_ACCESS_MEM_SIZE + \
34 (CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1))*1024*1024 + 0x100)
35#endif 35#endif
36 36
37/*
38 * We enable a real big DMA buffer if need be.
39 */
40#define CONSISTENT_DMA_SIZE SZ_4M
41
42#endif 37#endif
diff --git a/arch/arm/mach-u300/u300.c b/arch/arm/mach-u300/u300.c
index 48b3b7f39966..80e7305589c6 100644
--- a/arch/arm/mach-u300/u300.c
+++ b/arch/arm/mach-u300/u300.c
@@ -61,7 +61,7 @@ static void __init u300_init_machine(void)
61 61
62MACHINE_START(U300, MACH_U300_STRING) 62MACHINE_START(U300, MACH_U300_STRING)
63 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */ 63 /* Maintainer: Linus Walleij <linus.walleij@stericsson.com> */
64 .boot_params = BOOT_PARAMS_OFFSET, 64 .atag_offset = BOOT_PARAMS_OFFSET,
65 .map_io = u300_map_io, 65 .map_io = u300_map_io,
66 .reserve = u300_reserve, 66 .reserve = u300_reserve,
67 .init_irq = u300_init_irq, 67 .init_irq = u300_init_irq,
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 537ab63c1dc9..f67b83dd9010 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -646,7 +646,7 @@ static void __init mop500_init_machine(void)
646 646
647MACHINE_START(U8500, "ST-Ericsson MOP500 platform") 647MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
648 /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */ 648 /* Maintainer: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> */
649 .boot_params = 0x100, 649 .atag_offset = 0x100,
650 .map_io = u8500_map_io, 650 .map_io = u8500_map_io,
651 .init_irq = ux500_init_irq, 651 .init_irq = ux500_init_irq,
652 /* we re-use nomadik timer here */ 652 /* we re-use nomadik timer here */
@@ -655,7 +655,7 @@ MACHINE_START(U8500, "ST-Ericsson MOP500 platform")
655MACHINE_END 655MACHINE_END
656 656
657MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+") 657MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
658 .boot_params = 0x100, 658 .atag_offset = 0x100,
659 .map_io = u8500_map_io, 659 .map_io = u8500_map_io,
660 .init_irq = ux500_init_irq, 660 .init_irq = ux500_init_irq,
661 .timer = &ux500_timer, 661 .timer = &ux500_timer,
@@ -663,7 +663,7 @@ MACHINE_START(HREFV60, "ST-Ericsson U8500 Platform HREFv60+")
663MACHINE_END 663MACHINE_END
664 664
665MACHINE_START(SNOWBALL, "Calao Systems Snowball platform") 665MACHINE_START(SNOWBALL, "Calao Systems Snowball platform")
666 .boot_params = 0x100, 666 .atag_offset = 0x100,
667 .map_io = u8500_map_io, 667 .map_io = u8500_map_io,
668 .init_irq = ux500_init_irq, 668 .init_irq = ux500_init_irq,
669 /* we re-use nomadik timer here */ 669 /* we re-use nomadik timer here */
diff --git a/arch/arm/mach-ux500/board-u5500.c b/arch/arm/mach-ux500/board-u5500.c
index 2d9e191bd30a..e014aa749b03 100644
--- a/arch/arm/mach-ux500/board-u5500.c
+++ b/arch/arm/mach-ux500/board-u5500.c
@@ -118,7 +118,7 @@ static void __init u5500_init_machine(void)
118} 118}
119 119
120MACHINE_START(U5500, "ST-Ericsson U5500 Platform") 120MACHINE_START(U5500, "ST-Ericsson U5500 Platform")
121 .boot_params = 0x00000100, 121 .atag_offset = 0x100,
122 .map_io = u5500_map_io, 122 .map_io = u5500_map_io,
123 .init_irq = ux500_init_irq, 123 .init_irq = ux500_init_irq,
124 .timer = &ux500_timer, 124 .timer = &ux500_timer,
diff --git a/arch/arm/mach-ux500/include/mach/debug-macro.S b/arch/arm/mach-ux500/include/mach/debug-macro.S
index 700fb05ee815..8d74d927d4e2 100644
--- a/arch/arm/mach-ux500/include/mach/debug-macro.S
+++ b/arch/arm/mach-ux500/include/mach/debug-macro.S
@@ -35,7 +35,7 @@
35#define UX500_UART(n) __UX500_UART(n) 35#define UX500_UART(n) __UX500_UART(n)
36#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART) 36#define UART_BASE UX500_UART(CONFIG_UX500_DEBUG_UART)
37 37
38 .macro addruart, rp, rv 38 .macro addruart, rp, rv, tmp
39 ldr \rp, =UART_BASE @ no, physical address 39 ldr \rp, =UART_BASE @ no, physical address
40 ldr \rv, =IO_ADDRESS(UART_BASE) @ yes, virtual address 40 ldr \rv, =IO_ADDRESS(UART_BASE) @ yes, virtual address
41 .endm 41 .endm
diff --git a/arch/arm/mach-ux500/include/mach/memory.h b/arch/arm/mach-ux500/include/mach/memory.h
deleted file mode 100644
index 2ef697a67006..000000000000
--- a/arch/arm/mach-ux500/include/mach/memory.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9#ifndef __ASM_ARCH_MEMORY_H
10#define __ASM_ARCH_MEMORY_H
11
12/*
13 * Physical DRAM offset.
14 */
15#define PLAT_PHYS_OFFSET UL(0x00000000)
16#define BUS_OFFSET UL(0x00000000)
17
18#endif
diff --git a/arch/arm/mach-versatile/include/mach/debug-macro.S b/arch/arm/mach-versatile/include/mach/debug-macro.S
index eb2cf7dc5c44..d0fbd7f1cb00 100644
--- a/arch/arm/mach-versatile/include/mach/debug-macro.S
+++ b/arch/arm/mach-versatile/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0x001F0000 15 mov \rp, #0x001F0000
16 orr \rp, \rp, #0x00001000 16 orr \rp, \rp, #0x00001000
17 orr \rv, \rp, #0xf1000000 @ virtual base 17 orr \rv, \rp, #0xf1000000 @ virtual base
diff --git a/arch/arm/mach-versatile/include/mach/memory.h b/arch/arm/mach-versatile/include/mach/memory.h
deleted file mode 100644
index dacc9d8e4e6a..000000000000
--- a/arch/arm/mach-versatile/include/mach/memory.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-versatile/include/mach/memory.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_MEMORY_H
21#define __ASM_ARCH_MEMORY_H
22
23/*
24 * Physical DRAM offset.
25 */
26#define PLAT_PHYS_OFFSET UL(0x00000000)
27
28#endif
diff --git a/arch/arm/mach-versatile/versatile_ab.c b/arch/arm/mach-versatile/versatile_ab.c
index f8ae64b3eed0..fda4866703cd 100644
--- a/arch/arm/mach-versatile/versatile_ab.c
+++ b/arch/arm/mach-versatile/versatile_ab.c
@@ -35,7 +35,7 @@
35 35
36MACHINE_START(VERSATILE_AB, "ARM-Versatile AB") 36MACHINE_START(VERSATILE_AB, "ARM-Versatile AB")
37 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 37 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
38 .boot_params = 0x00000100, 38 .atag_offset = 0x100,
39 .map_io = versatile_map_io, 39 .map_io = versatile_map_io,
40 .init_early = versatile_init_early, 40 .init_early = versatile_init_early,
41 .init_irq = versatile_init_irq, 41 .init_irq = versatile_init_irq,
diff --git a/arch/arm/mach-versatile/versatile_pb.c b/arch/arm/mach-versatile/versatile_pb.c
index 37c23dfeefb7..feaf9cbe60f6 100644
--- a/arch/arm/mach-versatile/versatile_pb.c
+++ b/arch/arm/mach-versatile/versatile_pb.c
@@ -103,7 +103,7 @@ static void __init versatile_pb_init(void)
103 103
104MACHINE_START(VERSATILE_PB, "ARM-Versatile PB") 104MACHINE_START(VERSATILE_PB, "ARM-Versatile PB")
105 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */ 105 /* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
106 .boot_params = 0x00000100, 106 .atag_offset = 0x100,
107 .map_io = versatile_map_io, 107 .map_io = versatile_map_io,
108 .init_early = versatile_init_early, 108 .init_early = versatile_init_early,
109 .init_irq = versatile_init_irq, 109 .init_irq = versatile_init_irq,
diff --git a/arch/arm/mach-vexpress/include/mach/debug-macro.S b/arch/arm/mach-vexpress/include/mach/debug-macro.S
index 050d65e02a42..fd9e6c7ea49f 100644
--- a/arch/arm/mach-vexpress/include/mach/debug-macro.S
+++ b/arch/arm/mach-vexpress/include/mach/debug-macro.S
@@ -12,7 +12,7 @@
12 12
13#define DEBUG_LL_UART_OFFSET 0x00009000 13#define DEBUG_LL_UART_OFFSET 0x00009000
14 14
15 .macro addruart,rp,rv 15 .macro addruart,rp,rv,tmp
16 mov \rp, #DEBUG_LL_UART_OFFSET 16 mov \rp, #DEBUG_LL_UART_OFFSET
17 orr \rv, \rp, #0xf8000000 @ virtual base 17 orr \rv, \rp, #0xf8000000 @ virtual base
18 orr \rp, \rp, #0x10000000 @ physical base 18 orr \rp, \rp, #0x10000000 @ physical base
diff --git a/arch/arm/mach-vexpress/include/mach/memory.h b/arch/arm/mach-vexpress/include/mach/memory.h
deleted file mode 100644
index 5b7fcd439d87..000000000000
--- a/arch/arm/mach-vexpress/include/mach/memory.h
+++ /dev/null
@@ -1,25 +0,0 @@
1/*
2 * arch/arm/mach-vexpress/include/mach/memory.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_MEMORY_H
21#define __ASM_ARCH_MEMORY_H
22
23#define PLAT_PHYS_OFFSET UL(0x60000000)
24
25#endif
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index d0d267a8d3f9..1fafc3244607 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -443,7 +443,7 @@ static void __init v2m_init(void)
443} 443}
444 444
445MACHINE_START(VEXPRESS, "ARM-Versatile Express") 445MACHINE_START(VEXPRESS, "ARM-Versatile Express")
446 .boot_params = PLAT_PHYS_OFFSET + 0x00000100, 446 .atag_offset = 0x100,
447 .map_io = v2m_map_io, 447 .map_io = v2m_map_io,
448 .init_early = v2m_init_early, 448 .init_early = v2m_init_early,
449 .init_irq = v2m_init_irq, 449 .init_irq = v2m_init_irq,
diff --git a/arch/arm/mach-vt8500/bv07.c b/arch/arm/mach-vt8500/bv07.c
index 94a261d86bf0..a464c7584411 100644
--- a/arch/arm/mach-vt8500/bv07.c
+++ b/arch/arm/mach-vt8500/bv07.c
@@ -68,7 +68,7 @@ void __init bv07_init(void)
68} 68}
69 69
70MACHINE_START(BV07, "Benign BV07 Mini Netbook") 70MACHINE_START(BV07, "Benign BV07 Mini Netbook")
71 .boot_params = 0x00000100, 71 .atag_offset = 0x100,
72 .reserve = vt8500_reserve_mem, 72 .reserve = vt8500_reserve_mem,
73 .map_io = vt8500_map_io, 73 .map_io = vt8500_map_io,
74 .init_irq = vt8500_init_irq, 74 .init_irq = vt8500_init_irq,
diff --git a/arch/arm/mach-vt8500/include/mach/debug-macro.S b/arch/arm/mach-vt8500/include/mach/debug-macro.S
index f1191626ad51..ca292f29d4a3 100644
--- a/arch/arm/mach-vt8500/include/mach/debug-macro.S
+++ b/arch/arm/mach-vt8500/include/mach/debug-macro.S
@@ -11,7 +11,7 @@
11 * 11 *
12*/ 12*/
13 13
14 .macro addruart, rp, rv 14 .macro addruart, rp, rv, tmp
15 mov \rp, #0x00200000 15 mov \rp, #0x00200000
16 orr \rv, \rp, #0xf8000000 16 orr \rv, \rp, #0xf8000000
17 orr \rp, \rp, #0xd8000000 17 orr \rp, \rp, #0xd8000000
diff --git a/arch/arm/mach-vt8500/include/mach/memory.h b/arch/arm/mach-vt8500/include/mach/memory.h
deleted file mode 100644
index 175f914eff93..000000000000
--- a/arch/arm/mach-vt8500/include/mach/memory.h
+++ /dev/null
@@ -1,28 +0,0 @@
1/*
2 * arch/arm/mach-vt8500/include/mach/memory.h
3 *
4 * Copyright (C) 2003 ARM Limited
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20#ifndef __ASM_ARCH_MEMORY_H
21#define __ASM_ARCH_MEMORY_H
22
23/*
24 * Physical DRAM offset.
25 */
26#define PHYS_OFFSET UL(0x00000000)
27
28#endif
diff --git a/arch/arm/mach-vt8500/wm8505_7in.c b/arch/arm/mach-vt8500/wm8505_7in.c
index e73aadbcafd6..cf910a956080 100644
--- a/arch/arm/mach-vt8500/wm8505_7in.c
+++ b/arch/arm/mach-vt8500/wm8505_7in.c
@@ -68,7 +68,7 @@ void __init wm8505_7in_init(void)
68} 68}
69 69
70MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook") 70MACHINE_START(WM8505_7IN_NETBOOK, "WM8505 7-inch generic netbook")
71 .boot_params = 0x00000100, 71 .atag_offset = 0x100,
72 .reserve = wm8505_reserve_mem, 72 .reserve = wm8505_reserve_mem,
73 .map_io = wm8505_map_io, 73 .map_io = wm8505_map_io,
74 .init_irq = wm8505_init_irq, 74 .init_irq = wm8505_init_irq,
diff --git a/arch/arm/mach-w90x900/include/mach/memory.h b/arch/arm/mach-w90x900/include/mach/memory.h
deleted file mode 100644
index f02905ba7746..000000000000
--- a/arch/arm/mach-w90x900/include/mach/memory.h
+++ /dev/null
@@ -1,23 +0,0 @@
1/*
2 * arch/arm/mach-w90x900/include/mach/memory.h
3 *
4 * Copyright (c) 2008 Nuvoton technology corporation
5 * All rights reserved.
6 *
7 * Wan ZongShun <mcuos.com@gmail.com>
8 *
9 * Based on arch/arm/mach-s3c2410/include/mach/memory.h
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 */
17
18#ifndef __ASM_ARCH_MEMORY_H
19#define __ASM_ARCH_MEMORY_H
20
21#define PLAT_PHYS_OFFSET UL(0x00000000)
22
23#endif
diff --git a/arch/arm/mach-w90x900/mach-nuc910evb.c b/arch/arm/mach-w90x900/mach-nuc910evb.c
index 30fccde94fb8..31c109018228 100644
--- a/arch/arm/mach-w90x900/mach-nuc910evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc910evb.c
@@ -34,7 +34,6 @@ static void __init nuc910evb_init(void)
34 34
35MACHINE_START(W90P910EVB, "W90P910EVB") 35MACHINE_START(W90P910EVB, "W90P910EVB")
36 /* Maintainer: Wan ZongShun */ 36 /* Maintainer: Wan ZongShun */
37 .boot_params = 0,
38 .map_io = nuc910evb_map_io, 37 .map_io = nuc910evb_map_io,
39 .init_irq = nuc900_init_irq, 38 .init_irq = nuc900_init_irq,
40 .init_machine = nuc910evb_init, 39 .init_machine = nuc910evb_init,
diff --git a/arch/arm/mach-w90x900/mach-nuc950evb.c b/arch/arm/mach-w90x900/mach-nuc950evb.c
index 590c99b96dc1..4062e55a57d8 100644
--- a/arch/arm/mach-w90x900/mach-nuc950evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc950evb.c
@@ -37,7 +37,6 @@ static void __init nuc950evb_init(void)
37 37
38MACHINE_START(W90P950EVB, "W90P950EVB") 38MACHINE_START(W90P950EVB, "W90P950EVB")
39 /* Maintainer: Wan ZongShun */ 39 /* Maintainer: Wan ZongShun */
40 .boot_params = 0,
41 .map_io = nuc950evb_map_io, 40 .map_io = nuc950evb_map_io,
42 .init_irq = nuc900_init_irq, 41 .init_irq = nuc900_init_irq,
43 .init_machine = nuc950evb_init, 42 .init_machine = nuc950evb_init,
diff --git a/arch/arm/mach-w90x900/mach-nuc960evb.c b/arch/arm/mach-w90x900/mach-nuc960evb.c
index e09c645d61b6..0ab9995d5b58 100644
--- a/arch/arm/mach-w90x900/mach-nuc960evb.c
+++ b/arch/arm/mach-w90x900/mach-nuc960evb.c
@@ -34,7 +34,6 @@ static void __init nuc960evb_init(void)
34 34
35MACHINE_START(W90N960EVB, "W90N960EVB") 35MACHINE_START(W90N960EVB, "W90N960EVB")
36 /* Maintainer: Wan ZongShun */ 36 /* Maintainer: Wan ZongShun */
37 .boot_params = 0,
38 .map_io = nuc960evb_map_io, 37 .map_io = nuc960evb_map_io,
39 .init_irq = nuc900_init_irq, 38 .init_irq = nuc900_init_irq,
40 .init_machine = nuc960evb_init, 39 .init_machine = nuc960evb_init,
diff --git a/arch/arm/mach-zynq/include/mach/debug-macro.S b/arch/arm/mach-zynq/include/mach/debug-macro.S
index 9f664d5eb81d..3ab0be1f6191 100644
--- a/arch/arm/mach-zynq/include/mach/debug-macro.S
+++ b/arch/arm/mach-zynq/include/mach/debug-macro.S
@@ -17,7 +17,7 @@
17#include <mach/zynq_soc.h> 17#include <mach/zynq_soc.h>
18#include <mach/uart.h> 18#include <mach/uart.h>
19 19
20 .macro addruart, rp, rv 20 .macro addruart, rp, rv, tmp
21 ldr \rp, =LL_UART_PADDR @ physical 21 ldr \rp, =LL_UART_PADDR @ physical
22 ldr \rv, =LL_UART_VADDR @ virtual 22 ldr \rv, =LL_UART_VADDR @ virtual
23 .endm 23 .endm
diff --git a/arch/arm/mach-zynq/include/mach/memory.h b/arch/arm/mach-zynq/include/mach/memory.h
deleted file mode 100644
index 35a92634dcc1..000000000000
--- a/arch/arm/mach-zynq/include/mach/memory.h
+++ /dev/null
@@ -1,22 +0,0 @@
1/* arch/arm/mach-zynq/include/mach/memory.h
2 *
3 * Copyright (C) 2011 Xilinx
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#ifndef __MACH_MEMORY_H__
16#define __MACH_MEMORY_H__
17
18#include <asm/sizes.h>
19
20#define PLAT_PHYS_OFFSET UL(0x0)
21
22#endif
diff --git a/arch/arm/mm/dma-mapping.c b/arch/arm/mm/dma-mapping.c
index 235eb775fc78..e4e7f6cba1ab 100644
--- a/arch/arm/mm/dma-mapping.c
+++ b/arch/arm/mm/dma-mapping.c
@@ -18,12 +18,14 @@
18#include <linux/device.h> 18#include <linux/device.h>
19#include <linux/dma-mapping.h> 19#include <linux/dma-mapping.h>
20#include <linux/highmem.h> 20#include <linux/highmem.h>
21#include <linux/slab.h>
21 22
22#include <asm/memory.h> 23#include <asm/memory.h>
23#include <asm/highmem.h> 24#include <asm/highmem.h>
24#include <asm/cacheflush.h> 25#include <asm/cacheflush.h>
25#include <asm/tlbflush.h> 26#include <asm/tlbflush.h>
26#include <asm/sizes.h> 27#include <asm/sizes.h>
28#include <asm/mach/arch.h>
27 29
28#include "mm.h" 30#include "mm.h"
29 31
@@ -117,26 +119,36 @@ static void __dma_free_buffer(struct page *page, size_t size)
117} 119}
118 120
119#ifdef CONFIG_MMU 121#ifdef CONFIG_MMU
120/* Sanity check size */
121#if (CONSISTENT_DMA_SIZE % SZ_2M)
122#error "CONSISTENT_DMA_SIZE must be multiple of 2MiB"
123#endif
124 122
125#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) 123#define CONSISTENT_OFFSET(x) (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT)
126#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PMD_SHIFT) 124#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT)
127#define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PMD_SHIFT)
128 125
129/* 126/*
130 * These are the page tables (2MB each) covering uncached, DMA consistent allocations 127 * These are the page tables (2MB each) covering uncached, DMA consistent allocations
131 */ 128 */
132static pte_t *consistent_pte[NUM_CONSISTENT_PTES]; 129static pte_t **consistent_pte;
130
131#define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M
132
133unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE;
134
135void __init init_consistent_dma_size(unsigned long size)
136{
137 unsigned long base = CONSISTENT_END - ALIGN(size, SZ_2M);
138
139 BUG_ON(consistent_pte); /* Check we're called before DMA region init */
140 BUG_ON(base < VMALLOC_END);
141
142 /* Grow region to accommodate specified size */
143 if (base < consistent_base)
144 consistent_base = base;
145}
133 146
134#include "vmregion.h" 147#include "vmregion.h"
135 148
136static struct arm_vmregion_head consistent_head = { 149static struct arm_vmregion_head consistent_head = {
137 .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock), 150 .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock),
138 .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), 151 .vm_list = LIST_HEAD_INIT(consistent_head.vm_list),
139 .vm_start = CONSISTENT_BASE,
140 .vm_end = CONSISTENT_END, 152 .vm_end = CONSISTENT_END,
141}; 153};
142 154
@@ -155,7 +167,17 @@ static int __init consistent_init(void)
155 pmd_t *pmd; 167 pmd_t *pmd;
156 pte_t *pte; 168 pte_t *pte;
157 int i = 0; 169 int i = 0;
158 u32 base = CONSISTENT_BASE; 170 unsigned long base = consistent_base;
171 unsigned long num_ptes = (CONSISTENT_END - base) >> PGDIR_SHIFT;
172
173 consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL);
174 if (!consistent_pte) {
175 pr_err("%s: no memory\n", __func__);
176 return -ENOMEM;
177 }
178
179 pr_debug("DMA memory: 0x%08lx - 0x%08lx:\n", base, CONSISTENT_END);
180 consistent_head.vm_start = base;
159 181
160 do { 182 do {
161 pgd = pgd_offset(&init_mm, base); 183 pgd = pgd_offset(&init_mm, base);
@@ -198,7 +220,7 @@ __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot)
198 size_t align; 220 size_t align;
199 int bit; 221 int bit;
200 222
201 if (!consistent_pte[0]) { 223 if (!consistent_pte) {
202 printk(KERN_ERR "%s: not initialised\n", __func__); 224 printk(KERN_ERR "%s: not initialised\n", __func__);
203 dump_stack(); 225 dump_stack();
204 return NULL; 226 return NULL;
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index f8037ba338ac..04e9a92bb47a 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -660,9 +660,6 @@ void __init mem_init(void)
660 " ITCM : 0x%08lx - 0x%08lx (%4ld kB)\n" 660 " ITCM : 0x%08lx - 0x%08lx (%4ld kB)\n"
661#endif 661#endif
662 " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n" 662 " fixmap : 0x%08lx - 0x%08lx (%4ld kB)\n"
663#ifdef CONFIG_MMU
664 " DMA : 0x%08lx - 0x%08lx (%4ld MB)\n"
665#endif
666 " vmalloc : 0x%08lx - 0x%08lx (%4ld MB)\n" 663 " vmalloc : 0x%08lx - 0x%08lx (%4ld MB)\n"
667 " lowmem : 0x%08lx - 0x%08lx (%4ld MB)\n" 664 " lowmem : 0x%08lx - 0x%08lx (%4ld MB)\n"
668#ifdef CONFIG_HIGHMEM 665#ifdef CONFIG_HIGHMEM
@@ -681,9 +678,6 @@ void __init mem_init(void)
681 MLK(ITCM_OFFSET, (unsigned long) itcm_end), 678 MLK(ITCM_OFFSET, (unsigned long) itcm_end),
682#endif 679#endif
683 MLK(FIXADDR_START, FIXADDR_TOP), 680 MLK(FIXADDR_START, FIXADDR_TOP),
684#ifdef CONFIG_MMU
685 MLM(CONSISTENT_BASE, CONSISTENT_END),
686#endif
687 MLM(VMALLOC_START, VMALLOC_END), 681 MLM(VMALLOC_START, VMALLOC_END),
688 MLM(PAGE_OFFSET, (unsigned long)high_memory), 682 MLM(PAGE_OFFSET, (unsigned long)high_memory),
689#ifdef CONFIG_HIGHMEM 683#ifdef CONFIG_HIGHMEM
@@ -706,9 +700,6 @@ void __init mem_init(void)
706 * be detected at build time already. 700 * be detected at build time already.
707 */ 701 */
708#ifdef CONFIG_MMU 702#ifdef CONFIG_MMU
709 BUILD_BUG_ON(VMALLOC_END > CONSISTENT_BASE);
710 BUG_ON(VMALLOC_END > CONSISTENT_BASE);
711
712 BUILD_BUG_ON(TASK_SIZE > MODULES_VADDR); 703 BUILD_BUG_ON(TASK_SIZE > MODULES_VADDR);
713 BUG_ON(TASK_SIZE > MODULES_VADDR); 704 BUG_ON(TASK_SIZE > MODULES_VADDR);
714#endif 705#endif
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 226f1804be12..dc8c550e6cbd 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -273,6 +273,14 @@ static struct mem_type mem_types[] = {
273 .prot_l1 = PMD_TYPE_TABLE, 273 .prot_l1 = PMD_TYPE_TABLE,
274 .domain = DOMAIN_KERNEL, 274 .domain = DOMAIN_KERNEL,
275 }, 275 },
276 [MT_MEMORY_SO] = {
277 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
278 L_PTE_MT_UNCACHED,
279 .prot_l1 = PMD_TYPE_TABLE,
280 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
281 PMD_SECT_UNCACHED | PMD_SECT_XN,
282 .domain = DOMAIN_KERNEL,
283 },
276}; 284};
277 285
278const struct mem_type *get_mem_type(unsigned int type) 286const struct mem_type *get_mem_type(unsigned int type)
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 2e6849b41f66..88fb3d9e0640 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -379,31 +379,26 @@ ENTRY(cpu_arm920_set_pte_ext)
379 379
380/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ 380/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
381.globl cpu_arm920_suspend_size 381.globl cpu_arm920_suspend_size
382.equ cpu_arm920_suspend_size, 4 * 4 382.equ cpu_arm920_suspend_size, 4 * 3
383#ifdef CONFIG_PM_SLEEP 383#ifdef CONFIG_PM_SLEEP
384ENTRY(cpu_arm920_do_suspend) 384ENTRY(cpu_arm920_do_suspend)
385 stmfd sp!, {r4 - r7, lr} 385 stmfd sp!, {r4 - r6, lr}
386 mrc p15, 0, r4, c13, c0, 0 @ PID 386 mrc p15, 0, r4, c13, c0, 0 @ PID
387 mrc p15, 0, r5, c3, c0, 0 @ Domain ID 387 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
388 mrc p15, 0, r6, c2, c0, 0 @ TTB address 388 mrc p15, 0, r6, c1, c0, 0 @ Control register
389 mrc p15, 0, r7, c1, c0, 0 @ Control register 389 stmia r0, {r4 - r6}
390 stmia r0, {r4 - r7} 390 ldmfd sp!, {r4 - r6, pc}
391 ldmfd sp!, {r4 - r7, pc}
392ENDPROC(cpu_arm920_do_suspend) 391ENDPROC(cpu_arm920_do_suspend)
393 392
394ENTRY(cpu_arm920_do_resume) 393ENTRY(cpu_arm920_do_resume)
395 mov ip, #0 394 mov ip, #0
396 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs 395 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
397 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 396 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
398 ldmia r0, {r4 - r7} 397 ldmia r0, {r4 - r6}
399 mcr p15, 0, r4, c13, c0, 0 @ PID 398 mcr p15, 0, r4, c13, c0, 0 @ PID
400 mcr p15, 0, r5, c3, c0, 0 @ Domain ID 399 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
401 mcr p15, 0, r6, c2, c0, 0 @ TTB address 400 mcr p15, 0, r1, c2, c0, 0 @ TTB address
402 mov r0, r7 @ control register 401 mov r0, r6 @ control register
403 mov r2, r6, lsr #14 @ get TTB0 base
404 mov r2, r2, lsl #14
405 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
406 PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
407 b cpu_resume_mmu 402 b cpu_resume_mmu
408ENDPROC(cpu_arm920_do_resume) 403ENDPROC(cpu_arm920_do_resume)
409#endif 404#endif
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index cd8f79c3a282..9f8fd91f918a 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -394,31 +394,26 @@ ENTRY(cpu_arm926_set_pte_ext)
394 394
395/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */ 395/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
396.globl cpu_arm926_suspend_size 396.globl cpu_arm926_suspend_size
397.equ cpu_arm926_suspend_size, 4 * 4 397.equ cpu_arm926_suspend_size, 4 * 3
398#ifdef CONFIG_PM_SLEEP 398#ifdef CONFIG_PM_SLEEP
399ENTRY(cpu_arm926_do_suspend) 399ENTRY(cpu_arm926_do_suspend)
400 stmfd sp!, {r4 - r7, lr} 400 stmfd sp!, {r4 - r6, lr}
401 mrc p15, 0, r4, c13, c0, 0 @ PID 401 mrc p15, 0, r4, c13, c0, 0 @ PID
402 mrc p15, 0, r5, c3, c0, 0 @ Domain ID 402 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
403 mrc p15, 0, r6, c2, c0, 0 @ TTB address 403 mrc p15, 0, r6, c1, c0, 0 @ Control register
404 mrc p15, 0, r7, c1, c0, 0 @ Control register 404 stmia r0, {r4 - r6}
405 stmia r0, {r4 - r7} 405 ldmfd sp!, {r4 - r6, pc}
406 ldmfd sp!, {r4 - r7, pc}
407ENDPROC(cpu_arm926_do_suspend) 406ENDPROC(cpu_arm926_do_suspend)
408 407
409ENTRY(cpu_arm926_do_resume) 408ENTRY(cpu_arm926_do_resume)
410 mov ip, #0 409 mov ip, #0
411 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs 410 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
412 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches 411 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
413 ldmia r0, {r4 - r7} 412 ldmia r0, {r4 - r6}
414 mcr p15, 0, r4, c13, c0, 0 @ PID 413 mcr p15, 0, r4, c13, c0, 0 @ PID
415 mcr p15, 0, r5, c3, c0, 0 @ Domain ID 414 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
416 mcr p15, 0, r6, c2, c0, 0 @ TTB address 415 mcr p15, 0, r1, c2, c0, 0 @ TTB address
417 mov r0, r7 @ control register 416 mov r0, r6 @ control register
418 mov r2, r6, lsr #14 @ get TTB0 base
419 mov r2, r2, lsl #14
420 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
421 PMD_SECT_CACHEABLE | PMD_BIT4 | PMD_SECT_AP_WRITE
422 b cpu_resume_mmu 417 b cpu_resume_mmu
423ENDPROC(cpu_arm926_do_resume) 418ENDPROC(cpu_arm926_do_resume)
424#endif 419#endif
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 69e7f2ef7384..7d91545d089b 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -168,20 +168,19 @@ ENTRY(cpu_sa1100_set_pte_ext)
168 mov pc, lr 168 mov pc, lr
169 169
170.globl cpu_sa1100_suspend_size 170.globl cpu_sa1100_suspend_size
171.equ cpu_sa1100_suspend_size, 4*4 171.equ cpu_sa1100_suspend_size, 4 * 3
172#ifdef CONFIG_PM_SLEEP 172#ifdef CONFIG_PM_SLEEP
173ENTRY(cpu_sa1100_do_suspend) 173ENTRY(cpu_sa1100_do_suspend)
174 stmfd sp!, {r4 - r7, lr} 174 stmfd sp!, {r4 - r6, lr}
175 mrc p15, 0, r4, c3, c0, 0 @ domain ID 175 mrc p15, 0, r4, c3, c0, 0 @ domain ID
176 mrc p15, 0, r5, c2, c0, 0 @ translation table base addr 176 mrc p15, 0, r5, c13, c0, 0 @ PID
177 mrc p15, 0, r6, c13, c0, 0 @ PID 177 mrc p15, 0, r6, c1, c0, 0 @ control reg
178 mrc p15, 0, r7, c1, c0, 0 @ control reg 178 stmia r0, {r4 - r6} @ store cp regs
179 stmia r0, {r4 - r7} @ store cp regs 179 ldmfd sp!, {r4 - r6, pc}
180 ldmfd sp!, {r4 - r7, pc}
181ENDPROC(cpu_sa1100_do_suspend) 180ENDPROC(cpu_sa1100_do_suspend)
182 181
183ENTRY(cpu_sa1100_do_resume) 182ENTRY(cpu_sa1100_do_resume)
184 ldmia r0, {r4 - r7} @ load cp regs 183 ldmia r0, {r4 - r6} @ load cp regs
185 mov ip, #0 184 mov ip, #0
186 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs 185 mcr p15, 0, ip, c8, c7, 0 @ flush I+D TLBs
187 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache 186 mcr p15, 0, ip, c7, c7, 0 @ flush I&D cache
@@ -189,13 +188,9 @@ ENTRY(cpu_sa1100_do_resume)
189 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB 188 mcr p15, 0, ip, c9, c0, 5 @ allow user space to use RB
190 189
191 mcr p15, 0, r4, c3, c0, 0 @ domain ID 190 mcr p15, 0, r4, c3, c0, 0 @ domain ID
192 mcr p15, 0, r5, c2, c0, 0 @ translation table base addr 191 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
193 mcr p15, 0, r6, c13, c0, 0 @ PID 192 mcr p15, 0, r5, c13, c0, 0 @ PID
194 mov r0, r7 @ control register 193 mov r0, r6 @ control register
195 mov r2, r5, lsr #14 @ get TTB0 base
196 mov r2, r2, lsl #14
197 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
198 PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
199 b cpu_resume_mmu 194 b cpu_resume_mmu
200ENDPROC(cpu_sa1100_do_resume) 195ENDPROC(cpu_sa1100_do_resume)
201#endif 196#endif
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index a923aa0fd00d..d061d2fa5506 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -128,20 +128,18 @@ ENTRY(cpu_v6_set_pte_ext)
128 128
129/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ 129/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
130.globl cpu_v6_suspend_size 130.globl cpu_v6_suspend_size
131.equ cpu_v6_suspend_size, 4 * 8 131.equ cpu_v6_suspend_size, 4 * 6
132#ifdef CONFIG_PM_SLEEP 132#ifdef CONFIG_PM_SLEEP
133ENTRY(cpu_v6_do_suspend) 133ENTRY(cpu_v6_do_suspend)
134 stmfd sp!, {r4 - r11, lr} 134 stmfd sp!, {r4 - r9, lr}
135 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 135 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
136 mrc p15, 0, r5, c13, c0, 1 @ Context ID 136 mrc p15, 0, r5, c3, c0, 0 @ Domain ID
137 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 137 mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
138 mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 138 mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
139 mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 139 mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
140 mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register 140 mrc p15, 0, r9, c1, c0, 0 @ control register
141 mrc p15, 0, r10, c1, c0, 2 @ co-processor access control 141 stmia r0, {r4 - r9}
142 mrc p15, 0, r11, c1, c0, 0 @ control register 142 ldmfd sp!, {r4- r9, pc}
143 stmia r0, {r4 - r11}
144 ldmfd sp!, {r4- r11, pc}
145ENDPROC(cpu_v6_do_suspend) 143ENDPROC(cpu_v6_do_suspend)
146 144
147ENTRY(cpu_v6_do_resume) 145ENTRY(cpu_v6_do_resume)
@@ -150,25 +148,21 @@ ENTRY(cpu_v6_do_resume)
150 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 148 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
151 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache 149 mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
152 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer 150 mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
153 ldmia r0, {r4 - r11} 151 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
152 ldmia r0, {r4 - r9}
154 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 153 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
155 mcr p15, 0, r5, c13, c0, 1 @ Context ID 154 mcr p15, 0, r5, c3, c0, 0 @ Domain ID
156 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 155 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
157 mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 156 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
158 mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 157 mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
159 mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register 158 mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
160 mcr p15, 0, r10, c1, c0, 2 @ co-processor access control 159 mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
160 mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
161 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 161 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
162 mcr p15, 0, ip, c7, c5, 4 @ ISB 162 mcr p15, 0, ip, c7, c5, 4 @ ISB
163 mov r0, r11 @ control register 163 mov r0, r9 @ control register
164 mov r2, r7, lsr #14 @ get TTB0 base
165 mov r2, r2, lsl #14
166 ldr r3, cpu_resume_l1_flags
167 b cpu_resume_mmu 164 b cpu_resume_mmu
168ENDPROC(cpu_v6_do_resume) 165ENDPROC(cpu_v6_do_resume)
169cpu_resume_l1_flags:
170 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
171 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
172#endif 166#endif
173 167
174 string cpu_v6_name, "ARMv6-compatible processor" 168 string cpu_v6_name, "ARMv6-compatible processor"
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 9591c8e9fb8c..2c559ac38142 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -217,56 +217,50 @@ ENDPROC(cpu_v7_set_pte_ext)
217 217
218/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ 218/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
219.globl cpu_v7_suspend_size 219.globl cpu_v7_suspend_size
220.equ cpu_v7_suspend_size, 4 * 9 220.equ cpu_v7_suspend_size, 4 * 7
221#ifdef CONFIG_ARM_CPU_SUSPEND 221#ifdef CONFIG_ARM_CPU_SUSPEND
222ENTRY(cpu_v7_do_suspend) 222ENTRY(cpu_v7_do_suspend)
223 stmfd sp!, {r4 - r11, lr} 223 stmfd sp!, {r4 - r10, lr}
224 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID 224 mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
225 mrc p15, 0, r5, c13, c0, 1 @ Context ID 225 mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
226 mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID 226 stmia r0!, {r4 - r5}
227 stmia r0!, {r4 - r6}
228 mrc p15, 0, r6, c3, c0, 0 @ Domain ID 227 mrc p15, 0, r6, c3, c0, 0 @ Domain ID
229 mrc p15, 0, r7, c2, c0, 0 @ TTB 0 228 mrc p15, 0, r7, c2, c0, 1 @ TTB 1
230 mrc p15, 0, r8, c2, c0, 1 @ TTB 1 229 mrc p15, 0, r8, c1, c0, 0 @ Control register
231 mrc p15, 0, r9, c1, c0, 0 @ Control register 230 mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
232 mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register 231 mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
233 mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control 232 stmia r0, {r6 - r10}
234 stmia r0, {r6 - r11} 233 ldmfd sp!, {r4 - r10, pc}
235 ldmfd sp!, {r4 - r11, pc}
236ENDPROC(cpu_v7_do_suspend) 234ENDPROC(cpu_v7_do_suspend)
237 235
238ENTRY(cpu_v7_do_resume) 236ENTRY(cpu_v7_do_resume)
239 mov ip, #0 237 mov ip, #0
240 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs 238 mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
241 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache 239 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
242 ldmia r0!, {r4 - r6} 240 mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
241 ldmia r0!, {r4 - r5}
243 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID 242 mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
244 mcr p15, 0, r5, c13, c0, 1 @ Context ID 243 mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
245 mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID 244 ldmia r0, {r6 - r10}
246 ldmia r0, {r6 - r11}
247 mcr p15, 0, r6, c3, c0, 0 @ Domain ID 245 mcr p15, 0, r6, c3, c0, 0 @ Domain ID
248 mcr p15, 0, r7, c2, c0, 0 @ TTB 0 246 ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
249 mcr p15, 0, r8, c2, c0, 1 @ TTB 1 247 ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
248 mcr p15, 0, r1, c2, c0, 0 @ TTB 0
249 mcr p15, 0, r7, c2, c0, 1 @ TTB 1
250 mcr p15, 0, ip, c2, c0, 2 @ TTB control register 250 mcr p15, 0, ip, c2, c0, 2 @ TTB control register
251 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register 251 mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
252 teq r4, r10 @ Is it already set? 252 teq r4, r9 @ Is it already set?
253 mcrne p15, 0, r10, c1, c0, 1 @ No, so write it 253 mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
254 mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control 254 mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
255 ldr r4, =PRRR @ PRRR 255 ldr r4, =PRRR @ PRRR
256 ldr r5, =NMRR @ NMRR 256 ldr r5, =NMRR @ NMRR
257 mcr p15, 0, r4, c10, c2, 0 @ write PRRR 257 mcr p15, 0, r4, c10, c2, 0 @ write PRRR
258 mcr p15, 0, r5, c10, c2, 1 @ write NMRR 258 mcr p15, 0, r5, c10, c2, 1 @ write NMRR
259 isb 259 isb
260 dsb 260 dsb
261 mov r0, r9 @ control register 261 mov r0, r8 @ control register
262 mov r2, r7, lsr #14 @ get TTB0 base
263 mov r2, r2, lsl #14
264 ldr r3, cpu_resume_l1_flags
265 b cpu_resume_mmu 262 b cpu_resume_mmu
266ENDPROC(cpu_v7_do_resume) 263ENDPROC(cpu_v7_do_resume)
267cpu_resume_l1_flags:
268 ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP)
269 ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP)
270#endif 264#endif
271 265
272 __CPUINIT 266 __CPUINIT
diff --git a/arch/arm/mm/proc-xsc3.S b/arch/arm/mm/proc-xsc3.S
index 755e1bf22681..abf0507a08ae 100644
--- a/arch/arm/mm/proc-xsc3.S
+++ b/arch/arm/mm/proc-xsc3.S
@@ -406,24 +406,23 @@ ENTRY(cpu_xsc3_set_pte_ext)
406 .align 406 .align
407 407
408.globl cpu_xsc3_suspend_size 408.globl cpu_xsc3_suspend_size
409.equ cpu_xsc3_suspend_size, 4 * 7 409.equ cpu_xsc3_suspend_size, 4 * 6
410#ifdef CONFIG_PM_SLEEP 410#ifdef CONFIG_PM_SLEEP
411ENTRY(cpu_xsc3_do_suspend) 411ENTRY(cpu_xsc3_do_suspend)
412 stmfd sp!, {r4 - r10, lr} 412 stmfd sp!, {r4 - r9, lr}
413 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 413 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
414 mrc p15, 0, r5, c15, c1, 0 @ CP access reg 414 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
415 mrc p15, 0, r6, c13, c0, 0 @ PID 415 mrc p15, 0, r6, c13, c0, 0 @ PID
416 mrc p15, 0, r7, c3, c0, 0 @ domain ID 416 mrc p15, 0, r7, c3, c0, 0 @ domain ID
417 mrc p15, 0, r8, c2, c0, 0 @ translation table base addr 417 mrc p15, 0, r8, c1, c0, 1 @ auxiliary control reg
418 mrc p15, 0, r9, c1, c0, 1 @ auxiliary control reg 418 mrc p15, 0, r9, c1, c0, 0 @ control reg
419 mrc p15, 0, r10, c1, c0, 0 @ control reg
420 bic r4, r4, #2 @ clear frequency change bit 419 bic r4, r4, #2 @ clear frequency change bit
421 stmia r0, {r4 - r10} @ store cp regs 420 stmia r0, {r4 - r9} @ store cp regs
422 ldmia sp!, {r4 - r10, pc} 421 ldmia sp!, {r4 - r9, pc}
423ENDPROC(cpu_xsc3_do_suspend) 422ENDPROC(cpu_xsc3_do_suspend)
424 423
425ENTRY(cpu_xsc3_do_resume) 424ENTRY(cpu_xsc3_do_resume)
426 ldmia r0, {r4 - r10} @ load cp regs 425 ldmia r0, {r4 - r9} @ load cp regs
427 mov ip, #0 426 mov ip, #0
428 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 427 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
429 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer 428 mcr p15, 0, ip, c7, c10, 4 @ drain write (&fill) buffer
@@ -433,15 +432,10 @@ ENTRY(cpu_xsc3_do_resume)
433 mcr p15, 0, r5, c15, c1, 0 @ CP access reg 432 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
434 mcr p15, 0, r6, c13, c0, 0 @ PID 433 mcr p15, 0, r6, c13, c0, 0 @ PID
435 mcr p15, 0, r7, c3, c0, 0 @ domain ID 434 mcr p15, 0, r7, c3, c0, 0 @ domain ID
436 mcr p15, 0, r8, c2, c0, 0 @ translation table base addr 435 orr r1, r1, #0x18 @ cache the page table in L2
437 mcr p15, 0, r9, c1, c0, 1 @ auxiliary control reg 436 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
438 437 mcr p15, 0, r8, c1, c0, 1 @ auxiliary control reg
439 @ temporarily map resume_turn_on_mmu into the page table, 438 mov r0, r9 @ control register
440 @ otherwise prefetch abort occurs after MMU is turned on
441 mov r0, r10 @ control register
442 mov r2, r8, lsr #14 @ get TTB0 base
443 mov r2, r2, lsl #14
444 ldr r3, =0x542e @ section flags
445 b cpu_resume_mmu 439 b cpu_resume_mmu
446ENDPROC(cpu_xsc3_do_resume) 440ENDPROC(cpu_xsc3_do_resume)
447#endif 441#endif
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index fbc06e55b87a..3277904bebaf 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -520,24 +520,23 @@ ENTRY(cpu_xscale_set_pte_ext)
520 .align 520 .align
521 521
522.globl cpu_xscale_suspend_size 522.globl cpu_xscale_suspend_size
523.equ cpu_xscale_suspend_size, 4 * 7 523.equ cpu_xscale_suspend_size, 4 * 6
524#ifdef CONFIG_PM_SLEEP 524#ifdef CONFIG_PM_SLEEP
525ENTRY(cpu_xscale_do_suspend) 525ENTRY(cpu_xscale_do_suspend)
526 stmfd sp!, {r4 - r10, lr} 526 stmfd sp!, {r4 - r9, lr}
527 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode 527 mrc p14, 0, r4, c6, c0, 0 @ clock configuration, for turbo mode
528 mrc p15, 0, r5, c15, c1, 0 @ CP access reg 528 mrc p15, 0, r5, c15, c1, 0 @ CP access reg
529 mrc p15, 0, r6, c13, c0, 0 @ PID 529 mrc p15, 0, r6, c13, c0, 0 @ PID
530 mrc p15, 0, r7, c3, c0, 0 @ domain ID 530 mrc p15, 0, r7, c3, c0, 0 @ domain ID
531 mrc p15, 0, r8, c2, c0, 0 @ translation table base addr 531 mrc p15, 0, r8, c1, c1, 0 @ auxiliary control reg
532 mrc p15, 0, r9, c1, c1, 0 @ auxiliary control reg 532 mrc p15, 0, r9, c1, c0, 0 @ control reg
533 mrc p15, 0, r10, c1, c0, 0 @ control reg
534 bic r4, r4, #2 @ clear frequency change bit 533 bic r4, r4, #2 @ clear frequency change bit
535 stmia r0, {r4 - r10} @ store cp regs 534 stmia r0, {r4 - r9} @ store cp regs
536 ldmfd sp!, {r4 - r10, pc} 535 ldmfd sp!, {r4 - r9, pc}
537ENDPROC(cpu_xscale_do_suspend) 536ENDPROC(cpu_xscale_do_suspend)
538 537
539ENTRY(cpu_xscale_do_resume) 538ENTRY(cpu_xscale_do_resume)
540 ldmia r0, {r4 - r10} @ load cp regs 539 ldmia r0, {r4 - r9} @ load cp regs
541 mov ip, #0 540 mov ip, #0
542 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs 541 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
543 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB 542 mcr p15, 0, ip, c7, c7, 0 @ invalidate I & D caches, BTB
@@ -545,13 +544,9 @@ ENTRY(cpu_xscale_do_resume)
545 mcr p15, 0, r5, c15, c1, 0 @ CP access reg 544 mcr p15, 0, r5, c15, c1, 0 @ CP access reg
546 mcr p15, 0, r6, c13, c0, 0 @ PID 545 mcr p15, 0, r6, c13, c0, 0 @ PID
547 mcr p15, 0, r7, c3, c0, 0 @ domain ID 546 mcr p15, 0, r7, c3, c0, 0 @ domain ID
548 mcr p15, 0, r8, c2, c0, 0 @ translation table base addr 547 mcr p15, 0, r1, c2, c0, 0 @ translation table base addr
549 mcr p15, 0, r9, c1, c1, 0 @ auxiliary control reg 548 mcr p15, 0, r8, c1, c1, 0 @ auxiliary control reg
550 mov r0, r10 @ control register 549 mov r0, r9 @ control register
551 mov r2, r8, lsr #14 @ get TTB0 base
552 mov r2, r2, lsl #14
553 ldr r3, =PMD_TYPE_SECT | PMD_SECT_BUFFERABLE | \
554 PMD_SECT_CACHEABLE | PMD_SECT_AP_WRITE
555 b cpu_resume_mmu 550 b cpu_resume_mmu
556ENDPROC(cpu_xscale_do_resume) 551ENDPROC(cpu_xscale_do_resume)
557#endif 552#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index e4dde91f0231..a3045937fc2f 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -54,7 +54,7 @@
54 54
55#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR) 55#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
56 56
57 .macro addruart, rp, rv 57 .macro addruart, rp, rv, tmp
58 ldr \rp, =UART_PADDR @ physical 58 ldr \rp, =UART_PADDR @ physical
59 ldr \rv, =UART_VADDR @ virtual 59 ldr \rv, =UART_VADDR @ virtual
60 .endm 60 .endm
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
deleted file mode 100644
index 11be5cdbdd1a..000000000000
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ /dev/null
@@ -1,58 +0,0 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_MXC_MEMORY_H__
12#define __ASM_ARCH_MXC_MEMORY_H__
13
14#define MX1_PHYS_OFFSET UL(0x08000000)
15#define MX21_PHYS_OFFSET UL(0xc0000000)
16#define MX25_PHYS_OFFSET UL(0x80000000)
17#define MX27_PHYS_OFFSET UL(0xa0000000)
18#define MX3x_PHYS_OFFSET UL(0x80000000)
19#define MX50_PHYS_OFFSET UL(0x70000000)
20#define MX51_PHYS_OFFSET UL(0x90000000)
21#define MX53_PHYS_OFFSET UL(0x70000000)
22
23#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
24# if defined CONFIG_ARCH_MX1
25# define PLAT_PHYS_OFFSET MX1_PHYS_OFFSET
26# elif defined CONFIG_MACH_MX21
27# define PLAT_PHYS_OFFSET MX21_PHYS_OFFSET
28# elif defined CONFIG_ARCH_MX25
29# define PLAT_PHYS_OFFSET MX25_PHYS_OFFSET
30# elif defined CONFIG_MACH_MX27
31# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET
32# elif defined CONFIG_ARCH_MX3
33# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET
34# elif defined CONFIG_ARCH_MX50
35# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET
36# elif defined CONFIG_ARCH_MX51
37# define PLAT_PHYS_OFFSET MX51_PHYS_OFFSET
38# elif defined CONFIG_ARCH_MX53
39# define PLAT_PHYS_OFFSET MX53_PHYS_OFFSET
40# endif
41#endif
42
43#if defined(CONFIG_MX3_VIDEO)
44/*
45 * Increase size of DMA-consistent memory region.
46 * This is required for mx3 camera driver to capture at least two QXGA frames.
47 */
48#define CONSISTENT_DMA_SIZE SZ_8M
49
50#elif defined(CONFIG_MX1_VIDEO) || defined(CONFIG_VIDEO_MX2_HOSTSUPPORT)
51/*
52 * Increase size of DMA-consistent memory region.
53 * This is required for i.MX camera driver to capture at least four VGA frames.
54 */
55#define CONSISTENT_DMA_SIZE SZ_4M
56#endif /* CONFIG_MX1_VIDEO || CONFIG_VIDEO_MX2_HOSTSUPPORT */
57
58#endif /* __ASM_ARCH_MXC_MEMORY_H__ */
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 5b605a9eb091..6f4edd3408c2 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -15,6 +15,7 @@ config ARCH_OMAP1
15 select CLKSRC_MMIO 15 select CLKSRC_MMIO
16 select GENERIC_IRQ_CHIP 16 select GENERIC_IRQ_CHIP
17 select HAVE_IDE 17 select HAVE_IDE
18 select NEED_MACH_MEMORY_H
18 help 19 help
19 "Systems based on omap7xx, omap15xx or omap16xx" 20 "Systems based on omap7xx, omap15xx or omap16xx"
20 21
diff --git a/arch/arm/plat-omap/include/plat/io.h b/arch/arm/plat-omap/include/plat/io.h
index d72ec85c97e6..ebe67ea8d068 100644
--- a/arch/arm/plat-omap/include/plat/io.h
+++ b/arch/arm/plat-omap/include/plat/io.h
@@ -309,6 +309,8 @@ extern void omap2_init_common_devices(struct omap_sdrc_params *sdrc_cs0,
309void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type); 309void __iomem *omap_ioremap(unsigned long phys, size_t size, unsigned int type);
310void omap_iounmap(volatile void __iomem *addr); 310void omap_iounmap(volatile void __iomem *addr);
311 311
312extern void __init omap_init_consistent_dma_size(void);
313
312#endif 314#endif
313 315
314#endif 316#endif
diff --git a/arch/arm/plat-omap/include/plat/memory.h b/arch/arm/plat-omap/include/plat/memory.h
deleted file mode 100644
index e6720aa2d553..000000000000
--- a/arch/arm/plat-omap/include/plat/memory.h
+++ /dev/null
@@ -1,102 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/memory.h
3 *
4 * Memory map for OMAP-1510 and 1610
5 *
6 * Copyright (C) 2000 RidgeRun, Inc.
7 * Author: Greg Lonnon <glonnon@ridgerun.com>
8 *
9 * This file was derived from arch/arm/mach-intergrator/include/mach/memory.h
10 * Copyright (C) 1999 ARM Limited
11 *
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms of the GNU General Public License as published by the
14 * Free Software Foundation; either version 2 of the License, or (at your
15 * option) any later version.
16 *
17 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
18 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
20 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
24 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * You should have received a copy of the GNU General Public License along
29 * with this program; if not, write to the Free Software Foundation, Inc.,
30 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 */
32
33#ifndef __ASM_ARCH_MEMORY_H
34#define __ASM_ARCH_MEMORY_H
35
36/*
37 * Physical DRAM offset.
38 */
39#if defined(CONFIG_ARCH_OMAP1)
40#define PLAT_PHYS_OFFSET UL(0x10000000)
41#else
42#define PLAT_PHYS_OFFSET UL(0x80000000)
43#endif
44
45/*
46 * Bus address is physical address, except for OMAP-1510 Local Bus.
47 * OMAP-1510 bus address is translated into a Local Bus address if the
48 * OMAP bus type is lbus. We do the address translation based on the
49 * device overriding the defaults used in the dma-mapping API.
50 * Note that the is_lbus_device() test is not very efficient on 1510
51 * because of the strncmp().
52 */
53#ifdef CONFIG_ARCH_OMAP15XX
54
55/*
56 * OMAP-1510 Local Bus address offset
57 */
58#define OMAP1510_LB_OFFSET UL(0x30000000)
59
60#define virt_to_lbus(x) ((x) - PAGE_OFFSET + OMAP1510_LB_OFFSET)
61#define lbus_to_virt(x) ((x) - OMAP1510_LB_OFFSET + PAGE_OFFSET)
62#define is_lbus_device(dev) (cpu_is_omap15xx() && dev && (strncmp(dev_name(dev), "ohci", 4) == 0))
63
64#define __arch_pfn_to_dma(dev, pfn) \
65 ({ dma_addr_t __dma = __pfn_to_phys(pfn); \
66 if (is_lbus_device(dev)) \
67 __dma = __dma - PHYS_OFFSET + OMAP1510_LB_OFFSET; \
68 __dma; })
69
70#define __arch_dma_to_pfn(dev, addr) \
71 ({ dma_addr_t __dma = addr; \
72 if (is_lbus_device(dev)) \
73 __dma += PHYS_OFFSET - OMAP1510_LB_OFFSET; \
74 __phys_to_pfn(__dma); \
75 })
76
77#define __arch_dma_to_virt(dev, addr) ({ (void *) (is_lbus_device(dev) ? \
78 lbus_to_virt(addr) : \
79 __phys_to_virt(addr)); })
80
81#define __arch_virt_to_dma(dev, addr) ({ unsigned long __addr = (unsigned long)(addr); \
82 (dma_addr_t) (is_lbus_device(dev) ? \
83 virt_to_lbus(__addr) : \
84 __virt_to_phys(__addr)); })
85
86#endif /* CONFIG_ARCH_OMAP15XX */
87
88/* Override the ARM default */
89#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
90
91#if (CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE == 0)
92#undef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
93#define CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE 2
94#endif
95
96#define CONSISTENT_DMA_SIZE \
97 (((CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE + 1) & ~1) * 1024 * 1024)
98
99#endif
100
101#endif
102
diff --git a/arch/arm/plat-omap/include/plat/serial.h b/arch/arm/plat-omap/include/plat/serial.h
index de3b10c18127..1ab9fd6abe6d 100644
--- a/arch/arm/plat-omap/include/plat/serial.h
+++ b/arch/arm/plat-omap/include/plat/serial.h
@@ -16,8 +16,8 @@
16#include <linux/init.h> 16#include <linux/init.h>
17 17
18/* 18/*
19 * Memory entry used for the DEBUG_LL UART configuration. See also 19 * Memory entry used for the DEBUG_LL UART configuration, relative to
20 * uncompress.h and debug-macro.S. 20 * start of RAM. See also uncompress.h and debug-macro.S.
21 * 21 *
22 * Note that using a memory location for storing the UART configuration 22 * Note that using a memory location for storing the UART configuration
23 * has at least two limitations: 23 * has at least two limitations:
@@ -27,7 +27,7 @@
27 * 2. We assume printascii is called at least once before paging_init, 27 * 2. We assume printascii is called at least once before paging_init,
28 * and addruart has a chance to read OMAP_UART_INFO 28 * and addruart has a chance to read OMAP_UART_INFO
29 */ 29 */
30#define OMAP_UART_INFO (PLAT_PHYS_OFFSET + 0x3ffc) 30#define OMAP_UART_INFO_OFS 0x3ffc
31 31
32/* OMAP1 serial ports */ 32/* OMAP1 serial ports */
33#define OMAP1_UART1_BASE 0xfffb0000 33#define OMAP1_UART1_BASE 0xfffb0000
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index a067484cc4a2..2f472e989ec6 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -36,7 +36,13 @@ int uart_shift;
36 */ 36 */
37static void set_omap_uart_info(unsigned char port) 37static void set_omap_uart_info(unsigned char port)
38{ 38{
39 *(volatile u32 *)OMAP_UART_INFO = port; 39 /*
40 * Get address of some.bss variable and round it down
41 * a la CONFIG_AUTO_ZRELADDR.
42 */
43 u32 ram_start = (u32)&uart_shift & 0xf8000000;
44 u32 *uart_info = (u32 *)(ram_start + OMAP_UART_INFO_OFS);
45 *uart_info = port;
40} 46}
41 47
42static void putc(int c) 48static void putc(int c)
diff --git a/arch/arm/plat-omap/io.c b/arch/arm/plat-omap/io.c
index f1ecfa9fc61d..e9b0e23edd0a 100644
--- a/arch/arm/plat-omap/io.c
+++ b/arch/arm/plat-omap/io.c
@@ -12,6 +12,7 @@
12#include <linux/module.h> 12#include <linux/module.h>
13#include <linux/io.h> 13#include <linux/io.h>
14#include <linux/mm.h> 14#include <linux/mm.h>
15#include <linux/dma-mapping.h>
15 16
16#include <plat/omap7xx.h> 17#include <plat/omap7xx.h>
17#include <plat/omap1510.h> 18#include <plat/omap1510.h>
@@ -139,3 +140,10 @@ void omap_iounmap(volatile void __iomem *addr)
139 __iounmap(addr); 140 __iounmap(addr);
140} 141}
141EXPORT_SYMBOL(omap_iounmap); 142EXPORT_SYMBOL(omap_iounmap);
143
144void __init omap_init_consistent_dma_size(void)
145{
146#ifdef CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE
147 init_consistent_dma_size(CONFIG_FB_OMAP_CONSISTENT_DMA_SIZE << 20);
148#endif
149}
diff --git a/arch/arm/plat-spear/include/plat/debug-macro.S b/arch/arm/plat-spear/include/plat/debug-macro.S
index 8501bbf2c092..02b160a1ec9b 100644
--- a/arch/arm/plat-spear/include/plat/debug-macro.S
+++ b/arch/arm/plat-spear/include/plat/debug-macro.S
@@ -14,7 +14,7 @@
14#include <linux/amba/serial.h> 14#include <linux/amba/serial.h>
15#include <mach/hardware.h> 15#include <mach/hardware.h>
16 16
17 .macro addruart, rp, rv 17 .macro addruart, rp, rv, tmp
18 mov \rp, #SPEAR_DBG_UART_BASE @ Physical base 18 mov \rp, #SPEAR_DBG_UART_BASE @ Physical base
19 mov \rv, #VA_SPEAR_DBG_UART_BASE @ Virtual base 19 mov \rv, #VA_SPEAR_DBG_UART_BASE @ Virtual base
20 .endm 20 .endm
diff --git a/arch/arm/plat-spear/include/plat/memory.h b/arch/arm/plat-spear/include/plat/memory.h
deleted file mode 100644
index 7e3599e1104e..000000000000
--- a/arch/arm/plat-spear/include/plat/memory.h
+++ /dev/null
@@ -1,20 +0,0 @@
1/*
2 * arch/arm/plat-spear/include/plat/memory.h
3 *
4 * Memory map for SPEAr platform
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Viresh Kumar<viresh.kumar@st.com>
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#ifndef __PLAT_MEMORY_H
15#define __PLAT_MEMORY_H
16
17/* Physical DRAM offset */
18#define PLAT_PHYS_OFFSET UL(0x00000000)
19
20#endif /* __PLAT_MEMORY_H */
diff --git a/arch/arm/plat-tcc/include/mach/debug-macro.S b/arch/arm/plat-tcc/include/mach/debug-macro.S
index 7662f736e42b..cf17d04ec30d 100644
--- a/arch/arm/plat-tcc/include/mach/debug-macro.S
+++ b/arch/arm/plat-tcc/include/mach/debug-macro.S
@@ -9,7 +9,7 @@
9 * 9 *
10 */ 10 */
11 11
12 .macro addruart, rp, rv 12 .macro addruart, rp, rv, tmp
13 moveq \rp, #0x90000000 @ physical base address 13 moveq \rp, #0x90000000 @ physical base address
14 movne \rv, #0xF1000000 @ virtual base 14 movne \rv, #0xF1000000 @ virtual base
15 orr \rp, \rp, #0x00007000 @ UART0 15 orr \rp, \rp, #0x00007000 @ UART0
diff --git a/arch/arm/plat-tcc/include/mach/memory.h b/arch/arm/plat-tcc/include/mach/memory.h
deleted file mode 100644
index 28a6e0cd13b3..000000000000
--- a/arch/arm/plat-tcc/include/mach/memory.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 RidgeRun, Inc.
4 * Copyright (C) 2008-2009 Telechips
5 * Copyright (C) 2010 Hans J. Koch <hjk@linutronix.de>
6 *
7 * Licensed under the terms of the GPL v2.
8 */
9
10#ifndef __ASM_ARCH_MEMORY_H
11#define __ASM_ARCH_MEMORY_H
12
13/*
14 * Physical DRAM offset.
15 */
16#define PLAT_PHYS_OFFSET UL(0x20000000)
17
18#endif
diff --git a/arch/arm/vfp/vfpmodule.c b/arch/arm/vfp/vfpmodule.c
index 79bcb4316930..0cbd5a0a9332 100644
--- a/arch/arm/vfp/vfpmodule.c
+++ b/arch/arm/vfp/vfpmodule.c
@@ -11,6 +11,7 @@
11#include <linux/module.h> 11#include <linux/module.h>
12#include <linux/types.h> 12#include <linux/types.h>
13#include <linux/cpu.h> 13#include <linux/cpu.h>
14#include <linux/cpu_pm.h>
14#include <linux/kernel.h> 15#include <linux/kernel.h>
15#include <linux/notifier.h> 16#include <linux/notifier.h>
16#include <linux/signal.h> 17#include <linux/signal.h>
@@ -68,7 +69,7 @@ static bool vfp_state_in_hw(unsigned int cpu, struct thread_info *thread)
68/* 69/*
69 * Force a reload of the VFP context from the thread structure. We do 70 * Force a reload of the VFP context from the thread structure. We do
70 * this by ensuring that access to the VFP hardware is disabled, and 71 * this by ensuring that access to the VFP hardware is disabled, and
71 * clear last_VFP_context. Must be called from non-preemptible context. 72 * clear vfp_current_hw_state. Must be called from non-preemptible context.
72 */ 73 */
73static void vfp_force_reload(unsigned int cpu, struct thread_info *thread) 74static void vfp_force_reload(unsigned int cpu, struct thread_info *thread)
74{ 75{
@@ -436,9 +437,7 @@ static void vfp_enable(void *unused)
436 set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11)); 437 set_copro_access(access | CPACC_FULL(10) | CPACC_FULL(11));
437} 438}
438 439
439#ifdef CONFIG_PM 440#ifdef CONFIG_CPU_PM
440#include <linux/syscore_ops.h>
441
442static int vfp_pm_suspend(void) 441static int vfp_pm_suspend(void)
443{ 442{
444 struct thread_info *ti = current_thread_info(); 443 struct thread_info *ti = current_thread_info();
@@ -468,19 +467,33 @@ static void vfp_pm_resume(void)
468 fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN); 467 fmxr(FPEXC, fmrx(FPEXC) & ~FPEXC_EN);
469} 468}
470 469
471static struct syscore_ops vfp_pm_syscore_ops = { 470static int vfp_cpu_pm_notifier(struct notifier_block *self, unsigned long cmd,
472 .suspend = vfp_pm_suspend, 471 void *v)
473 .resume = vfp_pm_resume, 472{
473 switch (cmd) {
474 case CPU_PM_ENTER:
475 vfp_pm_suspend();
476 break;
477 case CPU_PM_ENTER_FAILED:
478 case CPU_PM_EXIT:
479 vfp_pm_resume();
480 break;
481 }
482 return NOTIFY_OK;
483}
484
485static struct notifier_block vfp_cpu_pm_notifier_block = {
486 .notifier_call = vfp_cpu_pm_notifier,
474}; 487};
475 488
476static void vfp_pm_init(void) 489static void vfp_pm_init(void)
477{ 490{
478 register_syscore_ops(&vfp_pm_syscore_ops); 491 cpu_pm_register_notifier(&vfp_cpu_pm_notifier_block);
479} 492}
480 493
481#else 494#else
482static inline void vfp_pm_init(void) { } 495static inline void vfp_pm_init(void) { }
483#endif /* CONFIG_PM */ 496#endif /* CONFIG_CPU_PM */
484 497
485/* 498/*
486 * Ensure that the VFP state stored in 'thread->vfpstate' is up to date 499 * Ensure that the VFP state stored in 'thread->vfpstate' is up to date