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authorRussell King <rmk+kernel@arm.linux.org.uk>2011-01-05 05:23:38 -0500
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-01-05 05:23:38 -0500
commit1051b9f0f9eab8091fe3bf98320741adf36b4cfa (patch)
tree68ea1c8f9c446d6ebd96caf3ba4ec73f1fa5ace6 /arch
parentcde9efef401563943d5a58eb9b7274bfdc08ca9b (diff)
parenta58154d1c3535f451a409abbd0bda6770b2d9380 (diff)
Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6 into devel-stable
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/Kconfig10
-rw-r--r--arch/arm/Makefile3
-rw-r--r--arch/arm/configs/mx3_defconfig1
-rw-r--r--arch/arm/mach-imx/Kconfig138
-rw-r--r--arch/arm/mach-imx/Makefile8
-rw-r--r--arch/arm/mach-imx/Makefile.boot4
-rw-r--r--arch/arm/mach-imx/clock-imx21.c2
-rw-r--r--arch/arm/mach-imx/clock-imx25.c (renamed from arch/arm/mach-mx25/clock.c)2
-rw-r--r--arch/arm/mach-imx/clock-imx27.c24
-rw-r--r--arch/arm/mach-imx/cpu-imx27.c14
-rw-r--r--arch/arm/mach-imx/devices-imx21.h24
-rw-r--r--arch/arm/mach-imx/devices-imx25.h (renamed from arch/arm/mach-mx25/devices-imx25.h)51
-rw-r--r--arch/arm/mach-imx/devices-imx27.h35
-rw-r--r--arch/arm/mach-imx/devices.c553
-rw-r--r--arch/arm/mach-imx/devices.h29
-rw-r--r--arch/arm/mach-imx/dma-v1.c4
-rw-r--r--arch/arm/mach-imx/eukrea_mbimx27-baseboard.c17
-rw-r--r--arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c (renamed from arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c)10
-rw-r--r--arch/arm/mach-imx/mach-cpuimx27.c21
-rw-r--r--arch/arm/mach-imx/mach-eukrea_cpuimx25.c (renamed from arch/arm/mach-mx25/mach-cpuimx25.c)19
-rw-r--r--arch/arm/mach-imx/mach-imx27_visstrim_m10.c12
-rw-r--r--arch/arm/mach-imx/mach-imx27lite.c1
-rw-r--r--arch/arm/mach-imx/mach-mx1ads.c1
-rw-r--r--arch/arm/mach-imx/mach-mx21ads.c20
-rw-r--r--arch/arm/mach-imx/mach-mx25_3ds.c (renamed from arch/arm/mach-mx25/mach-mx25_3ds.c)34
-rw-r--r--arch/arm/mach-imx/mach-mx27_3ds.c160
-rw-r--r--arch/arm/mach-imx/mach-mx27ads.c17
-rw-r--r--arch/arm/mach-imx/mach-mxt_td60.c11
-rw-r--r--arch/arm/mach-imx/mach-pca100.c33
-rw-r--r--arch/arm/mach-imx/mach-pcm038.c12
-rw-r--r--arch/arm/mach-imx/mach-scb9328.c1
-rw-r--r--arch/arm/mach-imx/mm-imx1.c7
-rw-r--r--arch/arm/mach-imx/mm-imx21.c21
-rw-r--r--arch/arm/mach-imx/mm-imx25.c (renamed from arch/arm/mach-mx25/mm.c)27
-rw-r--r--arch/arm/mach-imx/mm-imx27.c21
-rw-r--r--arch/arm/mach-imx/pcm970-baseboard.c12
-rw-r--r--arch/arm/mach-imx/pm-imx27.c3
-rw-r--r--arch/arm/mach-mx25/Kconfig34
-rw-r--r--arch/arm/mach-mx25/Makefile5
-rw-r--r--arch/arm/mach-mx25/Makefile.boot3
-rw-r--r--arch/arm/mach-mx25/devices.c308
-rw-r--r--arch/arm/mach-mx25/devices.h13
-rw-r--r--arch/arm/mach-mx3/Kconfig84
-rw-r--r--arch/arm/mach-mx3/Makefile7
-rw-r--r--arch/arm/mach-mx3/clock-imx31.c4
-rw-r--r--arch/arm/mach-mx3/clock-imx35.c2
-rw-r--r--arch/arm/mach-mx3/cpu.c31
-rw-r--r--arch/arm/mach-mx3/devices-imx31.h27
-rw-r--r--arch/arm/mach-mx3/devices-imx35.h41
-rw-r--r--arch/arm/mach-mx3/devices.c271
-rw-r--r--arch/arm/mach-mx3/devices.h10
-rw-r--r--arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c4
-rw-r--r--arch/arm/mach-mx3/mach-armadillo5x0.c14
-rw-r--r--arch/arm/mach-mx3/mach-cpuimx35.c22
-rw-r--r--arch/arm/mach-mx3/mach-kzm_arm11_01.c6
-rw-r--r--arch/arm/mach-mx3/mach-mx31_3ds.c124
-rw-r--r--arch/arm/mach-mx3/mach-mx31lilly.c9
-rw-r--r--arch/arm/mach-mx3/mach-mx31lite.c5
-rw-r--r--arch/arm/mach-mx3/mach-mx31moboard.c20
-rw-r--r--arch/arm/mach-mx3/mach-mx35_3ds.c40
-rw-r--r--arch/arm/mach-mx3/mach-pcm037.c23
-rw-r--r--arch/arm/mach-mx3/mach-pcm043.c48
-rw-r--r--arch/arm/mach-mx3/mm.c84
-rw-r--r--arch/arm/mach-mx3/mx31lilly-db.c5
-rw-r--r--arch/arm/mach-mx3/mx31lite-db.c8
-rw-r--r--arch/arm/mach-mx3/mx31moboard-devboard.c20
-rw-r--r--arch/arm/mach-mx3/mx31moboard-marxbot.c21
-rw-r--r--arch/arm/mach-mx3/mx31moboard-smartbot.c16
-rw-r--r--arch/arm/mach-mx5/Kconfig63
-rw-r--r--arch/arm/mach-mx5/Makefile5
-rw-r--r--arch/arm/mach-mx5/Makefile.boot12
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51.c32
-rw-r--r--arch/arm/mach-mx5/board-cpuimx51sd.c68
-rw-r--r--arch/arm/mach-mx5/board-mx50_rdp.c197
-rw-r--r--arch/arm/mach-mx5/board-mx51_3ds.c9
-rw-r--r--arch/arm/mach-mx5/board-mx51_babbage.c101
-rw-r--r--arch/arm/mach-mx5/board-mx51_efikamx.c247
-rw-r--r--arch/arm/mach-mx5/board-mx53_evk.c84
-rw-r--r--arch/arm/mach-mx5/clock-mx51-mx53.c (renamed from arch/arm/mach-mx5/clock-mx51.c)296
-rw-r--r--arch/arm/mach-mx5/cpu.c118
-rw-r--r--arch/arm/mach-mx5/crm_regs.h10
-rw-r--r--arch/arm/mach-mx5/devices-imx51.h11
-rw-r--r--arch/arm/mach-mx5/devices-imx53.h13
-rw-r--r--arch/arm/mach-mx5/devices-mx50.h26
-rw-r--r--arch/arm/mach-mx5/devices.c51
-rw-r--r--arch/arm/mach-mx5/devices.h2
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c26
-rw-r--r--arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c17
-rw-r--r--arch/arm/mach-mx5/mm-mx50.c59
-rw-r--r--arch/arm/mach-mx5/mm.c75
-rw-r--r--arch/arm/mach-mxc91231/mm.c53
-rw-r--r--arch/arm/mach-mxs/Kconfig34
-rw-r--r--arch/arm/mach-mxs/Makefile10
-rw-r--r--arch/arm/mach-mxs/Makefile.boot1
-rw-r--r--arch/arm/mach-mxs/clock-mx23.c526
-rw-r--r--arch/arm/mach-mxs/clock-mx28.c734
-rw-r--r--arch/arm/mach-mxs/clock.c200
-rw-r--r--arch/arm/mach-mxs/devices-mx23.h16
-rw-r--r--arch/arm/mach-mxs/devices-mx28.h20
-rw-r--r--arch/arm/mach-mxs/devices.c75
-rw-r--r--arch/arm/mach-mxs/devices/Kconfig5
-rw-r--r--arch/arm/mach-mxs/devices/Makefile2
-rw-r--r--arch/arm/mach-mxs/devices/platform-duart.c48
-rw-r--r--arch/arm/mach-mxs/devices/platform-fec.c50
-rw-r--r--arch/arm/mach-mxs/gpio.c325
-rw-r--r--arch/arm/mach-mxs/gpio.h34
-rw-r--r--arch/arm/mach-mxs/icoll.c81
-rw-r--r--arch/arm/mach-mxs/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-mxs/include/mach/clock.h64
-rw-r--r--arch/arm/mach-mxs/include/mach/common.h31
-rw-r--r--arch/arm/mach-mxs/include/mach/debug-macro.S38
-rw-r--r--arch/arm/mach-mxs/include/mach/devices-common.h46
-rw-r--r--arch/arm/mach-mxs/include/mach/entry-macro.S41
-rw-r--r--arch/arm/mach-mxs/include/mach/gpio.h35
-rw-r--r--arch/arm/mach-mxs/include/mach/hardware.h29
-rw-r--r--arch/arm/mach-mxs/include/mach/io.h22
-rw-r--r--arch/arm/mach-mxs/include/mach/iomux-mx23.h355
-rw-r--r--arch/arm/mach-mxs/include/mach/iomux-mx28.h537
-rw-r--r--arch/arm/mach-mxs/include/mach/iomux.h165
-rw-r--r--arch/arm/mach-mxs/include/mach/irqs.h32
-rw-r--r--arch/arm/mach-mxs/include/mach/memory.h24
-rw-r--r--arch/arm/mach-mxs/include/mach/mx23.h145
-rw-r--r--arch/arm/mach-mxs/include/mach/mx28.h188
-rw-r--r--arch/arm/mach-mxs/include/mach/mxs.h105
-rw-r--r--arch/arm/mach-mxs/include/mach/system.h27
-rw-r--r--arch/arm/mach-mxs/include/mach/timex.h21
-rw-r--r--arch/arm/mach-mxs/include/mach/uncompress.h76
-rw-r--r--arch/arm/mach-mxs/include/mach/vmalloc.h22
-rw-r--r--arch/arm/mach-mxs/iomux.c101
-rw-r--r--arch/arm/mach-mxs/mach-mx23evk.c57
-rw-r--r--arch/arm/mach-mxs/mach-mx28evk.c138
-rw-r--r--arch/arm/mach-mxs/mm-mx23.c45
-rw-r--r--arch/arm/mach-mxs/mm-mx28.c45
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx23.h455
-rw-r--r--arch/arm/mach-mxs/regs-clkctrl-mx28.h663
-rw-r--r--arch/arm/mach-mxs/system.c137
-rw-r--r--arch/arm/mach-mxs/timer.c296
-rw-r--r--arch/arm/plat-mxc/Kconfig15
-rw-r--r--arch/arm/plat-mxc/Makefile5
-rw-r--r--arch/arm/plat-mxc/audmux-v2.c4
-rw-r--r--arch/arm/plat-mxc/avic.c (renamed from arch/arm/plat-mxc/irq.c)32
-rw-r--r--arch/arm/plat-mxc/cpufreq.c1
-rw-r--r--arch/arm/plat-mxc/devices.c23
-rw-r--r--arch/arm/plat-mxc/devices/Kconfig54
-rw-r--r--arch/arm/plat-mxc/devices/Makefile16
-rw-r--r--arch/arm/plat-mxc/devices/platform-esdhc.c71
-rw-r--r--arch/arm/plat-mxc/devices/platform-fec.c8
-rw-r--r--arch/arm/plat-mxc/devices/platform-flexcan.c48
-rw-r--r--arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c56
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-dma.c127
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-fb.c52
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-i2c.c16
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-keypad.c62
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-ssi.c17
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx-uart.c38
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx2-wdt.c68
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx21-hcd.c41
-rw-r--r--arch/arm/plat-mxc/devices/platform-imx_udc.c75
-rw-r--r--arch/arm/plat-mxc/devices/platform-imxdi_rtc.c41
-rw-r--r--arch/arm/plat-mxc/devices/platform-mx1-camera.c42
-rw-r--r--arch/arm/plat-mxc/devices/platform-mx2-camera.c64
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc-ehci.c69
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc-mmc.c72
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_nand.c10
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_pwm.c60
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_rnga.c56
-rw-r--r--arch/arm/plat-mxc/devices/platform-mxc_w1.c50
-rw-r--r--arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c74
-rw-r--r--arch/arm/plat-mxc/devices/platform-spi_imx.c16
-rw-r--r--arch/arm/plat-mxc/ehci.c77
-rw-r--r--arch/arm/plat-mxc/gpio.c114
-rw-r--r--arch/arm/plat-mxc/include/mach/common.h9
-rw-r--r--arch/arm/plat-mxc/include/mach/debug-macro.S23
-rw-r--r--arch/arm/plat-mxc/include/mach/devices-common.h174
-rw-r--r--arch/arm/plat-mxc/include/mach/entry-macro.S14
-rw-r--r--arch/arm/plat-mxc/include/mach/gpio.h5
-rw-r--r--arch/arm/plat-mxc/include/mach/hardware.h94
-rw-r--r--arch/arm/plat-mxc/include/mach/imxfb.h3
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx50.h977
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx51.h1898
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-mx53.h323
-rw-r--r--arch/arm/plat-mxc/include/mach/iomux-v3.h64
-rw-r--r--arch/arm/plat-mxc/include/mach/irqs.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/memory.h8
-rw-r--r--arch/arm/plat-mxc/include/mach/mx1.h155
-rw-r--r--arch/arm/plat-mxc/include/mach/mx21.h50
-rw-r--r--arch/arm/plat-mxc/include/mach/mx25.h46
-rw-r--r--arch/arm/plat-mxc/include/mach/mx27.h105
-rw-r--r--arch/arm/plat-mxc/include/mach/mx2x.h149
-rw-r--r--arch/arm/plat-mxc/include/mach/mx31.h87
-rw-r--r--arch/arm/plat-mxc/include/mach/mx35.h51
-rw-r--r--arch/arm/plat-mxc/include/mach/mx3x.h198
-rw-r--r--arch/arm/plat-mxc/include/mach/mx50.h285
-rw-r--r--arch/arm/plat-mxc/include/mach/mx51.h73
-rw-r--r--arch/arm/plat-mxc/include/mach/mx53.h353
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc.h42
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc91231.h23
-rw-r--r--arch/arm/plat-mxc/include/mach/mxc_ehci.h1
-rw-r--r--arch/arm/plat-mxc/include/mach/sdma.h46
-rw-r--r--arch/arm/plat-mxc/include/mach/uncompress.h8
-rw-r--r--arch/arm/plat-mxc/iomux-v3.c31
-rw-r--r--arch/arm/plat-mxc/irq-common.c60
-rw-r--r--arch/arm/plat-mxc/irq-common.h29
-rw-r--r--arch/arm/plat-mxc/system.c10
-rw-r--r--arch/arm/plat-mxc/tzic.c46
205 files changed, 13965 insertions, 3411 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4d1c3093a133..fac58916adec 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -352,6 +352,14 @@ config ARCH_MXC
352 help 352 help
353 Support for Freescale MXC/iMX-based family of processors 353 Support for Freescale MXC/iMX-based family of processors
354 354
355config ARCH_MXS
356 bool "Freescale MXS-based"
357 select GENERIC_CLOCKEVENTS
358 select ARCH_REQUIRE_GPIOLIB
359 select COMMON_CLKDEV
360 help
361 Support for Freescale MXS-based family of processors
362
355config ARCH_STMP3XXX 363config ARCH_STMP3XXX
356 bool "Freescale STMP3xxx" 364 bool "Freescale STMP3xxx"
357 select CPU_ARM926T 365 select CPU_ARM926T
@@ -904,6 +912,8 @@ source "arch/arm/mach-mv78xx0/Kconfig"
904 912
905source "arch/arm/plat-mxc/Kconfig" 913source "arch/arm/plat-mxc/Kconfig"
906 914
915source "arch/arm/mach-mxs/Kconfig"
916
907source "arch/arm/mach-netx/Kconfig" 917source "arch/arm/mach-netx/Kconfig"
908 918
909source "arch/arm/mach-nomadik/Kconfig" 919source "arch/arm/mach-nomadik/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index b87aed028eef..c22c1adfedd6 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -154,10 +154,11 @@ machine-$(CONFIG_ARCH_MSM) := msm
154machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0 154machine-$(CONFIG_ARCH_MV78XX0) := mv78xx0
155machine-$(CONFIG_ARCH_MX1) := imx 155machine-$(CONFIG_ARCH_MX1) := imx
156machine-$(CONFIG_ARCH_MX2) := imx 156machine-$(CONFIG_ARCH_MX2) := imx
157machine-$(CONFIG_ARCH_MX25) := mx25 157machine-$(CONFIG_ARCH_MX25) := imx
158machine-$(CONFIG_ARCH_MX3) := mx3 158machine-$(CONFIG_ARCH_MX3) := mx3
159machine-$(CONFIG_ARCH_MX5) := mx5 159machine-$(CONFIG_ARCH_MX5) := mx5
160machine-$(CONFIG_ARCH_MXC91231) := mxc91231 160machine-$(CONFIG_ARCH_MXC91231) := mxc91231
161machine-$(CONFIG_ARCH_MXS) := mxs
161machine-$(CONFIG_ARCH_NETX) := netx 162machine-$(CONFIG_ARCH_NETX) := netx
162machine-$(CONFIG_ARCH_NOMADIK) := nomadik 163machine-$(CONFIG_ARCH_NOMADIK) := nomadik
163machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx 164machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
diff --git a/arch/arm/configs/mx3_defconfig b/arch/arm/configs/mx3_defconfig
index f0c339fd5d21..e648ea3429be 100644
--- a/arch/arm/configs/mx3_defconfig
+++ b/arch/arm/configs/mx3_defconfig
@@ -84,6 +84,7 @@ CONFIG_SERIAL_IMX_CONSOLE=y
84CONFIG_I2C=y 84CONFIG_I2C=y
85CONFIG_I2C_CHARDEV=y 85CONFIG_I2C_CHARDEV=y
86CONFIG_I2C_IMX=y 86CONFIG_I2C_IMX=y
87CONFIG_SPI=y
87CONFIG_W1=y 88CONFIG_W1=y
88CONFIG_W1_MASTER_MXC=y 89CONFIG_W1_MASTER_MXC=y
89CONFIG_W1_SLAVE_THERM=y 90CONFIG_W1_SLAVE_THERM=y
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 197f9e241cff..17d2e608a214 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,13 +1,37 @@
1config IMX_HAVE_DMA_V1 1config IMX_HAVE_DMA_V1
2 bool 2 bool
3 3
4if ARCH_MX1
5
6config SOC_IMX1 4config SOC_IMX1
5 bool
7 select CPU_ARM920T 6 select CPU_ARM920T
8 select IMX_HAVE_DMA_V1 7 select IMX_HAVE_DMA_V1
9 select IMX_HAVE_IOMUX_V1 8 select IMX_HAVE_IOMUX_V1
9 select MXC_AVIC
10
11config SOC_IMX21
12 bool
13 select CPU_ARM926T
14 select ARCH_MXC_AUDMUX_V1
15 select IMX_HAVE_DMA_V1
16 select IMX_HAVE_IOMUX_V1
17 select MXC_AVIC
18
19config SOC_IMX25
10 bool 20 bool
21 select CPU_ARM926T
22 select ARCH_MXC_AUDMUX_V2
23 select ARCH_MXC_IOMUX_V3
24 select MXC_AVIC
25
26config SOC_IMX27
27 bool
28 select CPU_ARM926T
29 select ARCH_MXC_AUDMUX_V1
30 select IMX_HAVE_DMA_V1
31 select IMX_HAVE_IOMUX_V1
32 select MXC_AVIC
33
34if ARCH_MX1
11 35
12comment "MX1 platforms:" 36comment "MX1 platforms:"
13config MACH_MXLADS 37config MACH_MXLADS
@@ -31,33 +55,17 @@ endif
31 55
32if ARCH_MX2 56if ARCH_MX2
33 57
34config SOC_IMX21
35 select CPU_ARM926T
36 select ARCH_MXC_AUDMUX_V1
37 select IMX_HAVE_DMA_V1
38 select IMX_HAVE_IOMUX_V1
39 bool
40
41config SOC_IMX27
42 select CPU_ARM926T
43 select ARCH_MXC_AUDMUX_V1
44 select IMX_HAVE_DMA_V1
45 select IMX_HAVE_IOMUX_V1
46 bool
47
48choice 58choice
49 prompt "CPUs:" 59 prompt "CPUs:"
50 default MACH_MX21 60 default MACH_MX21
51 61
52config MACH_MX21 62config MACH_MX21
53 bool "i.MX21 support" 63 bool "i.MX21 support"
54 select SOC_IMX21
55 help 64 help
56 This enables support for Freescale's MX2 based i.MX21 processor. 65 This enables support for Freescale's MX2 based i.MX21 processor.
57 66
58config MACH_MX27 67config MACH_MX27
59 bool "i.MX27 support" 68 bool "i.MX27 support"
60 select SOC_IMX27
61 help 69 help
62 This enables support for Freescale's MX2 based i.MX27 processor. 70 This enables support for Freescale's MX2 based i.MX27 processor.
63 71
@@ -71,7 +79,10 @@ comment "MX21 platforms:"
71 79
72config MACH_MX21ADS 80config MACH_MX21ADS
73 bool "MX21ADS platform" 81 bool "MX21ADS platform"
82 select SOC_IMX21
83 select IMX_HAVE_PLATFORM_IMX_FB
74 select IMX_HAVE_PLATFORM_IMX_UART 84 select IMX_HAVE_PLATFORM_IMX_UART
85 select IMX_HAVE_PLATFORM_MXC_MMC
75 select IMX_HAVE_PLATFORM_MXC_NAND 86 select IMX_HAVE_PLATFORM_MXC_NAND
76 help 87 help
77 Include support for MX21ADS platform. This includes specific 88 Include support for MX21ADS platform. This includes specific
@@ -79,24 +90,79 @@ config MACH_MX21ADS
79 90
80endif 91endif
81 92
93if ARCH_MX25
94
95comment "MX25 platforms:"
96
97config MACH_MX25_3DS
98 bool "Support MX25PDK (3DS) Platform"
99 select SOC_IMX25
100 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
101 select IMX_HAVE_PLATFORM_IMX2_WDT
102 select IMX_HAVE_PLATFORM_IMXDI_RTC
103 select IMX_HAVE_PLATFORM_IMX_FB
104 select IMX_HAVE_PLATFORM_IMX_KEYPAD
105 select IMX_HAVE_PLATFORM_IMX_UART
106 select IMX_HAVE_PLATFORM_MXC_EHCI
107 select IMX_HAVE_PLATFORM_MXC_NAND
108 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
109
110config MACH_EUKREA_CPUIMX25
111 bool "Support Eukrea CPUIMX25 Platform"
112 select SOC_IMX25
113 select IMX_HAVE_PLATFORM_FLEXCAN
114 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
115 select IMX_HAVE_PLATFORM_IMXDI_RTC
116 select IMX_HAVE_PLATFORM_IMX_FB
117 select IMX_HAVE_PLATFORM_IMX_I2C
118 select IMX_HAVE_PLATFORM_IMX_UART
119 select IMX_HAVE_PLATFORM_MXC_EHCI
120 select IMX_HAVE_PLATFORM_MXC_NAND
121 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
122 select MXC_ULPI if USB_ULPI
123
124choice
125 prompt "Baseboard"
126 depends on MACH_EUKREA_CPUIMX25
127 default MACH_EUKREA_MBIMXSD25_BASEBOARD
128
129config MACH_EUKREA_MBIMXSD25_BASEBOARD
130 bool "Eukrea MBIMXSD development board"
131 select IMX_HAVE_PLATFORM_IMX_SSI
132 help
133 This adds board specific devices that can be found on Eukrea's
134 MBIMXSD evaluation board.
135
136endchoice
137
138endif
139
82if MACH_MX27 140if MACH_MX27
83 141
84comment "MX27 platforms:" 142comment "MX27 platforms:"
85 143
86config MACH_MX27ADS 144config MACH_MX27ADS
87 bool "MX27ADS platform" 145 bool "MX27ADS platform"
146 select SOC_IMX27
147 select IMX_HAVE_PLATFORM_IMX_FB
88 select IMX_HAVE_PLATFORM_IMX_I2C 148 select IMX_HAVE_PLATFORM_IMX_I2C
89 select IMX_HAVE_PLATFORM_IMX_UART 149 select IMX_HAVE_PLATFORM_IMX_UART
150 select IMX_HAVE_PLATFORM_MXC_MMC
90 select IMX_HAVE_PLATFORM_MXC_NAND 151 select IMX_HAVE_PLATFORM_MXC_NAND
152 select IMX_HAVE_PLATFORM_MXC_W1
91 help 153 help
92 Include support for MX27ADS platform. This includes specific 154 Include support for MX27ADS platform. This includes specific
93 configurations for the board and its peripherals. 155 configurations for the board and its peripherals.
94 156
95config MACH_PCM038 157config MACH_PCM038
96 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)" 158 bool "Phytec phyCORE-i.MX27 CPU module (pcm038)"
159 select SOC_IMX27
160 select IMX_HAVE_PLATFORM_IMX2_WDT
97 select IMX_HAVE_PLATFORM_IMX_I2C 161 select IMX_HAVE_PLATFORM_IMX_I2C
98 select IMX_HAVE_PLATFORM_IMX_UART 162 select IMX_HAVE_PLATFORM_IMX_UART
163 select IMX_HAVE_PLATFORM_MXC_EHCI
99 select IMX_HAVE_PLATFORM_MXC_NAND 164 select IMX_HAVE_PLATFORM_MXC_NAND
165 select IMX_HAVE_PLATFORM_MXC_W1
100 select IMX_HAVE_PLATFORM_SPI_IMX 166 select IMX_HAVE_PLATFORM_SPI_IMX
101 select MXC_ULPI if USB_ULPI 167 select MXC_ULPI if USB_ULPI
102 help 168 help
@@ -109,8 +175,9 @@ choice
109 default MACH_PCM970_BASEBOARD 175 default MACH_PCM970_BASEBOARD
110 176
111config MACH_PCM970_BASEBOARD 177config MACH_PCM970_BASEBOARD
112 prompt "PHYTEC PCM970 development board" 178 bool "PHYTEC PCM970 development board"
113 bool 179 select IMX_HAVE_PLATFORM_IMX_FB
180 select IMX_HAVE_PLATFORM_MXC_MMC
114 help 181 help
115 This adds board specific devices that can be found on Phytec's 182 This adds board specific devices that can be found on Phytec's
116 PCM970 evaluation board. 183 PCM970 evaluation board.
@@ -119,9 +186,14 @@ endchoice
119 186
120config MACH_CPUIMX27 187config MACH_CPUIMX27
121 bool "Eukrea CPUIMX27 module" 188 bool "Eukrea CPUIMX27 module"
189 select SOC_IMX27
190 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
191 select IMX_HAVE_PLATFORM_IMX2_WDT
122 select IMX_HAVE_PLATFORM_IMX_I2C 192 select IMX_HAVE_PLATFORM_IMX_I2C
123 select IMX_HAVE_PLATFORM_IMX_UART 193 select IMX_HAVE_PLATFORM_IMX_UART
194 select IMX_HAVE_PLATFORM_MXC_EHCI
124 select IMX_HAVE_PLATFORM_MXC_NAND 195 select IMX_HAVE_PLATFORM_MXC_NAND
196 select IMX_HAVE_PLATFORM_MXC_W1
125 select MXC_ULPI if USB_ULPI 197 select MXC_ULPI if USB_ULPI
126 help 198 help
127 Include support for Eukrea CPUIMX27 platform. This includes 199 Include support for Eukrea CPUIMX27 platform. This includes
@@ -130,6 +202,7 @@ config MACH_CPUIMX27
130config MACH_EUKREA_CPUIMX27_USESDHC2 202config MACH_EUKREA_CPUIMX27_USESDHC2
131 bool "CPUIMX27 integrates SDHC2 module" 203 bool "CPUIMX27 integrates SDHC2 module"
132 depends on MACH_CPUIMX27 204 depends on MACH_CPUIMX27
205 select IMX_HAVE_PLATFORM_MXC_MMC
133 help 206 help
134 This adds support for the internal SDHC2 used on CPUIMX27 207 This adds support for the internal SDHC2 used on CPUIMX27
135 for wifi or eMMC. 208 for wifi or eMMC.
@@ -148,8 +221,11 @@ choice
148 221
149config MACH_EUKREA_MBIMX27_BASEBOARD 222config MACH_EUKREA_MBIMX27_BASEBOARD
150 bool "Eukrea MBIMX27 development board" 223 bool "Eukrea MBIMX27 development board"
224 select IMX_HAVE_PLATFORM_IMX_FB
225 select IMX_HAVE_PLATFORM_IMX_KEYPAD
151 select IMX_HAVE_PLATFORM_IMX_SSI 226 select IMX_HAVE_PLATFORM_IMX_SSI
152 select IMX_HAVE_PLATFORM_IMX_UART 227 select IMX_HAVE_PLATFORM_IMX_UART
228 select IMX_HAVE_PLATFORM_MXC_MMC
153 select IMX_HAVE_PLATFORM_SPI_IMX 229 select IMX_HAVE_PLATFORM_SPI_IMX
154 help 230 help
155 This adds board specific devices that can be found on Eukrea's 231 This adds board specific devices that can be found on Eukrea's
@@ -159,15 +235,26 @@ endchoice
159 235
160config MACH_MX27_3DS 236config MACH_MX27_3DS
161 bool "MX27PDK platform" 237 bool "MX27PDK platform"
238 select SOC_IMX27
239 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
240 select IMX_HAVE_PLATFORM_IMX2_WDT
241 select IMX_HAVE_PLATFORM_IMX_KEYPAD
162 select IMX_HAVE_PLATFORM_IMX_UART 242 select IMX_HAVE_PLATFORM_IMX_UART
243 select IMX_HAVE_PLATFORM_MXC_EHCI
244 select IMX_HAVE_PLATFORM_MXC_MMC
245 select IMX_HAVE_PLATFORM_SPI_IMX
246 select MXC_ULPI if USB_ULPI
163 help 247 help
164 Include support for MX27PDK platform. This includes specific 248 Include support for MX27PDK platform. This includes specific
165 configurations for the board and its peripherals. 249 configurations for the board and its peripherals.
166 250
167config MACH_IMX27_VISSTRIM_M10 251config MACH_IMX27_VISSTRIM_M10
168 bool "Vista Silicon i.MX27 Visstrim_m10" 252 bool "Vista Silicon i.MX27 Visstrim_m10"
253 select SOC_IMX27
169 select IMX_HAVE_PLATFORM_IMX_I2C 254 select IMX_HAVE_PLATFORM_IMX_I2C
170 select IMX_HAVE_PLATFORM_IMX_UART 255 select IMX_HAVE_PLATFORM_IMX_UART
256 select IMX_HAVE_PLATFORM_MXC_MMC
257 select IMX_HAVE_PLATFORM_MXC_EHCI
171 help 258 help
172 Include support for Visstrim_m10 platform and its different variants. 259 Include support for Visstrim_m10 platform and its different variants.
173 This includes specific configurations for the board and its 260 This includes specific configurations for the board and its
@@ -175,6 +262,7 @@ config MACH_IMX27_VISSTRIM_M10
175 262
176config MACH_IMX27LITE 263config MACH_IMX27LITE
177 bool "LogicPD MX27 LITEKIT platform" 264 bool "LogicPD MX27 LITEKIT platform"
265 select SOC_IMX27
178 select IMX_HAVE_PLATFORM_IMX_UART 266 select IMX_HAVE_PLATFORM_IMX_UART
179 help 267 help
180 Include support for MX27 LITEKIT platform. This includes specific 268 Include support for MX27 LITEKIT platform. This includes specific
@@ -182,10 +270,17 @@ config MACH_IMX27LITE
182 270
183config MACH_PCA100 271config MACH_PCA100
184 bool "Phytec phyCARD-s (pca100)" 272 bool "Phytec phyCARD-s (pca100)"
273 select SOC_IMX27
274 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
275 select IMX_HAVE_PLATFORM_IMX2_WDT
276 select IMX_HAVE_PLATFORM_IMX_FB
185 select IMX_HAVE_PLATFORM_IMX_I2C 277 select IMX_HAVE_PLATFORM_IMX_I2C
186 select IMX_HAVE_PLATFORM_IMX_SSI 278 select IMX_HAVE_PLATFORM_IMX_SSI
187 select IMX_HAVE_PLATFORM_IMX_UART 279 select IMX_HAVE_PLATFORM_IMX_UART
280 select IMX_HAVE_PLATFORM_MXC_EHCI
281 select IMX_HAVE_PLATFORM_MXC_MMC
188 select IMX_HAVE_PLATFORM_MXC_NAND 282 select IMX_HAVE_PLATFORM_MXC_NAND
283 select IMX_HAVE_PLATFORM_MXC_W1
189 select IMX_HAVE_PLATFORM_SPI_IMX 284 select IMX_HAVE_PLATFORM_SPI_IMX
190 select MXC_ULPI if USB_ULPI 285 select MXC_ULPI if USB_ULPI
191 help 286 help
@@ -194,8 +289,11 @@ config MACH_PCA100
194 289
195config MACH_MXT_TD60 290config MACH_MXT_TD60
196 bool "Maxtrack i-MXT TD60" 291 bool "Maxtrack i-MXT TD60"
292 select SOC_IMX27
293 select IMX_HAVE_PLATFORM_IMX_FB
197 select IMX_HAVE_PLATFORM_IMX_I2C 294 select IMX_HAVE_PLATFORM_IMX_I2C
198 select IMX_HAVE_PLATFORM_IMX_UART 295 select IMX_HAVE_PLATFORM_IMX_UART
296 select IMX_HAVE_PLATFORM_MXC_MMC
199 select IMX_HAVE_PLATFORM_MXC_NAND 297 select IMX_HAVE_PLATFORM_MXC_NAND
200 help 298 help
201 Include support for i-MXT (aka td60) platform. This 299 Include support for i-MXT (aka td60) platform. This
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index 5582692bb176..77100bf26153 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -4,13 +4,13 @@
4 4
5# Object file lists. 5# Object file lists.
6 6
7obj-y := devices.o
8
9obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o 7obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
10 8
11obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o 9obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
12obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o 10obj-$(CONFIG_MACH_MX21) += clock-imx21.o mm-imx21.o
13 11
12obj-$(CONFIG_ARCH_MX25) += clock-imx25.o mm-imx25.o
13
14obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o 14obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
15obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o 15obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o
16 16
@@ -22,6 +22,10 @@ obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
22 22
23obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o 23obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
24 24
25obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
26obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
27obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
28
25obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o 29obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
26obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o 30obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
27obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o 31obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 7988a85cf07d..3953d60bff0b 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -6,6 +6,10 @@ zreladdr-$(CONFIG_MACH_MX21) := 0xC0008000
6params_phys-$(CONFIG_MACH_MX21) := 0xC0000100 6params_phys-$(CONFIG_MACH_MX21) := 0xC0000100
7initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000 7initrd_phys-$(CONFIG_MACH_MX21) := 0xC0800000
8 8
9zreladdr-$(CONFIG_ARCH_MX25) := 0x80008000
10params_phys-$(CONFIG_ARCH_MX25) := 0x80000100
11initrd_phys-$(CONFIG_ARCH_MX25) := 0x80800000
12
9zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000 13zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
10params_phys-$(CONFIG_MACH_MX27) := 0xA0000100 14params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
11initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000 15initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c
index cf15ea516a72..c63a4f5ffcb6 100644
--- a/arch/arm/mach-imx/clock-imx21.c
+++ b/arch/arm/mach-imx/clock-imx21.c
@@ -1185,7 +1185,7 @@ static struct clk_lookup lookups[] = {
1185 _REGISTER_CLOCK(NULL, "brom", brom_clk) 1185 _REGISTER_CLOCK(NULL, "brom", brom_clk)
1186 _REGISTER_CLOCK(NULL, "emma", emma_clk[0]) 1186 _REGISTER_CLOCK(NULL, "emma", emma_clk[0])
1187 _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0]) 1187 _REGISTER_CLOCK(NULL, "slcdc", slcdc_clk[0])
1188 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) 1188 _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
1189 _REGISTER_CLOCK(NULL, "gpio", gpio_clk) 1189 _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
1190 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk) 1190 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
1191 _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk) 1191 _REGISTER_CLOCK("mxc-keypad", NULL, kpp_clk)
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-imx/clock-imx25.c
index 9e4a5578c2fb..21ef34c501e5 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-imx/clock-imx25.c
@@ -296,7 +296,7 @@ static struct clk_lookup lookups[] = {
296 _REGISTER_CLOCK("fec.0", NULL, fec_clk) 296 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
297 _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk) 297 _REGISTER_CLOCK("imxdi_rtc.0", NULL, dryice_clk)
298 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk) 298 _REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
299 _REGISTER_CLOCK("imx-wdt.0", NULL, wdt_clk) 299 _REGISTER_CLOCK("imx2-wdt.0", NULL, wdt_clk)
300 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) 300 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
301 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) 301 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
302 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) 302 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 98a25bada783..f32f3b8e8ba4 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -125,7 +125,7 @@ static int clk_cpu_set_parent(struct clk *clk, struct clk *parent)
125 if (clk->parent == parent) 125 if (clk->parent == parent)
126 return 0; 126 return 0;
127 127
128 if (mx27_revision() >= CHIP_REV_2_0) { 128 if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
129 if (parent == &mpll_main1_clk) { 129 if (parent == &mpll_main1_clk) {
130 cscr |= CCM_CSCR_ARM_SRC; 130 cscr |= CCM_CSCR_ARM_SRC;
131 } else { 131 } else {
@@ -174,7 +174,7 @@ static int set_rate_cpu(struct clk *clk, unsigned long rate)
174 div--; 174 div--;
175 175
176 reg = __raw_readl(CCM_CSCR); 176 reg = __raw_readl(CCM_CSCR);
177 if (mx27_revision() >= CHIP_REV_2_0) { 177 if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
178 reg &= ~(3 << 12); 178 reg &= ~(3 << 12);
179 reg |= div << 12; 179 reg |= div << 12;
180 reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN); 180 reg &= ~(CCM_CSCR_FPM | CCM_CSCR_SPEN);
@@ -244,7 +244,7 @@ static unsigned long get_rate_ssix(struct clk *clk, unsigned long pdf)
244 244
245 parent_rate = clk_get_rate(clk->parent); 245 parent_rate = clk_get_rate(clk->parent);
246 246
247 if (mx27_revision() >= CHIP_REV_2_0) 247 if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
248 pdf += 4; /* MX27 TO2+ */ 248 pdf += 4; /* MX27 TO2+ */
249 else 249 else
250 pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */ 250 pdf = (pdf < 2) ? 124UL : pdf; /* MX21 & MX27 TO1 */
@@ -269,7 +269,7 @@ static unsigned long get_rate_nfc(struct clk *clk)
269 269
270 parent_rate = clk_get_rate(clk->parent); 270 parent_rate = clk_get_rate(clk->parent);
271 271
272 if (mx27_revision() >= CHIP_REV_2_0) 272 if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
273 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf; 273 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 6) & 0xf;
274 else 274 else
275 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf; 275 nfc_pdf = (__raw_readl(CCM_PCDR0) >> 12) & 0xf;
@@ -284,7 +284,7 @@ static unsigned long get_rate_vpu(struct clk *clk)
284 284
285 parent_rate = clk_get_rate(clk->parent); 285 parent_rate = clk_get_rate(clk->parent);
286 286
287 if (mx27_revision() >= CHIP_REV_2_0) { 287 if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
288 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f; 288 vpu_pdf = (__raw_readl(CCM_PCDR0) >> 10) & 0x3f;
289 vpu_pdf += 4; 289 vpu_pdf += 4;
290 } else { 290 } else {
@@ -347,7 +347,7 @@ static unsigned long get_rate_mpll_main(struct clk *clk)
347 * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2 347 * clk->id == 0: arm clock source path 1 which is from 2 * MPLL / 2
348 * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3 348 * clk->id == 1: arm clock source path 2 which is from 2 * MPLL / 3
349 */ 349 */
350 if (mx27_revision() >= CHIP_REV_2_0 && clk->id == 1) 350 if (mx27_revision() >= IMX_CHIP_REVISION_2_0 && clk->id == 1)
351 return 2UL * parent_rate / 3UL; 351 return 2UL * parent_rate / 3UL;
352 352
353 return parent_rate; 353 return parent_rate;
@@ -365,7 +365,7 @@ static unsigned long get_rate_spll(struct clk *clk)
365 /* On TO2 we have to write the value back. Otherwise we 365 /* On TO2 we have to write the value back. Otherwise we
366 * read 0 from this register the next time. 366 * read 0 from this register the next time.
367 */ 367 */
368 if (mx27_revision() >= CHIP_REV_2_0) 368 if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
369 __raw_writel(reg, CCM_SPCTL0); 369 __raw_writel(reg, CCM_SPCTL0);
370 370
371 return mxc_decode_pll(reg, rate); 371 return mxc_decode_pll(reg, rate);
@@ -376,7 +376,7 @@ static unsigned long get_rate_cpu(struct clk *clk)
376 u32 div; 376 u32 div;
377 unsigned long rate; 377 unsigned long rate;
378 378
379 if (mx27_revision() >= CHIP_REV_2_0) 379 if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
380 div = (__raw_readl(CCM_CSCR) >> 12) & 0x3; 380 div = (__raw_readl(CCM_CSCR) >> 12) & 0x3;
381 else 381 else
382 div = (__raw_readl(CCM_CSCR) >> 13) & 0x7; 382 div = (__raw_readl(CCM_CSCR) >> 13) & 0x7;
@@ -389,7 +389,7 @@ static unsigned long get_rate_ahb(struct clk *clk)
389{ 389{
390 unsigned long rate, bclk_pdf; 390 unsigned long rate, bclk_pdf;
391 391
392 if (mx27_revision() >= CHIP_REV_2_0) 392 if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
393 bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3; 393 bclk_pdf = (__raw_readl(CCM_CSCR) >> 8) & 0x3;
394 else 394 else
395 bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf; 395 bclk_pdf = (__raw_readl(CCM_CSCR) >> 9) & 0xf;
@@ -402,7 +402,7 @@ static unsigned long get_rate_ipg(struct clk *clk)
402{ 402{
403 unsigned long rate, ipg_pdf; 403 unsigned long rate, ipg_pdf;
404 404
405 if (mx27_revision() >= CHIP_REV_2_0) 405 if (mx27_revision() >= IMX_CHIP_REVISION_2_0)
406 return clk_get_rate(clk->parent); 406 return clk_get_rate(clk->parent);
407 else 407 else
408 ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1; 408 ipg_pdf = (__raw_readl(CCM_CSCR) >> 8) & 1;
@@ -667,7 +667,7 @@ static struct clk_lookup lookups[] = {
667 _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk) 667 _REGISTER_CLOCK(NULL, "sahara2", sahara2_clk)
668 _REGISTER_CLOCK(NULL, "ata", ata_clk) 668 _REGISTER_CLOCK(NULL, "ata", ata_clk)
669 _REGISTER_CLOCK(NULL, "mstick", mstick_clk) 669 _REGISTER_CLOCK(NULL, "mstick", mstick_clk)
670 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) 670 _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
671 _REGISTER_CLOCK(NULL, "gpio", gpio_clk) 671 _REGISTER_CLOCK(NULL, "gpio", gpio_clk)
672 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk) 672 _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
673 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) 673 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
@@ -683,7 +683,7 @@ static void __init to2_adjust_clocks(void)
683{ 683{
684 unsigned long cscr = __raw_readl(CCM_CSCR); 684 unsigned long cscr = __raw_readl(CCM_CSCR);
685 685
686 if (mx27_revision() >= CHIP_REV_2_0) { 686 if (mx27_revision() >= IMX_CHIP_REVISION_2_0) {
687 if (cscr & CCM_CSCR_ARM_SRC) 687 if (cscr & CCM_CSCR_ARM_SRC)
688 cpu_clk.parent = &mpll_main1_clk; 688 cpu_clk.parent = &mpll_main1_clk;
689 689
diff --git a/arch/arm/mach-imx/cpu-imx27.c b/arch/arm/mach-imx/cpu-imx27.c
index d8d3b2d84dc5..3b117be37bd2 100644
--- a/arch/arm/mach-imx/cpu-imx27.c
+++ b/arch/arm/mach-imx/cpu-imx27.c
@@ -42,7 +42,19 @@ static void query_silicon_parameter(void)
42 val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR 42 val = __raw_readl(MX27_IO_ADDRESS(MX27_SYSCTRL_BASE_ADDR
43 + SYS_CHIP_ID)); 43 + SYS_CHIP_ID));
44 44
45 cpu_silicon_rev = (int)(val >> 28); 45 switch (val >> 28) {
46 case 0:
47 cpu_silicon_rev = IMX_CHIP_REVISION_1_0;
48 break;
49 case 1:
50 cpu_silicon_rev = IMX_CHIP_REVISION_2_0;
51 break;
52 case 2:
53 cpu_silicon_rev = IMX_CHIP_REVISION_2_1;
54 break;
55 default:
56 cpu_silicon_rev = IMX_CHIP_REVISION_UNKNOWN;
57 }
46 cpu_partnumber = (int)((val >> 12) & 0xFFFF); 58 cpu_partnumber = (int)((val >> 12) & 0xFFFF);
47} 59}
48 60
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index d189039749b0..16744d2d9b81 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -9,10 +9,26 @@
9#include <mach/mx21.h> 9#include <mach/mx21.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst;
13#define imx21_add_imx21_hcd(pdata) \
14 imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
15
16extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst;
17#define imx21_add_imx2_wdt(pdata) \
18 imx_add_imx2_wdt(&imx21_imx2_wdt_data)
19
20extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst;
21#define imx21_add_imx_fb(pdata) \
22 imx_add_imx_fb(&imx21_imx_fb_data, pdata)
23
12extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst; 24extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
13#define imx21_add_imx_i2c(pdata) \ 25#define imx21_add_imx_i2c(pdata) \
14 imx_add_imx_i2c(&imx21_imx_i2c_data, pdata) 26 imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
15 27
28extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst;
29#define imx21_add_imx_keypad(pdata) \
30 imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
31
16extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst; 32extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
17#define imx21_add_imx_ssi(id, pdata) \ 33#define imx21_add_imx_ssi(id, pdata) \
18 imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata) 34 imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
@@ -25,10 +41,18 @@ extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
25#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata) 41#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
26#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata) 42#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
27 43
44extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst;
45#define imx21_add_mxc_mmc(id, pdata) \
46 imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
47
28extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst; 48extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
29#define imx21_add_mxc_nand(pdata) \ 49#define imx21_add_mxc_nand(pdata) \
30 imx_add_mxc_nand(&imx21_mxc_nand_data, pdata) 50 imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
31 51
52extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst;
53#define imx21_add_mxc_w1(pdata) \
54 imx_add_mxc_w1(&imx21_mxc_w1_data)
55
32extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst; 56extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
33#define imx21_add_cspi(id, pdata) \ 57#define imx21_add_cspi(id, pdata) \
34 imx_add_spi_imx(&imx21_cspi_data[id], pdata) 58 imx_add_spi_imx(&imx21_cspi_data[id], pdata)
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index d94d282fa676..bde33caf1b90 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -13,10 +13,27 @@ extern const struct imx_fec_data imx25_fec_data __initconst;
13#define imx25_add_fec(pdata) \ 13#define imx25_add_fec(pdata) \
14 imx_add_fec(&imx25_fec_data, pdata) 14 imx_add_fec(&imx25_fec_data, pdata)
15 15
16#define imx25_add_flexcan0(pdata) \ 16extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst;
17 imx_add_flexcan(0, MX25_CAN1_BASE_ADDR, SZ_16K, MX25_INT_CAN1, pdata) 17#define imx25_add_flexcan(id, pdata) \
18#define imx25_add_flexcan1(pdata) \ 18 imx_add_flexcan(&imx25_flexcan_data[id], pdata)
19 imx_add_flexcan(1, MX25_CAN2_BASE_ADDR, SZ_16K, MX25_INT_CAN2, pdata) 19#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata)
20#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata)
21
22extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst;
23#define imx25_add_fsl_usb2_udc(pdata) \
24 imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
25
26extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst;
27#define imx25_add_imxdi_rtc(pdata) \
28 imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
29
30extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst;
31#define imx25_add_imx2_wdt(pdata) \
32 imx_add_imx2_wdt(&imx25_imx2_wdt_data)
33
34extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst;
35#define imx25_add_imx_fb(pdata) \
36 imx_add_imx_fb(&imx25_imx_fb_data, pdata)
20 37
21extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst; 38extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
22#define imx25_add_imx_i2c(id, pdata) \ 39#define imx25_add_imx_i2c(id, pdata) \
@@ -25,6 +42,10 @@ extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
25#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata) 42#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
26#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata) 43#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
27 44
45extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst;
46#define imx25_add_imx_keypad(pdata) \
47 imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
48
28extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst; 49extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
29#define imx25_add_imx_ssi(id, pdata) \ 50#define imx25_add_imx_ssi(id, pdata) \
30 imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata) 51 imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
@@ -38,17 +59,29 @@ extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
38#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata) 59#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
39#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata) 60#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
40 61
62extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst;
63#define imx25_add_mx2_camera(pdata) \
64 imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
65
66extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst;
67#define imx25_add_mxc_ehci_otg(pdata) \
68 imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
69extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst;
70#define imx25_add_mxc_ehci_hs(pdata) \
71 imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
72
41extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst; 73extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
42#define imx25_add_mxc_nand(pdata) \ 74#define imx25_add_mxc_nand(pdata) \
43 imx_add_mxc_nand(&imx25_mxc_nand_data, pdata) 75 imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
44 76
77extern const struct imx_sdhci_esdhc_imx_data
78imx25_sdhci_esdhc_imx_data[] __initconst;
79#define imx25_add_sdhci_esdhc_imx(id, pdata) \
80 imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
81
45extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst; 82extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
46#define imx25_add_spi_imx(id, pdata) \ 83#define imx25_add_spi_imx(id, pdata) \
47 imx_add_spi_imx(&imx25_cspi_data[id], pdata) 84 imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
48#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata) 85#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
49#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata) 86#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
50#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata) 87#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
51
52extern const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst;
53#define imx25_add_esdhc(id, pdata) \
54 imx_add_esdhc(&imx25_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 7011690364f2..f1272d4b5a33 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -13,10 +13,26 @@ extern const struct imx_fec_data imx27_fec_data __initconst;
13#define imx27_add_fec(pdata) \ 13#define imx27_add_fec(pdata) \
14 imx_add_fec(&imx27_fec_data, pdata) 14 imx_add_fec(&imx27_fec_data, pdata)
15 15
16extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst;
17#define imx27_add_fsl_usb2_udc(pdata) \
18 imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
19
20extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst;
21#define imx27_add_imx2_wdt(pdata) \
22 imx_add_imx2_wdt(&imx27_imx2_wdt_data)
23
24extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst;
25#define imx27_add_imx_fb(pdata) \
26 imx_add_imx_fb(&imx27_imx_fb_data, pdata)
27
16extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst; 28extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
17#define imx27_add_imx_i2c(id, pdata) \ 29#define imx27_add_imx_i2c(id, pdata) \
18 imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata) 30 imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
19 31
32extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst;
33#define imx27_add_imx_keypad(pdata) \
34 imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
35
20extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst; 36extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
21#define imx27_add_imx_ssi(id, pdata) \ 37#define imx27_add_imx_ssi(id, pdata) \
22 imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata) 38 imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
@@ -31,10 +47,29 @@ extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
31#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata) 47#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
32#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata) 48#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
33 49
50extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst;
51#define imx27_add_mx2_camera(pdata) \
52 imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
53
54extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst;
55#define imx27_add_mxc_ehci_otg(pdata) \
56 imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
57extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst;
58#define imx27_add_mxc_ehci_hs(id, pdata) \
59 imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
60
61extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst;
62#define imx27_add_mxc_mmc(id, pdata) \
63 imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
64
34extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst; 65extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
35#define imx27_add_mxc_nand(pdata) \ 66#define imx27_add_mxc_nand(pdata) \
36 imx_add_mxc_nand(&imx27_mxc_nand_data, pdata) 67 imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
37 68
69extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst;
70#define imx27_add_mxc_w1(pdata) \
71 imx_add_mxc_w1(&imx27_mxc_w1_data)
72
38extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst; 73extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
39#define imx27_add_cspi(id, pdata) \ 74#define imx27_add_cspi(id, pdata) \
40 imx_add_spi_imx(&imx27_cspi_data[id], pdata) 75 imx_add_spi_imx(&imx27_cspi_data[id], pdata)
diff --git a/arch/arm/mach-imx/devices.c b/arch/arm/mach-imx/devices.c
deleted file mode 100644
index fba5047de8b1..000000000000
--- a/arch/arm/mach-imx/devices.c
+++ /dev/null
@@ -1,553 +0,0 @@
1/*
2 * Author: MontaVista Software, Inc.
3 * <source@mvista.com>
4 *
5 * Based on the OMAP devices.c
6 *
7 * 2005 (c) MontaVista Software, Inc. This file is licensed under the
8 * terms of the GNU General Public License version 2. This program is
9 * licensed "as is" without any warranty of any kind, whether express
10 * or implied.
11 *
12 * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
13 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
14 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
15 * Copyright (c) 2008 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
16 * Copyright (c) 2008 Darius Augulis <darius.augulis@teltonika.lt>
17 *
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License
20 * as published by the Free Software Foundation; either version 2
21 * of the License, or (at your option) any later version.
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
30 * MA 02110-1301, USA.
31 */
32#include <linux/module.h>
33#include <linux/kernel.h>
34#include <linux/init.h>
35#include <linux/platform_device.h>
36#include <linux/gpio.h>
37#include <linux/dma-mapping.h>
38#include <linux/serial.h>
39
40#include <mach/irqs.h>
41#include <mach/hardware.h>
42#include <mach/common.h>
43#include <mach/mmc.h>
44
45#include "devices.h"
46
47#if defined(CONFIG_ARCH_MX1)
48static struct resource imx1_camera_resources[] = {
49 {
50 .start = 0x00224000,
51 .end = 0x00224010,
52 .flags = IORESOURCE_MEM,
53 }, {
54 .start = MX1_CSI_INT,
55 .end = MX1_CSI_INT,
56 .flags = IORESOURCE_IRQ,
57 },
58};
59
60static u64 imx1_camera_dmamask = DMA_BIT_MASK(32);
61
62struct platform_device imx1_camera_device = {
63 .name = "mx1-camera",
64 .id = 0, /* This is used to put cameras on this interface */
65 .dev = {
66 .dma_mask = &imx1_camera_dmamask,
67 .coherent_dma_mask = DMA_BIT_MASK(32),
68 },
69 .resource = imx1_camera_resources,
70 .num_resources = ARRAY_SIZE(imx1_camera_resources),
71};
72
73static struct resource imx_rtc_resources[] = {
74 {
75 .start = 0x00204000,
76 .end = 0x00204024,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX1_RTC_INT,
80 .end = MX1_RTC_INT,
81 .flags = IORESOURCE_IRQ,
82 }, {
83 .start = MX1_RTC_SAMINT,
84 .end = MX1_RTC_SAMINT,
85 .flags = IORESOURCE_IRQ,
86 },
87};
88
89struct platform_device imx_rtc_device = {
90 .name = "rtc-imx",
91 .id = 0,
92 .resource = imx_rtc_resources,
93 .num_resources = ARRAY_SIZE(imx_rtc_resources),
94};
95
96static struct resource imx_wdt_resources[] = {
97 {
98 .start = 0x00201000,
99 .end = 0x00201008,
100 .flags = IORESOURCE_MEM,
101 }, {
102 .start = MX1_WDT_INT,
103 .end = MX1_WDT_INT,
104 .flags = IORESOURCE_IRQ,
105 },
106};
107
108struct platform_device imx_wdt_device = {
109 .name = "imx-wdt",
110 .id = 0,
111 .resource = imx_wdt_resources,
112 .num_resources = ARRAY_SIZE(imx_wdt_resources),
113};
114
115static struct resource imx_usb_resources[] = {
116 {
117 .start = 0x00212000,
118 .end = 0x00212148,
119 .flags = IORESOURCE_MEM,
120 }, {
121 .start = MX1_USBD_INT0,
122 .end = MX1_USBD_INT0,
123 .flags = IORESOURCE_IRQ,
124 }, {
125 .start = MX1_USBD_INT1,
126 .end = MX1_USBD_INT1,
127 .flags = IORESOURCE_IRQ,
128 }, {
129 .start = MX1_USBD_INT2,
130 .end = MX1_USBD_INT2,
131 .flags = IORESOURCE_IRQ,
132 }, {
133 .start = MX1_USBD_INT3,
134 .end = MX1_USBD_INT3,
135 .flags = IORESOURCE_IRQ,
136 }, {
137 .start = MX1_USBD_INT4,
138 .end = MX1_USBD_INT4,
139 .flags = IORESOURCE_IRQ,
140 }, {
141 .start = MX1_USBD_INT5,
142 .end = MX1_USBD_INT5,
143 .flags = IORESOURCE_IRQ,
144 }, {
145 .start = MX1_USBD_INT6,
146 .end = MX1_USBD_INT6,
147 .flags = IORESOURCE_IRQ,
148 },
149};
150
151struct platform_device imx_usb_device = {
152 .name = "imx_udc",
153 .id = 0,
154 .num_resources = ARRAY_SIZE(imx_usb_resources),
155 .resource = imx_usb_resources,
156};
157
158/* GPIO port description */
159static struct mxc_gpio_port imx_gpio_ports[] = {
160 {
161 .chip.label = "gpio-0",
162 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR),
163 .irq = MX1_GPIO_INT_PORTA,
164 .virtual_irq_start = MXC_GPIO_IRQ_START,
165 }, {
166 .chip.label = "gpio-1",
167 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x100),
168 .irq = MX1_GPIO_INT_PORTB,
169 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
170 }, {
171 .chip.label = "gpio-2",
172 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x200),
173 .irq = MX1_GPIO_INT_PORTC,
174 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
175 }, {
176 .chip.label = "gpio-3",
177 .base = (void __iomem *)MX1_IO_ADDRESS(MX1_GPIO_BASE_ADDR + 0x300),
178 .irq = MX1_GPIO_INT_PORTD,
179 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
180 }
181};
182
183int __init imx1_register_gpios(void)
184{
185 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
186}
187#endif
188
189#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
190
191#ifdef CONFIG_MACH_MX27
192static struct resource mx27_camera_resources[] = {
193 {
194 .start = MX27_CSI_BASE_ADDR,
195 .end = MX27_CSI_BASE_ADDR + 0x1f,
196 .flags = IORESOURCE_MEM,
197 }, {
198 .start = MX27_EMMA_PRP_BASE_ADDR,
199 .end = MX27_EMMA_PRP_BASE_ADDR + 0x1f,
200 .flags = IORESOURCE_MEM,
201 }, {
202 .start = MX27_INT_CSI,
203 .end = MX27_INT_CSI,
204 .flags = IORESOURCE_IRQ,
205 },{
206 .start = MX27_INT_EMMAPRP,
207 .end = MX27_INT_EMMAPRP,
208 .flags = IORESOURCE_IRQ,
209 },
210};
211struct platform_device mx27_camera_device = {
212 .name = "mx2-camera",
213 .id = 0,
214 .num_resources = ARRAY_SIZE(mx27_camera_resources),
215 .resource = mx27_camera_resources,
216 .dev = {
217 .coherent_dma_mask = 0xffffffff,
218 },
219};
220#endif
221
222/*
223 * General Purpose Timer
224 * - i.MX21: 3 timers
225 * - i.MX27: 6 timers
226 */
227#define DEFINE_IMX_GPT_DEVICE(n, baseaddr, irq) \
228 static struct resource timer ## n ##_resources[] = { \
229 { \
230 .start = baseaddr, \
231 .end = baseaddr + SZ_4K - 1, \
232 .flags = IORESOURCE_MEM, \
233 }, { \
234 .start = irq, \
235 .end = irq, \
236 .flags = IORESOURCE_IRQ, \
237 } \
238 }; \
239 \
240 struct platform_device mxc_gpt ## n = { \
241 .name = "imx_gpt", \
242 .id = n, \
243 .num_resources = ARRAY_SIZE(timer ## n ## _resources), \
244 .resource = timer ## n ## _resources, \
245 }
246
247/* We use gpt1 as system timer, so do not add a device for this one */
248DEFINE_IMX_GPT_DEVICE(1, MX2x_GPT2_BASE_ADDR, MX2x_INT_GPT2);
249DEFINE_IMX_GPT_DEVICE(2, MX2x_GPT3_BASE_ADDR, MX2x_INT_GPT3);
250
251#ifdef CONFIG_MACH_MX27
252DEFINE_IMX_GPT_DEVICE(3, MX27_GPT4_BASE_ADDR, MX27_INT_GPT4);
253DEFINE_IMX_GPT_DEVICE(4, MX27_GPT5_BASE_ADDR, MX27_INT_GPT5);
254DEFINE_IMX_GPT_DEVICE(5, MX27_GPT6_BASE_ADDR, MX27_INT_GPT6);
255#endif
256
257/* Watchdog: i.MX1 has seperate driver, i.MX21 and i.MX27 are equal */
258static struct resource mxc_wdt_resources[] = {
259 {
260 .start = MX2x_WDOG_BASE_ADDR,
261 .end = MX2x_WDOG_BASE_ADDR + SZ_4K - 1,
262 .flags = IORESOURCE_MEM,
263 },
264};
265
266struct platform_device mxc_wdt = {
267 .name = "imx2-wdt",
268 .id = 0,
269 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
270 .resource = mxc_wdt_resources,
271};
272
273static struct resource mxc_w1_master_resources[] = {
274 {
275 .start = MX2x_OWIRE_BASE_ADDR,
276 .end = MX2x_OWIRE_BASE_ADDR + SZ_4K - 1,
277 .flags = IORESOURCE_MEM,
278 },
279};
280
281struct platform_device mxc_w1_master_device = {
282 .name = "mxc_w1",
283 .id = 0,
284 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
285 .resource = mxc_w1_master_resources,
286};
287
288/*
289 * lcdc:
290 * - i.MX1: the basic controller
291 * - i.MX21: to be checked
292 * - i.MX27: like i.MX1, with slightly variations
293 */
294static struct resource mxc_fb[] = {
295 {
296 .start = MX2x_LCDC_BASE_ADDR,
297 .end = MX2x_LCDC_BASE_ADDR + SZ_4K - 1,
298 .flags = IORESOURCE_MEM,
299 }, {
300 .start = MX2x_INT_LCDC,
301 .end = MX2x_INT_LCDC,
302 .flags = IORESOURCE_IRQ,
303 }
304};
305
306/* mxc lcd driver */
307struct platform_device mxc_fb_device = {
308 .name = "imx-fb",
309 .id = 0,
310 .num_resources = ARRAY_SIZE(mxc_fb),
311 .resource = mxc_fb,
312 .dev = {
313 .coherent_dma_mask = DMA_BIT_MASK(32),
314 },
315};
316
317static struct resource mxc_pwm_resources[] = {
318 {
319 .start = MX2x_PWM_BASE_ADDR,
320 .end = MX2x_PWM_BASE_ADDR + SZ_4K - 1,
321 .flags = IORESOURCE_MEM,
322 }, {
323 .start = MX2x_INT_PWM,
324 .end = MX2x_INT_PWM,
325 .flags = IORESOURCE_IRQ,
326 }
327};
328
329struct platform_device mxc_pwm_device = {
330 .name = "mxc_pwm",
331 .id = 0,
332 .num_resources = ARRAY_SIZE(mxc_pwm_resources),
333 .resource = mxc_pwm_resources,
334};
335
336#define DEFINE_MXC_MMC_DEVICE(n, baseaddr, irq, dmareq) \
337 static struct resource mxc_sdhc_resources ## n[] = { \
338 { \
339 .start = baseaddr, \
340 .end = baseaddr + SZ_4K - 1, \
341 .flags = IORESOURCE_MEM, \
342 }, { \
343 .start = irq, \
344 .end = irq, \
345 .flags = IORESOURCE_IRQ, \
346 }, { \
347 .start = dmareq, \
348 .end = dmareq, \
349 .flags = IORESOURCE_DMA, \
350 }, \
351 }; \
352 \
353 static u64 mxc_sdhc ## n ## _dmamask = DMA_BIT_MASK(32); \
354 \
355 struct platform_device mxc_sdhc_device ## n = { \
356 .name = "mxc-mmc", \
357 .id = n, \
358 .dev = { \
359 .dma_mask = &mxc_sdhc ## n ## _dmamask, \
360 .coherent_dma_mask = DMA_BIT_MASK(32), \
361 }, \
362 .num_resources = ARRAY_SIZE(mxc_sdhc_resources ## n), \
363 .resource = mxc_sdhc_resources ## n, \
364 }
365
366DEFINE_MXC_MMC_DEVICE(0, MX2x_SDHC1_BASE_ADDR, MX2x_INT_SDHC1, MX2x_DMA_REQ_SDHC1);
367DEFINE_MXC_MMC_DEVICE(1, MX2x_SDHC2_BASE_ADDR, MX2x_INT_SDHC2, MX2x_DMA_REQ_SDHC2);
368
369#ifdef CONFIG_MACH_MX27
370static struct resource otg_resources[] = {
371 {
372 .start = MX27_USBOTG_BASE_ADDR,
373 .end = MX27_USBOTG_BASE_ADDR + 0x1ff,
374 .flags = IORESOURCE_MEM,
375 }, {
376 .start = MX27_INT_USB3,
377 .end = MX27_INT_USB3,
378 .flags = IORESOURCE_IRQ,
379 },
380};
381
382static u64 otg_dmamask = DMA_BIT_MASK(32);
383
384/* OTG gadget device */
385struct platform_device mxc_otg_udc_device = {
386 .name = "fsl-usb2-udc",
387 .id = -1,
388 .dev = {
389 .dma_mask = &otg_dmamask,
390 .coherent_dma_mask = DMA_BIT_MASK(32),
391 },
392 .resource = otg_resources,
393 .num_resources = ARRAY_SIZE(otg_resources),
394};
395
396/* OTG host */
397struct platform_device mxc_otg_host = {
398 .name = "mxc-ehci",
399 .id = 0,
400 .dev = {
401 .coherent_dma_mask = DMA_BIT_MASK(32),
402 .dma_mask = &otg_dmamask,
403 },
404 .resource = otg_resources,
405 .num_resources = ARRAY_SIZE(otg_resources),
406};
407
408/* USB host 1 */
409
410static u64 usbh1_dmamask = DMA_BIT_MASK(32);
411
412static struct resource mxc_usbh1_resources[] = {
413 {
414 .start = MX27_USBOTG_BASE_ADDR + 0x200,
415 .end = MX27_USBOTG_BASE_ADDR + 0x3ff,
416 .flags = IORESOURCE_MEM,
417 }, {
418 .start = MX27_INT_USB1,
419 .end = MX27_INT_USB1,
420 .flags = IORESOURCE_IRQ,
421 },
422};
423
424struct platform_device mxc_usbh1 = {
425 .name = "mxc-ehci",
426 .id = 1,
427 .dev = {
428 .coherent_dma_mask = DMA_BIT_MASK(32),
429 .dma_mask = &usbh1_dmamask,
430 },
431 .resource = mxc_usbh1_resources,
432 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
433};
434
435/* USB host 2 */
436static u64 usbh2_dmamask = DMA_BIT_MASK(32);
437
438static struct resource mxc_usbh2_resources[] = {
439 {
440 .start = MX27_USBOTG_BASE_ADDR + 0x400,
441 .end = MX27_USBOTG_BASE_ADDR + 0x5ff,
442 .flags = IORESOURCE_MEM,
443 }, {
444 .start = MX27_INT_USB2,
445 .end = MX27_INT_USB2,
446 .flags = IORESOURCE_IRQ,
447 },
448};
449
450struct platform_device mxc_usbh2 = {
451 .name = "mxc-ehci",
452 .id = 2,
453 .dev = {
454 .coherent_dma_mask = DMA_BIT_MASK(32),
455 .dma_mask = &usbh2_dmamask,
456 },
457 .resource = mxc_usbh2_resources,
458 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
459};
460#endif
461
462/* GPIO port description */
463#define DEFINE_MXC_GPIO_PORT_IRQ(SOC, n, _irq) \
464 { \
465 .chip.label = "gpio-" #n, \
466 .irq = _irq, \
467 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
468 n * 0x100), \
469 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
470 }
471
472#define DEFINE_MXC_GPIO_PORT(SOC, n) \
473 { \
474 .chip.label = "gpio-" #n, \
475 .base = SOC ## _IO_ADDRESS(MX2x_GPIO_BASE_ADDR + \
476 n * 0x100), \
477 .virtual_irq_start = MXC_GPIO_IRQ_START + n * 32, \
478 }
479
480#define DEFINE_MXC_GPIO_PORTS(SOC, pfx) \
481 static struct mxc_gpio_port pfx ## _gpio_ports[] = { \
482 DEFINE_MXC_GPIO_PORT_IRQ(SOC, 0, SOC ## _INT_GPIO), \
483 DEFINE_MXC_GPIO_PORT(SOC, 1), \
484 DEFINE_MXC_GPIO_PORT(SOC, 2), \
485 DEFINE_MXC_GPIO_PORT(SOC, 3), \
486 DEFINE_MXC_GPIO_PORT(SOC, 4), \
487 DEFINE_MXC_GPIO_PORT(SOC, 5), \
488 }
489
490#ifdef CONFIG_MACH_MX21
491DEFINE_MXC_GPIO_PORTS(MX21, imx21);
492
493int __init imx21_register_gpios(void)
494{
495 return mxc_gpio_init(imx21_gpio_ports, ARRAY_SIZE(imx21_gpio_ports));
496}
497#endif
498
499#ifdef CONFIG_MACH_MX27
500DEFINE_MXC_GPIO_PORTS(MX27, imx27);
501
502int __init imx27_register_gpios(void)
503{
504 return mxc_gpio_init(imx27_gpio_ports, ARRAY_SIZE(imx27_gpio_ports));
505}
506#endif
507
508#ifdef CONFIG_MACH_MX21
509static struct resource mx21_usbhc_resources[] = {
510 {
511 .start = MX21_USBOTG_BASE_ADDR,
512 .end = MX21_USBOTG_BASE_ADDR + SZ_8K - 1,
513 .flags = IORESOURCE_MEM,
514 },
515 {
516 .start = MX21_INT_USBHOST,
517 .end = MX21_INT_USBHOST,
518 .flags = IORESOURCE_IRQ,
519 },
520};
521
522struct platform_device mx21_usbhc_device = {
523 .name = "imx21-hcd",
524 .id = 0,
525 .dev = {
526 .dma_mask = &mx21_usbhc_device.dev.coherent_dma_mask,
527 .coherent_dma_mask = DMA_BIT_MASK(32),
528 },
529 .num_resources = ARRAY_SIZE(mx21_usbhc_resources),
530 .resource = mx21_usbhc_resources,
531};
532#endif
533
534static struct resource imx_kpp_resources[] = {
535 {
536 .start = MX2x_KPP_BASE_ADDR,
537 .end = MX2x_KPP_BASE_ADDR + 0xf,
538 .flags = IORESOURCE_MEM
539 }, {
540 .start = MX2x_INT_KPP,
541 .end = MX2x_INT_KPP,
542 .flags = IORESOURCE_IRQ,
543 },
544};
545
546struct platform_device imx_kpp_device = {
547 .name = "imx-keypad",
548 .id = -1,
549 .num_resources = ARRAY_SIZE(imx_kpp_resources),
550 .resource = imx_kpp_resources,
551};
552
553#endif
diff --git a/arch/arm/mach-imx/devices.h b/arch/arm/mach-imx/devices.h
deleted file mode 100644
index 807f02a031c9..000000000000
--- a/arch/arm/mach-imx/devices.h
+++ /dev/null
@@ -1,29 +0,0 @@
1#ifdef CONFIG_ARCH_MX1
2extern struct platform_device imx1_camera_device;
3extern struct platform_device imx_rtc_device;
4extern struct platform_device imx_wdt_device;
5extern struct platform_device imx_usb_device;
6#endif
7
8#if defined(CONFIG_MACH_MX21) || defined(CONFIG_MACH_MX27)
9extern struct platform_device mxc_gpt1;
10extern struct platform_device mxc_gpt2;
11#ifdef CONFIG_MACH_MX27
12extern struct platform_device mxc_gpt3;
13extern struct platform_device mxc_gpt4;
14extern struct platform_device mxc_gpt5;
15#endif
16extern struct platform_device mxc_wdt;
17extern struct platform_device mxc_w1_master_device;
18extern struct platform_device mxc_fb_device;
19extern struct platform_device mxc_pwm_device;
20extern struct platform_device mxc_sdhc_device0;
21extern struct platform_device mxc_sdhc_device1;
22extern struct platform_device mxc_otg_udc_device;
23extern struct platform_device mx27_camera_device;
24extern struct platform_device mxc_otg_host;
25extern struct platform_device mxc_usbh1;
26extern struct platform_device mxc_usbh2;
27extern struct platform_device mx21_usbhc_device;
28extern struct platform_device imx_kpp_device;
29#endif
diff --git a/arch/arm/mach-imx/dma-v1.c b/arch/arm/mach-imx/dma-v1.c
index 3e8c47c63bac..e9f1769b49f5 100644
--- a/arch/arm/mach-imx/dma-v1.c
+++ b/arch/arm/mach-imx/dma-v1.c
@@ -818,9 +818,11 @@ static int __init imx_dma_init(void)
818 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR); 818 imx_dmav1_baseaddr = MX27_IO_ADDRESS(MX27_DMA_BASE_ADDR);
819 else 819 else
820#endif 820#endif
821 BUG(); 821 return 0;
822 822
823 dma_clk = clk_get(NULL, "dma"); 823 dma_clk = clk_get(NULL, "dma");
824 if (IS_ERR(dma_clk))
825 return PTR_ERR(dma_clk);
824 clk_enable(dma_clk); 826 clk_enable(dma_clk);
825 827
826 /* reset DMA module */ 828 /* reset DMA module */
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index 7e1e9dc2c8fc..275c8589d797 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -26,20 +26,16 @@
26#include <linux/spi/ads7846.h> 26#include <linux/spi/ads7846.h>
27#include <linux/backlight.h> 27#include <linux/backlight.h>
28#include <video/platform_lcd.h> 28#include <video/platform_lcd.h>
29#include <linux/input/matrix_keypad.h>
30 29
31#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
32 31
33#include <mach/common.h> 32#include <mach/common.h>
34#include <mach/iomux-mx27.h> 33#include <mach/iomux-mx27.h>
35#include <mach/imxfb.h>
36#include <mach/hardware.h> 34#include <mach/hardware.h>
37#include <mach/mmc.h>
38#include <mach/spi.h> 35#include <mach/spi.h>
39#include <mach/audmux.h> 36#include <mach/audmux.h>
40 37
41#include "devices-imx27.h" 38#include "devices-imx27.h"
42#include "devices.h"
43 39
44static const int eukrea_mbimx27_pins[] __initconst = { 40static const int eukrea_mbimx27_pins[] __initconst = {
45 /* UART2 */ 41 /* UART2 */
@@ -111,7 +107,8 @@ static const uint32_t eukrea_mbimx27_keymap[] = {
111 KEY(1, 1, KEY_LEFT), 107 KEY(1, 1, KEY_LEFT),
112}; 108};
113 109
114static struct matrix_keymap_data eukrea_mbimx27_keymap_data = { 110static const struct matrix_keymap_data
111eukrea_mbimx27_keymap_data __initconst = {
115 .keymap = eukrea_mbimx27_keymap, 112 .keymap = eukrea_mbimx27_keymap,
116 .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap), 113 .keymap_size = ARRAY_SIZE(eukrea_mbimx27_keymap),
117}; 114};
@@ -196,7 +193,7 @@ static struct imx_fb_videomode eukrea_mbimx27_modes[] = {
196 }, 193 },
197}; 194};
198 195
199static struct imx_fb_platform_data eukrea_mbimx27_fb_data = { 196static const struct imx_fb_platform_data eukrea_mbimx27_fb_data __initconst = {
200 .mode = eukrea_mbimx27_modes, 197 .mode = eukrea_mbimx27_modes,
201 .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes), 198 .num_modes = ARRAY_SIZE(eukrea_mbimx27_modes),
202 199
@@ -300,7 +297,7 @@ static struct platform_device *platform_devices[] __initdata = {
300 &leds_gpio, 297 &leds_gpio,
301}; 298};
302 299
303static struct imxmmc_platform_data sdhc_pdata = { 300static const struct imxmmc_platform_data sdhc_pdata __initconst = {
304 .dat3_card_detect = 1, 301 .dat3_card_detect = 1,
305}; 302};
306 303
@@ -345,8 +342,8 @@ void __init eukrea_mbimx27_baseboard_init(void)
345 imx27_add_imx_uart3(&uart_pdata); 342 imx27_add_imx_uart3(&uart_pdata);
346#endif 343#endif
347 344
348 mxc_register_device(&mxc_fb_device, &eukrea_mbimx27_fb_data); 345 imx27_add_imx_fb(&eukrea_mbimx27_fb_data);
349 mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata); 346 imx27_add_mxc_mmc(0, &sdhc_pdata);
350 347
351 i2c_register_board_info(0, eukrea_mbimx27_i2c_devices, 348 i2c_register_board_info(0, eukrea_mbimx27_i2c_devices,
352 ARRAY_SIZE(eukrea_mbimx27_i2c_devices)); 349 ARRAY_SIZE(eukrea_mbimx27_i2c_devices));
@@ -380,7 +377,7 @@ void __init eukrea_mbimx27_baseboard_init(void)
380 gpio_request(GPIO_PORTA | 25, "lcd_enable"); 377 gpio_request(GPIO_PORTA | 25, "lcd_enable");
381 platform_device_register(&eukrea_mbimx27_lcd_powerdev); 378 platform_device_register(&eukrea_mbimx27_lcd_powerdev);
382 379
383 mxc_register_device(&imx_kpp_device, &eukrea_mbimx27_keymap_data); 380 imx27_add_imx_keypad(&eukrea_mbimx27_keymap_data);
384 381
385 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 382 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
386} 383}
diff --git a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index e765ac5d9a08..cb705c28de02 100644
--- a/arch/arm/mach-mx25/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -33,13 +33,11 @@
33#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
34#include <mach/mx25.h> 34#include <mach/mx25.h>
35#include <mach/imx-uart.h> 35#include <mach/imx-uart.h>
36#include <mach/imxfb.h>
37#include <mach/audmux.h> 36#include <mach/audmux.h>
38 37
39#include "devices-imx25.h" 38#include "devices-imx25.h"
40#include "devices.h"
41 39
42static struct pad_desc eukrea_mbimxsd_pads[] = { 40static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
43 /* LCD */ 41 /* LCD */
44 MX25_PAD_LD0__LD0, 42 MX25_PAD_LD0__LD0,
45 MX25_PAD_LD1__LD1, 43 MX25_PAD_LD1__LD1,
@@ -151,7 +149,7 @@ static struct imx_fb_videomode eukrea_mximxsd_modes[] = {
151 }, 149 },
152}; 150};
153 151
154static struct imx_fb_platform_data eukrea_mximxsd_fb_pdata = { 152static const struct imx_fb_platform_data eukrea_mximxsd_fb_pdata __initconst = {
155 .mode = eukrea_mximxsd_modes, 153 .mode = eukrea_mximxsd_modes,
156 .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes), 154 .num_modes = ARRAY_SIZE(eukrea_mximxsd_modes),
157 .pwmr = 0x00A903FF, 155 .pwmr = 0x00A903FF,
@@ -273,11 +271,11 @@ void __init eukrea_mbimxsd25_baseboard_init(void)
273#endif 271#endif
274 272
275 imx25_add_imx_uart1(&uart_pdata); 273 imx25_add_imx_uart1(&uart_pdata);
276 mxc_register_device(&mx25_fb_device, &eukrea_mximxsd_fb_pdata); 274 imx25_add_imx_fb(&eukrea_mximxsd_fb_pdata);
277 imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); 275 imx25_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
278 276
279 imx25_add_flexcan1(NULL); 277 imx25_add_flexcan1(NULL);
280 imx25_add_esdhc(0, NULL); 278 imx25_add_sdhci_esdhc_imx(0, NULL);
281 279
282 gpio_request(GPIO_LED1, "LED1"); 280 gpio_request(GPIO_LED1, "LED1");
283 gpio_direction_output(GPIO_LED1, 1); 281 gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 745ee60fb068..6cf04da2456a 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -28,7 +28,6 @@
28#include <linux/serial_8250.h> 28#include <linux/serial_8250.h>
29#include <linux/usb/otg.h> 29#include <linux/usb/otg.h>
30#include <linux/usb/ulpi.h> 30#include <linux/usb/ulpi.h>
31#include <linux/fsl_devices.h>
32 31
33#include <asm/mach-types.h> 32#include <asm/mach-types.h>
34#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
@@ -40,11 +39,9 @@
40#include <mach/hardware.h> 39#include <mach/hardware.h>
41#include <mach/iomux-mx27.h> 40#include <mach/iomux-mx27.h>
42#include <mach/mxc_nand.h> 41#include <mach/mxc_nand.h>
43#include <mach/mxc_ehci.h>
44#include <mach/ulpi.h> 42#include <mach/ulpi.h>
45 43
46#include "devices-imx27.h" 44#include "devices-imx27.h"
47#include "devices.h"
48 45
49static const int eukrea_cpuimx27_pins[] __initconst = { 46static const int eukrea_cpuimx27_pins[] __initconst = {
50 /* UART1 */ 47 /* UART1 */
@@ -157,8 +154,6 @@ cpuimx27_nand_board_info __initconst = {
157 154
158static struct platform_device *platform_devices[] __initdata = { 155static struct platform_device *platform_devices[] __initdata = {
159 &eukrea_cpuimx27_nor_mtd_device, 156 &eukrea_cpuimx27_nor_mtd_device,
160 &mxc_wdt,
161 &mxc_w1_master_device,
162}; 157};
163 158
164static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = { 159static const struct imxi2c_platform_data cpuimx27_i2c1_data __initconst = {
@@ -215,18 +210,18 @@ static struct platform_device serial_device = {
215#endif 210#endif
216 211
217#if defined(CONFIG_USB_ULPI) 212#if defined(CONFIG_USB_ULPI)
218static struct mxc_usbh_platform_data otg_pdata = { 213static struct mxc_usbh_platform_data otg_pdata __initdata = {
219 .portsc = MXC_EHCI_MODE_ULPI, 214 .portsc = MXC_EHCI_MODE_ULPI,
220 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 215 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
221}; 216};
222 217
223static struct mxc_usbh_platform_data usbh2_pdata = { 218static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
224 .portsc = MXC_EHCI_MODE_ULPI, 219 .portsc = MXC_EHCI_MODE_ULPI,
225 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 220 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
226}; 221};
227#endif 222#endif
228 223
229static struct fsl_usb2_platform_data otg_device_pdata = { 224static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
230 .operating_mode = FSL_USB2_DR_DEVICE, 225 .operating_mode = FSL_USB2_DR_DEVICE,
231 .phy_mode = FSL_USB2_PHY_ULPI, 226 .phy_mode = FSL_USB2_PHY_ULPI,
232}; 227};
@@ -262,10 +257,12 @@ static void __init eukrea_cpuimx27_init(void)
262 257
263 imx27_add_fec(NULL); 258 imx27_add_fec(NULL);
264 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 259 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
260 imx27_add_imx2_wdt(NULL);
261 imx27_add_mxc_w1(NULL);
265 262
266#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2) 263#if defined(CONFIG_MACH_EUKREA_CPUIMX27_USESDHC2)
267 /* SDHC2 can be used for Wifi */ 264 /* SDHC2 can be used for Wifi */
268 mxc_register_device(&mxc_sdhc_device1, NULL); 265 imx27_add_mxc_mmc(1, NULL);
269#endif 266#endif
270#if defined(MACH_EUKREA_CPUIMX27_USEUART4) 267#if defined(MACH_EUKREA_CPUIMX27_USEUART4)
271 /* in which case UART4 is also used for Bluetooth */ 268 /* in which case UART4 is also used for Bluetooth */
@@ -281,16 +278,16 @@ static void __init eukrea_cpuimx27_init(void)
281 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 278 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
282 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 279 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
283 280
284 mxc_register_device(&mxc_otg_host, &otg_pdata); 281 imx27_add_mxc_ehci_otg(&otg_pdata);
285 } 282 }
286 283
287 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 284 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
288 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 285 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
289 286
290 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 287 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
291#endif 288#endif
292 if (!otg_mode_host) 289 if (!otg_mode_host)
293 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 290 imx27_add_fsl_usb2_udc(&otg_device_pdata);
294 291
295#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD 292#ifdef CONFIG_MACH_EUKREA_MBIMX27_BASEBOARD
296 eukrea_mbimx27_baseboard_init(); 293 eukrea_mbimx27_baseboard_init();
diff --git a/arch/arm/mach-mx25/mach-cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index f6f9ad60c25e..eb395aba9237 100644
--- a/arch/arm/mach-mx25/mach-cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -26,7 +26,6 @@
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/usb/otg.h> 27#include <linux/usb/otg.h>
28#include <linux/usb/ulpi.h> 28#include <linux/usb/ulpi.h>
29#include <linux/fsl_devices.h>
30 29
31#include <mach/eukrea-baseboards.h> 30#include <mach/eukrea-baseboards.h>
32#include <mach/hardware.h> 31#include <mach/hardware.h>
@@ -39,17 +38,15 @@
39#include <mach/mx25.h> 38#include <mach/mx25.h>
40#include <mach/mxc_nand.h> 39#include <mach/mxc_nand.h>
41#include <mach/imxfb.h> 40#include <mach/imxfb.h>
42#include <mach/mxc_ehci.h>
43#include <mach/iomux-mx25.h> 41#include <mach/iomux-mx25.h>
44 42
45#include "devices-imx25.h" 43#include "devices-imx25.h"
46#include "devices.h"
47 44
48static const struct imxuart_platform_data uart_pdata __initconst = { 45static const struct imxuart_platform_data uart_pdata __initconst = {
49 .flags = IMXUART_HAVE_RTSCTS, 46 .flags = IMXUART_HAVE_RTSCTS,
50}; 47};
51 48
52static struct pad_desc eukrea_cpuimx25_pads[] = { 49static iomux_v3_cfg_t eukrea_cpuimx25_pads[] = {
53 /* FEC - RMII */ 50 /* FEC - RMII */
54 MX25_PAD_FEC_MDC__FEC_MDC, 51 MX25_PAD_FEC_MDC__FEC_MDC,
55 MX25_PAD_FEC_MDIO__FEC_MDIO, 52 MX25_PAD_FEC_MDIO__FEC_MDIO,
@@ -87,18 +84,18 @@ static struct i2c_board_info eukrea_cpuimx25_i2c_devices[] = {
87 }, 84 },
88}; 85};
89 86
90static struct mxc_usbh_platform_data otg_pdata = { 87static const struct mxc_usbh_platform_data otg_pdata __initconst = {
91 .portsc = MXC_EHCI_MODE_UTMI, 88 .portsc = MXC_EHCI_MODE_UTMI,
92 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 89 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
93}; 90};
94 91
95static struct mxc_usbh_platform_data usbh2_pdata = { 92static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
96 .portsc = MXC_EHCI_MODE_SERIAL, 93 .portsc = MXC_EHCI_MODE_SERIAL,
97 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | 94 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
98 MXC_EHCI_IPPUE_DOWN, 95 MXC_EHCI_IPPUE_DOWN,
99}; 96};
100 97
101static struct fsl_usb2_platform_data otg_device_pdata = { 98static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
102 .operating_mode = FSL_USB2_DR_DEVICE, 99 .operating_mode = FSL_USB2_DR_DEVICE,
103 .phy_mode = FSL_USB2_PHY_UTMI, 100 .phy_mode = FSL_USB2_PHY_UTMI,
104}; 101};
@@ -126,7 +123,7 @@ static void __init eukrea_cpuimx25_init(void)
126 123
127 imx25_add_imx_uart0(&uart_pdata); 124 imx25_add_imx_uart0(&uart_pdata);
128 imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info); 125 imx25_add_mxc_nand(&eukrea_cpuimx25_nand_board_info);
129 mxc_register_device(&mx25_rtc_device, NULL); 126 imx25_add_imxdi_rtc(NULL);
130 imx25_add_fec(&mx25_fec_pdata); 127 imx25_add_fec(&mx25_fec_pdata);
131 128
132 i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices, 129 i2c_register_board_info(0, eukrea_cpuimx25_i2c_devices,
@@ -134,11 +131,11 @@ static void __init eukrea_cpuimx25_init(void)
134 imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data); 131 imx25_add_imx_i2c0(&eukrea_cpuimx25_i2c0_data);
135 132
136 if (otg_mode_host) 133 if (otg_mode_host)
137 mxc_register_device(&mxc_otg, &otg_pdata); 134 imx25_add_mxc_ehci_otg(&otg_pdata);
138 else 135 else
139 mxc_register_device(&otg_udc_device, &otg_device_pdata); 136 imx25_add_fsl_usb2_udc(&otg_device_pdata);
140 137
141 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 138 imx25_add_mxc_ehci_hs(&usbh2_pdata);
142 139
143#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD 140#ifdef CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD
144 eukrea_mbimxsd25_baseboard_init(); 141 eukrea_mbimxsd25_baseboard_init();
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index 59716fab586d..40a3666ea632 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -34,12 +34,9 @@
34#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
35#include <asm/mach/time.h> 35#include <asm/mach/time.h>
36#include <mach/common.h> 36#include <mach/common.h>
37#include <mach/mmc.h>
38#include <mach/iomux.h> 37#include <mach/iomux.h>
39#include <mach/mxc_ehci.h>
40 38
41#include "devices-imx27.h" 39#include "devices-imx27.h"
42#include "devices.h"
43 40
44#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17) 41#define OTG_PHY_CS_GPIO (GPIO_PORTF + 17)
45#define SDHC1_IRQ IRQ_GPIOB(25) 42#define SDHC1_IRQ IRQ_GPIOB(25)
@@ -156,7 +153,7 @@ static void visstrim_m10_sdhc1_exit(struct device *dev, void *data)
156 free_irq(SDHC1_IRQ, data); 153 free_irq(SDHC1_IRQ, data);
157} 154}
158 155
159static struct imxmmc_platform_data visstrim_m10_sdhc_pdata = { 156static const struct imxmmc_platform_data visstrim_m10_sdhc_pdata __initconst = {
160 .init = visstrim_m10_sdhc1_init, 157 .init = visstrim_m10_sdhc1_init,
161 .exit = visstrim_m10_sdhc1_exit, 158 .exit = visstrim_m10_sdhc1_exit,
162}; 159};
@@ -216,7 +213,8 @@ static int otg_phy_init(struct platform_device *pdev)
216 return 0; 213 return 0;
217} 214}
218 215
219static struct mxc_usbh_platform_data visstrim_m10_usbotg_pdata = { 216static const struct mxc_usbh_platform_data
217visstrim_m10_usbotg_pdata __initconst = {
220 .init = otg_phy_init, 218 .init = otg_phy_init,
221 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 219 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
222 .flags = MXC_EHCI_POWER_PINS_ENABLED, 220 .flags = MXC_EHCI_POWER_PINS_ENABLED,
@@ -237,8 +235,8 @@ static void __init visstrim_m10_board_init(void)
237 ARRAY_SIZE(visstrim_m10_i2c_devices)); 235 ARRAY_SIZE(visstrim_m10_i2c_devices));
238 imx27_add_imx_i2c(0, &visstrim_m10_i2c_data); 236 imx27_add_imx_i2c(0, &visstrim_m10_i2c_data);
239 imx27_add_imx_i2c(1, &visstrim_m10_i2c_data); 237 imx27_add_imx_i2c(1, &visstrim_m10_i2c_data);
240 mxc_register_device(&mxc_sdhc_device0, &visstrim_m10_sdhc_pdata); 238 imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
241 mxc_register_device(&mxc_otg_host, &visstrim_m10_usbotg_pdata); 239 imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
242 imx27_add_fec(NULL); 240 imx27_add_fec(NULL);
243 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 241 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
244} 242}
diff --git a/arch/arm/mach-imx/mach-imx27lite.c b/arch/arm/mach-imx/mach-imx27lite.c
index bbdbc75127d3..3a1202e47212 100644
--- a/arch/arm/mach-imx/mach-imx27lite.c
+++ b/arch/arm/mach-imx/mach-imx27lite.c
@@ -25,7 +25,6 @@
25#include <mach/iomux-mx27.h> 25#include <mach/iomux-mx27.h>
26 26
27#include "devices-imx27.h" 27#include "devices-imx27.h"
28#include "devices.h"
29 28
30static const int mx27lite_pins[] __initconst = { 29static const int mx27lite_pins[] __initconst = {
31 /* UART1 */ 30 /* UART1 */
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 6187ce9ba7d5..1f446e5eb636 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -30,7 +30,6 @@
30#include <mach/irqs.h> 30#include <mach/irqs.h>
31 31
32#include "devices-imx1.h" 32#include "devices-imx1.h"
33#include "devices.h"
34 33
35static const int mx1ads_pins[] __initconst = { 34static const int mx1ads_pins[] __initconst = {
36 /* UART1 */ 35 /* UART1 */
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index e1282e9f50ff..0a372577c2ac 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -24,13 +24,10 @@
24#include <asm/mach/arch.h> 24#include <asm/mach/arch.h>
25#include <asm/mach/time.h> 25#include <asm/mach/time.h>
26#include <asm/mach/map.h> 26#include <asm/mach/map.h>
27#include <mach/imxfb.h>
28#include <mach/iomux-mx21.h> 27#include <mach/iomux-mx21.h>
29#include <mach/mxc_nand.h> 28#include <mach/mxc_nand.h>
30#include <mach/mmc.h>
31 29
32#include "devices-imx21.h" 30#include "devices-imx21.h"
33#include "devices.h"
34 31
35/* 32/*
36 * Memory-mapped I/O on MX21ADS base board 33 * Memory-mapped I/O on MX21ADS base board
@@ -213,7 +210,7 @@ static struct imx_fb_videomode mx21ads_modes[] = {
213 }, 210 },
214}; 211};
215 212
216static struct imx_fb_platform_data mx21ads_fb_data = { 213static const struct imx_fb_platform_data mx21ads_fb_data __initconst = {
217 .mode = mx21ads_modes, 214 .mode = mx21ads_modes,
218 .num_modes = ARRAY_SIZE(mx21ads_modes), 215 .num_modes = ARRAY_SIZE(mx21ads_modes),
219 216
@@ -233,15 +230,8 @@ static int mx21ads_sdhc_get_ro(struct device *dev)
233static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq, 230static int mx21ads_sdhc_init(struct device *dev, irq_handler_t detect_irq,
234 void *data) 231 void *data)
235{ 232{
236 int ret; 233 return request_irq(IRQ_GPIOD(25), detect_irq,
237
238 ret = request_irq(IRQ_GPIOD(25), detect_irq,
239 IRQF_TRIGGER_FALLING, "mmc-detect", data); 234 IRQF_TRIGGER_FALLING, "mmc-detect", data);
240 if (ret)
241 goto out;
242 return 0;
243out:
244 return ret;
245} 235}
246 236
247static void mx21ads_sdhc_exit(struct device *dev, void *data) 237static void mx21ads_sdhc_exit(struct device *dev, void *data)
@@ -249,7 +239,7 @@ static void mx21ads_sdhc_exit(struct device *dev, void *data)
249 free_irq(IRQ_GPIOD(25), data); 239 free_irq(IRQ_GPIOD(25), data);
250} 240}
251 241
252static struct imxmmc_platform_data mx21ads_sdhc_pdata = { 242static const struct imxmmc_platform_data mx21ads_sdhc_pdata __initconst = {
253 .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */ 243 .ocr_avail = MMC_VDD_29_30 | MMC_VDD_30_31, /* 3.0V */
254 .get_ro = mx21ads_sdhc_get_ro, 244 .get_ro = mx21ads_sdhc_get_ro,
255 .init = mx21ads_sdhc_init, 245 .init = mx21ads_sdhc_init,
@@ -296,8 +286,8 @@ static void __init mx21ads_board_init(void)
296 imx21_add_imx_uart0(&uart_pdata_rts); 286 imx21_add_imx_uart0(&uart_pdata_rts);
297 imx21_add_imx_uart2(&uart_pdata_norts); 287 imx21_add_imx_uart2(&uart_pdata_norts);
298 imx21_add_imx_uart3(&uart_pdata_rts); 288 imx21_add_imx_uart3(&uart_pdata_rts);
299 mxc_register_device(&mxc_fb_device, &mx21ads_fb_data); 289 imx21_add_imx_fb(&mx21ads_fb_data);
300 mxc_register_device(&mxc_sdhc_device0, &mx21ads_sdhc_pdata); 290 imx21_add_mxc_mmc(0, &mx21ads_sdhc_pdata);
301 imx21_add_mxc_nand(&mx21ads_nand_board_info); 291 imx21_add_mxc_nand(&mx21ads_nand_board_info);
302 292
303 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 293 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
diff --git a/arch/arm/mach-mx25/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index f8be1eb0c062..aa76cfd9f348 100644
--- a/arch/arm/mach-mx25/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -30,6 +30,7 @@
30#include <linux/gpio.h> 30#include <linux/gpio.h>
31#include <linux/platform_device.h> 31#include <linux/platform_device.h>
32#include <linux/input/matrix_keypad.h> 32#include <linux/input/matrix_keypad.h>
33#include <linux/usb/otg.h>
33 34
34#include <mach/hardware.h> 35#include <mach/hardware.h>
35#include <asm/mach-types.h> 36#include <asm/mach-types.h>
@@ -39,17 +40,15 @@
39#include <asm/mach/map.h> 40#include <asm/mach/map.h>
40#include <mach/common.h> 41#include <mach/common.h>
41#include <mach/mx25.h> 42#include <mach/mx25.h>
42#include <mach/imxfb.h>
43#include <mach/iomux-mx25.h> 43#include <mach/iomux-mx25.h>
44 44
45#include "devices-imx25.h" 45#include "devices-imx25.h"
46#include "devices.h"
47 46
48static const struct imxuart_platform_data uart_pdata __initconst = { 47static const struct imxuart_platform_data uart_pdata __initconst = {
49 .flags = IMXUART_HAVE_RTSCTS, 48 .flags = IMXUART_HAVE_RTSCTS,
50}; 49};
51 50
52static struct pad_desc mx25pdk_pads[] = { 51static iomux_v3_cfg_t mx25pdk_pads[] = {
53 MX25_PAD_FEC_MDC__FEC_MDC, 52 MX25_PAD_FEC_MDC__FEC_MDC,
54 MX25_PAD_FEC_MDIO__FEC_MDIO, 53 MX25_PAD_FEC_MDIO__FEC_MDIO,
55 MX25_PAD_FEC_TDATA0__FEC_TDATA0, 54 MX25_PAD_FEC_TDATA0__FEC_TDATA0,
@@ -107,7 +106,7 @@ static struct pad_desc mx25pdk_pads[] = {
107}; 106};
108 107
109static const struct fec_platform_data mx25_fec_pdata __initconst = { 108static const struct fec_platform_data mx25_fec_pdata __initconst = {
110 .phy = PHY_INTERFACE_MODE_RMII, 109 .phy = PHY_INTERFACE_MODE_RMII,
111}; 110};
112 111
113#define FEC_ENABLE_GPIO 35 112#define FEC_ENABLE_GPIO 35
@@ -154,7 +153,7 @@ static struct imx_fb_videomode mx25pdk_modes[] = {
154 }, 153 },
155}; 154};
156 155
157static struct imx_fb_platform_data mx25pdk_fb_pdata = { 156static const struct imx_fb_platform_data mx25pdk_fb_pdata __initconst = {
158 .mode = mx25pdk_modes, 157 .mode = mx25pdk_modes,
159 .num_modes = ARRAY_SIZE(mx25pdk_modes), 158 .num_modes = ARRAY_SIZE(mx25pdk_modes),
160 .pwmr = 0x00A903FF, 159 .pwmr = 0x00A903FF,
@@ -181,28 +180,39 @@ static const uint32_t mx25pdk_keymap[] = {
181 KEY(3, 3, KEY_POWER), 180 KEY(3, 3, KEY_POWER),
182}; 181};
183 182
184static struct matrix_keymap_data mx25pdk_keymap_data = { 183static const struct matrix_keymap_data mx25pdk_keymap_data __initdata = {
185 .keymap = mx25pdk_keymap, 184 .keymap = mx25pdk_keymap,
186 .keymap_size = ARRAY_SIZE(mx25pdk_keymap), 185 .keymap_size = ARRAY_SIZE(mx25pdk_keymap),
187}; 186};
188 187
188static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
189 .portsc = MXC_EHCI_MODE_SERIAL,
190 .flags = MXC_EHCI_INTERNAL_PHY,
191};
192
193static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
194 .operating_mode = FSL_USB2_DR_DEVICE,
195 .phy_mode = FSL_USB2_PHY_UTMI,
196};
197
189static void __init mx25pdk_init(void) 198static void __init mx25pdk_init(void)
190{ 199{
191 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads, 200 mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
192 ARRAY_SIZE(mx25pdk_pads)); 201 ARRAY_SIZE(mx25pdk_pads));
193 202
194 imx25_add_imx_uart0(&uart_pdata); 203 imx25_add_imx_uart0(&uart_pdata);
195 mxc_register_device(&mxc_usbh2, NULL); 204 imx25_add_fsl_usb2_udc(&otg_device_pdata);
205 imx25_add_mxc_ehci_hs(&usbh2_pdata);
196 imx25_add_mxc_nand(&mx25pdk_nand_board_info); 206 imx25_add_mxc_nand(&mx25pdk_nand_board_info);
197 mxc_register_device(&mx25_rtc_device, NULL); 207 imx25_add_imxdi_rtc(NULL);
198 mxc_register_device(&mx25_fb_device, &mx25pdk_fb_pdata); 208 imx25_add_imx_fb(&mx25pdk_fb_pdata);
199 mxc_register_device(&mxc_wdt, NULL); 209 imx25_add_imx2_wdt(NULL);
200 210
201 mx25pdk_fec_reset(); 211 mx25pdk_fec_reset();
202 imx25_add_fec(&mx25_fec_pdata); 212 imx25_add_fec(&mx25_fec_pdata);
203 mxc_register_device(&mx25_kpp_device, &mx25pdk_keymap_data); 213 imx25_add_imx_keypad(&mx25pdk_keymap_data);
204 214
205 imx25_add_esdhc(0, NULL); 215 imx25_add_sdhci_esdhc_imx(0, NULL);
206} 216}
207 217
208static void __init mx25pdk_timer_init(void) 218static void __init mx25pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx27_3ds.c b/arch/arm/mach-imx/mach-mx27_3ds.c
index 84a5ba03f1ba..6fd0f8f6deb6 100644
--- a/arch/arm/mach-imx/mach-mx27_3ds.c
+++ b/arch/arm/mach-imx/mach-mx27_3ds.c
@@ -22,20 +22,27 @@
22 22
23#include <linux/platform_device.h> 23#include <linux/platform_device.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/input/matrix_keypad.h>
26#include <linux/irq.h> 25#include <linux/irq.h>
26#include <linux/usb/otg.h>
27#include <linux/usb/ulpi.h>
28#include <linux/delay.h>
29#include <linux/mfd/mc13783.h>
30#include <linux/spi/spi.h>
31#include <linux/regulator/machine.h>
32
27#include <asm/mach-types.h> 33#include <asm/mach-types.h>
28#include <asm/mach/arch.h> 34#include <asm/mach/arch.h>
29#include <asm/mach/time.h> 35#include <asm/mach/time.h>
30#include <mach/hardware.h> 36#include <mach/hardware.h>
31#include <mach/common.h> 37#include <mach/common.h>
32#include <mach/iomux-mx27.h> 38#include <mach/iomux-mx27.h>
33#include <mach/mmc.h> 39#include <mach/ulpi.h>
34 40
35#include "devices-imx27.h" 41#include "devices-imx27.h"
36#include "devices.h"
37 42
38#define SD1_EN_GPIO (GPIO_PORTB + 25) 43#define SD1_EN_GPIO (GPIO_PORTB + 25)
44#define OTG_PHY_RESET_GPIO (GPIO_PORTB + 23)
45#define SPI2_SS0 (GPIO_PORTD + 21)
39 46
40static const int mx27pdk_pins[] __initconst = { 47static const int mx27pdk_pins[] __initconst = {
41 /* UART1 */ 48 /* UART1 */
@@ -70,6 +77,24 @@ static const int mx27pdk_pins[] __initconst = {
70 PE22_PF_SD1_CMD, 77 PE22_PF_SD1_CMD,
71 PE23_PF_SD1_CLK, 78 PE23_PF_SD1_CLK,
72 SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT, 79 SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
80 /* OTG */
81 OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT,
82 PC7_PF_USBOTG_DATA5,
83 PC8_PF_USBOTG_DATA6,
84 PC9_PF_USBOTG_DATA0,
85 PC10_PF_USBOTG_DATA2,
86 PC11_PF_USBOTG_DATA1,
87 PC12_PF_USBOTG_DATA4,
88 PC13_PF_USBOTG_DATA3,
89 PE0_PF_USBOTG_NXT,
90 PE1_PF_USBOTG_STP,
91 PE2_PF_USBOTG_DIR,
92 PE24_PF_USBOTG_CLK,
93 PE25_PF_USBOTG_DATA7,
94 /* CSPI2 */
95 PD22_PF_CSPI2_SCLK,
96 PD23_PF_CSPI2_MISO,
97 PD24_PF_CSPI2_MOSI,
73}; 98};
74 99
75static const struct imxuart_platform_data uart_pdata __initconst = { 100static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -92,7 +117,7 @@ static const uint32_t mx27_3ds_keymap[] = {
92 KEY(2, 3, KEY_F10), 117 KEY(2, 3, KEY_F10),
93}; 118};
94 119
95static struct matrix_keymap_data mx27_3ds_keymap_data = { 120static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = {
96 .keymap = mx27_3ds_keymap, 121 .keymap = mx27_3ds_keymap,
97 .keymap_size = ARRAY_SIZE(mx27_3ds_keymap), 122 .keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
98}; 123};
@@ -109,7 +134,7 @@ static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
109 free_irq(IRQ_GPIOB(26), data); 134 free_irq(IRQ_GPIOB(26), data);
110} 135}
111 136
112static struct imxmmc_platform_data sdhc1_pdata = { 137static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
113 .init = mx27_3ds_sdhc1_init, 138 .init = mx27_3ds_sdhc1_init,
114 .exit = mx27_3ds_sdhc1_exit, 139 .exit = mx27_3ds_sdhc1_exit,
115}; 140};
@@ -121,6 +146,111 @@ static void mx27_3ds_sdhc1_enable_level_translator(void)
121 gpio_direction_output(SD1_EN_GPIO, 1); 146 gpio_direction_output(SD1_EN_GPIO, 1);
122} 147}
123 148
149
150static int otg_phy_init(void)
151{
152 gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset");
153 gpio_direction_output(OTG_PHY_RESET_GPIO, 0);
154 mdelay(1);
155 gpio_set_value(OTG_PHY_RESET_GPIO, 1);
156 return 0;
157}
158
159#if defined(CONFIG_USB_ULPI)
160
161static struct mxc_usbh_platform_data otg_pdata __initdata = {
162 .portsc = MXC_EHCI_MODE_ULPI,
163 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
164};
165#endif
166
167static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
168 .operating_mode = FSL_USB2_DR_DEVICE,
169 .phy_mode = FSL_USB2_PHY_ULPI,
170};
171
172static int otg_mode_host;
173
174static int __init mx27_3ds_otg_mode(char *options)
175{
176 if (!strcmp(options, "host"))
177 otg_mode_host = 1;
178 else if (!strcmp(options, "device"))
179 otg_mode_host = 0;
180 else
181 pr_info("otg_mode neither \"host\" nor \"device\". "
182 "Defaulting to device\n");
183 return 0;
184}
185__setup("otg_mode=", mx27_3ds_otg_mode);
186
187/* Regulators */
188static struct regulator_consumer_supply vmmc1_consumers[] = {
189 REGULATOR_SUPPLY("lcd_2v8", NULL),
190};
191
192static struct regulator_init_data vmmc1_init = {
193 .constraints = {
194 .min_uV = 2800000,
195 .max_uV = 2800000,
196 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
197 },
198 .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
199 .consumer_supplies = vmmc1_consumers,
200};
201
202static struct regulator_consumer_supply vgen_consumers[] = {
203 REGULATOR_SUPPLY("vdd_lcdio", NULL),
204};
205
206static struct regulator_init_data vgen_init = {
207 .constraints = {
208 .min_uV = 1800000,
209 .max_uV = 1800000,
210 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
211 },
212 .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
213 .consumer_supplies = vgen_consumers,
214};
215
216static struct mc13783_regulator_init_data mx27_3ds_regulators[] = {
217 {
218 .id = MC13783_REGU_VMMC1,
219 .init_data = &vmmc1_init,
220 }, {
221 .id = MC13783_REGU_VGEN,
222 .init_data = &vgen_init,
223 },
224};
225
226/* MC13783 */
227static struct mc13783_platform_data mc13783_pdata __initdata = {
228 .regulators = mx27_3ds_regulators,
229 .num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
230 .flags = MC13783_USE_REGULATOR,
231};
232
233/* SPI */
234static int spi2_internal_chipselect[] = {SPI2_SS0};
235
236static const struct spi_imx_master spi2_pdata __initconst = {
237 .chipselect = spi2_internal_chipselect,
238 .num_chipselect = ARRAY_SIZE(spi2_internal_chipselect),
239};
240
241static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
242 {
243 .modalias = "mc13783",
244 .max_speed_hz = 1000000,
245 .bus_num = 1,
246 .chip_select = 0, /* SS0 */
247 .platform_data = &mc13783_pdata,
248 .irq = IRQ_GPIOC(14),
249 .mode = SPI_CS_HIGH,
250 },
251};
252
253
124static void __init mx27pdk_init(void) 254static void __init mx27pdk_init(void)
125{ 255{
126 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins), 256 mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
@@ -128,8 +258,24 @@ static void __init mx27pdk_init(void)
128 mx27_3ds_sdhc1_enable_level_translator(); 258 mx27_3ds_sdhc1_enable_level_translator();
129 imx27_add_imx_uart0(&uart_pdata); 259 imx27_add_imx_uart0(&uart_pdata);
130 imx27_add_fec(NULL); 260 imx27_add_fec(NULL);
131 mxc_register_device(&imx_kpp_device, &mx27_3ds_keymap_data); 261 imx27_add_imx_keypad(&mx27_3ds_keymap_data);
132 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); 262 imx27_add_mxc_mmc(0, &sdhc1_pdata);
263 imx27_add_imx2_wdt(NULL);
264 otg_phy_init();
265#if defined(CONFIG_USB_ULPI)
266 if (otg_mode_host) {
267 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
268 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
269
270 imx27_add_mxc_ehci_otg(&otg_pdata);
271 }
272#endif
273 if (!otg_mode_host)
274 imx27_add_fsl_usb2_udc(&otg_device_pdata);
275
276 imx27_add_spi_imx1(&spi2_pdata);
277 spi_register_board_info(mx27_3ds_spi_devs,
278 ARRAY_SIZE(mx27_3ds_spi_devs));
133} 279}
134 280
135static void __init mx27pdk_timer_init(void) 281static void __init mx27pdk_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index a1e4bc573afc..b832f960fec4 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -30,11 +30,8 @@
30#include <mach/gpio.h> 30#include <mach/gpio.h>
31#include <mach/iomux-mx27.h> 31#include <mach/iomux-mx27.h>
32#include <mach/mxc_nand.h> 32#include <mach/mxc_nand.h>
33#include <mach/imxfb.h>
34#include <mach/mmc.h>
35 33
36#include "devices-imx27.h" 34#include "devices-imx27.h"
37#include "devices.h"
38 35
39/* 36/*
40 * Base address of PBC controller, CS4 37 * Base address of PBC controller, CS4
@@ -228,7 +225,7 @@ static struct imx_fb_videomode mx27ads_modes[] = {
228 }, 225 },
229}; 226};
230 227
231static struct imx_fb_platform_data mx27ads_fb_data = { 228static const struct imx_fb_platform_data mx27ads_fb_data __initconst = {
232 .mode = mx27ads_modes, 229 .mode = mx27ads_modes,
233 .num_modes = ARRAY_SIZE(mx27ads_modes), 230 .num_modes = ARRAY_SIZE(mx27ads_modes),
234 231
@@ -272,19 +269,18 @@ static void mx27ads_sdhc2_exit(struct device *dev, void *data)
272 free_irq(IRQ_GPIOB(7), data); 269 free_irq(IRQ_GPIOB(7), data);
273} 270}
274 271
275static struct imxmmc_platform_data sdhc1_pdata = { 272static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
276 .init = mx27ads_sdhc1_init, 273 .init = mx27ads_sdhc1_init,
277 .exit = mx27ads_sdhc1_exit, 274 .exit = mx27ads_sdhc1_exit,
278}; 275};
279 276
280static struct imxmmc_platform_data sdhc2_pdata = { 277static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
281 .init = mx27ads_sdhc2_init, 278 .init = mx27ads_sdhc2_init,
282 .exit = mx27ads_sdhc2_exit, 279 .exit = mx27ads_sdhc2_exit,
283}; 280};
284 281
285static struct platform_device *platform_devices[] __initdata = { 282static struct platform_device *platform_devices[] __initdata = {
286 &mx27ads_nor_mtd_device, 283 &mx27ads_nor_mtd_device,
287 &mxc_w1_master_device,
288}; 284};
289 285
290static const struct imxuart_platform_data uart_pdata __initconst = { 286static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -308,12 +304,13 @@ static void __init mx27ads_board_init(void)
308 i2c_register_board_info(1, mx27ads_i2c_devices, 304 i2c_register_board_info(1, mx27ads_i2c_devices,
309 ARRAY_SIZE(mx27ads_i2c_devices)); 305 ARRAY_SIZE(mx27ads_i2c_devices));
310 imx27_add_imx_i2c(1, &mx27ads_i2c1_data); 306 imx27_add_imx_i2c(1, &mx27ads_i2c1_data);
311 mxc_register_device(&mxc_fb_device, &mx27ads_fb_data); 307 imx27_add_imx_fb(&mx27ads_fb_data);
312 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); 308 imx27_add_mxc_mmc(0, &sdhc1_pdata);
313 mxc_register_device(&mxc_sdhc_device1, &sdhc2_pdata); 309 imx27_add_mxc_mmc(1, &sdhc2_pdata);
314 310
315 imx27_add_fec(NULL); 311 imx27_add_fec(NULL);
316 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 312 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
313 imx27_add_mxc_w1(NULL);
317} 314}
318 315
319static void __init mx27ads_timer_init(void) 316static void __init mx27ads_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 38d3a4ae17c7..4ce71b0401db 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -31,11 +31,8 @@
31#include <mach/iomux-mx27.h> 31#include <mach/iomux-mx27.h>
32#include <mach/mxc_nand.h> 32#include <mach/mxc_nand.h>
33#include <linux/i2c/pca953x.h> 33#include <linux/i2c/pca953x.h>
34#include <mach/imxfb.h>
35#include <mach/mmc.h>
36 34
37#include "devices-imx27.h" 35#include "devices-imx27.h"
38#include "devices.h"
39 36
40static const int mxt_td60_pins[] __initconst = { 37static const int mxt_td60_pins[] __initconst = {
41 /* UART0 */ 38 /* UART0 */
@@ -196,7 +193,7 @@ static struct imx_fb_videomode mxt_td60_modes[] = {
196 }, 193 },
197}; 194};
198 195
199static struct imx_fb_platform_data mxt_td60_fb_data = { 196static const struct imx_fb_platform_data mxt_td60_fb_data __initconst = {
200 .mode = mxt_td60_modes, 197 .mode = mxt_td60_modes,
201 .num_modes = ARRAY_SIZE(mxt_td60_modes), 198 .num_modes = ARRAY_SIZE(mxt_td60_modes),
202 199
@@ -226,7 +223,7 @@ static void mxt_td60_sdhc1_exit(struct device *dev, void *data)
226 free_irq(IRQ_GPIOF(8), data); 223 free_irq(IRQ_GPIOF(8), data);
227} 224}
228 225
229static struct imxmmc_platform_data sdhc1_pdata = { 226static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
230 .init = mxt_td60_sdhc1_init, 227 .init = mxt_td60_sdhc1_init,
231 .exit = mxt_td60_sdhc1_exit, 228 .exit = mxt_td60_sdhc1_exit,
232}; 229};
@@ -253,8 +250,8 @@ static void __init mxt_td60_board_init(void)
253 250
254 imx27_add_imx_i2c(0, &mxt_td60_i2c0_data); 251 imx27_add_imx_i2c(0, &mxt_td60_i2c0_data);
255 imx27_add_imx_i2c(1, &mxt_td60_i2c1_data); 252 imx27_add_imx_i2c(1, &mxt_td60_i2c1_data);
256 mxc_register_device(&mxc_fb_device, &mxt_td60_fb_data); 253 imx27_add_imx_fb(&mxt_td60_fb_data);
257 mxc_register_device(&mxc_sdhc_device0, &sdhc1_pdata); 254 imx27_add_mxc_mmc(0, &sdhc1_pdata);
258 imx27_add_fec(NULL); 255 imx27_add_fec(NULL);
259} 256}
260 257
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 8c720d44602a..cccc0a0a9c72 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -29,7 +29,6 @@
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/usb/otg.h> 30#include <linux/usb/otg.h>
31#include <linux/usb/ulpi.h> 31#include <linux/usb/ulpi.h>
32#include <linux/fsl_devices.h>
33 32
34#include <asm/mach/arch.h> 33#include <asm/mach/arch.h>
35#include <asm/mach-types.h> 34#include <asm/mach-types.h>
@@ -40,13 +39,9 @@
40#include <mach/audmux.h> 39#include <mach/audmux.h>
41#include <mach/mxc_nand.h> 40#include <mach/mxc_nand.h>
42#include <mach/irqs.h> 41#include <mach/irqs.h>
43#include <mach/mmc.h>
44#include <mach/mxc_ehci.h>
45#include <mach/ulpi.h> 42#include <mach/ulpi.h>
46#include <mach/imxfb.h>
47 43
48#include "devices-imx27.h" 44#include "devices-imx27.h"
49#include "devices.h"
50 45
51#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23) 46#define OTG_PHY_CS_GPIO (GPIO_PORTB + 23)
52#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24) 47#define USBH2_PHY_CS_GPIO (GPIO_PORTB + 24)
@@ -171,11 +166,6 @@ pca100_nand_board_info __initconst = {
171 .hw_ecc = 1, 166 .hw_ecc = 1,
172}; 167};
173 168
174static struct platform_device *platform_devices[] __initdata = {
175 &mxc_w1_master_device,
176 &mxc_wdt,
177};
178
179static const struct imxi2c_platform_data pca100_i2c1_data __initconst = { 169static const struct imxi2c_platform_data pca100_i2c1_data __initconst = {
180 .bitrate = 100000, 170 .bitrate = 100000,
181}; 171};
@@ -274,7 +264,7 @@ static void pca100_sdhc2_exit(struct device *dev, void *data)
274 free_irq(IRQ_GPIOC(29), data); 264 free_irq(IRQ_GPIOC(29), data);
275} 265}
276 266
277static struct imxmmc_platform_data sdhc_pdata = { 267static const struct imxmmc_platform_data sdhc_pdata __initconst = {
278 .init = pca100_sdhc2_init, 268 .init = pca100_sdhc2_init,
279 .exit = pca100_sdhc2_exit, 269 .exit = pca100_sdhc2_exit,
280}; 270};
@@ -286,7 +276,7 @@ static int otg_phy_init(struct platform_device *pdev)
286 return 0; 276 return 0;
287} 277}
288 278
289static struct mxc_usbh_platform_data otg_pdata = { 279static struct mxc_usbh_platform_data otg_pdata __initdata = {
290 .init = otg_phy_init, 280 .init = otg_phy_init,
291 .portsc = MXC_EHCI_MODE_ULPI, 281 .portsc = MXC_EHCI_MODE_ULPI,
292 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 282 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -298,14 +288,14 @@ static int usbh2_phy_init(struct platform_device *pdev)
298 return 0; 288 return 0;
299} 289}
300 290
301static struct mxc_usbh_platform_data usbh2_pdata = { 291static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
302 .init = usbh2_phy_init, 292 .init = usbh2_phy_init,
303 .portsc = MXC_EHCI_MODE_ULPI, 293 .portsc = MXC_EHCI_MODE_ULPI,
304 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 294 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
305}; 295};
306#endif 296#endif
307 297
308static struct fsl_usb2_platform_data otg_device_pdata = { 298static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
309 .operating_mode = FSL_USB2_DR_DEVICE, 299 .operating_mode = FSL_USB2_DR_DEVICE,
310 .phy_mode = FSL_USB2_PHY_ULPI, 300 .phy_mode = FSL_USB2_PHY_ULPI,
311}; 301};
@@ -355,7 +345,7 @@ static struct imx_fb_videomode pca100_fb_modes[] = {
355 }, 345 },
356}; 346};
357 347
358static struct imx_fb_platform_data pca100_fb_data = { 348static const struct imx_fb_platform_data pca100_fb_data __initconst = {
359 .mode = pca100_fb_modes, 349 .mode = pca100_fb_modes,
360 .num_modes = ARRAY_SIZE(pca100_fb_modes), 350 .num_modes = ARRAY_SIZE(pca100_fb_modes),
361 351
@@ -389,7 +379,7 @@ static void __init pca100_init(void)
389 379
390 imx27_add_imx_uart0(&uart_pdata); 380 imx27_add_imx_uart0(&uart_pdata);
391 381
392 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); 382 imx27_add_mxc_mmc(1, &sdhc_pdata);
393 383
394 imx27_add_mxc_nand(&pca100_nand_board_info); 384 imx27_add_mxc_nand(&pca100_nand_board_info);
395 385
@@ -417,23 +407,24 @@ static void __init pca100_init(void)
417 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 407 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
418 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 408 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
419 409
420 mxc_register_device(&mxc_otg_host, &otg_pdata); 410 imx27_add_mxc_ehci_otg(&otg_pdata);
421 } 411 }
422 412
423 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 413 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
424 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 414 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
425 415
426 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 416 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
427#endif 417#endif
428 if (!otg_mode_host) { 418 if (!otg_mode_host) {
429 gpio_set_value(OTG_PHY_CS_GPIO, 0); 419 gpio_set_value(OTG_PHY_CS_GPIO, 0);
430 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 420 imx27_add_fsl_usb2_udc(&otg_device_pdata);
431 } 421 }
432 422
433 mxc_register_device(&mxc_fb_device, &pca100_fb_data); 423 imx27_add_imx_fb(&pca100_fb_data);
434 424
435 imx27_add_fec(NULL); 425 imx27_add_fec(NULL);
436 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 426 imx27_add_imx2_wdt(NULL);
427 imx27_add_mxc_w1(NULL);
437} 428}
438 429
439static void __init pca100_timer_init(void) 430static void __init pca100_timer_init(void)
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 49a97ce07426..f667a262dfc1 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -37,11 +37,9 @@
37#include <mach/hardware.h> 37#include <mach/hardware.h>
38#include <mach/iomux-mx27.h> 38#include <mach/iomux-mx27.h>
39#include <mach/mxc_nand.h> 39#include <mach/mxc_nand.h>
40#include <mach/mxc_ehci.h>
41#include <mach/ulpi.h> 40#include <mach/ulpi.h>
42 41
43#include "devices-imx27.h" 42#include "devices-imx27.h"
44#include "devices.h"
45 43
46static const int pcm038_pins[] __initconst = { 44static const int pcm038_pins[] __initconst = {
47 /* UART1 */ 45 /* UART1 */
@@ -172,9 +170,7 @@ pcm038_nand_board_info __initconst = {
172 170
173static struct platform_device *platform_devices[] __initdata = { 171static struct platform_device *platform_devices[] __initdata = {
174 &pcm038_nor_mtd_device, 172 &pcm038_nor_mtd_device,
175 &mxc_w1_master_device,
176 &pcm038_sram_mtd_device, 173 &pcm038_sram_mtd_device,
177 &mxc_wdt,
178}; 174};
179 175
180/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and 176/* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
@@ -214,7 +210,7 @@ static const struct spi_imx_master pcm038_spi0_data __initconst = {
214 210
215static struct regulator_consumer_supply sdhc1_consumers[] = { 211static struct regulator_consumer_supply sdhc1_consumers[] = {
216 { 212 {
217 .dev = &mxc_sdhc_device1.dev, 213 .dev_name = "mxc-mmc.1",
218 .supply = "sdhc_vcc", 214 .supply = "sdhc_vcc",
219 }, 215 },
220}; 216};
@@ -285,7 +281,7 @@ static struct spi_board_info pcm038_spi_board_info[] __initdata = {
285 } 281 }
286}; 282};
287 283
288static struct mxc_usbh_platform_data usbh2_pdata = { 284static const struct mxc_usbh_platform_data usbh2_pdata __initconst = {
289 .portsc = MXC_EHCI_MODE_ULPI, 285 .portsc = MXC_EHCI_MODE_ULPI,
290 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, 286 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
291}; 287};
@@ -322,10 +318,12 @@ static void __init pcm038_init(void)
322 spi_register_board_info(pcm038_spi_board_info, 318 spi_register_board_info(pcm038_spi_board_info,
323 ARRAY_SIZE(pcm038_spi_board_info)); 319 ARRAY_SIZE(pcm038_spi_board_info));
324 320
325 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 321 imx27_add_mxc_ehci_hs(2, &usbh2_pdata);
326 322
327 imx27_add_fec(NULL); 323 imx27_add_fec(NULL);
328 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices)); 324 platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
325 imx27_add_imx2_wdt(NULL);
326 imx27_add_mxc_w1(NULL);
329 327
330#ifdef CONFIG_MACH_PCM970_BASEBOARD 328#ifdef CONFIG_MACH_PCM970_BASEBOARD
331 pcm970_baseboard_init(); 329 pcm970_baseboard_init();
diff --git a/arch/arm/mach-imx/mach-scb9328.c b/arch/arm/mach-imx/mach-scb9328.c
index 1fbdd3faa7ab..eae878f306c6 100644
--- a/arch/arm/mach-imx/mach-scb9328.c
+++ b/arch/arm/mach-imx/mach-scb9328.c
@@ -25,7 +25,6 @@
25#include <mach/iomux-mx1.h> 25#include <mach/iomux-mx1.h>
26 26
27#include "devices-imx1.h" 27#include "devices-imx1.h"
28#include "devices.h"
29 28
30/* 29/*
31 * This scb9328 has a 32MiB flash 30 * This scb9328 has a 32MiB flash
diff --git a/arch/arm/mach-imx/mm-imx1.c b/arch/arm/mach-imx/mm-imx1.c
index 9be92b96dc89..729ae0915af8 100644
--- a/arch/arm/mach-imx/mm-imx1.c
+++ b/arch/arm/mach-imx/mm-imx1.c
@@ -25,12 +25,7 @@
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26 26
27static struct map_desc imx_io_desc[] __initdata = { 27static struct map_desc imx_io_desc[] __initdata = {
28 { 28 imx_map_entry(MX1, IO, MT_DEVICE),
29 .virtual = MX1_IO_BASE_ADDR_VIRT,
30 .pfn = __phys_to_pfn(MX1_IO_BASE_ADDR),
31 .length = MX1_IO_SIZE,
32 .type = MT_DEVICE
33 }
34}; 29};
35 30
36void __init mx1_map_io(void) 31void __init mx1_map_io(void)
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c
index 12faeeaa0a97..e728af81d1b1 100644
--- a/arch/arm/mach-imx/mm-imx21.c
+++ b/arch/arm/mach-imx/mm-imx21.c
@@ -35,33 +35,18 @@ static struct map_desc imx21_io_desc[] __initdata = {
35 * - ROM Patch 35 * - ROM Patch
36 * - and some reserved space 36 * - and some reserved space
37 */ 37 */
38 { 38 imx_map_entry(MX21, AIPI, MT_DEVICE),
39 .virtual = MX21_AIPI_BASE_ADDR_VIRT,
40 .pfn = __phys_to_pfn(MX21_AIPI_BASE_ADDR),
41 .length = MX21_AIPI_SIZE,
42 .type = MT_DEVICE
43 },
44 /* 39 /*
45 * this fixed mapping covers: 40 * this fixed mapping covers:
46 * - CSI 41 * - CSI
47 * - ATA 42 * - ATA
48 */ 43 */
49 { 44 imx_map_entry(MX21, SAHB1, MT_DEVICE),
50 .virtual = MX21_SAHB1_BASE_ADDR_VIRT,
51 .pfn = __phys_to_pfn(MX21_SAHB1_BASE_ADDR),
52 .length = MX21_SAHB1_SIZE,
53 .type = MT_DEVICE
54 },
55 /* 45 /*
56 * this fixed mapping covers: 46 * this fixed mapping covers:
57 * - EMI 47 * - EMI
58 */ 48 */
59 { 49 imx_map_entry(MX21, X_MEMC, MT_DEVICE),
60 .virtual = MX21_X_MEMC_BASE_ADDR_VIRT,
61 .pfn = __phys_to_pfn(MX21_X_MEMC_BASE_ADDR),
62 .length = MX21_X_MEMC_SIZE,
63 .type = MT_DEVICE
64 },
65}; 50};
66 51
67/* 52/*
diff --git a/arch/arm/mach-mx25/mm.c b/arch/arm/mach-imx/mm-imx25.c
index bb677111fb0f..2edec6ce8fe7 100644
--- a/arch/arm/mach-mx25/mm.c
+++ b/arch/arm/mach-imx/mm-imx25.c
@@ -30,25 +30,12 @@
30 30
31/* 31/*
32 * This table defines static virtual address mappings for I/O regions. 32 * This table defines static virtual address mappings for I/O regions.
33 * These are the mappings common across all MX3 boards. 33 * These are the mappings common across all MX25 boards.
34 */ 34 */
35static struct map_desc mxc_io_desc[] __initdata = { 35static struct map_desc mx25_io_desc[] __initdata = {
36 { 36 imx_map_entry(MX25, AVIC, MT_DEVICE_NONSHARED),
37 .virtual = MX25_AVIC_BASE_ADDR_VIRT, 37 imx_map_entry(MX25, AIPS1, MT_DEVICE_NONSHARED),
38 .pfn = __phys_to_pfn(MX25_AVIC_BASE_ADDR), 38 imx_map_entry(MX25, AIPS2, MT_DEVICE_NONSHARED),
39 .length = MX25_AVIC_SIZE,
40 .type = MT_DEVICE_NONSHARED
41 }, {
42 .virtual = MX25_AIPS1_BASE_ADDR_VIRT,
43 .pfn = __phys_to_pfn(MX25_AIPS1_BASE_ADDR),
44 .length = MX25_AIPS1_SIZE,
45 .type = MT_DEVICE_NONSHARED
46 }, {
47 .virtual = MX25_AIPS2_BASE_ADDR_VIRT,
48 .pfn = __phys_to_pfn(MX25_AIPS2_BASE_ADDR),
49 .length = MX25_AIPS2_SIZE,
50 .type = MT_DEVICE_NONSHARED
51 },
52}; 39};
53 40
54/* 41/*
@@ -62,14 +49,14 @@ void __init mx25_map_io(void)
62 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR)); 49 mxc_iomux_v3_init(MX25_IO_ADDRESS(MX25_IOMUXC_BASE_ADDR));
63 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR)); 50 mxc_arch_reset_init(MX25_IO_ADDRESS(MX25_WDOG_BASE_ADDR));
64 51
65 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 52 iotable_init(mx25_io_desc, ARRAY_SIZE(mx25_io_desc));
66} 53}
67 54
68int imx25_register_gpios(void); 55int imx25_register_gpios(void);
69 56
70void __init mx25_init_irq(void) 57void __init mx25_init_irq(void)
71{ 58{
72 mxc_init_irq((void __iomem *)MX25_AVIC_BASE_ADDR_VIRT); 59 mxc_init_irq(MX25_IO_ADDRESS(MX25_AVIC_BASE_ADDR));
73 imx25_register_gpios(); 60 imx25_register_gpios();
74} 61}
75 62
diff --git a/arch/arm/mach-imx/mm-imx27.c b/arch/arm/mach-imx/mm-imx27.c
index a24622957ff2..374e48b7a412 100644
--- a/arch/arm/mach-imx/mm-imx27.c
+++ b/arch/arm/mach-imx/mm-imx27.c
@@ -35,33 +35,18 @@ static struct map_desc imx27_io_desc[] __initdata = {
35 * - ROM Patch 35 * - ROM Patch
36 * - and some reserved space 36 * - and some reserved space
37 */ 37 */
38 { 38 imx_map_entry(MX27, AIPI, MT_DEVICE),
39 .virtual = MX27_AIPI_BASE_ADDR_VIRT,
40 .pfn = __phys_to_pfn(MX27_AIPI_BASE_ADDR),
41 .length = MX27_AIPI_SIZE,
42 .type = MT_DEVICE
43 },
44 /* 39 /*
45 * this fixed mapping covers: 40 * this fixed mapping covers:
46 * - CSI 41 * - CSI
47 * - ATA 42 * - ATA
48 */ 43 */
49 { 44 imx_map_entry(MX27, SAHB1, MT_DEVICE),
50 .virtual = MX27_SAHB1_BASE_ADDR_VIRT,
51 .pfn = __phys_to_pfn(MX27_SAHB1_BASE_ADDR),
52 .length = MX27_SAHB1_SIZE,
53 .type = MT_DEVICE
54 },
55 /* 45 /*
56 * this fixed mapping covers: 46 * this fixed mapping covers:
57 * - EMI 47 * - EMI
58 */ 48 */
59 { 49 imx_map_entry(MX27, X_MEMC, MT_DEVICE),
60 .virtual = MX27_X_MEMC_BASE_ADDR_VIRT,
61 .pfn = __phys_to_pfn(MX27_X_MEMC_BASE_ADDR),
62 .length = MX27_X_MEMC_SIZE,
63 .type = MT_DEVICE
64 },
65}; 50};
66 51
67/* 52/*
diff --git a/arch/arm/mach-imx/pcm970-baseboard.c b/arch/arm/mach-imx/pcm970-baseboard.c
index 9110d9cca7a2..99afbc3f43a3 100644
--- a/arch/arm/mach-imx/pcm970-baseboard.c
+++ b/arch/arm/mach-imx/pcm970-baseboard.c
@@ -25,11 +25,9 @@
25 25
26#include <mach/common.h> 26#include <mach/common.h>
27#include <mach/iomux-mx27.h> 27#include <mach/iomux-mx27.h>
28#include <mach/imxfb.h>
29#include <mach/hardware.h> 28#include <mach/hardware.h>
30#include <mach/mmc.h>
31 29
32#include "devices.h" 30#include "devices-imx27.h"
33 31
34static const int pcm970_pins[] __initconst = { 32static const int pcm970_pins[] __initconst = {
35 /* SDHC */ 33 /* SDHC */
@@ -119,7 +117,7 @@ static void pcm970_sdhc2_exit(struct device *dev, void *data)
119 gpio_free(GPIO_PORTC + 28); 117 gpio_free(GPIO_PORTC + 28);
120} 118}
121 119
122static struct imxmmc_platform_data sdhc_pdata = { 120static const struct imxmmc_platform_data sdhc_pdata __initconst = {
123 .get_ro = pcm970_sdhc2_get_ro, 121 .get_ro = pcm970_sdhc2_get_ro,
124 .init = pcm970_sdhc2_init, 122 .init = pcm970_sdhc2_init,
125 .exit = pcm970_sdhc2_exit, 123 .exit = pcm970_sdhc2_exit,
@@ -179,7 +177,7 @@ static struct imx_fb_videomode pcm970_modes[] = {
179 }, 177 },
180}; 178};
181 179
182static struct imx_fb_platform_data pcm038_fb_data = { 180static const struct imx_fb_platform_data pcm038_fb_data __initconst = {
183 .mode = pcm970_modes, 181 .mode = pcm970_modes,
184 .num_modes = ARRAY_SIZE(pcm970_modes), 182 .num_modes = ARRAY_SIZE(pcm970_modes),
185 183
@@ -226,8 +224,8 @@ void __init pcm970_baseboard_init(void)
226 mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins), 224 mxc_gpio_setup_multiple_pins(pcm970_pins, ARRAY_SIZE(pcm970_pins),
227 "PCM970"); 225 "PCM970");
228 226
229 mxc_register_device(&mxc_fb_device, &pcm038_fb_data); 227 imx27_add_imx_fb(&pcm038_fb_data);
230 mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN); 228 mxc_gpio_mode(GPIO_PORTC | 28 | GPIO_GPIO | GPIO_IN);
231 mxc_register_device(&mxc_sdhc_device1, &sdhc_pdata); 229 imx27_add_mxc_mmc(1, &sdhc_pdata);
232 platform_device_register(&pcm970_sja1000); 230 platform_device_register(&pcm970_sja1000);
233} 231}
diff --git a/arch/arm/mach-imx/pm-imx27.c b/arch/arm/mach-imx/pm-imx27.c
index afc17ce0bb54..6bf81ceea137 100644
--- a/arch/arm/mach-imx/pm-imx27.c
+++ b/arch/arm/mach-imx/pm-imx27.c
@@ -39,6 +39,9 @@ static struct platform_suspend_ops mx27_suspend_ops = {
39 39
40static int __init mx27_pm_init(void) 40static int __init mx27_pm_init(void)
41{ 41{
42 if (!cpu_is_mx27())
43 return 0;
44
42 suspend_set_ops(&mx27_suspend_ops); 45 suspend_set_ops(&mx27_suspend_ops);
43 return 0; 46 return 0;
44} 47}
diff --git a/arch/arm/mach-mx25/Kconfig b/arch/arm/mach-mx25/Kconfig
deleted file mode 100644
index 38ca09a5df9d..000000000000
--- a/arch/arm/mach-mx25/Kconfig
+++ /dev/null
@@ -1,34 +0,0 @@
1if ARCH_MX25
2
3comment "MX25 platforms:"
4
5config MACH_MX25_3DS
6 bool "Support MX25PDK (3DS) Platform"
7 select IMX_HAVE_PLATFORM_IMX_UART
8 select IMX_HAVE_PLATFORM_MXC_NAND
9 select IMX_HAVE_PLATFORM_ESDHC
10
11config MACH_EUKREA_CPUIMX25
12 bool "Support Eukrea CPUIMX25 Platform"
13 select IMX_HAVE_PLATFORM_IMX_I2C
14 select IMX_HAVE_PLATFORM_IMX_UART
15 select IMX_HAVE_PLATFORM_MXC_NAND
16 select IMX_HAVE_PLATFORM_FLEXCAN
17 select IMX_HAVE_PLATFORM_ESDHC
18 select MXC_ULPI if USB_ULPI
19
20choice
21 prompt "Baseboard"
22 depends on MACH_EUKREA_CPUIMX25
23 default MACH_EUKREA_MBIMXSD25_BASEBOARD
24
25config MACH_EUKREA_MBIMXSD25_BASEBOARD
26 bool "Eukrea MBIMXSD development board"
27 select IMX_HAVE_PLATFORM_IMX_SSI
28 help
29 This adds board specific devices that can be found on Eukrea's
30 MBIMXSD evaluation board.
31
32endchoice
33
34endif
diff --git a/arch/arm/mach-mx25/Makefile b/arch/arm/mach-mx25/Makefile
deleted file mode 100644
index d9e46ce00a4e..000000000000
--- a/arch/arm/mach-mx25/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
1obj-y := mm.o devices.o
2obj-$(CONFIG_ARCH_MX25) += clock.o
3obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
4obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-cpuimx25.o
5obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd-baseboard.o
diff --git a/arch/arm/mach-mx25/Makefile.boot b/arch/arm/mach-mx25/Makefile.boot
deleted file mode 100644
index e1dd366f836b..000000000000
--- a/arch/arm/mach-mx25/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
1 zreladdr-y := 0x80008000
2params_phys-y := 0x80000100
3initrd_phys-y := 0x80800000
diff --git a/arch/arm/mach-mx25/devices.c b/arch/arm/mach-mx25/devices.c
deleted file mode 100644
index 1d0eb3e85941..000000000000
--- a/arch/arm/mach-mx25/devices.c
+++ /dev/null
@@ -1,308 +0,0 @@
1/*
2 * Copyright 2009 Sascha Hauer, <kernel@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
16 * Boston, MA 02110-1301, USA.
17 */
18
19#include <linux/platform_device.h>
20#include <linux/dma-mapping.h>
21#include <linux/gpio.h>
22#include <mach/mx25.h>
23#include <mach/irqs.h>
24
25static u64 otg_dmamask = DMA_BIT_MASK(32);
26
27static struct resource mxc_otg_resources[] = {
28 {
29 .start = MX25_OTG_BASE_ADDR,
30 .end = MX25_OTG_BASE_ADDR + 0x1ff,
31 .flags = IORESOURCE_MEM,
32 }, {
33 .start = 37,
34 .end = 37,
35 .flags = IORESOURCE_IRQ,
36 },
37};
38
39struct platform_device mxc_otg = {
40 .name = "mxc-ehci",
41 .id = 0,
42 .dev = {
43 .coherent_dma_mask = 0xffffffff,
44 .dma_mask = &otg_dmamask,
45 },
46 .resource = mxc_otg_resources,
47 .num_resources = ARRAY_SIZE(mxc_otg_resources),
48};
49
50/* OTG gadget device */
51struct platform_device otg_udc_device = {
52 .name = "fsl-usb2-udc",
53 .id = -1,
54 .dev = {
55 .dma_mask = &otg_dmamask,
56 .coherent_dma_mask = 0xffffffff,
57 },
58 .resource = mxc_otg_resources,
59 .num_resources = ARRAY_SIZE(mxc_otg_resources),
60};
61
62static u64 usbh2_dmamask = DMA_BIT_MASK(32);
63
64static struct resource mxc_usbh2_resources[] = {
65 {
66 .start = MX25_OTG_BASE_ADDR + 0x400,
67 .end = MX25_OTG_BASE_ADDR + 0x5ff,
68 .flags = IORESOURCE_MEM,
69 }, {
70 .start = 35,
71 .end = 35,
72 .flags = IORESOURCE_IRQ,
73 },
74};
75
76struct platform_device mxc_usbh2 = {
77 .name = "mxc-ehci",
78 .id = 1,
79 .dev = {
80 .coherent_dma_mask = 0xffffffff,
81 .dma_mask = &usbh2_dmamask,
82 },
83 .resource = mxc_usbh2_resources,
84 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
85};
86
87static struct resource mxc_pwm_resources0[] = {
88 {
89 .start = 0x53fe0000,
90 .end = 0x53fe3fff,
91 .flags = IORESOURCE_MEM,
92 }, {
93 .start = 26,
94 .end = 26,
95 .flags = IORESOURCE_IRQ,
96 }
97};
98
99struct platform_device mxc_pwm_device0 = {
100 .name = "mxc_pwm",
101 .id = 0,
102 .num_resources = ARRAY_SIZE(mxc_pwm_resources0),
103 .resource = mxc_pwm_resources0,
104};
105
106static struct resource mxc_pwm_resources1[] = {
107 {
108 .start = 0x53fa0000,
109 .end = 0x53fa3fff,
110 .flags = IORESOURCE_MEM,
111 }, {
112 .start = 36,
113 .end = 36,
114 .flags = IORESOURCE_IRQ,
115 }
116};
117
118struct platform_device mxc_pwm_device1 = {
119 .name = "mxc_pwm",
120 .id = 1,
121 .num_resources = ARRAY_SIZE(mxc_pwm_resources1),
122 .resource = mxc_pwm_resources1,
123};
124
125static struct resource mxc_pwm_resources2[] = {
126 {
127 .start = 0x53fa8000,
128 .end = 0x53fabfff,
129 .flags = IORESOURCE_MEM,
130 }, {
131 .start = 41,
132 .end = 41,
133 .flags = IORESOURCE_IRQ,
134 }
135};
136
137struct platform_device mxc_pwm_device2 = {
138 .name = "mxc_pwm",
139 .id = 2,
140 .num_resources = ARRAY_SIZE(mxc_pwm_resources2),
141 .resource = mxc_pwm_resources2,
142};
143
144static struct resource mxc_keypad_resources[] = {
145 {
146 .start = 0x43fa8000,
147 .end = 0x43fabfff,
148 .flags = IORESOURCE_MEM,
149 }, {
150 .start = 24,
151 .end = 24,
152 .flags = IORESOURCE_IRQ,
153 }
154};
155
156struct platform_device mxc_keypad_device = {
157 .name = "mxc-keypad",
158 .id = -1,
159 .num_resources = ARRAY_SIZE(mxc_keypad_resources),
160 .resource = mxc_keypad_resources,
161};
162
163static struct resource mxc_pwm_resources3[] = {
164 {
165 .start = 0x53fc8000,
166 .end = 0x53fcbfff,
167 .flags = IORESOURCE_MEM,
168 }, {
169 .start = 42,
170 .end = 42,
171 .flags = IORESOURCE_IRQ,
172 }
173};
174
175struct platform_device mxc_pwm_device3 = {
176 .name = "mxc_pwm",
177 .id = 3,
178 .num_resources = ARRAY_SIZE(mxc_pwm_resources3),
179 .resource = mxc_pwm_resources3,
180};
181
182static struct mxc_gpio_port imx_gpio_ports[] = {
183 {
184 .chip.label = "gpio-0",
185 .base = (void __iomem *)MX25_GPIO1_BASE_ADDR_VIRT,
186 .irq = 52,
187 .virtual_irq_start = MXC_GPIO_IRQ_START,
188 }, {
189 .chip.label = "gpio-1",
190 .base = (void __iomem *)MX25_GPIO2_BASE_ADDR_VIRT,
191 .irq = 51,
192 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
193 }, {
194 .chip.label = "gpio-2",
195 .base = (void __iomem *)MX25_GPIO3_BASE_ADDR_VIRT,
196 .irq = 16,
197 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
198 }, {
199 .chip.label = "gpio-3",
200 .base = (void __iomem *)MX25_GPIO4_BASE_ADDR_VIRT,
201 .irq = 23,
202 .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
203 }
204};
205
206int __init imx25_register_gpios(void)
207{
208 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
209}
210
211static struct resource mx25_rtc_resources[] = {
212 {
213 .start = MX25_DRYICE_BASE_ADDR,
214 .end = MX25_DRYICE_BASE_ADDR + 0x40,
215 .flags = IORESOURCE_MEM,
216 },
217 {
218 .start = MX25_INT_DRYICE,
219 .flags = IORESOURCE_IRQ
220 },
221};
222
223struct platform_device mx25_rtc_device = {
224 .name = "imxdi_rtc",
225 .id = 0,
226 .num_resources = ARRAY_SIZE(mx25_rtc_resources),
227 .resource = mx25_rtc_resources,
228};
229
230static struct resource mx25_fb_resources[] = {
231 {
232 .start = MX25_LCDC_BASE_ADDR,
233 .end = MX25_LCDC_BASE_ADDR + 0xfff,
234 .flags = IORESOURCE_MEM,
235 },
236 {
237 .start = MX25_INT_LCDC,
238 .end = MX25_INT_LCDC,
239 .flags = IORESOURCE_IRQ,
240 },
241};
242
243struct platform_device mx25_fb_device = {
244 .name = "imx-fb",
245 .id = 0,
246 .resource = mx25_fb_resources,
247 .num_resources = ARRAY_SIZE(mx25_fb_resources),
248 .dev = {
249 .coherent_dma_mask = 0xFFFFFFFF,
250 },
251};
252
253static struct resource mxc_wdt_resources[] = {
254 {
255 .start = MX25_WDOG_BASE_ADDR,
256 .end = MX25_WDOG_BASE_ADDR + SZ_16K - 1,
257 .flags = IORESOURCE_MEM,
258 },
259};
260
261struct platform_device mxc_wdt = {
262 .name = "imx2-wdt",
263 .id = 0,
264 .num_resources = ARRAY_SIZE(mxc_wdt_resources),
265 .resource = mxc_wdt_resources,
266};
267
268static struct resource mx25_kpp_resources[] = {
269 {
270 .start = MX25_KPP_BASE_ADDR,
271 .end = MX25_KPP_BASE_ADDR + 0xf,
272 .flags = IORESOURCE_MEM,
273 },
274 {
275 .start = MX25_INT_KPP,
276 .end = MX25_INT_KPP,
277 .flags = IORESOURCE_IRQ,
278 },
279};
280
281struct platform_device mx25_kpp_device = {
282 .name = "imx-keypad",
283 .id = -1,
284 .num_resources = ARRAY_SIZE(mx25_kpp_resources),
285 .resource = mx25_kpp_resources,
286};
287
288static struct resource mx25_csi_resources[] = {
289 {
290 .start = MX25_CSI_BASE_ADDR,
291 .end = MX25_CSI_BASE_ADDR + 0xfff,
292 .flags = IORESOURCE_MEM,
293 },
294 {
295 .start = MX25_INT_CSI,
296 .flags = IORESOURCE_IRQ
297 },
298};
299
300struct platform_device mx25_csi_device = {
301 .name = "mx2-camera",
302 .id = 0,
303 .num_resources = ARRAY_SIZE(mx25_csi_resources),
304 .resource = mx25_csi_resources,
305 .dev = {
306 .coherent_dma_mask = 0xffffffff,
307 },
308};
diff --git a/arch/arm/mach-mx25/devices.h b/arch/arm/mach-mx25/devices.h
deleted file mode 100644
index 7b70a43c3a4b..000000000000
--- a/arch/arm/mach-mx25/devices.h
+++ /dev/null
@@ -1,13 +0,0 @@
1extern struct platform_device mxc_otg;
2extern struct platform_device otg_udc_device;
3extern struct platform_device mxc_usbh2;
4extern struct platform_device mxc_pwm_device0;
5extern struct platform_device mxc_pwm_device1;
6extern struct platform_device mxc_pwm_device2;
7extern struct platform_device mxc_pwm_device3;
8extern struct platform_device mxc_keypad_device;
9extern struct platform_device mx25_rtc_device;
10extern struct platform_device mx25_fb_device;
11extern struct platform_device mxc_wdt;
12extern struct platform_device mx25_kpp_device;
13extern struct platform_device mx25_csi_device;
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
index 5000ac1f93e3..0717f887cba0 100644
--- a/arch/arm/mach-mx3/Kconfig
+++ b/arch/arm/mach-mx3/Kconfig
@@ -1,21 +1,35 @@
1if ARCH_MX3 1if ARCH_MX3
2 2
3# ARCH_MX31 and ARCH_MX35 are left for compatibility
4# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
5# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
6# more sensible) names are used: SOC_IMX31 and SOC_IMX35
3config ARCH_MX31 7config ARCH_MX31
4 select ARCH_HAS_RNGA
5 select ARCH_MXC_AUDMUX_V2
6 bool 8 bool
7 9
8config ARCH_MX35 10config ARCH_MX35
9 bool 11 bool
12
13config SOC_IMX31
14 bool
15 select IMX_HAVE_PLATFORM_MXC_RNGA
16 select ARCH_MXC_AUDMUX_V2
17 select ARCH_MX31
18 select MXC_AVIC
19
20config SOC_IMX35
21 bool
10 select ARCH_MXC_IOMUX_V3 22 select ARCH_MXC_IOMUX_V3
11 select ARCH_MXC_AUDMUX_V2 23 select ARCH_MXC_AUDMUX_V2
12 select HAVE_EPIT 24 select HAVE_EPIT
25 select ARCH_MX35
26 select MXC_AVIC
13 27
14comment "MX3 platforms:" 28comment "MX3 platforms:"
15 29
16config MACH_MX31ADS 30config MACH_MX31ADS
17 bool "Support MX31ADS platforms" 31 bool "Support MX31ADS platforms"
18 select ARCH_MX31 32 select SOC_IMX31
19 select IMX_HAVE_PLATFORM_IMX_I2C 33 select IMX_HAVE_PLATFORM_IMX_I2C
20 select IMX_HAVE_PLATFORM_IMX_SSI 34 select IMX_HAVE_PLATFORM_IMX_SSI
21 select IMX_HAVE_PLATFORM_IMX_UART 35 select IMX_HAVE_PLATFORM_IMX_UART
@@ -37,10 +51,15 @@ config MACH_MX31ADS_WM1133_EV1
37 51
38config MACH_PCM037 52config MACH_PCM037
39 bool "Support Phytec pcm037 (i.MX31) platforms" 53 bool "Support Phytec pcm037 (i.MX31) platforms"
40 select ARCH_MX31 54 select SOC_IMX31
55 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
56 select IMX_HAVE_PLATFORM_IMX2_WDT
41 select IMX_HAVE_PLATFORM_IMX_I2C 57 select IMX_HAVE_PLATFORM_IMX_I2C
42 select IMX_HAVE_PLATFORM_IMX_UART 58 select IMX_HAVE_PLATFORM_IMX_UART
59 select IMX_HAVE_PLATFORM_MXC_EHCI
60 select IMX_HAVE_PLATFORM_MXC_MMC
43 select IMX_HAVE_PLATFORM_MXC_NAND 61 select IMX_HAVE_PLATFORM_MXC_NAND
62 select IMX_HAVE_PLATFORM_MXC_W1
44 select MXC_ULPI if USB_ULPI 63 select MXC_ULPI if USB_ULPI
45 help 64 help
46 Include support for Phytec pcm037 platform. This includes 65 Include support for Phytec pcm037 platform. This includes
@@ -57,9 +76,12 @@ config MACH_PCM037_EET
57 76
58config MACH_MX31LITE 77config MACH_MX31LITE
59 bool "Support MX31 LITEKIT (LogicPD)" 78 bool "Support MX31 LITEKIT (LogicPD)"
60 select ARCH_MX31 79 select SOC_IMX31
61 select MXC_ULPI if USB_ULPI 80 select MXC_ULPI if USB_ULPI
81 select IMX_HAVE_PLATFORM_IMX2_WDT
62 select IMX_HAVE_PLATFORM_IMX_UART 82 select IMX_HAVE_PLATFORM_IMX_UART
83 select IMX_HAVE_PLATFORM_MXC_EHCI
84 select IMX_HAVE_PLATFORM_MXC_MMC
63 select IMX_HAVE_PLATFORM_MXC_NAND 85 select IMX_HAVE_PLATFORM_MXC_NAND
64 select IMX_HAVE_PLATFORM_SPI_IMX 86 select IMX_HAVE_PLATFORM_SPI_IMX
65 help 87 help
@@ -68,11 +90,16 @@ config MACH_MX31LITE
68 90
69config MACH_MX31_3DS 91config MACH_MX31_3DS
70 bool "Support MX31PDK (3DS)" 92 bool "Support MX31PDK (3DS)"
71 select ARCH_MX31 93 select SOC_IMX31
72 select MXC_DEBUG_BOARD 94 select MXC_DEBUG_BOARD
95 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
96 select IMX_HAVE_PLATFORM_IMX2_WDT
97 select IMX_HAVE_PLATFORM_IMX_KEYPAD
73 select IMX_HAVE_PLATFORM_IMX_UART 98 select IMX_HAVE_PLATFORM_IMX_UART
99 select IMX_HAVE_PLATFORM_MXC_EHCI
74 select IMX_HAVE_PLATFORM_MXC_NAND 100 select IMX_HAVE_PLATFORM_MXC_NAND
75 select IMX_HAVE_PLATFORM_SPI_IMX 101 select IMX_HAVE_PLATFORM_SPI_IMX
102 select MXC_ULPI if USB_ULPI
76 help 103 help
77 Include support for MX31PDK (3DS) platform. This includes specific 104 Include support for MX31PDK (3DS) platform. This includes specific
78 configurations for the board and its peripherals. 105 configurations for the board and its peripherals.
@@ -88,9 +115,12 @@ config MACH_MX31_3DS_MXC_NAND_USE_BBT
88 115
89config MACH_MX31MOBOARD 116config MACH_MX31MOBOARD
90 bool "Support mx31moboard platforms (EPFL Mobots group)" 117 bool "Support mx31moboard platforms (EPFL Mobots group)"
91 select ARCH_MX31 118 select SOC_IMX31
119 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
92 select IMX_HAVE_PLATFORM_IMX_I2C 120 select IMX_HAVE_PLATFORM_IMX_I2C
93 select IMX_HAVE_PLATFORM_IMX_UART 121 select IMX_HAVE_PLATFORM_IMX_UART
122 select IMX_HAVE_PLATFORM_MXC_EHCI
123 select IMX_HAVE_PLATFORM_MXC_MMC
94 select IMX_HAVE_PLATFORM_SPI_IMX 124 select IMX_HAVE_PLATFORM_SPI_IMX
95 select MXC_ULPI if USB_ULPI 125 select MXC_ULPI if USB_ULPI
96 help 126 help
@@ -99,8 +129,10 @@ config MACH_MX31MOBOARD
99 129
100config MACH_MX31LILLY 130config MACH_MX31LILLY
101 bool "Support MX31 LILLY-1131 platforms (INCO startec)" 131 bool "Support MX31 LILLY-1131 platforms (INCO startec)"
102 select ARCH_MX31 132 select SOC_IMX31
103 select IMX_HAVE_PLATFORM_IMX_UART 133 select IMX_HAVE_PLATFORM_IMX_UART
134 select IMX_HAVE_PLATFORM_MXC_EHCI
135 select IMX_HAVE_PLATFORM_MXC_MMC
104 select IMX_HAVE_PLATFORM_SPI_IMX 136 select IMX_HAVE_PLATFORM_SPI_IMX
105 select MXC_ULPI if USB_ULPI 137 select MXC_ULPI if USB_ULPI
106 help 138 help
@@ -109,7 +141,7 @@ config MACH_MX31LILLY
109 141
110config MACH_QONG 142config MACH_QONG
111 bool "Support Dave/DENX QongEVB-LITE platform" 143 bool "Support Dave/DENX QongEVB-LITE platform"
112 select ARCH_MX31 144 select SOC_IMX31
113 select IMX_HAVE_PLATFORM_IMX_UART 145 select IMX_HAVE_PLATFORM_IMX_UART
114 help 146 help
115 Include support for Dave/DENX QongEVB-LITE platform. This includes 147 Include support for Dave/DENX QongEVB-LITE platform. This includes
@@ -117,13 +149,16 @@ config MACH_QONG
117 149
118config MACH_PCM043 150config MACH_PCM043
119 bool "Support Phytec pcm043 (i.MX35) platforms" 151 bool "Support Phytec pcm043 (i.MX35) platforms"
120 select ARCH_MX35 152 select SOC_IMX35
153 select IMX_HAVE_PLATFORM_FLEXCAN
154 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
155 select IMX_HAVE_PLATFORM_IMX2_WDT
121 select IMX_HAVE_PLATFORM_IMX_I2C 156 select IMX_HAVE_PLATFORM_IMX_I2C
122 select IMX_HAVE_PLATFORM_IMX_SSI 157 select IMX_HAVE_PLATFORM_IMX_SSI
123 select IMX_HAVE_PLATFORM_IMX_UART 158 select IMX_HAVE_PLATFORM_IMX_UART
159 select IMX_HAVE_PLATFORM_MXC_EHCI
124 select IMX_HAVE_PLATFORM_MXC_NAND 160 select IMX_HAVE_PLATFORM_MXC_NAND
125 select IMX_HAVE_PLATFORM_FLEXCAN 161 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
126 select IMX_HAVE_PLATFORM_ESDHC
127 select MXC_ULPI if USB_ULPI 162 select MXC_ULPI if USB_ULPI
128 help 163 help
129 Include support for Phytec pcm043 platform. This includes 164 Include support for Phytec pcm043 platform. This includes
@@ -131,9 +166,11 @@ config MACH_PCM043
131 166
132config MACH_ARMADILLO5X0 167config MACH_ARMADILLO5X0
133 bool "Support Atmark Armadillo-500 Development Base Board" 168 bool "Support Atmark Armadillo-500 Development Base Board"
134 select ARCH_MX31 169 select SOC_IMX31
135 select IMX_HAVE_PLATFORM_IMX_I2C 170 select IMX_HAVE_PLATFORM_IMX_I2C
136 select IMX_HAVE_PLATFORM_IMX_UART 171 select IMX_HAVE_PLATFORM_IMX_UART
172 select IMX_HAVE_PLATFORM_MXC_EHCI
173 select IMX_HAVE_PLATFORM_MXC_MMC
137 select IMX_HAVE_PLATFORM_MXC_NAND 174 select IMX_HAVE_PLATFORM_MXC_NAND
138 select MXC_ULPI if USB_ULPI 175 select MXC_ULPI if USB_ULPI
139 help 176 help
@@ -142,19 +179,21 @@ config MACH_ARMADILLO5X0
142 179
143config MACH_MX35_3DS 180config MACH_MX35_3DS
144 bool "Support MX35PDK platform" 181 bool "Support MX35PDK platform"
145 select ARCH_MX35 182 select SOC_IMX35
146 select MXC_DEBUG_BOARD 183 select MXC_DEBUG_BOARD
184 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
185 select IMX_HAVE_PLATFORM_IMX2_WDT
147 select IMX_HAVE_PLATFORM_IMX_UART 186 select IMX_HAVE_PLATFORM_IMX_UART
187 select IMX_HAVE_PLATFORM_MXC_EHCI
148 select IMX_HAVE_PLATFORM_MXC_NAND 188 select IMX_HAVE_PLATFORM_MXC_NAND
149 select IMX_HAVE_PLATFORM_ESDHC 189 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
150 default n
151 help 190 help
152 Include support for MX35PDK platform. This includes specific 191 Include support for MX35PDK platform. This includes specific
153 configurations for the board and its peripherals. 192 configurations for the board and its peripherals.
154 193
155config MACH_KZM_ARM11_01 194config MACH_KZM_ARM11_01
156 bool "Support KZM-ARM11-01(Kyoto Microcomputer)" 195 bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
157 select ARCH_MX31 196 select SOC_IMX31
158 select IMX_HAVE_PLATFORM_IMX_UART 197 select IMX_HAVE_PLATFORM_IMX_UART
159 help 198 help
160 Include support for KZM-ARM11-01. This includes specific 199 Include support for KZM-ARM11-01. This includes specific
@@ -162,12 +201,15 @@ config MACH_KZM_ARM11_01
162 201
163config MACH_EUKREA_CPUIMX35 202config MACH_EUKREA_CPUIMX35
164 bool "Support Eukrea CPUIMX35 Platform" 203 bool "Support Eukrea CPUIMX35 Platform"
165 select ARCH_MX35 204 select SOC_IMX35
166 select IMX_HAVE_PLATFORM_IMX_UART 205 select IMX_HAVE_PLATFORM_FLEXCAN
206 select IMX_HAVE_PLATFORM_FSL_USB2_UDC
207 select IMX_HAVE_PLATFORM_IMX2_WDT
167 select IMX_HAVE_PLATFORM_IMX_I2C 208 select IMX_HAVE_PLATFORM_IMX_I2C
209 select IMX_HAVE_PLATFORM_IMX_UART
210 select IMX_HAVE_PLATFORM_MXC_EHCI
168 select IMX_HAVE_PLATFORM_MXC_NAND 211 select IMX_HAVE_PLATFORM_MXC_NAND
169 select IMX_HAVE_PLATFORM_FLEXCAN 212 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
170 select IMX_HAVE_PLATFORM_ESDHC
171 select MXC_ULPI if USB_ULPI 213 select MXC_ULPI if USB_ULPI
172 help 214 help
173 Include support for Eukrea CPUIMX35 platform. This includes 215 Include support for Eukrea CPUIMX35 platform. This includes
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
index 8a182d0a3fcf..8db13294ad27 100644
--- a/arch/arm/mach-mx3/Makefile
+++ b/arch/arm/mach-mx3/Makefile
@@ -5,17 +5,14 @@
5# Object file lists. 5# Object file lists.
6 6
7obj-y := mm.o devices.o cpu.o 7obj-y := mm.o devices.o cpu.o
8CFLAGS_mm.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS 8obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o
9CFLAGS_devices.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS 9obj-$(CONFIG_SOC_IMX35) += clock-imx35.o
10obj-$(CONFIG_ARCH_MX31) += clock-imx31.o iomux-imx31.o
11obj-$(CONFIG_ARCH_MX35) += clock-imx35.o
12obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o 10obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
13obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o 11obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
14obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o 12obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
15obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o 13obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
16obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o 14obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
17obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o 15obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
18CFLAGS_mach-mx31_3ds.o = -DIMX_NEEDS_DEPRECATED_SYMBOLS
19obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \ 16obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
20 mx31moboard-marxbot.o mx31moboard-smartbot.o 17 mx31moboard-marxbot.o mx31moboard-smartbot.o
21obj-$(CONFIG_MACH_QONG) += mach-qong.o 18obj-$(CONFIG_MACH_QONG) += mach-qong.o
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
index 109e98f323e0..4193cf5a2637 100644
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -530,7 +530,7 @@ static struct clk_lookup lookups[] = {
530 _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk) 530 _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
531 _REGISTER_CLOCK(NULL, "gpt", gpt_clk) 531 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
532 _REGISTER_CLOCK(NULL, "pwm", pwm_clk) 532 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
533 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) 533 _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
534 _REGISTER_CLOCK(NULL, "rtc", rtc_clk) 534 _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
535 _REGISTER_CLOCK(NULL, "epit", epit1_clk) 535 _REGISTER_CLOCK(NULL, "epit", epit1_clk)
536 _REGISTER_CLOCK(NULL, "epit", epit2_clk) 536 _REGISTER_CLOCK(NULL, "epit", epit2_clk)
@@ -615,7 +615,7 @@ int __init mx31_clocks_init(unsigned long fref)
615 615
616 mx31_read_cpu_rev(); 616 mx31_read_cpu_rev();
617 617
618 if (mx31_revision() >= MX31_CHIP_REV_2_0) { 618 if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
619 reg = __raw_readl(MXC_CCM_PMCR1); 619 reg = __raw_readl(MXC_CCM_PMCR1);
620 /* No PLL restart on DVFS switch; enable auto EMI handshake */ 620 /* No PLL restart on DVFS switch; enable auto EMI handshake */
621 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN; 621 reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index 61e4a318980a..22259d955837 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -495,7 +495,7 @@ static struct clk_lookup lookups[] = {
495 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk) 495 _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
496 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk) 496 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
497 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk) 497 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
498 _REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk) 498 _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
499 _REGISTER_CLOCK(NULL, "max", max_clk) 499 _REGISTER_CLOCK(NULL, "max", max_clk)
500 _REGISTER_CLOCK(NULL, "audmux", audmux_clk) 500 _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
501 _REGISTER_CLOCK(NULL, "csi", csi_clk) 501 _REGISTER_CLOCK(NULL, "csi", csi_clk)
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
index d00a75457812..d1d339576fdf 100644
--- a/arch/arm/mach-mx3/cpu.c
+++ b/arch/arm/mach-mx3/cpu.c
@@ -25,15 +25,15 @@ struct mx3_cpu_type {
25}; 25};
26 26
27static struct mx3_cpu_type mx31_cpu_type[] __initdata = { 27static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
28 { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = MX3x_CHIP_REV_1_0 }, 28 { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
29 { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 }, 29 { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
30 { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = MX3x_CHIP_REV_1_1 }, 30 { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
31 { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 }, 31 { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
32 { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = MX3x_CHIP_REV_1_1 }, 32 { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
33 { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 }, 33 { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
34 { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = MX3x_CHIP_REV_1_2 }, 34 { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
35 { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 }, 35 { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
36 { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = MX3x_CHIP_REV_2_0 }, 36 { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
37}; 37};
38 38
39void __init mx31_read_cpu_rev(void) 39void __init mx31_read_cpu_rev(void)
@@ -53,6 +53,8 @@ void __init mx31_read_cpu_rev(void)
53 return; 53 return;
54 } 54 }
55 55
56 mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
57
56 printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev); 58 printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
57} 59}
58 60
@@ -62,22 +64,25 @@ EXPORT_SYMBOL(mx35_cpu_rev);
62void __init mx35_read_cpu_rev(void) 64void __init mx35_read_cpu_rev(void)
63{ 65{
64 u32 rev; 66 u32 rev;
65 char *srev = "unknown"; 67 char *srev;
66 68
67 rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV)); 69 rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
68 switch (rev) { 70 switch (rev) {
69 case 0x00: 71 case 0x00:
70 mx35_cpu_rev = MX3x_CHIP_REV_1_0; 72 mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
71 srev = "1.0"; 73 srev = "1.0";
72 break; 74 break;
73 case 0x10: 75 case 0x10:
74 mx35_cpu_rev = MX3x_CHIP_REV_2_0; 76 mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
75 srev = "2.0"; 77 srev = "2.0";
76 break; 78 break;
77 case 0x11: 79 case 0x11:
78 mx35_cpu_rev = MX3x_CHIP_REV_2_1; 80 mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
79 srev = "2.1"; 81 srev = "2.1";
80 break; 82 break;
83 default:
84 mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
85 srev = "unknown";
81 } 86 }
82 87
83 printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev); 88 printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
index de9598590eba..40f4e848a671 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -9,6 +9,14 @@
9#include <mach/mx31.h> 9#include <mach/mx31.h>
10#include <mach/devices-common.h> 10#include <mach/devices-common.h>
11 11
12extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst;
13#define imx31_add_fsl_usb2_udc(pdata) \
14 imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
15
16extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst;
17#define imx31_add_imx2_wdt(pdata) \
18 imx_add_imx2_wdt(&imx31_imx2_wdt_data)
19
12extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst; 20extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
13#define imx31_add_imx_i2c(id, pdata) \ 21#define imx31_add_imx_i2c(id, pdata) \
14 imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata) 22 imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
@@ -16,6 +24,10 @@ extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
16#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata) 24#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
17#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata) 25#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
18 26
27extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst;
28#define imx31_add_imx_keypad(pdata) \
29 imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
30
19extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst; 31extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
20#define imx31_add_imx_ssi(id, pdata) \ 32#define imx31_add_imx_ssi(id, pdata) \
21 imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata) 33 imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
@@ -29,10 +41,25 @@ extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
29#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata) 41#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
30#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata) 42#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
31 43
44extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst;
45#define imx31_add_mxc_ehci_otg(pdata) \
46 imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
47extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst;
48#define imx31_add_mxc_ehci_hs(id, pdata) \
49 imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
50
51extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst;
52#define imx31_add_mxc_mmc(id, pdata) \
53 imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
54
32extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst; 55extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
33#define imx31_add_mxc_nand(pdata) \ 56#define imx31_add_mxc_nand(pdata) \
34 imx_add_mxc_nand(&imx31_mxc_nand_data, pdata) 57 imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
35 58
59extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst;
60#define imx31_add_mxc_w1(pdata) \
61 imx_add_mxc_w1(&imx31_mxc_w1_data)
62
36extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst; 63extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
37#define imx31_add_cspi(id, pdata) \ 64#define imx31_add_cspi(id, pdata) \
38 imx_add_spi_imx(&imx31_cspi_data[id], pdata) 65 imx_add_spi_imx(&imx31_cspi_data[id], pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index 5eb917b638d0..677b18aa7ae6 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -13,10 +13,19 @@ extern const struct imx_fec_data imx35_fec_data __initconst;
13#define imx35_add_fec(pdata) \ 13#define imx35_add_fec(pdata) \
14 imx_add_fec(&imx35_fec_data, pdata) 14 imx_add_fec(&imx35_fec_data, pdata)
15 15
16#define imx35_add_flexcan0(pdata) \ 16extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst;
17 imx_add_flexcan(0, MX35_CAN1_BASE_ADDR, SZ_16K, MX35_INT_CAN1, pdata) 17#define imx35_add_fsl_usb2_udc(pdata) \
18#define imx35_add_flexcan1(pdata) \ 18 imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
19 imx_add_flexcan(1, MX35_CAN2_BASE_ADDR, SZ_16K, MX35_INT_CAN2, pdata) 19
20extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst;
21#define imx35_add_flexcan(id, pdata) \
22 imx_add_flexcan(&imx35_flexcan_data[id], pdata)
23#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata)
24#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata)
25
26extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst;
27#define imx35_add_imx2_wdt(pdata) \
28 imx_add_imx2_wdt(&imx35_imx2_wdt_data)
20 29
21extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst; 30extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
22#define imx35_add_imx_i2c(id, pdata) \ 31#define imx35_add_imx_i2c(id, pdata) \
@@ -25,6 +34,10 @@ extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
25#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata) 34#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
26#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata) 35#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
27 36
37extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
38#define imx31_add_imx_keypad(pdata) \
39 imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
40
28extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst; 41extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
29#define imx35_add_imx_ssi(id, pdata) \ 42#define imx35_add_imx_ssi(id, pdata) \
30 imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata) 43 imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
@@ -36,16 +49,28 @@ extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
36#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata) 49#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
37#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata) 50#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
38 51
52extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst;
53#define imx35_add_mxc_ehci_otg(pdata) \
54 imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
55extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst;
56#define imx35_add_mxc_ehci_hs(pdata) \
57 imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
58
39extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst; 59extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
40#define imx35_add_mxc_nand(pdata) \ 60#define imx35_add_mxc_nand(pdata) \
41 imx_add_mxc_nand(&imx35_mxc_nand_data, pdata) 61 imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
42 62
63extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst;
64#define imx35_add_mxc_w1(pdata) \
65 imx_add_mxc_w1(&imx35_mxc_w1_data)
66
67extern const struct imx_sdhci_esdhc_imx_data
68imx35_sdhci_esdhc_imx_data[] __initconst;
69#define imx35_add_sdhci_esdhc_imx(id, pdata) \
70 imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
71
43extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst; 72extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
44#define imx35_add_cspi(id, pdata) \ 73#define imx35_add_cspi(id, pdata) \
45 imx_add_spi_imx(&imx35_cspi_data[id], pdata) 74 imx_add_spi_imx(&imx35_cspi_data[id], pdata)
46#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata) 75#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
47#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata) 76#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
48
49extern const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst;
50#define imx35_add_esdhc(id, pdata) \
51 imx_add_esdhc(&imx35_esdhc_data[id], pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
index d4da9496089a..b6672db788fb 100644
--- a/arch/arm/mach-mx3/devices.c
+++ b/arch/arm/mach-mx3/devices.c
@@ -29,120 +29,25 @@
29 29
30#include "devices.h" 30#include "devices.h"
31 31
32/* GPIO port description */
33static struct mxc_gpio_port imx_gpio_ports[] = {
34 {
35 .chip.label = "gpio-0",
36 .base = IO_ADDRESS(GPIO1_BASE_ADDR),
37 .irq = MXC_INT_GPIO1,
38 .virtual_irq_start = MXC_GPIO_IRQ_START,
39 }, {
40 .chip.label = "gpio-1",
41 .base = IO_ADDRESS(GPIO2_BASE_ADDR),
42 .irq = MXC_INT_GPIO2,
43 .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
44 }, {
45 .chip.label = "gpio-2",
46 .base = IO_ADDRESS(GPIO3_BASE_ADDR),
47 .irq = MXC_INT_GPIO3,
48 .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
49 }
50};
51
52int __init imx3x_register_gpios(void)
53{
54 return mxc_gpio_init(imx_gpio_ports, ARRAY_SIZE(imx_gpio_ports));
55}
56
57static struct resource mxc_w1_master_resources[] = {
58 {
59 .start = OWIRE_BASE_ADDR,
60 .end = OWIRE_BASE_ADDR + SZ_4K - 1,
61 .flags = IORESOURCE_MEM,
62 },
63};
64
65struct platform_device mxc_w1_master_device = {
66 .name = "mxc_w1",
67 .id = 0,
68 .num_resources = ARRAY_SIZE(mxc_w1_master_resources),
69 .resource = mxc_w1_master_resources,
70};
71
72#ifdef CONFIG_ARCH_MX31
73static struct resource mxcsdhc0_resources[] = {
74 {
75 .start = MX31_MMC_SDHC1_BASE_ADDR,
76 .end = MX31_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
77 .flags = IORESOURCE_MEM,
78 }, {
79 .start = MX31_INT_MMC_SDHC1,
80 .end = MX31_INT_MMC_SDHC1,
81 .flags = IORESOURCE_IRQ,
82 },
83};
84
85static struct resource mxcsdhc1_resources[] = {
86 {
87 .start = MX31_MMC_SDHC2_BASE_ADDR,
88 .end = MX31_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
89 .flags = IORESOURCE_MEM,
90 }, {
91 .start = MX31_INT_MMC_SDHC2,
92 .end = MX31_INT_MMC_SDHC2,
93 .flags = IORESOURCE_IRQ,
94 },
95};
96
97struct platform_device mxcsdhc_device0 = {
98 .name = "mxc-mmc",
99 .id = 0,
100 .num_resources = ARRAY_SIZE(mxcsdhc0_resources),
101 .resource = mxcsdhc0_resources,
102};
103
104struct platform_device mxcsdhc_device1 = {
105 .name = "mxc-mmc",
106 .id = 1,
107 .num_resources = ARRAY_SIZE(mxcsdhc1_resources),
108 .resource = mxcsdhc1_resources,
109};
110
111static struct resource rnga_resources[] = {
112 {
113 .start = RNGA_BASE_ADDR,
114 .end = RNGA_BASE_ADDR + 0x28,
115 .flags = IORESOURCE_MEM,
116 },
117};
118
119struct platform_device mxc_rnga_device = {
120 .name = "mxc_rnga",
121 .id = -1,
122 .num_resources = 1,
123 .resource = rnga_resources,
124};
125#endif /* CONFIG_ARCH_MX31 */
126
127/* i.MX31 Image Processing Unit */ 32/* i.MX31 Image Processing Unit */
128 33
129/* The resource order is important! */ 34/* The resource order is important! */
130static struct resource mx3_ipu_rsrc[] = { 35static struct resource mx3_ipu_rsrc[] = {
131 { 36 {
132 .start = IPU_CTRL_BASE_ADDR, 37 .start = MX3x_IPU_CTRL_BASE_ADDR,
133 .end = IPU_CTRL_BASE_ADDR + 0x5F, 38 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
134 .flags = IORESOURCE_MEM, 39 .flags = IORESOURCE_MEM,
135 }, { 40 }, {
136 .start = IPU_CTRL_BASE_ADDR + 0x88, 41 .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
137 .end = IPU_CTRL_BASE_ADDR + 0xB3, 42 .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
138 .flags = IORESOURCE_MEM, 43 .flags = IORESOURCE_MEM,
139 }, { 44 }, {
140 .start = MXC_INT_IPU_SYN, 45 .start = MX3x_INT_IPU_SYN,
141 .end = MXC_INT_IPU_SYN, 46 .end = MX3x_INT_IPU_SYN,
142 .flags = IORESOURCE_IRQ, 47 .flags = IORESOURCE_IRQ,
143 }, { 48 }, {
144 .start = MXC_INT_IPU_ERR, 49 .start = MX3x_INT_IPU_ERR,
145 .end = MXC_INT_IPU_ERR, 50 .end = MX3x_INT_IPU_ERR,
146 .flags = IORESOURCE_IRQ, 51 .flags = IORESOURCE_IRQ,
147 }, 52 },
148}; 53};
@@ -156,8 +61,8 @@ struct platform_device mx3_ipu = {
156 61
157static struct resource fb_resources[] = { 62static struct resource fb_resources[] = {
158 { 63 {
159 .start = IPU_CTRL_BASE_ADDR + 0xB4, 64 .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
160 .end = IPU_CTRL_BASE_ADDR + 0x1BF, 65 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
161 .flags = IORESOURCE_MEM, 66 .flags = IORESOURCE_MEM,
162 }, 67 },
163}; 68};
@@ -174,8 +79,8 @@ struct platform_device mx3_fb = {
174 79
175static struct resource camera_resources[] = { 80static struct resource camera_resources[] = {
176 { 81 {
177 .start = IPU_CTRL_BASE_ADDR + 0x60, 82 .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
178 .end = IPU_CTRL_BASE_ADDR + 0x87, 83 .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
179 .flags = IORESOURCE_MEM, 84 .flags = IORESOURCE_MEM,
180 }, 85 },
181}; 86};
@@ -190,110 +95,6 @@ struct platform_device mx3_camera = {
190 }, 95 },
191}; 96};
192 97
193static struct resource otg_resources[] = {
194 {
195 .start = MX31_OTG_BASE_ADDR,
196 .end = MX31_OTG_BASE_ADDR + 0x1ff,
197 .flags = IORESOURCE_MEM,
198 }, {
199 .start = MXC_INT_USB3,
200 .end = MXC_INT_USB3,
201 .flags = IORESOURCE_IRQ,
202 },
203};
204
205static u64 otg_dmamask = DMA_BIT_MASK(32);
206
207/* OTG gadget device */
208struct platform_device mxc_otg_udc_device = {
209 .name = "fsl-usb2-udc",
210 .id = -1,
211 .dev = {
212 .dma_mask = &otg_dmamask,
213 .coherent_dma_mask = DMA_BIT_MASK(32),
214 },
215 .resource = otg_resources,
216 .num_resources = ARRAY_SIZE(otg_resources),
217};
218
219/* OTG host */
220struct platform_device mxc_otg_host = {
221 .name = "mxc-ehci",
222 .id = 0,
223 .dev = {
224 .coherent_dma_mask = 0xffffffff,
225 .dma_mask = &otg_dmamask,
226 },
227 .resource = otg_resources,
228 .num_resources = ARRAY_SIZE(otg_resources),
229};
230
231/* USB host 1 */
232
233static u64 usbh1_dmamask = ~(u32)0;
234
235static struct resource mxc_usbh1_resources[] = {
236 {
237 .start = MX31_OTG_BASE_ADDR + 0x200,
238 .end = MX31_OTG_BASE_ADDR + 0x3ff,
239 .flags = IORESOURCE_MEM,
240 }, {
241 .start = MXC_INT_USB1,
242 .end = MXC_INT_USB1,
243 .flags = IORESOURCE_IRQ,
244 },
245};
246
247struct platform_device mxc_usbh1 = {
248 .name = "mxc-ehci",
249 .id = 1,
250 .dev = {
251 .coherent_dma_mask = 0xffffffff,
252 .dma_mask = &usbh1_dmamask,
253 },
254 .resource = mxc_usbh1_resources,
255 .num_resources = ARRAY_SIZE(mxc_usbh1_resources),
256};
257
258/* USB host 2 */
259static u64 usbh2_dmamask = ~(u32)0;
260
261static struct resource mxc_usbh2_resources[] = {
262 {
263 .start = MX31_OTG_BASE_ADDR + 0x400,
264 .end = MX31_OTG_BASE_ADDR + 0x5ff,
265 .flags = IORESOURCE_MEM,
266 }, {
267 .start = MXC_INT_USB2,
268 .end = MXC_INT_USB2,
269 .flags = IORESOURCE_IRQ,
270 },
271};
272
273struct platform_device mxc_usbh2 = {
274 .name = "mxc-ehci",
275 .id = 2,
276 .dev = {
277 .coherent_dma_mask = 0xffffffff,
278 .dma_mask = &usbh2_dmamask,
279 },
280 .resource = mxc_usbh2_resources,
281 .num_resources = ARRAY_SIZE(mxc_usbh2_resources),
282};
283
284static struct resource imx_wdt_resources[] = {
285 {
286 .flags = IORESOURCE_MEM,
287 },
288};
289
290struct platform_device imx_wdt_device0 = {
291 .name = "imx2-wdt",
292 .id = 0,
293 .num_resources = ARRAY_SIZE(imx_wdt_resources),
294 .resource = imx_wdt_resources,
295};
296
297static struct resource imx_rtc_resources[] = { 98static struct resource imx_rtc_resources[] = {
298 { 99 {
299 .start = MX31_RTC_BASE_ADDR, 100 .start = MX31_RTC_BASE_ADDR,
@@ -312,51 +113,3 @@ struct platform_device imx_rtc_device0 = {
312 .num_resources = ARRAY_SIZE(imx_rtc_resources), 113 .num_resources = ARRAY_SIZE(imx_rtc_resources),
313 .resource = imx_rtc_resources, 114 .resource = imx_rtc_resources,
314}; 115};
315
316static struct resource imx_kpp_resources[] = {
317 {
318 .start = MX3x_KPP_BASE_ADDR,
319 .end = MX3x_KPP_BASE_ADDR + 0xf,
320 .flags = IORESOURCE_MEM
321 }, {
322 .start = MX3x_INT_KPP,
323 .end = MX3x_INT_KPP,
324 .flags = IORESOURCE_IRQ,
325 },
326};
327
328struct platform_device imx_kpp_device = {
329 .name = "imx-keypad",
330 .id = -1,
331 .num_resources = ARRAY_SIZE(imx_kpp_resources),
332 .resource = imx_kpp_resources,
333};
334
335static int __init mx3_devices_init(void)
336{
337#if defined(CONFIG_ARCH_MX31)
338 if (cpu_is_mx31()) {
339 imx_wdt_resources[0].start = MX31_WDOG_BASE_ADDR;
340 imx_wdt_resources[0].end = MX31_WDOG_BASE_ADDR + 0x3fff;
341 mxc_register_device(&mxc_rnga_device, NULL);
342 }
343#endif
344#if defined(CONFIG_ARCH_MX35)
345 if (cpu_is_mx35()) {
346 otg_resources[0].start = MX35_OTG_BASE_ADDR;
347 otg_resources[0].end = MX35_OTG_BASE_ADDR + 0x1ff;
348 otg_resources[1].start = MXC_INT_USBOTG;
349 otg_resources[1].end = MXC_INT_USBOTG;
350 mxc_usbh1_resources[0].start = MX35_OTG_BASE_ADDR + 0x400;
351 mxc_usbh1_resources[0].end = MX35_OTG_BASE_ADDR + 0x5ff;
352 mxc_usbh1_resources[1].start = MXC_INT_USBHS;
353 mxc_usbh1_resources[1].end = MXC_INT_USBHS;
354 imx_wdt_resources[0].start = MX35_WDOG_BASE_ADDR;
355 imx_wdt_resources[0].end = MX35_WDOG_BASE_ADDR + 0x3fff;
356 }
357#endif
358
359 return 0;
360}
361
362subsys_initcall(mx3_devices_init);
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
index 585f814473d5..121962c568d1 100644
--- a/arch/arm/mach-mx3/devices.h
+++ b/arch/arm/mach-mx3/devices.h
@@ -1,14 +1,4 @@
1extern struct platform_device mxc_w1_master_device;
2extern struct platform_device mx3_ipu; 1extern struct platform_device mx3_ipu;
3extern struct platform_device mx3_fb; 2extern struct platform_device mx3_fb;
4extern struct platform_device mx3_camera; 3extern struct platform_device mx3_camera;
5extern struct platform_device mxcsdhc_device0;
6extern struct platform_device mxcsdhc_device1;
7extern struct platform_device mxc_otg_udc_device;
8extern struct platform_device mxc_otg_host;
9extern struct platform_device mxc_usbh1;
10extern struct platform_device mxc_usbh2;
11extern struct platform_device mxc_rnga_device;
12extern struct platform_device imx_wdt_device0;
13extern struct platform_device imx_rtc_device0; 4extern struct platform_device imx_rtc_device0;
14extern struct platform_device imx_kpp_device;
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
index 1abc10d52922..14a5ffc939ad 100644
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
@@ -111,7 +111,7 @@ static struct mx3fb_platform_data mx3fb_pdata = {
111 .num_modes = ARRAY_SIZE(fb_modedb), 111 .num_modes = ARRAY_SIZE(fb_modedb),
112}; 112};
113 113
114static struct pad_desc eukrea_mbimxsd_pads[] = { 114static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
115 /* LCD */ 115 /* LCD */
116 MX35_PAD_LD0__IPU_DISPB_DAT_0, 116 MX35_PAD_LD0__IPU_DISPB_DAT_0,
117 MX35_PAD_LD1__IPU_DISPB_DAT_1, 117 MX35_PAD_LD1__IPU_DISPB_DAT_1,
@@ -289,7 +289,7 @@ void __init eukrea_mbimxsd35_baseboard_init(void)
289 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata); 289 imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
290 290
291 imx35_add_flexcan1(NULL); 291 imx35_add_flexcan1(NULL);
292 imx35_add_esdhc(0, NULL); 292 imx35_add_sdhci_esdhc_imx(0, NULL);
293 293
294 gpio_request(GPIO_LED1, "LED1"); 294 gpio_request(GPIO_LED1, "LED1");
295 gpio_direction_output(GPIO_LED1, 1); 295 gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
index aaa30fe18f85..28b6f414b5d5 100644
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ b/arch/arm/mach-mx3/mach-armadillo5x0.c
@@ -49,10 +49,8 @@
49 49
50#include <mach/common.h> 50#include <mach/common.h>
51#include <mach/iomux-mx3.h> 51#include <mach/iomux-mx3.h>
52#include <mach/mmc.h>
53#include <mach/ipu.h> 52#include <mach/ipu.h>
54#include <mach/mx3fb.h> 53#include <mach/mx3fb.h>
55#include <mach/mxc_ehci.h>
56#include <mach/ulpi.h> 54#include <mach/ulpi.h>
57 55
58#include "devices-imx31.h" 56#include "devices-imx31.h"
@@ -245,13 +243,13 @@ h2_free_cs:
245 return err; 243 return err;
246} 244}
247 245
248static struct mxc_usbh_platform_data usbotg_pdata = { 246static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
249 .init = usbotg_init, 247 .init = usbotg_init,
250 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 248 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
251 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, 249 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
252}; 250};
253 251
254static struct mxc_usbh_platform_data usbh2_pdata = { 252static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
255 .init = usbh2_init, 253 .init = usbh2_init,
256 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 254 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
257 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI, 255 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_DIFF_UNI,
@@ -453,7 +451,7 @@ static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
453 gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B)); 451 gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
454} 452}
455 453
456static struct imxmmc_platform_data sdhc_pdata = { 454static const struct imxmmc_platform_data sdhc_pdata __initconst = {
457 .get_ro = armadillo5x0_sdhc1_get_ro, 455 .get_ro = armadillo5x0_sdhc1_get_ro,
458 .init = armadillo5x0_sdhc1_init, 456 .init = armadillo5x0_sdhc1_init,
459 .exit = armadillo5x0_sdhc1_exit, 457 .exit = armadillo5x0_sdhc1_exit,
@@ -520,7 +518,7 @@ static void __init armadillo5x0_init(void)
520 gpio_direction_input(MX31_PIN_GPIO1_0); 518 gpio_direction_input(MX31_PIN_GPIO1_0);
521 519
522 /* Register SDHC */ 520 /* Register SDHC */
523 mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); 521 imx31_add_mxc_mmc(0, &sdhc_pdata);
524 522
525 /* Register FB */ 523 /* Register FB */
526 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 524 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
@@ -555,8 +553,8 @@ static void __init armadillo5x0_init(void)
555 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 553 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
556 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 554 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
557 555
558 mxc_register_device(&mxc_otg_host, &usbotg_pdata); 556 imx31_add_mxc_ehci_otg(&usbotg_pdata);
559 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 557 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
560#endif 558#endif
561} 559}
562 560
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
index 9fde873f5889..26ae90f02582 100644
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ b/arch/arm/mach-mx3/mach-cpuimx35.c
@@ -30,7 +30,6 @@
30#include <linux/i2c/tsc2007.h> 30#include <linux/i2c/tsc2007.h>
31#include <linux/usb/otg.h> 31#include <linux/usb/otg.h>
32#include <linux/usb/ulpi.h> 32#include <linux/usb/ulpi.h>
33#include <linux/fsl_devices.h>
34#include <linux/i2c-gpio.h> 33#include <linux/i2c-gpio.h>
35 34
36#include <asm/mach-types.h> 35#include <asm/mach-types.h>
@@ -43,7 +42,6 @@
43#include <mach/common.h> 42#include <mach/common.h>
44#include <mach/iomux-mx35.h> 43#include <mach/iomux-mx35.h>
45#include <mach/mxc_nand.h> 44#include <mach/mxc_nand.h>
46#include <mach/mxc_ehci.h>
47 45
48#include "devices-imx35.h" 46#include "devices-imx35.h"
49#include "devices.h" 47#include "devices.h"
@@ -74,11 +72,7 @@ static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
74 }, 72 },
75}; 73};
76 74
77static struct platform_device *devices[] __initdata = { 75static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
78 &imx_wdt_device0,
79};
80
81static struct pad_desc eukrea_cpuimx35_pads[] = {
82 /* UART1 */ 76 /* UART1 */
83 MX35_PAD_CTS1__UART1_CTS, 77 MX35_PAD_CTS1__UART1_CTS,
84 MX35_PAD_RTS1__UART1_RTS, 78 MX35_PAD_RTS1__UART1_RTS,
@@ -117,18 +111,18 @@ static const struct mxc_nand_platform_data
117 .flash_bbt = 1, 111 .flash_bbt = 1,
118}; 112};
119 113
120static struct mxc_usbh_platform_data __maybe_unused otg_pdata = { 114static const struct mxc_usbh_platform_data otg_pdata __initconst = {
121 .portsc = MXC_EHCI_MODE_UTMI, 115 .portsc = MXC_EHCI_MODE_UTMI,
122 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 116 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
123}; 117};
124 118
125static struct mxc_usbh_platform_data __maybe_unused usbh1_pdata = { 119static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
126 .portsc = MXC_EHCI_MODE_SERIAL, 120 .portsc = MXC_EHCI_MODE_SERIAL,
127 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | 121 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
128 MXC_EHCI_IPPUE_DOWN, 122 MXC_EHCI_IPPUE_DOWN,
129}; 123};
130 124
131static struct fsl_usb2_platform_data otg_device_pdata = { 125static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
132 .operating_mode = FSL_USB2_DR_DEVICE, 126 .operating_mode = FSL_USB2_DR_DEVICE,
133 .phy_mode = FSL_USB2_PHY_UTMI, 127 .phy_mode = FSL_USB2_PHY_UTMI,
134 .workaround = FLS_USB2_WORKAROUND_ENGCM09152, 128 .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
@@ -158,7 +152,7 @@ static void __init mxc_board_init(void)
158 ARRAY_SIZE(eukrea_cpuimx35_pads)); 152 ARRAY_SIZE(eukrea_cpuimx35_pads));
159 153
160 imx35_add_fec(NULL); 154 imx35_add_fec(NULL);
161 platform_add_devices(devices, ARRAY_SIZE(devices)); 155 imx35_add_imx2_wdt(NULL);
162 156
163 imx35_add_imx_uart0(&uart_pdata); 157 imx35_add_imx_uart0(&uart_pdata);
164 imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info); 158 imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
@@ -168,11 +162,11 @@ static void __init mxc_board_init(void)
168 imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data); 162 imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
169 163
170 if (otg_mode_host) 164 if (otg_mode_host)
171 mxc_register_device(&mxc_otg_host, &otg_pdata); 165 imx35_add_mxc_ehci_otg(&otg_pdata);
172 else 166 else
173 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 167 imx35_add_fsl_usb2_udc(&otg_device_pdata);
174 168
175 mxc_register_device(&mxc_usbh1, &usbh1_pdata); 169 imx35_add_mxc_ehci_hs(&usbh1_pdata);
176 170
177#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD 171#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
178 eukrea_mbimxsd35_baseboard_init(); 172 eukrea_mbimxsd35_baseboard_init();
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
index 042cd5655e17..a5f3eb24e4d5 100644
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
@@ -41,9 +41,9 @@
41#include "devices-imx31.h" 41#include "devices-imx31.h"
42#include "devices.h" 42#include "devices.h"
43 43
44#define KZM_ARM11_IO_ADDRESS(x) ( \ 44#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
45 IMX_IO_ADDRESS(x, MX31_CS4) ?: \ 45 IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
46 IMX_IO_ADDRESS(x, MX31_CS5) ?: \ 46 IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
47 MX31_IO_ADDRESS(x)) 47 MX31_IO_ADDRESS(x))
48 48
49/* 49/*
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
index 0ad9e7821082..4e516b49a901 100644
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx31_3ds.c
@@ -22,8 +22,8 @@
22#include <linux/mfd/mc13783.h> 22#include <linux/mfd/mc13783.h>
23#include <linux/spi/spi.h> 23#include <linux/spi/spi.h>
24#include <linux/regulator/machine.h> 24#include <linux/regulator/machine.h>
25#include <linux/fsl_devices.h> 25#include <linux/usb/otg.h>
26#include <linux/input/matrix_keypad.h> 26#include <linux/usb/ulpi.h>
27 27
28#include <mach/hardware.h> 28#include <mach/hardware.h>
29#include <asm/mach-types.h> 29#include <asm/mach-types.h>
@@ -34,6 +34,7 @@
34#include <mach/common.h> 34#include <mach/common.h>
35#include <mach/iomux-mx3.h> 35#include <mach/iomux-mx3.h>
36#include <mach/3ds_debugboard.h> 36#include <mach/3ds_debugboard.h>
37#include <mach/ulpi.h>
37 38
38#include "devices-imx31.h" 39#include "devices-imx31.h"
39#include "devices.h" 40#include "devices.h"
@@ -84,6 +85,21 @@ static int mx31_3ds_pins[] = {
84 MX31_PIN_KEY_COL1_KEY_COL1, 85 MX31_PIN_KEY_COL1_KEY_COL1,
85 MX31_PIN_KEY_COL2_KEY_COL2, 86 MX31_PIN_KEY_COL2_KEY_COL2,
86 MX31_PIN_KEY_COL3_KEY_COL3, 87 MX31_PIN_KEY_COL3_KEY_COL3,
88 /* USB Host 2 */
89 IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
90 IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
91 IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
92 IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
93 IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
94 IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
95 IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
96 IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
97 IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
98 IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
99 IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
100 IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
101 /* USB Host2 reset */
102 IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
87}; 103};
88 104
89/* 105/*
@@ -102,7 +118,7 @@ static const uint32_t mx31_3ds_keymap[] = {
102 KEY(2, 3, KEY_F10), 118 KEY(2, 3, KEY_F10),
103}; 119};
104 120
105static struct matrix_keymap_data mx31_3ds_keymap_data = { 121static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
106 .keymap = mx31_3ds_keymap, 122 .keymap = mx31_3ds_keymap,
107 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap), 123 .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
108}; 124};
@@ -115,6 +131,13 @@ static struct regulator_init_data pwgtx_init = {
115 }, 131 },
116}; 132};
117 133
134static struct regulator_init_data gpo_init = {
135 .constraints = {
136 .boot_on = 1,
137 .always_on = 1,
138 }
139};
140
118static struct mc13783_regulator_init_data mx31_3ds_regulators[] = { 141static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
119 { 142 {
120 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */ 143 .id = MC13783_REGU_PWGT1SPI, /* Power Gate for ARM core. */
@@ -122,6 +145,13 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
122 }, { 145 }, {
123 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */ 146 .id = MC13783_REGU_PWGT2SPI, /* Power Gate for L2 Cache. */
124 .init_data = &pwgtx_init, 147 .init_data = &pwgtx_init,
148 }, {
149
150 .id = MC13783_REGU_GPO1, /* Turn on 1.8V */
151 .init_data = &gpo_init,
152 }, {
153 .id = MC13783_REGU_GPO3, /* Turn on 3.3V */
154 .init_data = &gpo_init,
125 }, 155 },
126}; 156};
127 157
@@ -129,7 +159,7 @@ static struct mc13783_regulator_init_data mx31_3ds_regulators[] = {
129static struct mc13783_platform_data mc13783_pdata __initdata = { 159static struct mc13783_platform_data mc13783_pdata __initdata = {
130 .regulators = mx31_3ds_regulators, 160 .regulators = mx31_3ds_regulators,
131 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators), 161 .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
132 .flags = MC13783_USE_REGULATOR, 162 .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
133}; 163};
134 164
135/* SPI */ 165/* SPI */
@@ -175,6 +205,7 @@ mx31_3ds_nand_board_info __initconst = {
175 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU) 205 PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
176 206
177#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR) 207#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
208#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
178 209
179static int mx31_3ds_usbotg_init(void) 210static int mx31_3ds_usbotg_init(void)
180{ 211{
@@ -214,11 +245,77 @@ usbotg_free_reset:
214 return err; 245 return err;
215} 246}
216 247
217static struct fsl_usb2_platform_data usbotg_pdata = { 248static int mx31_3ds_host2_init(struct platform_device *pdev)
249{
250 int err;
251
252 mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
253 mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
254 mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
255 mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
256 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
257 mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
258 mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
259 mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
260 mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
261 mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
262 mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
263 mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
264
265 err = gpio_request(USBH2_RST_B, "usbh2-reset");
266 if (err) {
267 pr_err("Failed to request the USB Host 2 reset gpio\n");
268 return err;
269 }
270
271 err = gpio_direction_output(USBH2_RST_B, 0);
272 if (err) {
273 pr_err("Failed to drive the USB Host 2 reset gpio\n");
274 goto usbotg_free_reset;
275 }
276
277 mdelay(1);
278 gpio_set_value(USBH2_RST_B, 1);
279 return 0;
280
281usbotg_free_reset:
282 gpio_free(USBH2_RST_B);
283 return err;
284}
285
286#if defined(CONFIG_USB_ULPI)
287static struct mxc_usbh_platform_data otg_pdata __initdata = {
288 .portsc = MXC_EHCI_MODE_ULPI,
289 .flags = MXC_EHCI_POWER_PINS_ENABLED,
290};
291
292static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
293 .init = mx31_3ds_host2_init,
294 .portsc = MXC_EHCI_MODE_ULPI,
295 .flags = MXC_EHCI_POWER_PINS_ENABLED,
296};
297#endif
298
299static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
218 .operating_mode = FSL_USB2_DR_DEVICE, 300 .operating_mode = FSL_USB2_DR_DEVICE,
219 .phy_mode = FSL_USB2_PHY_ULPI, 301 .phy_mode = FSL_USB2_PHY_ULPI,
220}; 302};
221 303
304static int otg_mode_host;
305
306static int __init mx31_3ds_otg_mode(char *options)
307{
308 if (!strcmp(options, "host"))
309 otg_mode_host = 1;
310 else if (!strcmp(options, "device"))
311 otg_mode_host = 0;
312 else
313 pr_info("otg_mode neither \"host\" nor \"device\". "
314 "Defaulting to device\n");
315 return 0;
316}
317__setup("otg_mode=", mx31_3ds_otg_mode);
318
222static const struct imxuart_platform_data uart_pdata __initconst = { 319static const struct imxuart_platform_data uart_pdata __initconst = {
223 .flags = IMXUART_HAVE_RTSCTS, 320 .flags = IMXUART_HAVE_RTSCTS,
224}; 321};
@@ -246,14 +343,27 @@ static void __init mxc_board_init(void)
246 spi_register_board_info(mx31_3ds_spi_devs, 343 spi_register_board_info(mx31_3ds_spi_devs,
247 ARRAY_SIZE(mx31_3ds_spi_devs)); 344 ARRAY_SIZE(mx31_3ds_spi_devs));
248 345
249 mxc_register_device(&imx_kpp_device, &mx31_3ds_keymap_data); 346 imx31_add_imx_keypad(&mx31_3ds_keymap_data);
250 347
251 mx31_3ds_usbotg_init(); 348 mx31_3ds_usbotg_init();
252 mxc_register_device(&mxc_otg_udc_device, &usbotg_pdata); 349#if defined(CONFIG_USB_ULPI)
350 if (otg_mode_host) {
351 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
352 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
353
354 imx31_add_mxc_ehci_otg(&otg_pdata);
355 }
356 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
357 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
358 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
359#endif
360 if (!otg_mode_host)
361 imx31_add_fsl_usb2_udc(&usbotg_pdata);
253 362
254 if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT)) 363 if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
255 printk(KERN_WARNING "Init of the debug board failed, all " 364 printk(KERN_WARNING "Init of the debug board failed, all "
256 "devices on the debug board are unusable.\n"); 365 "devices on the debug board are unusable.\n");
366 imx31_add_imx2_wdt(NULL);
257} 367}
258 368
259static void __init mx31_3ds_timer_init(void) 369static void __init mx31_3ds_timer_init(void)
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
index 42f47faa6fd6..2c595483f356 100644
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ b/arch/arm/mach-mx3/mach-mx31lilly.c
@@ -42,7 +42,6 @@
42#include <mach/common.h> 42#include <mach/common.h>
43#include <mach/iomux-mx3.h> 43#include <mach/iomux-mx3.h>
44#include <mach/board-mx31lilly.h> 44#include <mach/board-mx31lilly.h>
45#include <mach/mxc_ehci.h>
46#include <mach/ulpi.h> 45#include <mach/ulpi.h>
47 46
48#include "devices-imx31.h" 47#include "devices-imx31.h"
@@ -230,13 +229,13 @@ static struct mxc_usbh_platform_data usbotg_pdata = {
230 .flags = MXC_EHCI_POWER_PINS_ENABLED, 229 .flags = MXC_EHCI_POWER_PINS_ENABLED,
231}; 230};
232 231
233static struct mxc_usbh_platform_data usbh1_pdata = { 232static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
234 .init = usbh1_init, 233 .init = usbh1_init,
235 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, 234 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
236 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, 235 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
237}; 236};
238 237
239static struct mxc_usbh_platform_data usbh2_pdata = { 238static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
240 .init = usbh2_init, 239 .init = usbh2_init,
241 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 240 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
242 .flags = MXC_EHCI_POWER_PINS_ENABLED, 241 .flags = MXC_EHCI_POWER_PINS_ENABLED,
@@ -249,8 +248,8 @@ static void lilly1131_usb_init(void)
249 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 248 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
250 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 249 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
251 250
252 mxc_register_device(&mxc_usbh1, &usbh1_pdata); 251 imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
253 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 252 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
254} 253}
255 254
256#else 255#else
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
index b93895814cdf..9e64c66396e0 100644
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ b/arch/arm/mach-mx3/mach-mx31lite.c
@@ -40,7 +40,6 @@
40#include <mach/board-mx31lite.h> 40#include <mach/board-mx31lite.h>
41#include <mach/iomux-mx3.h> 41#include <mach/iomux-mx3.h>
42#include <mach/irqs.h> 42#include <mach/irqs.h>
43#include <mach/mxc_ehci.h>
44#include <mach/ulpi.h> 43#include <mach/ulpi.h>
45 44
46#include "devices-imx31.h" 45#include "devices-imx31.h"
@@ -171,7 +170,7 @@ static int usbh2_init(struct platform_device *pdev)
171 return 0; 170 return 0;
172} 171}
173 172
174static struct mxc_usbh_platform_data usbh2_pdata = { 173static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
175 .init = usbh2_init, 174 .init = usbh2_init,
176 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 175 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
177 .flags = MXC_EHCI_POWER_PINS_ENABLED, 176 .flags = MXC_EHCI_POWER_PINS_ENABLED,
@@ -258,7 +257,7 @@ static void __init mxc_board_init(void)
258 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 257 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
259 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 258 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
260 259
261 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 260 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
262#endif 261#endif
263 262
264 /* SMSC9117 IRQ pin */ 263 /* SMSC9117 IRQ pin */
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
index eb5f426df224..203d21a510aa 100644
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ b/arch/arm/mach-mx3/mach-mx31moboard.c
@@ -40,8 +40,6 @@
40#include <mach/hardware.h> 40#include <mach/hardware.h>
41#include <mach/iomux-mx3.h> 41#include <mach/iomux-mx3.h>
42#include <mach/ipu.h> 42#include <mach/ipu.h>
43#include <mach/mmc.h>
44#include <mach/mxc_ehci.h>
45#include <mach/mx3_camera.h> 43#include <mach/mx3_camera.h>
46#include <mach/spi.h> 44#include <mach/spi.h>
47#include <mach/ulpi.h> 45#include <mach/ulpi.h>
@@ -170,11 +168,11 @@ static const struct spi_imx_master moboard_spi1_pdata __initconst = {
170 168
171static struct regulator_consumer_supply sdhc_consumers[] = { 169static struct regulator_consumer_supply sdhc_consumers[] = {
172 { 170 {
173 .dev = &mxcsdhc_device0.dev, 171 .dev_name = "mxc-mmc.0",
174 .supply = "sdhc0_vcc", 172 .supply = "sdhc0_vcc",
175 }, 173 },
176 { 174 {
177 .dev = &mxcsdhc_device1.dev, 175 .dev_name = "mxc-mmc.1",
178 .supply = "sdhc1_vcc", 176 .supply = "sdhc1_vcc",
179 }, 177 },
180}; 178};
@@ -345,7 +343,7 @@ static void moboard_sdhc1_exit(struct device *dev, void *data)
345 gpio_free(SDHC1_CD); 343 gpio_free(SDHC1_CD);
346} 344}
347 345
348static struct imxmmc_platform_data sdhc1_pdata = { 346static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
349 .get_ro = moboard_sdhc1_get_ro, 347 .get_ro = moboard_sdhc1_get_ro,
350 .init = moboard_sdhc1_init, 348 .init = moboard_sdhc1_init,
351 .exit = moboard_sdhc1_exit, 349 .exit = moboard_sdhc1_exit,
@@ -404,17 +402,23 @@ static void usb_xcvr_reset(void)
404 402
405#if defined(CONFIG_USB_ULPI) 403#if defined(CONFIG_USB_ULPI)
406 404
407static struct mxc_usbh_platform_data usbh2_pdata = { 405static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
408 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 406 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
409 .flags = MXC_EHCI_POWER_PINS_ENABLED, 407 .flags = MXC_EHCI_POWER_PINS_ENABLED,
410}; 408};
411 409
412static int __init moboard_usbh2_init(void) 410static int __init moboard_usbh2_init(void)
413{ 411{
412 struct platform_device *pdev;
413
414 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 414 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
415 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 415 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
416 416
417 return mxc_register_device(&mxc_usbh2, &usbh2_pdata); 417 pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
418 if (IS_ERR(pdev))
419 return PTR_ERR(pdev);
420
421 return 0;
418} 422}
419#else 423#else
420static inline int moboard_usbh2_init(void) { return 0; } 424static inline int moboard_usbh2_init(void) { return 0; }
@@ -520,7 +524,7 @@ static void __init mxc_board_init(void)
520 spi_register_board_info(moboard_spi_board_info, 524 spi_register_board_info(moboard_spi_board_info,
521 ARRAY_SIZE(moboard_spi_board_info)); 525 ARRAY_SIZE(moboard_spi_board_info));
522 526
523 mxc_register_device(&mxcsdhc_device0, &sdhc1_pdata); 527 imx31_add_mxc_mmc(0, &sdhc1_pdata);
524 528
525 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 529 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
526 if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE)) 530 if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
index b66a75aa2e88..b1963f257c20 100644
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ b/arch/arm/mach-mx3/mach-mx35_3ds.c
@@ -26,7 +26,7 @@
26#include <linux/platform_device.h> 26#include <linux/platform_device.h>
27#include <linux/memory.h> 27#include <linux/memory.h>
28#include <linux/gpio.h> 28#include <linux/gpio.h>
29#include <linux/fsl_devices.h> 29#include <linux/usb/otg.h>
30 30
31#include <linux/mtd/physmap.h> 31#include <linux/mtd/physmap.h>
32 32
@@ -40,7 +40,6 @@
40#include <mach/iomux-mx35.h> 40#include <mach/iomux-mx35.h>
41#include <mach/irqs.h> 41#include <mach/irqs.h>
42#include <mach/3ds_debugboard.h> 42#include <mach/3ds_debugboard.h>
43#include <mach/mxc_ehci.h>
44 43
45#include "devices-imx35.h" 44#include "devices-imx35.h"
46#include "devices.h" 45#include "devices.h"
@@ -81,7 +80,7 @@ static struct platform_device *devices[] __initdata = {
81 &mx35pdk_flash, 80 &mx35pdk_flash,
82}; 81};
83 82
84static struct pad_desc mx35pdk_pads[] = { 83static iomux_v3_cfg_t mx35pdk_pads[] = {
85 /* UART1 */ 84 /* UART1 */
86 MX35_PAD_CTS1__UART1_CTS, 85 MX35_PAD_CTS1__UART1_CTS,
87 MX35_PAD_RTS1__UART1_RTS, 86 MX35_PAD_RTS1__UART1_RTS,
@@ -122,18 +121,38 @@ static struct pad_desc mx35pdk_pads[] = {
122}; 121};
123 122
124/* OTG config */ 123/* OTG config */
125static struct fsl_usb2_platform_data usb_otg_pdata = { 124static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
126 .operating_mode = FSL_USB2_DR_DEVICE, 125 .operating_mode = FSL_USB2_DR_DEVICE,
127 .phy_mode = FSL_USB2_PHY_UTMI_WIDE, 126 .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
128}; 127};
129 128
129static struct mxc_usbh_platform_data otg_pdata __initdata = {
130 .portsc = MXC_EHCI_MODE_UTMI,
131 .flags = MXC_EHCI_INTERNAL_PHY,
132};
133
130/* USB HOST config */ 134/* USB HOST config */
131static struct mxc_usbh_platform_data usb_host_pdata = { 135static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
132 .portsc = MXC_EHCI_MODE_SERIAL, 136 .portsc = MXC_EHCI_MODE_SERIAL,
133 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | 137 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI |
134 MXC_EHCI_INTERNAL_PHY, 138 MXC_EHCI_INTERNAL_PHY,
135}; 139};
136 140
141static int otg_mode_host;
142
143static int __init mx35_3ds_otg_mode(char *options)
144{
145 if (!strcmp(options, "host"))
146 otg_mode_host = 1;
147 else if (!strcmp(options, "device"))
148 otg_mode_host = 0;
149 else
150 pr_info("otg_mode neither \"host\" nor \"device\". "
151 "Defaulting to device\n");
152 return 0;
153}
154__setup("otg_mode=", mx35_3ds_otg_mode);
155
137/* 156/*
138 * Board specific initialization. 157 * Board specific initialization.
139 */ 158 */
@@ -142,16 +161,21 @@ static void __init mxc_board_init(void)
142 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads)); 161 mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
143 162
144 imx35_add_fec(NULL); 163 imx35_add_fec(NULL);
164 imx35_add_imx2_wdt(NULL);
145 platform_add_devices(devices, ARRAY_SIZE(devices)); 165 platform_add_devices(devices, ARRAY_SIZE(devices));
146 166
147 imx35_add_imx_uart0(&uart_pdata); 167 imx35_add_imx_uart0(&uart_pdata);
148 168
149 mxc_register_device(&mxc_otg_udc_device, &usb_otg_pdata); 169 if (otg_mode_host)
170 imx35_add_mxc_ehci_otg(&otg_pdata);
171
172 imx35_add_mxc_ehci_hs(&usb_host_pdata);
150 173
151 mxc_register_device(&mxc_usbh1, &usb_host_pdata); 174 if (!otg_mode_host)
175 imx35_add_fsl_usb2_udc(&usb_otg_pdata);
152 176
153 imx35_add_mxc_nand(&mx35pdk_nand_board_info); 177 imx35_add_mxc_nand(&mx35pdk_nand_board_info);
154 imx35_add_esdhc(0, NULL); 178 imx35_add_sdhci_esdhc_imx(0, NULL);
155 179
156 if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT)) 180 if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
157 pr_warn("Init of the debugboard failed, all " 181 pr_warn("Init of the debugboard failed, all "
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
index 2ff3f661a48e..b752f6bc20a2 100644
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ b/arch/arm/mach-mx3/mach-pcm037.c
@@ -27,7 +27,6 @@
27#include <linux/delay.h> 27#include <linux/delay.h>
28#include <linux/spi/spi.h> 28#include <linux/spi/spi.h>
29#include <linux/irq.h> 29#include <linux/irq.h>
30#include <linux/fsl_devices.h>
31#include <linux/can/platform/sja1000.h> 30#include <linux/can/platform/sja1000.h>
32#include <linux/usb/otg.h> 31#include <linux/usb/otg.h>
33#include <linux/usb/ulpi.h> 32#include <linux/usb/ulpi.h>
@@ -43,10 +42,8 @@
43#include <mach/hardware.h> 42#include <mach/hardware.h>
44#include <mach/iomux-mx3.h> 43#include <mach/iomux-mx3.h>
45#include <mach/ipu.h> 44#include <mach/ipu.h>
46#include <mach/mmc.h>
47#include <mach/mx3_camera.h> 45#include <mach/mx3_camera.h>
48#include <mach/mx3fb.h> 46#include <mach/mx3fb.h>
49#include <mach/mxc_ehci.h>
50#include <mach/ulpi.h> 47#include <mach/ulpi.h>
51 48
52#include "devices-imx31.h" 49#include "devices-imx31.h"
@@ -399,7 +396,7 @@ static void pcm970_sdhc1_exit(struct device *dev, void *data)
399 gpio_free(SDHC1_GPIO_WP); 396 gpio_free(SDHC1_GPIO_WP);
400} 397}
401 398
402static struct imxmmc_platform_data sdhc_pdata = { 399static const struct imxmmc_platform_data sdhc_pdata __initconst = {
403#ifdef PCM970_SDHC_RW_SWITCH 400#ifdef PCM970_SDHC_RW_SWITCH
404 .get_ro = pcm970_sdhc1_get_ro, 401 .get_ro = pcm970_sdhc1_get_ro,
405#endif 402#endif
@@ -441,7 +438,6 @@ static int __init pcm037_camera_alloc_dma(const size_t buf_size)
441static struct platform_device *devices[] __initdata = { 438static struct platform_device *devices[] __initdata = {
442 &pcm037_flash, 439 &pcm037_flash,
443 &pcm037_sram_device, 440 &pcm037_sram_device,
444 &imx_wdt_device0,
445 &pcm037_mt9t031, 441 &pcm037_mt9t031,
446 &pcm037_mt9v022, 442 &pcm037_mt9v022,
447}; 443};
@@ -538,18 +534,18 @@ static struct platform_device pcm970_sja1000 = {
538}; 534};
539 535
540#if defined(CONFIG_USB_ULPI) 536#if defined(CONFIG_USB_ULPI)
541static struct mxc_usbh_platform_data otg_pdata = { 537static struct mxc_usbh_platform_data otg_pdata __initdata = {
542 .portsc = MXC_EHCI_MODE_ULPI, 538 .portsc = MXC_EHCI_MODE_ULPI,
543 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 539 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
544}; 540};
545 541
546static struct mxc_usbh_platform_data usbh2_pdata = { 542static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
547 .portsc = MXC_EHCI_MODE_ULPI, 543 .portsc = MXC_EHCI_MODE_ULPI,
548 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 544 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
549}; 545};
550#endif 546#endif
551 547
552static struct fsl_usb2_platform_data otg_device_pdata = { 548static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
553 .operating_mode = FSL_USB2_DR_DEVICE, 549 .operating_mode = FSL_USB2_DR_DEVICE,
554 .phy_mode = FSL_USB2_PHY_ULPI, 550 .phy_mode = FSL_USB2_PHY_ULPI,
555}; 551};
@@ -607,12 +603,13 @@ static void __init mxc_board_init(void)
607 603
608 platform_add_devices(devices, ARRAY_SIZE(devices)); 604 platform_add_devices(devices, ARRAY_SIZE(devices));
609 605
606 imx31_add_imx2_wdt(NULL);
610 imx31_add_imx_uart0(&uart_pdata); 607 imx31_add_imx_uart0(&uart_pdata);
611 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */ 608 /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
612 imx31_add_imx_uart1(&uart_pdata); 609 imx31_add_imx_uart1(&uart_pdata);
613 imx31_add_imx_uart2(&uart_pdata); 610 imx31_add_imx_uart2(&uart_pdata);
614 611
615 mxc_register_device(&mxc_w1_master_device, NULL); 612 imx31_add_mxc_w1(NULL);
616 613
617 /* LAN9217 IRQ pin */ 614 /* LAN9217 IRQ pin */
618 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq"); 615 ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
@@ -632,7 +629,7 @@ static void __init mxc_board_init(void)
632 imx31_add_imx_i2c2(&pcm037_i2c2_data); 629 imx31_add_imx_i2c2(&pcm037_i2c2_data);
633 630
634 imx31_add_mxc_nand(&pcm037_nand_board_info); 631 imx31_add_mxc_nand(&pcm037_nand_board_info);
635 mxc_register_device(&mxcsdhc_device0, &sdhc_pdata); 632 imx31_add_mxc_mmc(0, &sdhc_pdata);
636 mxc_register_device(&mx3_ipu, &mx3_ipu_data); 633 mxc_register_device(&mx3_ipu, &mx3_ipu_data);
637 mxc_register_device(&mx3_fb, &mx3fb_pdata); 634 mxc_register_device(&mx3_fb, &mx3fb_pdata);
638 635
@@ -654,16 +651,16 @@ static void __init mxc_board_init(void)
654 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 651 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
655 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 652 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
656 653
657 mxc_register_device(&mxc_otg_host, &otg_pdata); 654 imx31_add_mxc_ehci_otg(&otg_pdata);
658 } 655 }
659 656
660 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 657 usbh2_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
661 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 658 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
662 659
663 mxc_register_device(&mxc_usbh2, &usbh2_pdata); 660 imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
664#endif 661#endif
665 if (!otg_mode_host) 662 if (!otg_mode_host)
666 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 663 imx31_add_fsl_usb2_udc(&otg_device_pdata);
667 664
668} 665}
669 666
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
index 4e1de87995d4..bcf83fc7e701 100644
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ b/arch/arm/mach-mx3/mach-pcm043.c
@@ -27,7 +27,6 @@
27#include <linux/i2c/at24.h> 27#include <linux/i2c/at24.h>
28#include <linux/usb/otg.h> 28#include <linux/usb/otg.h>
29#include <linux/usb/ulpi.h> 29#include <linux/usb/ulpi.h>
30#include <linux/fsl_devices.h>
31 30
32#include <asm/mach-types.h> 31#include <asm/mach-types.h>
33#include <asm/mach/arch.h> 32#include <asm/mach/arch.h>
@@ -39,7 +38,6 @@
39#include <mach/iomux-mx35.h> 38#include <mach/iomux-mx35.h>
40#include <mach/ipu.h> 39#include <mach/ipu.h>
41#include <mach/mx3fb.h> 40#include <mach/mx3fb.h>
42#include <mach/mxc_ehci.h>
43#include <mach/ulpi.h> 41#include <mach/ulpi.h>
44#include <mach/audmux.h> 42#include <mach/audmux.h>
45 43
@@ -140,10 +138,9 @@ static struct i2c_board_info pcm043_i2c_devices[] = {
140 138
141static struct platform_device *devices[] __initdata = { 139static struct platform_device *devices[] __initdata = {
142 &pcm043_flash, 140 &pcm043_flash,
143 &imx_wdt_device0,
144}; 141};
145 142
146static struct pad_desc pcm043_pads[] = { 143static iomux_v3_cfg_t pcm043_pads[] = {
147 /* UART1 */ 144 /* UART1 */
148 MX35_PAD_CTS1__UART1_CTS, 145 MX35_PAD_CTS1__UART1_CTS,
149 MX35_PAD_RTS1__UART1_RTS, 146 MX35_PAD_RTS1__UART1_RTS,
@@ -230,8 +227,8 @@ static struct pad_desc pcm043_pads[] = {
230 227
231static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97) 228static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
232{ 229{
233 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; 230 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
234 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; 231 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
235 int ret; 232 int ret;
236 233
237 ret = gpio_request(AC97_GPIO_TXFS, "SSI"); 234 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
@@ -240,7 +237,7 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
240 return; 237 return;
241 } 238 }
242 239
243 mxc_iomux_v3_setup_pad(&txfs_gpio); 240 mxc_iomux_v3_setup_pad(txfs_gpio);
244 241
245 /* warm reset */ 242 /* warm reset */
246 gpio_direction_output(AC97_GPIO_TXFS, 1); 243 gpio_direction_output(AC97_GPIO_TXFS, 1);
@@ -248,16 +245,16 @@ static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
248 gpio_set_value(AC97_GPIO_TXFS, 0); 245 gpio_set_value(AC97_GPIO_TXFS, 0);
249 246
250 gpio_free(AC97_GPIO_TXFS); 247 gpio_free(AC97_GPIO_TXFS);
251 mxc_iomux_v3_setup_pad(&txfs); 248 mxc_iomux_v3_setup_pad(txfs);
252} 249}
253 250
254static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97) 251static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
255{ 252{
256 struct pad_desc txfs_gpio = MX35_PAD_STXFS4__GPIO2_31; 253 iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
257 struct pad_desc txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS; 254 iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
258 struct pad_desc txd_gpio = MX35_PAD_STXD4__GPIO2_28; 255 iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
259 struct pad_desc txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD; 256 iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
260 struct pad_desc reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0; 257 iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
261 int ret; 258 int ret;
262 259
263 ret = gpio_request(AC97_GPIO_TXFS, "SSI"); 260 ret = gpio_request(AC97_GPIO_TXFS, "SSI");
@@ -272,9 +269,9 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
272 if (ret) 269 if (ret)
273 goto err3; 270 goto err3;
274 271
275 mxc_iomux_v3_setup_pad(&txfs_gpio); 272 mxc_iomux_v3_setup_pad(txfs_gpio);
276 mxc_iomux_v3_setup_pad(&txd_gpio); 273 mxc_iomux_v3_setup_pad(txd_gpio);
277 mxc_iomux_v3_setup_pad(&reset_gpio); 274 mxc_iomux_v3_setup_pad(reset_gpio);
278 275
279 gpio_direction_output(AC97_GPIO_TXFS, 0); 276 gpio_direction_output(AC97_GPIO_TXFS, 0);
280 gpio_direction_output(AC97_GPIO_TXD, 0); 277 gpio_direction_output(AC97_GPIO_TXD, 0);
@@ -284,8 +281,8 @@ static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
284 udelay(10); 281 udelay(10);
285 gpio_direction_output(AC97_GPIO_RESET, 1); 282 gpio_direction_output(AC97_GPIO_RESET, 1);
286 283
287 mxc_iomux_v3_setup_pad(&txd); 284 mxc_iomux_v3_setup_pad(txd);
288 mxc_iomux_v3_setup_pad(&txfs); 285 mxc_iomux_v3_setup_pad(txfs);
289 286
290 gpio_free(AC97_GPIO_RESET); 287 gpio_free(AC97_GPIO_RESET);
291err3: 288err3:
@@ -311,19 +308,19 @@ pcm037_nand_board_info __initconst = {
311}; 308};
312 309
313#if defined(CONFIG_USB_ULPI) 310#if defined(CONFIG_USB_ULPI)
314static struct mxc_usbh_platform_data otg_pdata = { 311static struct mxc_usbh_platform_data otg_pdata __initdata = {
315 .portsc = MXC_EHCI_MODE_UTMI, 312 .portsc = MXC_EHCI_MODE_UTMI,
316 .flags = MXC_EHCI_INTERFACE_DIFF_UNI, 313 .flags = MXC_EHCI_INTERFACE_DIFF_UNI,
317}; 314};
318 315
319static struct mxc_usbh_platform_data usbh1_pdata = { 316static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
320 .portsc = MXC_EHCI_MODE_SERIAL, 317 .portsc = MXC_EHCI_MODE_SERIAL,
321 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY | 318 .flags = MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY |
322 MXC_EHCI_IPPUE_DOWN, 319 MXC_EHCI_IPPUE_DOWN,
323}; 320};
324#endif 321#endif
325 322
326static struct fsl_usb2_platform_data otg_device_pdata = { 323static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
327 .operating_mode = FSL_USB2_DR_DEVICE, 324 .operating_mode = FSL_USB2_DR_DEVICE,
328 .phy_mode = FSL_USB2_PHY_UTMI, 325 .phy_mode = FSL_USB2_PHY_UTMI,
329}; 326};
@@ -364,6 +361,7 @@ static void __init mxc_board_init(void)
364 361
365 imx35_add_fec(NULL); 362 imx35_add_fec(NULL);
366 platform_add_devices(devices, ARRAY_SIZE(devices)); 363 platform_add_devices(devices, ARRAY_SIZE(devices));
364 imx35_add_imx2_wdt(NULL);
367 365
368 imx35_add_imx_uart0(&uart_pdata); 366 imx35_add_imx_uart0(&uart_pdata);
369 imx35_add_mxc_nand(&pcm037_nand_board_info); 367 imx35_add_mxc_nand(&pcm037_nand_board_info);
@@ -386,16 +384,16 @@ static void __init mxc_board_init(void)
386 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 384 otg_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
387 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 385 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
388 386
389 mxc_register_device(&mxc_otg_host, &otg_pdata); 387 imx35_add_mxc_ehci_otg(&otg_pdata);
390 } 388 }
391 389
392 mxc_register_device(&mxc_usbh1, &usbh1_pdata); 390 imx35_add_mxc_ehci_hs(&usbh1_pdata);
393#endif 391#endif
394 if (!otg_mode_host) 392 if (!otg_mode_host)
395 mxc_register_device(&mxc_otg_udc_device, &otg_device_pdata); 393 imx35_add_fsl_usb2_udc(&otg_device_pdata);
396 394
397 imx35_add_flexcan1(NULL); 395 imx35_add_flexcan1(NULL);
398 imx35_add_esdhc(0, NULL); 396 imx35_add_sdhci_esdhc_imx(0, NULL);
399} 397}
400 398
401static void __init pcm043_timer_init(void) 399static void __init pcm043_timer_init(void)
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
index b4ffc531a82c..47118f760244 100644
--- a/arch/arm/mach-mx3/mm.c
+++ b/arch/arm/mach-mx3/mm.c
@@ -36,40 +36,16 @@
36 * @ingroup Memory 36 * @ingroup Memory
37 */ 37 */
38 38
39/*! 39#ifdef CONFIG_SOC_IMX31
40 * This table defines static virtual address mappings for I/O regions. 40static struct map_desc mx31_io_desc[] __initdata = {
41 * These are the mappings common across all MX3 boards. 41 imx_map_entry(MX31, X_MEMC, MT_DEVICE),
42 */ 42 imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
43static struct map_desc mxc_io_desc[] __initdata = { 43 imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
44 { 44 imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
45 .virtual = X_MEMC_BASE_ADDR_VIRT, 45 imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
46 .pfn = __phys_to_pfn(X_MEMC_BASE_ADDR),
47 .length = X_MEMC_SIZE,
48 .type = MT_DEVICE
49 }, {
50 .virtual = AVIC_BASE_ADDR_VIRT,
51 .pfn = __phys_to_pfn(AVIC_BASE_ADDR),
52 .length = AVIC_SIZE,
53 .type = MT_DEVICE_NONSHARED
54 }, {
55 .virtual = AIPS1_BASE_ADDR_VIRT,
56 .pfn = __phys_to_pfn(AIPS1_BASE_ADDR),
57 .length = AIPS1_SIZE,
58 .type = MT_DEVICE_NONSHARED
59 }, {
60 .virtual = AIPS2_BASE_ADDR_VIRT,
61 .pfn = __phys_to_pfn(AIPS2_BASE_ADDR),
62 .length = AIPS2_SIZE,
63 .type = MT_DEVICE_NONSHARED
64 }, {
65 .virtual = SPBA0_BASE_ADDR_VIRT,
66 .pfn = __phys_to_pfn(SPBA0_BASE_ADDR),
67 .length = SPBA0_SIZE,
68 .type = MT_DEVICE_NONSHARED
69 },
70}; 46};
71 47
72/*! 48/*
73 * This function initializes the memory map. It is called during the 49 * This function initializes the memory map. It is called during the
74 * system startup to create static physical to virtual memory mappings 50 * system startup to create static physical to virtual memory mappings
75 * for the IO modules. 51 * for the IO modules.
@@ -77,34 +53,44 @@ static struct map_desc mxc_io_desc[] __initdata = {
77void __init mx31_map_io(void) 53void __init mx31_map_io(void)
78{ 54{
79 mxc_set_cpu_type(MXC_CPU_MX31); 55 mxc_set_cpu_type(MXC_CPU_MX31);
80 mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR)); 56 mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
81 57
82 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 58 iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
83} 59}
84 60
85#ifdef CONFIG_ARCH_MX35 61int imx31_register_gpios(void);
86void __init mx35_map_io(void) 62void __init mx31_init_irq(void)
87{ 63{
88 mxc_set_cpu_type(MXC_CPU_MX35); 64 mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
89 mxc_iomux_v3_init(IO_ADDRESS(IOMUXC_BASE_ADDR)); 65 imx31_register_gpios();
90 mxc_arch_reset_init(IO_ADDRESS(WDOG_BASE_ADDR));
91
92 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc));
93} 66}
94#endif 67#endif /* ifdef CONFIG_SOC_IMX31 */
95 68
96int imx3x_register_gpios(void); 69#ifdef CONFIG_SOC_IMX35
70static struct map_desc mx35_io_desc[] __initdata = {
71 imx_map_entry(MX35, X_MEMC, MT_DEVICE),
72 imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
73 imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
74 imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
75 imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
76};
97 77
98void __init mx31_init_irq(void) 78void __init mx35_map_io(void)
99{ 79{
100 mxc_init_irq(IO_ADDRESS(AVIC_BASE_ADDR)); 80 mxc_set_cpu_type(MXC_CPU_MX35);
101 imx3x_register_gpios(); 81 mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
82 mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
83
84 iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
102} 85}
103 86
87int imx35_register_gpios(void);
104void __init mx35_init_irq(void) 88void __init mx35_init_irq(void)
105{ 89{
106 mx31_init_irq(); 90 mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
91 imx35_register_gpios();
107} 92}
93#endif /* ifdef CONFIG_SOC_IMX35 */
108 94
109#ifdef CONFIG_CACHE_L2X0 95#ifdef CONFIG_CACHE_L2X0
110static int mxc_init_l2x0(void) 96static int mxc_init_l2x0(void)
@@ -129,7 +115,7 @@ static int mxc_init_l2x0(void)
129 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n"); 115 pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
130 } 116 }
131 117
132 l2x0_base = ioremap(L2CC_BASE_ADDR, 4096); 118 l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
133 if (IS_ERR(l2x0_base)) { 119 if (IS_ERR(l2x0_base)) {
134 printk(KERN_ERR "remapping L2 cache area failed with %ld\n", 120 printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
135 PTR_ERR(l2x0_base)); 121 PTR_ERR(l2x0_base));
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
index 827fd3c80201..8f1a38ebf5c8 100644
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ b/arch/arm/mach-mx3/mx31lilly-db.c
@@ -34,7 +34,6 @@
34#include <mach/common.h> 34#include <mach/common.h>
35#include <mach/iomux-mx3.h> 35#include <mach/iomux-mx3.h>
36#include <mach/board-mx31lilly.h> 36#include <mach/board-mx31lilly.h>
37#include <mach/mmc.h>
38#include <mach/mx3fb.h> 37#include <mach/mx3fb.h>
39#include <mach/ipu.h> 38#include <mach/ipu.h>
40 39
@@ -158,7 +157,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
158 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data); 157 free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
159} 158}
160 159
161static struct imxmmc_platform_data mmc_pdata = { 160static const struct imxmmc_platform_data mmc_pdata __initconst = {
162 .get_ro = mxc_mmc1_get_ro, 161 .get_ro = mxc_mmc1_get_ro,
163 .init = mxc_mmc1_init, 162 .init = mxc_mmc1_init,
164 .exit = mxc_mmc1_exit, 163 .exit = mxc_mmc1_exit,
@@ -216,7 +215,7 @@ void __init mx31lilly_db_init(void)
216 imx31_add_imx_uart0(&uart_pdata); 215 imx31_add_imx_uart0(&uart_pdata);
217 imx31_add_imx_uart1(&uart_pdata); 216 imx31_add_imx_uart1(&uart_pdata);
218 imx31_add_imx_uart2(&uart_pdata); 217 imx31_add_imx_uart2(&uart_pdata);
219 mxc_register_device(&mxcsdhc_device0, &mmc_pdata); 218 imx31_add_mxc_mmc(0, &mmc_pdata);
220 mx31lilly_init_fb(); 219 mx31lilly_init_fb();
221} 220}
222 221
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
index 7b0e74e275ba..3124ea837ac7 100644
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ b/arch/arm/mach-mx3/mx31lite-db.c
@@ -35,7 +35,6 @@
35#include <mach/common.h> 35#include <mach/common.h>
36#include <mach/iomux-mx3.h> 36#include <mach/iomux-mx3.h>
37#include <mach/board-mx31lite.h> 37#include <mach/board-mx31lite.h>
38#include <mach/mmc.h>
39 38
40#include "devices-imx31.h" 39#include "devices-imx31.h"
41#include "devices.h" 40#include "devices.h"
@@ -142,7 +141,7 @@ static void mxc_mmc1_exit(struct device *dev, void *data)
142 free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data); 141 free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
143} 142}
144 143
145static struct imxmmc_platform_data mmc_pdata = { 144static const struct imxmmc_platform_data mmc_pdata __initconst = {
146 .get_ro = mxc_mmc1_get_ro, 145 .get_ro = mxc_mmc1_get_ro,
147 .init = mxc_mmc1_init, 146 .init = mxc_mmc1_init,
148 .exit = mxc_mmc1_exit, 147 .exit = mxc_mmc1_exit,
@@ -197,10 +196,9 @@ void __init mx31lite_db_init(void)
197 ARRAY_SIZE(litekit_db_board_pins), 196 ARRAY_SIZE(litekit_db_board_pins),
198 "development board pins"); 197 "development board pins");
199 imx31_add_imx_uart0(&uart_pdata); 198 imx31_add_imx_uart0(&uart_pdata);
200 mxc_register_device(&mxcsdhc_device0, &mmc_pdata); 199 imx31_add_mxc_mmc(0, &mmc_pdata);
201 imx31_add_spi_imx0(&spi0_pdata); 200 imx31_add_spi_imx0(&spi0_pdata);
202 platform_device_register(&litekit_led_device); 201 platform_device_register(&litekit_led_device);
203 mxc_register_device(&imx_wdt_device0, NULL); 202 imx31_add_imx2_wdt(NULL);
204 mxc_register_device(&imx_rtc_device0, NULL); 203 mxc_register_device(&imx_rtc_device0, NULL);
205} 204}
206
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
index fc395a7a8599..94a0b9e4b7f3 100644
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ b/arch/arm/mach-mx3/mx31moboard-devboard.c
@@ -18,15 +18,12 @@
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/slab.h> 19#include <linux/slab.h>
20#include <linux/types.h> 20#include <linux/types.h>
21#include <linux/fsl_devices.h>
22 21
23#include <linux/usb/otg.h> 22#include <linux/usb/otg.h>
24 23
25#include <mach/common.h> 24#include <mach/common.h>
26#include <mach/iomux-mx3.h> 25#include <mach/iomux-mx3.h>
27#include <mach/hardware.h> 26#include <mach/hardware.h>
28#include <mach/mmc.h>
29#include <mach/mxc_ehci.h>
30#include <mach/ulpi.h> 27#include <mach/ulpi.h>
31 28
32#include "devices-imx31.h" 29#include "devices-imx31.h"
@@ -103,7 +100,7 @@ static void devboard_sdhc2_exit(struct device *dev, void *data)
103 gpio_free(SDHC2_CD); 100 gpio_free(SDHC2_CD);
104} 101}
105 102
106static struct imxmmc_platform_data sdhc2_pdata = { 103static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
107 .get_ro = devboard_sdhc2_get_ro, 104 .get_ro = devboard_sdhc2_get_ro,
108 .init = devboard_sdhc2_init, 105 .init = devboard_sdhc2_init,
109 .exit = devboard_sdhc2_exit, 106 .exit = devboard_sdhc2_exit,
@@ -187,7 +184,7 @@ static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
187 return 0; 184 return 0;
188} 185}
189 186
190static struct mxc_usbh_platform_data usbh1_pdata = { 187static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
191 .init = devboard_usbh1_hw_init, 188 .init = devboard_usbh1_hw_init,
192 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, 189 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
193 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, 190 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
@@ -196,6 +193,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
196static int __init devboard_usbh1_init(void) 193static int __init devboard_usbh1_init(void)
197{ 194{
198 struct otg_transceiver *otg; 195 struct otg_transceiver *otg;
196 struct platform_device *pdev;
199 197
200 otg = kzalloc(sizeof(*otg), GFP_KERNEL); 198 otg = kzalloc(sizeof(*otg), GFP_KERNEL);
201 if (!otg) 199 if (!otg)
@@ -207,11 +205,15 @@ static int __init devboard_usbh1_init(void)
207 205
208 usbh1_pdata.otg = otg; 206 usbh1_pdata.otg = otg;
209 207
210 return mxc_register_device(&mxc_usbh1, &usbh1_pdata); 208 pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
209 if (IS_ERR(pdev))
210 return PTR_ERR(pdev);
211
212 return 0;
211} 213}
212 214
213 215
214static struct fsl_usb2_platform_data usb_pdata = { 216static const struct fsl_usb2_platform_data usb_pdata __initconst = {
215 .operating_mode = FSL_USB2_DR_DEVICE, 217 .operating_mode = FSL_USB2_DR_DEVICE,
216 .phy_mode = FSL_USB2_PHY_ULPI, 218 .phy_mode = FSL_USB2_PHY_ULPI,
217}; 219};
@@ -228,11 +230,11 @@ void __init mx31moboard_devboard_init(void)
228 230
229 imx31_add_imx_uart1(&uart_pdata); 231 imx31_add_imx_uart1(&uart_pdata);
230 232
231 mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); 233 imx31_add_mxc_mmc(1, &sdhc2_pdata);
232 234
233 devboard_init_sel_gpios(); 235 devboard_init_sel_gpios();
234 236
235 mxc_register_device(&mxc_otg_udc_device, &usb_pdata); 237 imx31_add_fsl_usb2_udc(&usb_pdata);
236 238
237 devboard_usbh1_init(); 239 devboard_usbh1_init();
238} 240}
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
index 18069cb7d068..f449a97ae1a2 100644
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-marxbot.c
@@ -21,7 +21,6 @@
21#include <linux/slab.h> 21#include <linux/slab.h>
22#include <linux/platform_device.h> 22#include <linux/platform_device.h>
23#include <linux/types.h> 23#include <linux/types.h>
24#include <linux/fsl_devices.h>
25 24
26#include <linux/usb/otg.h> 25#include <linux/usb/otg.h>
27 26
@@ -29,12 +28,11 @@
29#include <mach/hardware.h> 28#include <mach/hardware.h>
30#include <mach/imx-uart.h> 29#include <mach/imx-uart.h>
31#include <mach/iomux-mx3.h> 30#include <mach/iomux-mx3.h>
32#include <mach/mmc.h>
33#include <mach/mxc_ehci.h>
34#include <mach/ulpi.h> 31#include <mach/ulpi.h>
35 32
36#include <media/soc_camera.h> 33#include <media/soc_camera.h>
37 34
35#include "devices-imx31.h"
38#include "devices.h" 36#include "devices.h"
39 37
40static unsigned int marxbot_pins[] = { 38static unsigned int marxbot_pins[] = {
@@ -116,7 +114,7 @@ static void marxbot_sdhc2_exit(struct device *dev, void *data)
116 gpio_free(SDHC2_CD); 114 gpio_free(SDHC2_CD);
117} 115}
118 116
119static struct imxmmc_platform_data sdhc2_pdata = { 117static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
120 .get_ro = marxbot_sdhc2_get_ro, 118 .get_ro = marxbot_sdhc2_get_ro,
121 .init = marxbot_sdhc2_init, 119 .init = marxbot_sdhc2_init,
122 .exit = marxbot_sdhc2_exit, 120 .exit = marxbot_sdhc2_exit,
@@ -302,7 +300,7 @@ static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
302 return 0; 300 return 0;
303} 301}
304 302
305static struct mxc_usbh_platform_data usbh1_pdata = { 303static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
306 .init = marxbot_usbh1_hw_init, 304 .init = marxbot_usbh1_hw_init,
307 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL, 305 .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
308 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI, 306 .flags = MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_INTERFACE_SINGLE_UNI,
@@ -311,6 +309,7 @@ static struct mxc_usbh_platform_data usbh1_pdata = {
311static int __init marxbot_usbh1_init(void) 309static int __init marxbot_usbh1_init(void)
312{ 310{
313 struct otg_transceiver *otg; 311 struct otg_transceiver *otg;
312 struct platform_device *pdev;
314 313
315 otg = kzalloc(sizeof(*otg), GFP_KERNEL); 314 otg = kzalloc(sizeof(*otg), GFP_KERNEL);
316 if (!otg) 315 if (!otg)
@@ -322,10 +321,14 @@ static int __init marxbot_usbh1_init(void)
322 321
323 usbh1_pdata.otg = otg; 322 usbh1_pdata.otg = otg;
324 323
325 return mxc_register_device(&mxc_usbh1, &usbh1_pdata); 324 pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
325 if (IS_ERR(pdev))
326 return PTR_ERR(pdev);
327
328 return 0;
326} 329}
327 330
328static struct fsl_usb2_platform_data usb_pdata = { 331static const struct fsl_usb2_platform_data usb_pdata __initconst = {
329 .operating_mode = FSL_USB2_DR_DEVICE, 332 .operating_mode = FSL_USB2_DR_DEVICE,
330 .phy_mode = FSL_USB2_PHY_ULPI, 333 .phy_mode = FSL_USB2_PHY_ULPI,
331}; 334};
@@ -344,7 +347,7 @@ void __init mx31moboard_marxbot_init(void)
344 347
345 dspics_resets_init(); 348 dspics_resets_init();
346 349
347 mxc_register_device(&mxcsdhc_device1, &sdhc2_pdata); 350 imx31_add_mxc_mmc(1, &sdhc2_pdata);
348 351
349 spi_register_board_info(marxbot_spi_board_info, 352 spi_register_board_info(marxbot_spi_board_info,
350 ARRAY_SIZE(marxbot_spi_board_info)); 353 ARRAY_SIZE(marxbot_spi_board_info));
@@ -357,7 +360,7 @@ void __init mx31moboard_marxbot_init(void)
357 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0)); 360 gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
358 gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false); 361 gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
359 362
360 mxc_register_device(&mxc_otg_udc_device, &usb_pdata); 363 imx31_add_fsl_usb2_udc(&usb_pdata);
361 364
362 marxbot_usbh1_init(); 365 marxbot_usbh1_init();
363} 366}
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
index 04760a53005a..bbec3c82264a 100644
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ b/arch/arm/mach-mx3/mx31moboard-smartbot.c
@@ -19,7 +19,6 @@
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/platform_device.h> 20#include <linux/platform_device.h>
21#include <linux/types.h> 21#include <linux/types.h>
22#include <linux/fsl_devices.h>
23 22
24#include <linux/usb/otg.h> 23#include <linux/usb/otg.h>
25#include <linux/usb/ulpi.h> 24#include <linux/usb/ulpi.h>
@@ -28,7 +27,6 @@
28#include <mach/hardware.h> 27#include <mach/hardware.h>
29#include <mach/iomux-mx3.h> 28#include <mach/iomux-mx3.h>
30#include <mach/board-mx31moboard.h> 29#include <mach/board-mx31moboard.h>
31#include <mach/mxc_ehci.h>
32#include <mach/ulpi.h> 30#include <mach/ulpi.h>
33 31
34#include <media/soc_camera.h> 32#include <media/soc_camera.h>
@@ -118,24 +116,30 @@ static int __init smartbot_cam_init(void)
118 return 0; 116 return 0;
119} 117}
120 118
121static struct fsl_usb2_platform_data usb_pdata = { 119static const struct fsl_usb2_platform_data usb_pdata __initconst = {
122 .operating_mode = FSL_USB2_DR_DEVICE, 120 .operating_mode = FSL_USB2_DR_DEVICE,
123 .phy_mode = FSL_USB2_PHY_ULPI, 121 .phy_mode = FSL_USB2_PHY_ULPI,
124}; 122};
125 123
126#if defined(CONFIG_USB_ULPI) 124#if defined(CONFIG_USB_ULPI)
127 125
128static struct mxc_usbh_platform_data otg_host_pdata = { 126static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
129 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT, 127 .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
130 .flags = MXC_EHCI_POWER_PINS_ENABLED, 128 .flags = MXC_EHCI_POWER_PINS_ENABLED,
131}; 129};
132 130
133static int __init smartbot_otg_host_init(void) 131static int __init smartbot_otg_host_init(void)
134{ 132{
133 struct platform_device *pdev;
134
135 otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops, 135 otg_host_pdata.otg = otg_ulpi_create(&mxc_ulpi_access_ops,
136 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); 136 ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT);
137 137
138 return mxc_register_device(&mxc_otg_host, &otg_host_pdata); 138 pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
139 if (IS_ERR(pdev))
140 return PTR_ERR(pdev);
141
142 return 0;
139} 143}
140#else 144#else
141static inline int smartbot_otg_host_init(void) { return 0; } 145static inline int smartbot_otg_host_init(void) { return 0; }
@@ -182,7 +186,7 @@ void __init mx31moboard_smartbot_init(int board)
182 186
183 switch (board) { 187 switch (board) {
184 case MX31SMARTBOT: 188 case MX31SMARTBOT:
185 mxc_register_device(&mxc_otg_udc_device, &usb_pdata); 189 imx31_add_fsl_usb2_udc(&usb_pdata);
186 break; 190 break;
187 case MX31EYEBOT: 191 case MX31EYEBOT:
188 smartbot_otg_host_init(); 192 smartbot_otg_host_init();
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 3ec910a7a182..55254b6e9460 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,20 +1,47 @@
1if ARCH_MX5 1if ARCH_MX5
2# ARCH_MX51 and ARCH_MX50 are left for compatibility
3
4config ARCH_MX50
5 bool
2 6
3config ARCH_MX51 7config ARCH_MX51
4 bool 8 bool
5 default y 9
10config ARCH_MX53
11 bool
12
13config SOC_IMX50
14 bool
15 select MXC_TZIC
16 select ARCH_MXC_IOMUX_V3
17 select ARCH_MXC_AUDMUX_V2
18 select ARCH_HAS_CPUFREQ
19 select ARCH_MX50
20
21config SOC_IMX51
22 bool
6 select MXC_TZIC 23 select MXC_TZIC
7 select ARCH_MXC_IOMUX_V3 24 select ARCH_MXC_IOMUX_V3
8 select ARCH_MXC_AUDMUX_V2 25 select ARCH_MXC_AUDMUX_V2
9 select ARCH_HAS_CPUFREQ 26 select ARCH_HAS_CPUFREQ
27 select ARCH_MX51
28
29config SOC_IMX53
30 bool
31 select MXC_TZIC
32 select ARCH_MXC_IOMUX_V3
33 select ARCH_MX53
10 34
11comment "MX5 platforms:" 35comment "MX5 platforms:"
12 36
13config MACH_MX51_BABBAGE 37config MACH_MX51_BABBAGE
14 bool "Support MX51 BABBAGE platforms" 38 bool "Support MX51 BABBAGE platforms"
39 select SOC_IMX51
40 select IMX_HAVE_PLATFORM_IMX2_WDT
15 select IMX_HAVE_PLATFORM_IMX_I2C 41 select IMX_HAVE_PLATFORM_IMX_I2C
16 select IMX_HAVE_PLATFORM_IMX_UART 42 select IMX_HAVE_PLATFORM_IMX_UART
17 select IMX_HAVE_PLATFORM_ESDHC 43 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
44 select IMX_HAVE_PLATFORM_SPI_IMX
18 help 45 help
19 Include support for MX51 Babbage platform, also known as MX51EVK in 46 Include support for MX51 Babbage platform, also known as MX51EVK in
20 u-boot. This includes specific configurations for the board and its 47 u-boot. This includes specific configurations for the board and its
@@ -22,7 +49,9 @@ config MACH_MX51_BABBAGE
22 49
23config MACH_MX51_3DS 50config MACH_MX51_3DS
24 bool "Support MX51PDK (3DS)" 51 bool "Support MX51PDK (3DS)"
52 select SOC_IMX51
25 select IMX_HAVE_PLATFORM_IMX_UART 53 select IMX_HAVE_PLATFORM_IMX_UART
54 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
26 select IMX_HAVE_PLATFORM_SPI_IMX 55 select IMX_HAVE_PLATFORM_SPI_IMX
27 select MXC_DEBUG_BOARD 56 select MXC_DEBUG_BOARD
28 help 57 help
@@ -31,6 +60,7 @@ config MACH_MX51_3DS
31 60
32config MACH_EUKREA_CPUIMX51 61config MACH_EUKREA_CPUIMX51
33 bool "Support Eukrea CPUIMX51 module" 62 bool "Support Eukrea CPUIMX51 module"
63 select SOC_IMX51
34 select IMX_HAVE_PLATFORM_IMX_I2C 64 select IMX_HAVE_PLATFORM_IMX_I2C
35 select IMX_HAVE_PLATFORM_IMX_UART 65 select IMX_HAVE_PLATFORM_IMX_UART
36 select IMX_HAVE_PLATFORM_MXC_NAND 66 select IMX_HAVE_PLATFORM_MXC_NAND
@@ -47,7 +77,7 @@ choice
47config MACH_EUKREA_MBIMX51_BASEBOARD 77config MACH_EUKREA_MBIMX51_BASEBOARD
48 prompt "Eukrea MBIMX51 development board" 78 prompt "Eukrea MBIMX51 development board"
49 bool 79 bool
50 select IMX_HAVE_PLATFORM_ESDHC 80 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
51 help 81 help
52 This adds board specific devices that can be found on Eukrea's 82 This adds board specific devices that can be found on Eukrea's
53 MBIMX51 evaluation board. 83 MBIMX51 evaluation board.
@@ -56,6 +86,7 @@ endchoice
56 86
57config MACH_EUKREA_CPUIMX51SD 87config MACH_EUKREA_CPUIMX51SD
58 bool "Support Eukrea CPUIMX51SD module" 88 bool "Support Eukrea CPUIMX51SD module"
89 select SOC_IMX51
59 select IMX_HAVE_PLATFORM_IMX_I2C 90 select IMX_HAVE_PLATFORM_IMX_I2C
60 select IMX_HAVE_PLATFORM_SPI_IMX 91 select IMX_HAVE_PLATFORM_SPI_IMX
61 select IMX_HAVE_PLATFORM_IMX_UART 92 select IMX_HAVE_PLATFORM_IMX_UART
@@ -72,7 +103,7 @@ choice
72config MACH_EUKREA_MBIMXSD51_BASEBOARD 103config MACH_EUKREA_MBIMXSD51_BASEBOARD
73 prompt "Eukrea MBIMXSD development board" 104 prompt "Eukrea MBIMXSD development board"
74 bool 105 bool
75 select IMX_HAVE_PLATFORM_ESDHC 106 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
76 help 107 help
77 This adds board specific devices that can be found on Eukrea's 108 This adds board specific devices that can be found on Eukrea's
78 MBIMXSD evaluation board. 109 MBIMXSD evaluation board.
@@ -81,9 +112,33 @@ endchoice
81 112
82config MACH_MX51_EFIKAMX 113config MACH_MX51_EFIKAMX
83 bool "Support MX51 Genesi Efika MX nettop" 114 bool "Support MX51 Genesi Efika MX nettop"
115 select SOC_IMX51
84 select IMX_HAVE_PLATFORM_IMX_UART 116 select IMX_HAVE_PLATFORM_IMX_UART
117 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
118 select IMX_HAVE_PLATFORM_SPI_IMX
85 help 119 help
86 Include support for Genesi Efika MX nettop. This includes specific 120 Include support for Genesi Efika MX nettop. This includes specific
87 configurations for the board and its peripherals. 121 configurations for the board and its peripherals.
88 122
123config MACH_MX53_EVK
124 bool "Support MX53 EVK platforms"
125 select SOC_IMX53
126 select IMX_HAVE_PLATFORM_IMX_UART
127 help
128 Include support for MX53 EVK platform. This includes specific
129 configurations for the board and its peripherals.
130
131
132config MACH_MX50_RDP
133 bool "Support MX50 reference design platform"
134 depends on BROKEN
135 select SOC_IMX50
136 select IMX_HAVE_PLATFORM_IMX_I2C
137 select IMX_HAVE_PLATFORM_IMX_UART
138 select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
139 select IMX_HAVE_PLATFORM_SPI_IMX
140 help
141 Include support for MX50 reference design platform (RDP) board. This
142 includes specific configurations for the board and its peripherals.
143
89endif 144endif
diff --git a/arch/arm/mach-mx5/Makefile b/arch/arm/mach-mx5/Makefile
index 462f177eddfe..0c398baf11fe 100644
--- a/arch/arm/mach-mx5/Makefile
+++ b/arch/arm/mach-mx5/Makefile
@@ -3,13 +3,16 @@
3# 3#
4 4
5# Object file lists. 5# Object file lists.
6obj-y := cpu.o mm.o clock-mx51.o devices.o 6obj-y := cpu.o mm.o clock-mx51-mx53.o devices.o
7obj-$(CONFIG_SOC_IMX50) += mm-mx50.o
7 8
8obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o 9obj-$(CONFIG_CPU_FREQ_IMX) += cpu_op-mx51.o
9obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o 10obj-$(CONFIG_MACH_MX51_BABBAGE) += board-mx51_babbage.o
10obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o 11obj-$(CONFIG_MACH_MX51_3DS) += board-mx51_3ds.o
12obj-$(CONFIG_MACH_MX53_EVK) += board-mx53_evk.o
11obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o 13obj-$(CONFIG_MACH_EUKREA_CPUIMX51) += board-cpuimx51.o
12obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o 14obj-$(CONFIG_MACH_EUKREA_MBIMX51_BASEBOARD) += eukrea_mbimx51-baseboard.o
13obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o 15obj-$(CONFIG_MACH_EUKREA_CPUIMX51SD) += board-cpuimx51sd.o
14obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o 16obj-$(CONFIG_MACH_EUKREA_MBIMXSD51_BASEBOARD) += eukrea_mbimxsd-baseboard.o
15obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o 17obj-$(CONFIG_MACH_MX51_EFIKAMX) += board-mx51_efikamx.o
18obj-$(CONFIG_MACH_MX50_RDP) += board-mx50_rdp.o
diff --git a/arch/arm/mach-mx5/Makefile.boot b/arch/arm/mach-mx5/Makefile.boot
index 9939a19d99a1..e928be1b6757 100644
--- a/arch/arm/mach-mx5/Makefile.boot
+++ b/arch/arm/mach-mx5/Makefile.boot
@@ -1,3 +1,9 @@
1 zreladdr-y := 0x90008000 1 zreladdr-$(CONFIG_ARCH_MX50) := 0x70008000
2params_phys-y := 0x90000100 2params_phys-$(CONFIG_ARCH_MX50) := 0x70000100
3initrd_phys-y := 0x90800000 3initrd_phys-$(CONFIG_ARCH_MX50) := 0x70800000
4 zreladdr-$(CONFIG_ARCH_MX51) := 0x90008000
5params_phys-$(CONFIG_ARCH_MX51) := 0x90000100
6initrd_phys-$(CONFIG_ARCH_MX51) := 0x90800000
7 zreladdr-$(CONFIG_ARCH_MX53) := 0x70008000
8params_phys-$(CONFIG_ARCH_MX53) := 0x70000100
9initrd_phys-$(CONFIG_ARCH_MX53) := 0x70800000
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index 6a9792fd0a76..f8652ef25f85 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -40,11 +40,11 @@
40#include "devices-imx51.h" 40#include "devices-imx51.h"
41#include "devices.h" 41#include "devices.h"
42 42
43#define CPUIMX51_USBH1_STP (0*32 + 27) 43#define CPUIMX51_USBH1_STP IMX_GPIO_NR(1, 27)
44#define CPUIMX51_QUARTA_GPIO (2*32 + 28) 44#define CPUIMX51_QUARTA_GPIO IMX_GPIO_NR(3, 28)
45#define CPUIMX51_QUARTB_GPIO (2*32 + 25) 45#define CPUIMX51_QUARTB_GPIO IMX_GPIO_NR(3, 25)
46#define CPUIMX51_QUARTC_GPIO (2*32 + 26) 46#define CPUIMX51_QUARTC_GPIO IMX_GPIO_NR(3, 26)
47#define CPUIMX51_QUARTD_GPIO (2*32 + 27) 47#define CPUIMX51_QUARTD_GPIO IMX_GPIO_NR(3, 27)
48#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO) 48#define CPUIMX51_QUARTA_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTA_GPIO)
49#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO) 49#define CPUIMX51_QUARTB_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTB_GPIO)
50#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO) 50#define CPUIMX51_QUARTC_IRQ (MXC_INTERNAL_IRQS + CPUIMX51_QUARTC_GPIO)
@@ -113,7 +113,7 @@ static struct platform_device *devices[] __initdata = {
113#endif 113#endif
114}; 114};
115 115
116static struct pad_desc eukrea_cpuimx51_pads[] = { 116static iomux_v3_cfg_t eukrea_cpuimx51_pads[] = {
117 /* UART1 */ 117 /* UART1 */
118 MX51_PAD_UART1_RXD__UART1_RXD, 118 MX51_PAD_UART1_RXD__UART1_RXD,
119 MX51_PAD_UART1_TXD__UART1_TXD, 119 MX51_PAD_UART1_TXD__UART1_TXD,
@@ -121,15 +121,15 @@ static struct pad_desc eukrea_cpuimx51_pads[] = {
121 MX51_PAD_UART1_CTS__UART1_CTS, 121 MX51_PAD_UART1_CTS__UART1_CTS,
122 122
123 /* I2C2 */ 123 /* I2C2 */
124 MX51_PAD_GPIO_1_2__I2C2_SCL, 124 MX51_PAD_GPIO1_2__I2C2_SCL,
125 MX51_PAD_GPIO_1_3__I2C2_SDA, 125 MX51_PAD_GPIO1_3__I2C2_SDA,
126 MX51_PAD_NANDF_D10__GPIO_3_30, 126 MX51_PAD_NANDF_D10__GPIO3_30,
127 127
128 /* QUART IRQ */ 128 /* QUART IRQ */
129 MX51_PAD_NANDF_D15__GPIO_3_25, 129 MX51_PAD_NANDF_D15__GPIO3_25,
130 MX51_PAD_NANDF_D14__GPIO_3_26, 130 MX51_PAD_NANDF_D14__GPIO3_26,
131 MX51_PAD_NANDF_D13__GPIO_3_27, 131 MX51_PAD_NANDF_D13__GPIO3_27,
132 MX51_PAD_NANDF_D12__GPIO_3_28, 132 MX51_PAD_NANDF_D12__GPIO3_28,
133 133
134 /* USB HOST1 */ 134 /* USB HOST1 */
135 MX51_PAD_USBH1_CLK__USBH1_CLK, 135 MX51_PAD_USBH1_CLK__USBH1_CLK,
@@ -178,6 +178,8 @@ static int initialize_otg_port(struct platform_device *pdev)
178 void __iomem *usbother_base; 178 void __iomem *usbother_base;
179 179
180 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 180 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
181 if (!usb_base)
182 return -ENOMEM;
181 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 183 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
182 184
183 /* Set the PHY clock to 19.2MHz */ 185 /* Set the PHY clock to 19.2MHz */
@@ -196,6 +198,8 @@ static int initialize_usbh1_port(struct platform_device *pdev)
196 void __iomem *usbother_base; 198 void __iomem *usbother_base;
197 199
198 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 200 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
201 if (!usb_base)
202 return -ENOMEM;
199 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 203 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
200 204
201 /* The clock for the USBH1 ULPI port will come externally from the PHY. */ 205 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
@@ -292,7 +296,7 @@ static struct sys_timer mxc_timer = {
292 296
293MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module") 297MACHINE_START(EUKREA_CPUIMX51, "Eukrea CPUIMX51 Module")
294 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 298 /* Maintainer: Eric Bénard <eric@eukrea.com> */
295 .boot_params = PHYS_OFFSET + 0x100, 299 .boot_params = MX51_PHYS_OFFSET + 0x100,
296 .map_io = mx51_map_io, 300 .map_io = mx51_map_io,
297 .init_irq = mx51_init_irq, 301 .init_irq = mx51_init_irq,
298 .init_machine = eukrea_cpuimx51_init, 302 .init_machine = eukrea_cpuimx51_init,
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index 4b3a6119c5fb..ad931895d8b6 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -43,19 +43,19 @@
43#include "devices-imx51.h" 43#include "devices-imx51.h"
44#include "devices.h" 44#include "devices.h"
45 45
46#define USBH1_RST (1*32 + 28) 46#define USBH1_RST IMX_GPIO_NR(2, 28)
47#define ETH_RST (1*32 + 31) 47#define ETH_RST IMX_GPIO_NR(2, 31)
48#define TSC2007_IRQGPIO (2*32 + 12) 48#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 12)
49#define CAN_IRQGPIO (0*32 + 1) 49#define CAN_IRQGPIO IMX_GPIO_NR(1, 1)
50#define CAN_RST (3*32 + 15) 50#define CAN_RST IMX_GPIO_NR(4, 15)
51#define CAN_NCS (3*32 + 24) 51#define CAN_NCS IMX_GPIO_NR(4, 24)
52#define CAN_RXOBF (0*32 + 4) 52#define CAN_RXOBF IMX_GPIO_NR(1, 4)
53#define CAN_RX1BF (0*32 + 6) 53#define CAN_RX1BF IMX_GPIO_NR(1, 6)
54#define CAN_TXORTS (0*32 + 7) 54#define CAN_TXORTS IMX_GPIO_NR(1, 7)
55#define CAN_TX1RTS (0*32 + 8) 55#define CAN_TX1RTS IMX_GPIO_NR(1, 8)
56#define CAN_TX2RTS (0*32 + 9) 56#define CAN_TX2RTS IMX_GPIO_NR(1, 9)
57#define I2C_SCL (3*32 + 16) 57#define I2C_SCL IMX_GPIO_NR(4, 16)
58#define I2C_SDA (3*32 + 17) 58#define I2C_SDA IMX_GPIO_NR(4, 17)
59 59
60/* USB_CTRL_1 */ 60/* USB_CTRL_1 */
61#define MX51_USB_CTRL_1_OFFSET 0x10 61#define MX51_USB_CTRL_1_OFFSET 0x10
@@ -65,10 +65,7 @@
65#define MX51_USB_PLL_DIV_19_2_MHZ 0x01 65#define MX51_USB_PLL_DIV_19_2_MHZ 0x01
66#define MX51_USB_PLL_DIV_24_MHZ 0x02 66#define MX51_USB_PLL_DIV_24_MHZ 0x02
67 67
68#define CPUIMX51SD_GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, \ 68static iomux_v3_cfg_t eukrea_cpuimx51sd_pads[] = {
69 MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
70
71static struct pad_desc eukrea_cpuimx51sd_pads[] = {
72 /* UART1 */ 69 /* UART1 */
73 MX51_PAD_UART1_RXD__UART1_RXD, 70 MX51_PAD_UART1_RXD__UART1_RXD,
74 MX51_PAD_UART1_TXD__UART1_TXD, 71 MX51_PAD_UART1_TXD__UART1_TXD,
@@ -88,30 +85,33 @@ static struct pad_desc eukrea_cpuimx51sd_pads[] = {
88 MX51_PAD_USBH1_DATA6__USBH1_DATA6, 85 MX51_PAD_USBH1_DATA6__USBH1_DATA6,
89 MX51_PAD_USBH1_DATA7__USBH1_DATA7, 86 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
90 MX51_PAD_USBH1_STP__USBH1_STP, 87 MX51_PAD_USBH1_STP__USBH1_STP,
91 MX51_PAD_EIM_CS3__GPIO_2_28, /* PHY nRESET */ 88 MX51_PAD_EIM_CS3__GPIO2_28, /* PHY nRESET */
92 89
93 /* FEC */ 90 /* FEC */
94 MX51_PAD_EIM_DTACK__GPIO_2_31, /* PHY nRESET */ 91 MX51_PAD_EIM_DTACK__GPIO2_31, /* PHY nRESET */
95 92
96 /* HSI2C */ 93 /* HSI2C */
97 MX51_PAD_I2C1_CLK__GPIO_4_16, 94 MX51_PAD_I2C1_CLK__GPIO4_16,
98 MX51_PAD_I2C1_DAT__GPIO_4_17, 95 MX51_PAD_I2C1_DAT__GPIO4_17,
99 96
100 /* CAN */ 97 /* CAN */
101 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, 98 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
102 MX51_PAD_CSPI1_MISO__ECSPI1_MISO, 99 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
103 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, 100 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
104 MX51_PAD_CSPI1_SS0__GPIO_4_24, /* nCS */ 101 MX51_PAD_CSPI1_SS0__GPIO4_24, /* nCS */
105 MX51_PAD_CSI2_PIXCLK__GPIO_4_15, /* nReset */ 102 MX51_PAD_CSI2_PIXCLK__GPIO4_15, /* nReset */
106 MX51_PAD_GPIO_1_1__GPIO_1_1, /* IRQ */ 103 MX51_PAD_GPIO1_1__GPIO1_1, /* IRQ */
107 MX51_PAD_GPIO_1_4__GPIO_1_4, /* Control signals */ 104 MX51_PAD_GPIO1_4__GPIO1_4, /* Control signals */
108 MX51_PAD_GPIO_1_6__GPIO_1_6, 105 MX51_PAD_GPIO1_6__GPIO1_6,
109 MX51_PAD_GPIO_1_7__GPIO_1_7, 106 MX51_PAD_GPIO1_7__GPIO1_7,
110 MX51_PAD_GPIO_1_8__GPIO_1_8, 107 MX51_PAD_GPIO1_8__GPIO1_8,
111 MX51_PAD_GPIO_1_9__GPIO_1_9, 108 MX51_PAD_GPIO1_9__GPIO1_9,
112 109
113 /* Touchscreen */ 110 /* Touchscreen */
114 CPUIMX51SD_GPIO_3_12, /* IRQ */ 111 /* IRQ */
112 _MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
113 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
114 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
115}; 115};
116 116
117static const struct imxuart_platform_data uart_pdata __initconst = { 117static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -157,6 +157,8 @@ static int initialize_otg_port(struct platform_device *pdev)
157 void __iomem *usbother_base; 157 void __iomem *usbother_base;
158 158
159 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 159 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
160 if (!usb_base)
161 return -ENOMEM;
160 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 162 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
161 163
162 /* Set the PHY clock to 19.2MHz */ 164 /* Set the PHY clock to 19.2MHz */
@@ -175,6 +177,8 @@ static int initialize_usbh1_port(struct platform_device *pdev)
175 void __iomem *usbother_base; 177 void __iomem *usbother_base;
176 178
177 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 179 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
180 if (!usb_base)
181 return -ENOMEM;
178 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 182 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
179 183
180 /* The clock for the USBH1 ULPI port will come from the PHY. */ 184 /* The clock for the USBH1 ULPI port will come from the PHY. */
@@ -243,7 +247,7 @@ static struct spi_board_info cpuimx51sd_spi_device[] = {
243 .mode = SPI_MODE_0, 247 .mode = SPI_MODE_0,
244 .chip_select = 0, 248 .chip_select = 0,
245 .platform_data = &mcp251x_info, 249 .platform_data = &mcp251x_info,
246 .irq = gpio_to_irq(0 * 32 + 1) 250 .irq = gpio_to_irq(CAN_IRQGPIO)
247 }, 251 },
248}; 252};
249 253
@@ -323,7 +327,7 @@ static struct sys_timer mxc_timer = {
323 327
324MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD") 328MACHINE_START(EUKREA_CPUIMX51SD, "Eukrea CPUIMX51SD")
325 /* Maintainer: Eric Bénard <eric@eukrea.com> */ 329 /* Maintainer: Eric Bénard <eric@eukrea.com> */
326 .boot_params = PHYS_OFFSET + 0x100, 330 .boot_params = MX51_PHYS_OFFSET + 0x100,
327 .map_io = mx51_map_io, 331 .map_io = mx51_map_io,
328 .init_irq = mx51_init_irq, 332 .init_irq = mx51_init_irq,
329 .init_machine = eukrea_cpuimx51sd_init, 333 .init_machine = eukrea_cpuimx51sd_init,
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
new file mode 100644
index 000000000000..fd32e4c450e8
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -0,0 +1,197 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <linux/init.h>
22#include <linux/platform_device.h>
23#include <linux/gpio.h>
24#include <linux/delay.h>
25#include <linux/io.h>
26#include <linux/fsl_devices.h>
27
28#include <mach/common.h>
29#include <mach/hardware.h>
30#include <mach/iomux-mx50.h>
31
32#include <asm/irq.h>
33#include <asm/setup.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37
38#include "devices-mx50.h"
39
40static iomux_v3_cfg_t mx50_rdp_pads[] __initdata = {
41 /* SD1 */
42 MX50_PAD_ECSPI2_SS0__GPIO_4_19,
43 MX50_PAD_EIM_CRE__GPIO_1_27,
44 MX50_PAD_SD1_CMD__SD1_CMD,
45
46 MX50_PAD_SD1_CLK__SD1_CLK,
47 MX50_PAD_SD1_D0__SD1_D0,
48 MX50_PAD_SD1_D1__SD1_D1,
49 MX50_PAD_SD1_D2__SD1_D2,
50 MX50_PAD_SD1_D3__SD1_D3,
51
52 /* SD2 */
53 MX50_PAD_SD2_CD__GPIO_5_17,
54 MX50_PAD_SD2_WP__GPIO_5_16,
55 MX50_PAD_SD2_CMD__SD2_CMD,
56 MX50_PAD_SD2_CLK__SD2_CLK,
57 MX50_PAD_SD2_D0__SD2_D0,
58 MX50_PAD_SD2_D1__SD2_D1,
59 MX50_PAD_SD2_D2__SD2_D2,
60 MX50_PAD_SD2_D3__SD2_D3,
61 MX50_PAD_SD2_D4__SD2_D4,
62 MX50_PAD_SD2_D5__SD2_D5,
63 MX50_PAD_SD2_D6__SD2_D6,
64 MX50_PAD_SD2_D7__SD2_D7,
65
66 /* SD3 */
67 MX50_PAD_SD3_CMD__SD3_CMD,
68 MX50_PAD_SD3_CLK__SD3_CLK,
69 MX50_PAD_SD3_D0__SD3_D0,
70 MX50_PAD_SD3_D1__SD3_D1,
71 MX50_PAD_SD3_D2__SD3_D2,
72 MX50_PAD_SD3_D3__SD3_D3,
73 MX50_PAD_SD3_D4__SD3_D4,
74 MX50_PAD_SD3_D5__SD3_D5,
75 MX50_PAD_SD3_D6__SD3_D6,
76 MX50_PAD_SD3_D7__SD3_D7,
77
78 /* PWR_INT */
79 MX50_PAD_ECSPI2_MISO__GPIO_4_18,
80
81 /* UART pad setting */
82 MX50_PAD_UART1_TXD__UART1_TXD,
83 MX50_PAD_UART1_RXD__UART1_RXD,
84 MX50_PAD_UART1_RTS__UART1_RTS,
85 MX50_PAD_UART2_TXD__UART2_TXD,
86 MX50_PAD_UART2_RXD__UART2_RXD,
87 MX50_PAD_UART2_CTS__UART2_CTS,
88 MX50_PAD_UART2_RTS__UART2_RTS,
89
90 MX50_PAD_I2C1_SCL__I2C1_SCL,
91 MX50_PAD_I2C1_SDA__I2C1_SDA,
92 MX50_PAD_I2C2_SCL__I2C2_SCL,
93 MX50_PAD_I2C2_SDA__I2C2_SDA,
94
95 MX50_PAD_EPITO__USBH1_PWR,
96 /* Need to comment below line if
97 * one needs to debug owire.
98 */
99 MX50_PAD_OWIRE__USBH1_OC,
100 /* using gpio to control otg pwr */
101 MX50_PAD_PWM2__GPIO_6_25,
102 MX50_PAD_I2C3_SCL__USBOTG_OC,
103
104 MX50_PAD_SSI_RXC__FEC_MDIO,
105 MX50_PAD_SSI_RXC__FEC_MDIO,
106 MX50_PAD_DISP_D0__FEC_TXCLK,
107 MX50_PAD_DISP_D1__FEC_RX_ER,
108 MX50_PAD_DISP_D2__FEC_RX_DV,
109 MX50_PAD_DISP_D3__FEC_RXD1,
110 MX50_PAD_DISP_D4__FEC_RXD0,
111 MX50_PAD_DISP_D5__FEC_TX_EN,
112 MX50_PAD_DISP_D6__FEC_TXD1,
113 MX50_PAD_DISP_D7__FEC_TXD0,
114 MX50_PAD_SSI_RXFS__FEC_MDC,
115 MX50_PAD_I2C3_SDA__GPIO_6_23,
116 MX50_PAD_ECSPI1_SCLK__GPIO_4_12,
117
118 MX50_PAD_CSPI_SS0__CSPI_SS0,
119 MX50_PAD_ECSPI1_MOSI__CSPI_SS1,
120 MX50_PAD_CSPI_MOSI__CSPI_MOSI,
121 MX50_PAD_CSPI_MISO__CSPI_MISO,
122
123 /* SGTL500_OSC_EN */
124 MX50_PAD_UART1_CTS__GPIO_6_8,
125
126 /* SGTL_AMP_SHDN */
127 MX50_PAD_UART3_RXD__GPIO_6_15,
128
129 /* Keypad */
130 MX50_PAD_KEY_COL0__KEY_COL0,
131 MX50_PAD_KEY_ROW0__KEY_ROW0,
132 MX50_PAD_KEY_COL1__KEY_COL1,
133 MX50_PAD_KEY_ROW1__KEY_ROW1,
134 MX50_PAD_KEY_COL2__KEY_COL2,
135 MX50_PAD_KEY_ROW2__KEY_ROW2,
136 MX50_PAD_KEY_COL3__KEY_COL3,
137 MX50_PAD_KEY_ROW3__KEY_ROW3,
138 MX50_PAD_EIM_DA0__KEY_COL4,
139 MX50_PAD_EIM_DA1__KEY_ROW4,
140 MX50_PAD_EIM_DA2__KEY_COL5,
141 MX50_PAD_EIM_DA3__KEY_ROW5,
142 MX50_PAD_EIM_DA4__KEY_COL6,
143 MX50_PAD_EIM_DA5__KEY_ROW6,
144 MX50_PAD_EIM_DA6__KEY_COL7,
145 MX50_PAD_EIM_DA7__KEY_ROW7,
146 /*EIM pads */
147 MX50_PAD_EIM_DA8__GPIO_1_8,
148 MX50_PAD_EIM_DA9__GPIO_1_9,
149 MX50_PAD_EIM_DA10__GPIO_1_10,
150 MX50_PAD_EIM_DA11__GPIO_1_11,
151 MX50_PAD_EIM_DA12__GPIO_1_12,
152 MX50_PAD_EIM_DA13__GPIO_1_13,
153 MX50_PAD_EIM_DA14__GPIO_1_14,
154 MX50_PAD_EIM_DA15__GPIO_1_15,
155 MX50_PAD_EIM_CS2__GPIO_1_16,
156 MX50_PAD_EIM_CS1__GPIO_1_17,
157 MX50_PAD_EIM_CS0__GPIO_1_18,
158 MX50_PAD_EIM_EB0__GPIO_1_19,
159 MX50_PAD_EIM_EB1__GPIO_1_20,
160 MX50_PAD_EIM_WAIT__GPIO_1_21,
161 MX50_PAD_EIM_BCLK__GPIO_1_22,
162 MX50_PAD_EIM_RDY__GPIO_1_23,
163 MX50_PAD_EIM_OE__GPIO_1_24,
164};
165
166/* Serial ports */
167static const struct imxuart_platform_data uart_pdata __initconst = {
168 .flags = IMXUART_HAVE_RTSCTS,
169};
170
171/*
172 * Board specific initialization.
173 */
174static void __init mx50_rdp_board_init(void)
175{
176 mxc_iomux_v3_setup_multiple_pads(mx50_rdp_pads,
177 ARRAY_SIZE(mx50_rdp_pads));
178
179 imx50_add_imx_uart(0, &uart_pdata);
180 imx50_add_imx_uart(1, &uart_pdata);
181}
182
183static void __init mx50_rdp_timer_init(void)
184{
185 mx50_clocks_init(32768, 24000000, 22579200);
186}
187
188static struct sys_timer mx50_rdp_timer = {
189 .init = mx50_rdp_timer_init,
190};
191
192MACHINE_START(MX50_RDP, "Freescale MX50 Reference Design Platform")
193 .map_io = mx50_map_io,
194 .init_irq = mx50_init_irq,
195 .init_machine = mx50_rdp_board_init,
196 .timer = &mx50_rdp_timer,
197MACHINE_END
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 79ce8dcf3cda..e42bd2eb034e 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -30,7 +30,7 @@
30#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6) 30#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
31#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28) 31#define MX51_3DS_ECSPI2_CS (GPIO_PORTC + 28)
32 32
33static struct pad_desc mx51_3ds_pads[] = { 33static iomux_v3_cfg_t mx51_3ds_pads[] = {
34 /* UART1 */ 34 /* UART1 */
35 MX51_PAD_UART1_RXD__UART1_RXD, 35 MX51_PAD_UART1_RXD__UART1_RXD,
36 MX51_PAD_UART1_TXD__UART1_TXD, 36 MX51_PAD_UART1_TXD__UART1_TXD,
@@ -50,7 +50,7 @@ static struct pad_desc mx51_3ds_pads[] = {
50 MX51_PAD_EIM_D27__UART3_RTS, 50 MX51_PAD_EIM_D27__UART3_RTS,
51 51
52 /* CPLD PARENT IRQ PIN */ 52 /* CPLD PARENT IRQ PIN */
53 MX51_PAD_GPIO_1_6__GPIO_1_6, 53 MX51_PAD_GPIO1_6__GPIO1_6,
54 54
55 /* KPP */ 55 /* KPP */
56 MX51_PAD_KEY_ROW0__KEY_ROW0, 56 MX51_PAD_KEY_ROW0__KEY_ROW0,
@@ -68,7 +68,7 @@ static struct pad_desc mx51_3ds_pads[] = {
68 MX51_PAD_NANDF_RB2__ECSPI2_SCLK, 68 MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
69 MX51_PAD_NANDF_RB3__ECSPI2_MISO, 69 MX51_PAD_NANDF_RB3__ECSPI2_MISO,
70 MX51_PAD_NANDF_D15__ECSPI2_MOSI, 70 MX51_PAD_NANDF_D15__ECSPI2_MOSI,
71 MX51_PAD_NANDF_D12__GPIO_3_28, 71 MX51_PAD_NANDF_D12__GPIO3_28,
72}; 72};
73 73
74/* Serial ports */ 74/* Serial ports */
@@ -172,6 +172,7 @@ static void __init mxc_board_init(void)
172 printk(KERN_WARNING "Init of the debugboard failed, all " 172 printk(KERN_WARNING "Init of the debugboard failed, all "
173 "devices on the board are unusable.\n"); 173 "devices on the board are unusable.\n");
174 174
175 imx51_add_sdhci_esdhc_imx(0, NULL);
175 mxc_init_keypad(); 176 mxc_init_keypad();
176} 177}
177 178
@@ -186,7 +187,7 @@ static struct sys_timer mxc_timer = {
186 187
187MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board") 188MACHINE_START(MX51_3DS, "Freescale MX51 3-Stack Board")
188 /* Maintainer: Freescale Semiconductor, Inc. */ 189 /* Maintainer: Freescale Semiconductor, Inc. */
189 .boot_params = PHYS_OFFSET + 0x100, 190 .boot_params = MX51_PHYS_OFFSET + 0x100,
190 .map_io = mx51_map_io, 191 .map_io = mx51_map_io,
191 .init_irq = mx51_init_irq, 192 .init_irq = mx51_init_irq,
192 .init_machine = mxc_board_init, 193 .init_machine = mxc_board_init,
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index acbe30df2e69..1d231e84107c 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -20,6 +20,8 @@
20#include <linux/fec.h> 20#include <linux/fec.h>
21#include <linux/gpio_keys.h> 21#include <linux/gpio_keys.h>
22#include <linux/input.h> 22#include <linux/input.h>
23#include <linux/spi/flash.h>
24#include <linux/spi/spi.h>
23 25
24#include <mach/common.h> 26#include <mach/common.h>
25#include <mach/hardware.h> 27#include <mach/hardware.h>
@@ -36,11 +38,13 @@
36#include "devices.h" 38#include "devices.h"
37#include "cpu_op-mx51.h" 39#include "cpu_op-mx51.h"
38 40
39#define BABBAGE_USB_HUB_RESET (0*32 + 7) /* GPIO_1_7 */ 41#define BABBAGE_USB_HUB_RESET IMX_GPIO_NR(1, 7)
40#define BABBAGE_USBH1_STP (0*32 + 27) /* GPIO_1_27 */ 42#define BABBAGE_USBH1_STP IMX_GPIO_NR(1, 27)
41#define BABBAGE_PHY_RESET (1*32 + 5) /* GPIO_2_5 */ 43#define BABBAGE_PHY_RESET IMX_GPIO_NR(2, 5)
42#define BABBAGE_FEC_PHY_RESET (1*32 + 14) /* GPIO_2_14 */ 44#define BABBAGE_FEC_PHY_RESET IMX_GPIO_NR(2, 14)
43#define BABBAGE_POWER_KEY (1*32 + 21) /* GPIO_2_21 */ 45#define BABBAGE_POWER_KEY IMX_GPIO_NR(2, 21)
46#define BABBAGE_ECSPI1_CS0 IMX_GPIO_NR(4, 24)
47#define BABBAGE_ECSPI1_CS1 IMX_GPIO_NR(4, 25)
44 48
45/* USB_CTRL_1 */ 49/* USB_CTRL_1 */
46#define MX51_USB_CTRL_1_OFFSET 0x10 50#define MX51_USB_CTRL_1_OFFSET 0x10
@@ -65,7 +69,7 @@ static const struct gpio_keys_platform_data imx_button_data __initconst = {
65 .nbuttons = ARRAY_SIZE(babbage_buttons), 69 .nbuttons = ARRAY_SIZE(babbage_buttons),
66}; 70};
67 71
68static struct pad_desc mx51babbage_pads[] = { 72static iomux_v3_cfg_t mx51babbage_pads[] = {
69 /* UART1 */ 73 /* UART1 */
70 MX51_PAD_UART1_RXD__UART1_RXD, 74 MX51_PAD_UART1_RXD__UART1_RXD,
71 MX51_PAD_UART1_TXD__UART1_TXD, 75 MX51_PAD_UART1_TXD__UART1_TXD,
@@ -91,8 +95,8 @@ static struct pad_desc mx51babbage_pads[] = {
91 MX51_PAD_KEY_COL5__I2C2_SDA, 95 MX51_PAD_KEY_COL5__I2C2_SDA,
92 96
93 /* HSI2C */ 97 /* HSI2C */
94 MX51_PAD_I2C1_CLK__HSI2C_CLK, 98 MX51_PAD_I2C1_CLK__I2C1_CLK,
95 MX51_PAD_I2C1_DAT__HSI2C_DAT, 99 MX51_PAD_I2C1_DAT__I2C1_DAT,
96 100
97 /* USB HOST1 */ 101 /* USB HOST1 */
98 MX51_PAD_USBH1_CLK__USBH1_CLK, 102 MX51_PAD_USBH1_CLK__USBH1_CLK,
@@ -108,29 +112,29 @@ static struct pad_desc mx51babbage_pads[] = {
108 MX51_PAD_USBH1_DATA7__USBH1_DATA7, 112 MX51_PAD_USBH1_DATA7__USBH1_DATA7,
109 113
110 /* USB HUB reset line*/ 114 /* USB HUB reset line*/
111 MX51_PAD_GPIO_1_7__GPIO_1_7, 115 MX51_PAD_GPIO1_7__GPIO1_7,
112 116
113 /* FEC */ 117 /* FEC */
114 MX51_PAD_EIM_EB2__FEC_MDIO, 118 MX51_PAD_EIM_EB2__FEC_MDIO,
115 MX51_PAD_EIM_EB3__FEC_RDAT1, 119 MX51_PAD_EIM_EB3__FEC_RDATA1,
116 MX51_PAD_EIM_CS2__FEC_RDAT2, 120 MX51_PAD_EIM_CS2__FEC_RDATA2,
117 MX51_PAD_EIM_CS3__FEC_RDAT3, 121 MX51_PAD_EIM_CS3__FEC_RDATA3,
118 MX51_PAD_EIM_CS4__FEC_RX_ER, 122 MX51_PAD_EIM_CS4__FEC_RX_ER,
119 MX51_PAD_EIM_CS5__FEC_CRS, 123 MX51_PAD_EIM_CS5__FEC_CRS,
120 MX51_PAD_NANDF_RB2__FEC_COL, 124 MX51_PAD_NANDF_RB2__FEC_COL,
121 MX51_PAD_NANDF_RB3__FEC_RXCLK, 125 MX51_PAD_NANDF_RB3__FEC_RX_CLK,
122 MX51_PAD_NANDF_RB6__FEC_RDAT0, 126 MX51_PAD_NANDF_D9__FEC_RDATA0,
123 MX51_PAD_NANDF_RB7__FEC_TDAT0, 127 MX51_PAD_NANDF_D8__FEC_TDATA0,
124 MX51_PAD_NANDF_CS2__FEC_TX_ER, 128 MX51_PAD_NANDF_CS2__FEC_TX_ER,
125 MX51_PAD_NANDF_CS3__FEC_MDC, 129 MX51_PAD_NANDF_CS3__FEC_MDC,
126 MX51_PAD_NANDF_CS4__FEC_TDAT1, 130 MX51_PAD_NANDF_CS4__FEC_TDATA1,
127 MX51_PAD_NANDF_CS5__FEC_TDAT2, 131 MX51_PAD_NANDF_CS5__FEC_TDATA2,
128 MX51_PAD_NANDF_CS6__FEC_TDAT3, 132 MX51_PAD_NANDF_CS6__FEC_TDATA3,
129 MX51_PAD_NANDF_CS7__FEC_TX_EN, 133 MX51_PAD_NANDF_CS7__FEC_TX_EN,
130 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK, 134 MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK,
131 135
132 /* FEC PHY reset line */ 136 /* FEC PHY reset line */
133 MX51_PAD_EIM_A20__GPIO_2_14, 137 MX51_PAD_EIM_A20__GPIO2_14,
134 138
135 /* SD 1 */ 139 /* SD 1 */
136 MX51_PAD_SD1_CMD__SD1_CMD, 140 MX51_PAD_SD1_CMD__SD1_CMD,
@@ -147,6 +151,13 @@ static struct pad_desc mx51babbage_pads[] = {
147 MX51_PAD_SD2_DATA1__SD2_DATA1, 151 MX51_PAD_SD2_DATA1__SD2_DATA1,
148 MX51_PAD_SD2_DATA2__SD2_DATA2, 152 MX51_PAD_SD2_DATA2__SD2_DATA2,
149 MX51_PAD_SD2_DATA3__SD2_DATA3, 153 MX51_PAD_SD2_DATA3__SD2_DATA3,
154
155 /* eCSPI1 */
156 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
157 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
158 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
159 MX51_PAD_CSPI1_SS0__GPIO4_24,
160 MX51_PAD_CSPI1_SS1__GPIO4_25,
150}; 161};
151 162
152/* Serial ports */ 163/* Serial ports */
@@ -177,12 +188,12 @@ static struct imxi2c_platform_data babbage_hsi2c_data = {
177 188
178static int gpio_usbh1_active(void) 189static int gpio_usbh1_active(void)
179{ 190{
180 struct pad_desc usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO_1_27; 191 iomux_v3_cfg_t usbh1stp_gpio = MX51_PAD_USBH1_STP__GPIO1_27;
181 struct pad_desc phyreset_gpio = MX51_PAD_EIM_D21__GPIO_2_5; 192 iomux_v3_cfg_t phyreset_gpio = MX51_PAD_EIM_D21__GPIO2_5;
182 int ret; 193 int ret;
183 194
184 /* Set USBH1_STP to GPIO and toggle it */ 195 /* Set USBH1_STP to GPIO and toggle it */
185 mxc_iomux_v3_setup_pad(&usbh1stp_gpio); 196 mxc_iomux_v3_setup_pad(usbh1stp_gpio);
186 ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp"); 197 ret = gpio_request(BABBAGE_USBH1_STP, "usbh1_stp");
187 198
188 if (ret) { 199 if (ret) {
@@ -195,7 +206,7 @@ static int gpio_usbh1_active(void)
195 gpio_free(BABBAGE_USBH1_STP); 206 gpio_free(BABBAGE_USBH1_STP);
196 207
197 /* De-assert USB PHY RESETB */ 208 /* De-assert USB PHY RESETB */
198 mxc_iomux_v3_setup_pad(&phyreset_gpio); 209 mxc_iomux_v3_setup_pad(phyreset_gpio);
199 ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset"); 210 ret = gpio_request(BABBAGE_PHY_RESET, "phy_reset");
200 211
201 if (ret) { 212 if (ret) {
@@ -251,6 +262,8 @@ static int initialize_otg_port(struct platform_device *pdev)
251 void __iomem *usbother_base; 262 void __iomem *usbother_base;
252 263
253 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 264 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
265 if (!usb_base)
266 return -ENOMEM;
254 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 267 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
255 268
256 /* Set the PHY clock to 19.2MHz */ 269 /* Set the PHY clock to 19.2MHz */
@@ -269,6 +282,8 @@ static int initialize_usbh1_port(struct platform_device *pdev)
269 void __iomem *usbother_base; 282 void __iomem *usbother_base;
270 283
271 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 284 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
285 if (!usb_base)
286 return -ENOMEM;
272 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; 287 usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
273 288
274 /* The clock for the USBH1 ULPI port will come externally from the PHY. */ 289 /* The clock for the USBH1 ULPI port will come externally from the PHY. */
@@ -310,13 +325,35 @@ static int __init babbage_otg_mode(char *options)
310} 325}
311__setup("otg_mode=", babbage_otg_mode); 326__setup("otg_mode=", babbage_otg_mode);
312 327
328static struct spi_board_info mx51_babbage_spi_board_info[] __initdata = {
329 {
330 .modalias = "mtd_dataflash",
331 .max_speed_hz = 25000000,
332 .bus_num = 0,
333 .chip_select = 1,
334 .mode = SPI_MODE_0,
335 .platform_data = NULL,
336 },
337};
338
339static int mx51_babbage_spi_cs[] = {
340 BABBAGE_ECSPI1_CS0,
341 BABBAGE_ECSPI1_CS1,
342};
343
344static const struct spi_imx_master mx51_babbage_spi_pdata __initconst = {
345 .chipselect = mx51_babbage_spi_cs,
346 .num_chipselect = ARRAY_SIZE(mx51_babbage_spi_cs),
347};
348
313/* 349/*
314 * Board specific initialization. 350 * Board specific initialization.
315 */ 351 */
316static void __init mxc_board_init(void) 352static void __init mxc_board_init(void)
317{ 353{
318 struct pad_desc usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; 354 iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP;
319 struct pad_desc power_key = MX51_PAD_EIM_A27__GPIO_2_21; 355 iomux_v3_cfg_t power_key = _MX51_PAD_EIM_A27__GPIO2_21 |
356 MUX_PAD_CTRL(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP);
320 357
321#if defined(CONFIG_CPU_FREQ_IMX) 358#if defined(CONFIG_CPU_FREQ_IMX)
322 get_cpu_op = mx51_get_cpu_op; 359 get_cpu_op = mx51_get_cpu_op;
@@ -328,8 +365,7 @@ static void __init mxc_board_init(void)
328 imx51_add_fec(NULL); 365 imx51_add_fec(NULL);
329 366
330 /* Set the PAD settings for the pwr key. */ 367 /* Set the PAD settings for the pwr key. */
331 power_key.pad_ctrl = MX51_GPIO_PAD_CTRL_2; 368 mxc_iomux_v3_setup_pad(power_key);
332 mxc_iomux_v3_setup_pad(&power_key);
333 imx51_add_gpio_keys(&imx_button_data); 369 imx51_add_gpio_keys(&imx_button_data);
334 370
335 imx51_add_imx_i2c(0, &babbage_i2c_data); 371 imx51_add_imx_i2c(0, &babbage_i2c_data);
@@ -346,11 +382,16 @@ static void __init mxc_board_init(void)
346 gpio_usbh1_active(); 382 gpio_usbh1_active();
347 mxc_register_device(&mxc_usbh1_device, &usbh1_config); 383 mxc_register_device(&mxc_usbh1_device, &usbh1_config);
348 /* setback USBH1_STP to be function */ 384 /* setback USBH1_STP to be function */
349 mxc_iomux_v3_setup_pad(&usbh1stp); 385 mxc_iomux_v3_setup_pad(usbh1stp);
350 babbage_usbhub_reset(); 386 babbage_usbhub_reset();
351 387
352 imx51_add_esdhc(0, NULL); 388 imx51_add_sdhci_esdhc_imx(0, NULL);
353 imx51_add_esdhc(1, NULL); 389 imx51_add_sdhci_esdhc_imx(1, NULL);
390
391 spi_register_board_info(mx51_babbage_spi_board_info,
392 ARRAY_SIZE(mx51_babbage_spi_board_info));
393 imx51_add_ecspi(0, &mx51_babbage_spi_pdata);
394 imx51_add_imx2_wdt(0, NULL);
354} 395}
355 396
356static void __init mx51_babbage_timer_init(void) 397static void __init mx51_babbage_timer_init(void)
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index 6e623bda3ee7..b7946f8e8d40 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -18,9 +18,13 @@
18#include <linux/platform_device.h> 18#include <linux/platform_device.h>
19#include <linux/i2c.h> 19#include <linux/i2c.h>
20#include <linux/gpio.h> 20#include <linux/gpio.h>
21#include <linux/leds.h>
22#include <linux/input.h>
21#include <linux/delay.h> 23#include <linux/delay.h>
22#include <linux/io.h> 24#include <linux/io.h>
23#include <linux/fsl_devices.h> 25#include <linux/fsl_devices.h>
26#include <linux/spi/flash.h>
27#include <linux/spi/spi.h>
24 28
25#include <mach/common.h> 29#include <mach/common.h>
26#include <mach/hardware.h> 30#include <mach/hardware.h>
@@ -39,12 +43,81 @@
39 43
40#define MX51_USB_PLL_DIV_24_MHZ 0x01 44#define MX51_USB_PLL_DIV_24_MHZ 0x01
41 45
42static struct pad_desc mx51efikamx_pads[] = { 46#define EFIKAMX_PCBID0 IMX_GPIO_NR(3, 16)
47#define EFIKAMX_PCBID1 IMX_GPIO_NR(3, 17)
48#define EFIKAMX_PCBID2 IMX_GPIO_NR(3, 11)
49
50#define EFIKAMX_BLUE_LED IMX_GPIO_NR(3, 13)
51#define EFIKAMX_GREEN_LED IMX_GPIO_NR(3, 14)
52#define EFIKAMX_RED_LED IMX_GPIO_NR(3, 15)
53
54#define EFIKAMX_POWER_KEY IMX_GPIO_NR(2, 31)
55
56#define EFIKAMX_SPI_CS0 IMX_GPIO_NR(4, 24)
57#define EFIKAMX_SPI_CS1 IMX_GPIO_NR(4, 25)
58
59/* board 1.1 doesn't have same reset gpio */
60#define EFIKAMX_RESET1_1 IMX_GPIO_NR(3, 2)
61#define EFIKAMX_RESET IMX_GPIO_NR(1, 4)
62
63/* the pci ids pin have pull up. they're driven low according to board id */
64#define MX51_PAD_PCBID0 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
65#define MX51_PAD_PCBID1 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
66#define MX51_PAD_PCBID2 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, PAD_CTL_PUS_100K_UP)
67#define MX51_PAD_PWRKEY IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, PAD_CTL_PUS_100K_UP | PAD_CTL_PKE)
68
69static iomux_v3_cfg_t mx51efikamx_pads[] = {
43 /* UART1 */ 70 /* UART1 */
44 MX51_PAD_UART1_RXD__UART1_RXD, 71 MX51_PAD_UART1_RXD__UART1_RXD,
45 MX51_PAD_UART1_TXD__UART1_TXD, 72 MX51_PAD_UART1_TXD__UART1_TXD,
46 MX51_PAD_UART1_RTS__UART1_RTS, 73 MX51_PAD_UART1_RTS__UART1_RTS,
47 MX51_PAD_UART1_CTS__UART1_CTS, 74 MX51_PAD_UART1_CTS__UART1_CTS,
75 /* board id */
76 MX51_PAD_PCBID0,
77 MX51_PAD_PCBID1,
78 MX51_PAD_PCBID2,
79
80 /* SD 1 */
81 MX51_PAD_SD1_CMD__SD1_CMD,
82 MX51_PAD_SD1_CLK__SD1_CLK,
83 MX51_PAD_SD1_DATA0__SD1_DATA0,
84 MX51_PAD_SD1_DATA1__SD1_DATA1,
85 MX51_PAD_SD1_DATA2__SD1_DATA2,
86 MX51_PAD_SD1_DATA3__SD1_DATA3,
87
88 /* SD 2 */
89 MX51_PAD_SD2_CMD__SD2_CMD,
90 MX51_PAD_SD2_CLK__SD2_CLK,
91 MX51_PAD_SD2_DATA0__SD2_DATA0,
92 MX51_PAD_SD2_DATA1__SD2_DATA1,
93 MX51_PAD_SD2_DATA2__SD2_DATA2,
94 MX51_PAD_SD2_DATA3__SD2_DATA3,
95
96 /* SD/MMC WP/CD */
97 MX51_PAD_GPIO1_0__SD1_CD,
98 MX51_PAD_GPIO1_1__SD1_WP,
99 MX51_PAD_GPIO1_7__SD2_WP,
100 MX51_PAD_GPIO1_8__SD2_CD,
101
102 /* leds */
103 MX51_PAD_CSI1_D9__GPIO3_13,
104 MX51_PAD_CSI1_VSYNC__GPIO3_14,
105 MX51_PAD_CSI1_HSYNC__GPIO3_15,
106
107 /* power key */
108 MX51_PAD_PWRKEY,
109
110 /* spi */
111 MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
112 MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
113 MX51_PAD_CSPI1_SS0__GPIO4_24,
114 MX51_PAD_CSPI1_SS1__GPIO4_25,
115 MX51_PAD_CSPI1_RDY__ECSPI1_RDY,
116 MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
117
118 /* reset */
119 MX51_PAD_DI1_PIN13__GPIO3_2,
120 MX51_PAD_GPIO1_4__GPIO1_4,
48}; 121};
49 122
50/* Serial ports */ 123/* Serial ports */
@@ -75,6 +148,8 @@ static int initialize_otg_port(struct platform_device *pdev)
75 void __iomem *usb_base; 148 void __iomem *usb_base;
76 void __iomem *usbother_base; 149 void __iomem *usbother_base;
77 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 150 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
151 if (!usb_base)
152 return -ENOMEM;
78 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); 153 usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET);
79 154
80 /* Set the PHY clock to 19.2MHz */ 155 /* Set the PHY clock to 19.2MHz */
@@ -92,12 +167,182 @@ static struct mxc_usbh_platform_data dr_utmi_config = {
92 .flags = MXC_EHCI_INTERNAL_PHY, 167 .flags = MXC_EHCI_INTERNAL_PHY,
93}; 168};
94 169
170/* PCBID2 PCBID1 PCBID0 STATE
171 1 1 1 ER1:rev1.1
172 1 1 0 ER2:rev1.2
173 1 0 1 ER3:rev1.3
174 1 0 0 ER4:rev1.4
175*/
176static void __init mx51_efikamx_board_id(void)
177{
178 int id;
179
180 /* things are taking time to settle */
181 msleep(150);
182
183 gpio_request(EFIKAMX_PCBID0, "pcbid0");
184 gpio_direction_input(EFIKAMX_PCBID0);
185 gpio_request(EFIKAMX_PCBID1, "pcbid1");
186 gpio_direction_input(EFIKAMX_PCBID1);
187 gpio_request(EFIKAMX_PCBID2, "pcbid2");
188 gpio_direction_input(EFIKAMX_PCBID2);
189
190 id = gpio_get_value(EFIKAMX_PCBID0);
191 id |= gpio_get_value(EFIKAMX_PCBID1) << 1;
192 id |= gpio_get_value(EFIKAMX_PCBID2) << 2;
193
194 switch (id) {
195 case 7:
196 system_rev = 0x11;
197 break;
198 case 6:
199 system_rev = 0x12;
200 break;
201 case 5:
202 system_rev = 0x13;
203 break;
204 case 4:
205 system_rev = 0x14;
206 break;
207 default:
208 system_rev = 0x10;
209 break;
210 }
211
212 if ((system_rev == 0x10)
213 || (system_rev == 0x12)
214 || (system_rev == 0x14)) {
215 printk(KERN_WARNING
216 "EfikaMX: Unsupported board revision 1.%u!\n",
217 system_rev & 0xf);
218 }
219}
220
221static struct gpio_led mx51_efikamx_leds[] = {
222 {
223 .name = "efikamx:green",
224 .default_trigger = "default-on",
225 .gpio = EFIKAMX_GREEN_LED,
226 },
227 {
228 .name = "efikamx:red",
229 .default_trigger = "ide-disk",
230 .gpio = EFIKAMX_RED_LED,
231 },
232 {
233 .name = "efikamx:blue",
234 .default_trigger = "mmc0",
235 .gpio = EFIKAMX_BLUE_LED,
236 },
237};
238
239static struct gpio_led_platform_data mx51_efikamx_leds_data = {
240 .leds = mx51_efikamx_leds,
241 .num_leds = ARRAY_SIZE(mx51_efikamx_leds),
242};
243
244static struct platform_device mx51_efikamx_leds_device = {
245 .name = "leds-gpio",
246 .id = -1,
247 .dev = {
248 .platform_data = &mx51_efikamx_leds_data,
249 },
250};
251
252static struct gpio_keys_button mx51_efikamx_powerkey[] = {
253 {
254 .code = KEY_POWER,
255 .gpio = EFIKAMX_POWER_KEY,
256 .type = EV_PWR,
257 .desc = "Power Button (CM)",
258 .wakeup = 1,
259 .debounce_interval = 10, /* ms */
260 },
261};
262
263static const struct gpio_keys_platform_data mx51_efikamx_powerkey_data __initconst = {
264 .buttons = mx51_efikamx_powerkey,
265 .nbuttons = ARRAY_SIZE(mx51_efikamx_powerkey),
266};
267
268static struct mtd_partition mx51_efikamx_spi_nor_partitions[] = {
269 {
270 .name = "u-boot",
271 .offset = 0,
272 .size = SZ_256K,
273 },
274 {
275 .name = "config",
276 .offset = MTDPART_OFS_APPEND,
277 .size = SZ_64K,
278 },
279};
280
281static struct flash_platform_data mx51_efikamx_spi_flash_data = {
282 .name = "spi_flash",
283 .parts = mx51_efikamx_spi_nor_partitions,
284 .nr_parts = ARRAY_SIZE(mx51_efikamx_spi_nor_partitions),
285 .type = "sst25vf032b",
286};
287
288static struct spi_board_info mx51_efikamx_spi_board_info[] __initdata = {
289 {
290 .modalias = "m25p80",
291 .max_speed_hz = 25000000,
292 .bus_num = 0,
293 .chip_select = 1,
294 .platform_data = &mx51_efikamx_spi_flash_data,
295 .irq = -1,
296 },
297};
298
299static int mx51_efikamx_spi_cs[] = {
300 EFIKAMX_SPI_CS0,
301 EFIKAMX_SPI_CS1,
302};
303
304static const struct spi_imx_master mx51_efikamx_spi_pdata __initconst = {
305 .chipselect = mx51_efikamx_spi_cs,
306 .num_chipselect = ARRAY_SIZE(mx51_efikamx_spi_cs),
307};
308
309void mx51_efikamx_reset(void)
310{
311 if (system_rev == 0x11)
312 gpio_direction_output(EFIKAMX_RESET1_1, 0);
313 else
314 gpio_direction_output(EFIKAMX_RESET, 0);
315}
316
95static void __init mxc_board_init(void) 317static void __init mxc_board_init(void)
96{ 318{
97 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads, 319 mxc_iomux_v3_setup_multiple_pads(mx51efikamx_pads,
98 ARRAY_SIZE(mx51efikamx_pads)); 320 ARRAY_SIZE(mx51efikamx_pads));
321 mx51_efikamx_board_id();
99 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config); 322 mxc_register_device(&mxc_usbdr_host_device, &dr_utmi_config);
100 mxc_init_imx_uart(); 323 mxc_init_imx_uart();
324 imx51_add_sdhci_esdhc_imx(0, NULL);
325
326 /* on < 1.2 boards both SD controllers are used */
327 if (system_rev < 0x12) {
328 imx51_add_sdhci_esdhc_imx(1, NULL);
329 mx51_efikamx_leds[2].default_trigger = "mmc1";
330 }
331
332 platform_device_register(&mx51_efikamx_leds_device);
333 imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
334
335 spi_register_board_info(mx51_efikamx_spi_board_info,
336 ARRAY_SIZE(mx51_efikamx_spi_board_info));
337 imx51_add_ecspi(0, &mx51_efikamx_spi_pdata);
338
339 if (system_rev == 0x11) {
340 gpio_request(EFIKAMX_RESET1_1, "reset");
341 gpio_direction_output(EFIKAMX_RESET1_1, 1);
342 } else {
343 gpio_request(EFIKAMX_RESET, "reset");
344 gpio_direction_output(EFIKAMX_RESET, 1);
345 }
101} 346}
102 347
103static void __init mx51_efikamx_timer_init(void) 348static void __init mx51_efikamx_timer_init(void)
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
new file mode 100644
index 000000000000..fa97d0d5dd05
--- /dev/null
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -0,0 +1,84 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
4 */
5
6/*
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21
22#include <linux/init.h>
23#include <linux/clk.h>
24#include <mach/common.h>
25#include <mach/hardware.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28#include <asm/mach/time.h>
29#include <mach/imx-uart.h>
30#include <mach/iomux-mx53.h>
31
32#include "crm_regs.h"
33#include "devices-imx53.h"
34
35static iomux_v3_cfg_t mx53_evk_pads[] = {
36 MX53_PAD_CSI0_D10__UART1_TXD,
37 MX53_PAD_CSI0_D11__UART1_RXD,
38 MX53_PAD_ATA_DIOW__UART1_TXD,
39 MX53_PAD_ATA_DMACK__UART1_RXD,
40
41 MX53_PAD_ATA_BUFFER_EN__UART2_RXD,
42 MX53_PAD_ATA_DMARQ__UART2_TXD,
43 MX53_PAD_ATA_DIOR__UART2_RTS,
44 MX53_PAD_ATA_INTRQ__UART2_CTS,
45
46 MX53_PAD_ATA_CS_0__UART3_TXD,
47 MX53_PAD_ATA_CS_1__UART3_RXD,
48 MX53_PAD_ATA_DA_1__UART3_CTS,
49 MX53_PAD_ATA_DA_2__UART3_RTS,
50};
51
52static const struct imxuart_platform_data mx53_evk_uart_pdata __initconst = {
53 .flags = IMXUART_HAVE_RTSCTS,
54};
55
56static inline void mx53_evk_init_uart(void)
57{
58 imx53_add_imx_uart(0, &mx53_evk_uart_pdata);
59 imx53_add_imx_uart(1, &mx53_evk_uart_pdata);
60 imx53_add_imx_uart(2, &mx53_evk_uart_pdata);
61}
62
63static void __init mx53_evk_board_init(void)
64{
65 mxc_iomux_v3_setup_multiple_pads(mx53_evk_pads,
66 ARRAY_SIZE(mx53_evk_pads));
67 mx53_evk_init_uart();
68}
69
70static void __init mx53_evk_timer_init(void)
71{
72 mx53_clocks_init(32768, 24000000, 22579200, 0);
73}
74
75static struct sys_timer mx53_evk_timer = {
76 .init = mx53_evk_timer_init,
77};
78
79MACHINE_START(MX53_EVK, "Freescale MX53 EVK Board")
80 .map_io = mx53_map_io,
81 .init_irq = mx53_init_irq,
82 .init_machine = mx53_evk_board_init,
83 .timer = &mx53_evk_timer,
84MACHINE_END
diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index 8ac36d882927..b21bc47d4827 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -33,11 +33,15 @@ static struct clk pll1_main_clk;
33static struct clk pll1_sw_clk; 33static struct clk pll1_sw_clk;
34static struct clk pll2_sw_clk; 34static struct clk pll2_sw_clk;
35static struct clk pll3_sw_clk; 35static struct clk pll3_sw_clk;
36static struct clk mx53_pll4_sw_clk;
36static struct clk lp_apm_clk; 37static struct clk lp_apm_clk;
37static struct clk periph_apm_clk; 38static struct clk periph_apm_clk;
38static struct clk ahb_clk; 39static struct clk ahb_clk;
39static struct clk ipg_clk; 40static struct clk ipg_clk;
40static struct clk usboh3_clk; 41static struct clk usboh3_clk;
42static struct clk emi_fast_clk;
43static struct clk ipu_clk;
44static struct clk mipi_hsc1_clk;
41 45
42#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */ 46#define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
43 47
@@ -123,7 +127,7 @@ static inline u32 _get_mux(struct clk *parent, struct clk *m0,
123 return -EINVAL; 127 return -EINVAL;
124} 128}
125 129
126static inline void __iomem *_get_pll_base(struct clk *pll) 130static inline void __iomem *_mx51_get_pll_base(struct clk *pll)
127{ 131{
128 if (pll == &pll1_main_clk) 132 if (pll == &pll1_main_clk)
129 return MX51_DPLL1_BASE; 133 return MX51_DPLL1_BASE;
@@ -137,6 +141,30 @@ static inline void __iomem *_get_pll_base(struct clk *pll)
137 return NULL; 141 return NULL;
138} 142}
139 143
144static inline void __iomem *_mx53_get_pll_base(struct clk *pll)
145{
146 if (pll == &pll1_main_clk)
147 return MX53_DPLL1_BASE;
148 else if (pll == &pll2_sw_clk)
149 return MX53_DPLL2_BASE;
150 else if (pll == &pll3_sw_clk)
151 return MX53_DPLL3_BASE;
152 else if (pll == &mx53_pll4_sw_clk)
153 return MX53_DPLL4_BASE;
154 else
155 BUG();
156
157 return NULL;
158}
159
160static inline void __iomem *_get_pll_base(struct clk *pll)
161{
162 if (cpu_is_mx51())
163 return _mx51_get_pll_base(pll);
164 else
165 return _mx53_get_pll_base(pll);
166}
167
140static unsigned long clk_pll_get_rate(struct clk *clk) 168static unsigned long clk_pll_get_rate(struct clk *clk)
141{ 169{
142 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs; 170 long mfi, mfn, mfd, pdf, ref_clk, mfn_abs;
@@ -514,7 +542,10 @@ static int _clk_max_enable(struct clk *clk)
514 542
515 /* Handshake with MAX when LPM is entered. */ 543 /* Handshake with MAX when LPM is entered. */
516 reg = __raw_readl(MXC_CCM_CLPCR); 544 reg = __raw_readl(MXC_CCM_CLPCR);
517 reg &= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; 545 if (cpu_is_mx51())
546 reg &= ~MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
547 else if (cpu_is_mx53())
548 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
518 __raw_writel(reg, MXC_CCM_CLPCR); 549 __raw_writel(reg, MXC_CCM_CLPCR);
519 550
520 return 0; 551 return 0;
@@ -528,7 +559,10 @@ static void _clk_max_disable(struct clk *clk)
528 559
529 /* No Handshake with MAX when LPM is entered as its disabled. */ 560 /* No Handshake with MAX when LPM is entered as its disabled. */
530 reg = __raw_readl(MXC_CCM_CLPCR); 561 reg = __raw_readl(MXC_CCM_CLPCR);
531 reg |= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS; 562 if (cpu_is_mx51())
563 reg |= MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS;
564 else if (cpu_is_mx53())
565 reg &= ~MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS;
532 __raw_writel(reg, MXC_CCM_CLPCR); 566 __raw_writel(reg, MXC_CCM_CLPCR);
533} 567}
534 568
@@ -679,6 +713,19 @@ static unsigned long clk_emi_slow_get_rate(struct clk *clk)
679 return clk_get_rate(clk->parent) / div; 713 return clk_get_rate(clk->parent) / div;
680} 714}
681 715
716static unsigned long _clk_ddr_hf_get_rate(struct clk *clk)
717{
718 unsigned long rate;
719 u32 reg, div;
720
721 reg = __raw_readl(MXC_CCM_CBCDR);
722 div = ((reg & MXC_CCM_CBCDR_DDR_PODF_MASK) >>
723 MXC_CCM_CBCDR_DDR_PODF_OFFSET) + 1;
724 rate = clk_get_rate(clk->parent) / div;
725
726 return rate;
727}
728
682/* External high frequency clock */ 729/* External high frequency clock */
683static struct clk ckih_clk = { 730static struct clk ckih_clk = {
684 .get_rate = get_high_reference_clock_rate, 731 .get_rate = get_high_reference_clock_rate,
@@ -739,6 +786,14 @@ static struct clk pll3_sw_clk = {
739 .disable = _clk_pll_disable, 786 .disable = _clk_pll_disable,
740}; 787};
741 788
789/* PLL4 SW supplies to LVDS Display Bridge(LDB) */
790static struct clk mx53_pll4_sw_clk = {
791 .parent = &osc_clk,
792 .set_rate = _clk_pll_set_rate,
793 .enable = _clk_pll_enable,
794 .disable = _clk_pll_disable,
795};
796
742/* Low-power Audio Playback Mode clock */ 797/* Low-power Audio Playback Mode clock */
743static struct clk lp_apm_clk = { 798static struct clk lp_apm_clk = {
744 .parent = &osc_clk, 799 .parent = &osc_clk,
@@ -763,6 +818,12 @@ static struct clk ahb_clk = {
763 .round_rate = _clk_ahb_round_rate, 818 .round_rate = _clk_ahb_round_rate,
764}; 819};
765 820
821static struct clk iim_clk = {
822 .parent = &ipg_clk,
823 .enable_reg = MXC_CCM_CCGR0,
824 .enable_shift = MXC_CCM_CCGRx_CG15_OFFSET,
825};
826
766/* Main IP interface clock for access to registers */ 827/* Main IP interface clock for access to registers */
767static struct clk ipg_clk = { 828static struct clk ipg_clk = {
768 .parent = &ahb_clk, 829 .parent = &ahb_clk,
@@ -810,6 +871,10 @@ static struct clk kpp_clk = {
810 .id = 0, 871 .id = 0,
811}; 872};
812 873
874static struct clk dummy_clk = {
875 .id = 0,
876};
877
813static struct clk emi_slow_clk = { 878static struct clk emi_slow_clk = {
814 .parent = &pll2_sw_clk, 879 .parent = &pll2_sw_clk,
815 .enable_reg = MXC_CCM_CCGR5, 880 .enable_reg = MXC_CCM_CCGR5,
@@ -819,6 +884,109 @@ static struct clk emi_slow_clk = {
819 .get_rate = clk_emi_slow_get_rate, 884 .get_rate = clk_emi_slow_get_rate,
820}; 885};
821 886
887static int clk_ipu_enable(struct clk *clk)
888{
889 u32 reg;
890
891 _clk_ccgr_enable(clk);
892
893 /* Enable handshake with IPU when certain clock rates are changed */
894 reg = __raw_readl(MXC_CCM_CCDR);
895 reg &= ~MXC_CCM_CCDR_IPU_HS_MASK;
896 __raw_writel(reg, MXC_CCM_CCDR);
897
898 /* Enable handshake with IPU when LPM is entered */
899 reg = __raw_readl(MXC_CCM_CLPCR);
900 reg &= ~MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
901 __raw_writel(reg, MXC_CCM_CLPCR);
902
903 return 0;
904}
905
906static void clk_ipu_disable(struct clk *clk)
907{
908 u32 reg;
909
910 _clk_ccgr_disable(clk);
911
912 /* Disable handshake with IPU whe dividers are changed */
913 reg = __raw_readl(MXC_CCM_CCDR);
914 reg |= MXC_CCM_CCDR_IPU_HS_MASK;
915 __raw_writel(reg, MXC_CCM_CCDR);
916
917 /* Disable handshake with IPU when LPM is entered */
918 reg = __raw_readl(MXC_CCM_CLPCR);
919 reg |= MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS;
920 __raw_writel(reg, MXC_CCM_CLPCR);
921}
922
923static struct clk ahbmux1_clk = {
924 .parent = &ahb_clk,
925 .secondary = &ahb_max_clk,
926 .enable_reg = MXC_CCM_CCGR0,
927 .enable_shift = MXC_CCM_CCGRx_CG8_OFFSET,
928 .enable = _clk_ccgr_enable,
929 .disable = _clk_ccgr_disable_inwait,
930};
931
932static struct clk ipu_sec_clk = {
933 .parent = &emi_fast_clk,
934 .secondary = &ahbmux1_clk,
935};
936
937static struct clk ddr_hf_clk = {
938 .parent = &pll1_sw_clk,
939 .get_rate = _clk_ddr_hf_get_rate,
940};
941
942static struct clk ddr_clk = {
943 .parent = &ddr_hf_clk,
944};
945
946/* clock definitions for MIPI HSC unit which has been removed
947 * from documentation, but not from hardware
948 */
949static int _clk_hsc_enable(struct clk *clk)
950{
951 u32 reg;
952
953 _clk_ccgr_enable(clk);
954 /* Handshake with IPU when certain clock rates are changed. */
955 reg = __raw_readl(MXC_CCM_CCDR);
956 reg &= ~MXC_CCM_CCDR_HSC_HS_MASK;
957 __raw_writel(reg, MXC_CCM_CCDR);
958
959 reg = __raw_readl(MXC_CCM_CLPCR);
960 reg &= ~MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
961 __raw_writel(reg, MXC_CCM_CLPCR);
962
963 return 0;
964}
965
966static void _clk_hsc_disable(struct clk *clk)
967{
968 u32 reg;
969
970 _clk_ccgr_disable(clk);
971 /* No handshake with HSC as its not enabled. */
972 reg = __raw_readl(MXC_CCM_CCDR);
973 reg |= MXC_CCM_CCDR_HSC_HS_MASK;
974 __raw_writel(reg, MXC_CCM_CCDR);
975
976 reg = __raw_readl(MXC_CCM_CLPCR);
977 reg |= MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS;
978 __raw_writel(reg, MXC_CCM_CLPCR);
979}
980
981static struct clk mipi_hsp_clk = {
982 .parent = &ipu_clk,
983 .enable_reg = MXC_CCM_CCGR4,
984 .enable_shift = MXC_CCM_CCGRx_CG6_OFFSET,
985 .enable = _clk_hsc_enable,
986 .disable = _clk_hsc_disable,
987 .secondary = &mipi_hsc1_clk,
988};
989
822#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \ 990#define DEFINE_CLOCK_CCGR(name, i, er, es, pfx, p, s) \
823 static struct clk name = { \ 991 static struct clk name = { \
824 .id = i, \ 992 .id = i, \
@@ -927,6 +1095,41 @@ static struct clk usboh3_clk = {
927 .parent = &pll2_sw_clk, 1095 .parent = &pll2_sw_clk,
928 .get_rate = clk_usboh3_get_rate, 1096 .get_rate = clk_usboh3_get_rate,
929 .set_parent = clk_usboh3_set_parent, 1097 .set_parent = clk_usboh3_set_parent,
1098 .enable = _clk_ccgr_enable,
1099 .disable = _clk_ccgr_disable,
1100 .enable_reg = MXC_CCM_CCGR2,
1101 .enable_shift = MXC_CCM_CCGRx_CG14_OFFSET,
1102};
1103
1104static struct clk usb_ahb_clk = {
1105 .parent = &ipg_clk,
1106 .enable = _clk_ccgr_enable,
1107 .disable = _clk_ccgr_disable,
1108 .enable_reg = MXC_CCM_CCGR2,
1109 .enable_shift = MXC_CCM_CCGRx_CG13_OFFSET,
1110};
1111
1112static int clk_usb_phy1_set_parent(struct clk *clk, struct clk *parent)
1113{
1114 u32 reg;
1115
1116 reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_USB_PHY_CLK_SEL;
1117
1118 if (parent == &pll3_sw_clk)
1119 reg |= 1 << MXC_CCM_CSCMR1_USB_PHY_CLK_SEL_OFFSET;
1120
1121 __raw_writel(reg, MXC_CCM_CSCMR1);
1122
1123 return 0;
1124}
1125
1126static struct clk usb_phy1_clk = {
1127 .parent = &pll3_sw_clk,
1128 .set_parent = clk_usb_phy1_set_parent,
1129 .enable = _clk_ccgr_enable,
1130 .enable_reg = MXC_CCM_CCGR2,
1131 .enable_shift = MXC_CCM_CCGRx_CG0_OFFSET,
1132 .disable = _clk_ccgr_disable,
930}; 1133};
931 1134
932/* eCSPI */ 1135/* eCSPI */
@@ -1013,6 +1216,10 @@ DEFINE_CLOCK(ssi2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG10_OFFSET,
1013 NULL, NULL, &ipg_clk, NULL); 1216 NULL, NULL, &ipg_clk, NULL);
1014DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET, 1217DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG11_OFFSET,
1015 NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk); 1218 NULL, NULL, &pll3_sw_clk, &ssi2_ipg_clk);
1219DEFINE_CLOCK(ssi3_ipg_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG12_OFFSET,
1220 NULL, NULL, &ipg_clk, NULL);
1221DEFINE_CLOCK(ssi3_clk, 2, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG13_OFFSET,
1222 NULL, NULL, &pll3_sw_clk, &ssi3_ipg_clk);
1016 1223
1017/* eCSPI */ 1224/* eCSPI */
1018DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET, 1225DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
@@ -1046,6 +1253,23 @@ DEFINE_CLOCK_FULL(esdhc2_ipg_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG2_OFFSET,
1046DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET, 1253DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1047 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk); 1254 clk_esdhc2, &pll2_sw_clk, &esdhc2_ipg_clk);
1048 1255
1256DEFINE_CLOCK(mipi_esc_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG5_OFFSET, NULL, NULL, NULL, &pll2_sw_clk);
1257DEFINE_CLOCK(mipi_hsc2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG4_OFFSET, NULL, NULL, &mipi_esc_clk, &pll2_sw_clk);
1258DEFINE_CLOCK(mipi_hsc1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG3_OFFSET, NULL, NULL, &mipi_hsc2_clk, &pll2_sw_clk);
1259
1260/* IPU */
1261DEFINE_CLOCK_FULL(ipu_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG5_OFFSET,
1262 NULL, NULL, clk_ipu_enable, clk_ipu_disable, &ahb_clk, &ipu_sec_clk);
1263
1264DEFINE_CLOCK_FULL(emi_fast_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG7_OFFSET,
1265 NULL, NULL, _clk_ccgr_enable, _clk_ccgr_disable_inwait,
1266 &ddr_clk, NULL);
1267
1268DEFINE_CLOCK(ipu_di0_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG5_OFFSET,
1269 NULL, NULL, &pll3_sw_clk, NULL);
1270DEFINE_CLOCK(ipu_di1_clk, 0, MXC_CCM_CCGR6, MXC_CCM_CCGRx_CG6_OFFSET,
1271 NULL, NULL, &pll3_sw_clk, NULL);
1272
1049#define _REGISTER_CLOCK(d, n, c) \ 1273#define _REGISTER_CLOCK(d, n, c) \
1050 { \ 1274 { \
1051 .dev_id = d, \ 1275 .dev_id = d, \
@@ -1053,7 +1277,7 @@ DEFINE_CLOCK_MAX(esdhc2_clk, 1, MXC_CCM_CCGR3, MXC_CCM_CCGRx_CG3_OFFSET,
1053 .clk = &c, \ 1277 .clk = &c, \
1054 }, 1278 },
1055 1279
1056static struct clk_lookup lookups[] = { 1280static struct clk_lookup mx51_lookups[] = {
1057 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk) 1281 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1058 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk) 1282 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1059 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk) 1283 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
@@ -1063,15 +1287,19 @@ static struct clk_lookup lookups[] = {
1063 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk) 1287 _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
1064 _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk) 1288 _REGISTER_CLOCK("imx-i2c.2", NULL, hsi2c_clk)
1065 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk) 1289 _REGISTER_CLOCK("mxc-ehci.0", "usb", usboh3_clk)
1066 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", ahb_clk) 1290 _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_ahb_clk)
1291 _REGISTER_CLOCK("mxc-ehci.0", "usb_phy1", usb_phy1_clk)
1067 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk) 1292 _REGISTER_CLOCK("mxc-ehci.1", "usb", usboh3_clk)
1068 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", ahb_clk) 1293 _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_ahb_clk)
1294 _REGISTER_CLOCK("mxc-ehci.2", "usb", usboh3_clk)
1295 _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_ahb_clk)
1069 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk) 1296 _REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
1070 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk) 1297 _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
1071 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk) 1298 _REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
1072 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk) 1299 _REGISTER_CLOCK("mxc_nand", NULL, nfc_clk)
1073 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk) 1300 _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
1074 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk) 1301 _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
1302 _REGISTER_CLOCK("imx-ssi.2", NULL, ssi3_clk)
1075 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk) 1303 _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
1076 _REGISTER_CLOCK(NULL, "ckih", ckih_clk) 1304 _REGISTER_CLOCK(NULL, "ckih", ckih_clk)
1077 _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk) 1305 _REGISTER_CLOCK(NULL, "ckih2", ckih2_clk)
@@ -1082,6 +1310,22 @@ static struct clk_lookup lookups[] = {
1082 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk) 1310 _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
1083 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk) 1311 _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
1084 _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk) 1312 _REGISTER_CLOCK(NULL, "cpu_clk", cpu_clk)
1313 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1314 _REGISTER_CLOCK("imx2-wdt.0", NULL, dummy_clk)
1315 _REGISTER_CLOCK("imx2-wdt.1", NULL, dummy_clk)
1316 _REGISTER_CLOCK(NULL, "mipi_hsp", mipi_hsp_clk)
1317 _REGISTER_CLOCK("imx-ipuv3", NULL, ipu_clk)
1318 _REGISTER_CLOCK("imx-ipuv3", "di0", ipu_di0_clk)
1319 _REGISTER_CLOCK("imx-ipuv3", "di1", ipu_di1_clk)
1320};
1321
1322static struct clk_lookup mx53_lookups[] = {
1323 _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
1324 _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
1325 _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
1326 _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
1327 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
1328 _REGISTER_CLOCK(NULL, "iim_clk", iim_clk)
1085}; 1329};
1086 1330
1087static void clk_tree_init(void) 1331static void clk_tree_init(void)
@@ -1114,14 +1358,22 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1114 ckih2_reference = ckih2; 1358 ckih2_reference = ckih2;
1115 oscillator_reference = osc; 1359 oscillator_reference = osc;
1116 1360
1117 for (i = 0; i < ARRAY_SIZE(lookups); i++) 1361 for (i = 0; i < ARRAY_SIZE(mx51_lookups); i++)
1118 clkdev_add(&lookups[i]); 1362 clkdev_add(&mx51_lookups[i]);
1119 1363
1120 clk_tree_init(); 1364 clk_tree_init();
1121 1365
1366 clk_set_parent(&uart_root_clk, &pll3_sw_clk);
1122 clk_enable(&cpu_clk); 1367 clk_enable(&cpu_clk);
1123 clk_enable(&main_bus_clk); 1368 clk_enable(&main_bus_clk);
1124 1369
1370 clk_enable(&iim_clk);
1371 mx51_revision();
1372 clk_disable(&iim_clk);
1373
1374 /* move usb_phy_clk to 24MHz */
1375 clk_set_parent(&usb_phy1_clk, &osc_clk);
1376
1125 /* set the usboh3_clk parent to pll2_sw_clk */ 1377 /* set the usboh3_clk parent to pll2_sw_clk */
1126 clk_set_parent(&usboh3_clk, &pll2_sw_clk); 1378 clk_set_parent(&usboh3_clk, &pll2_sw_clk);
1127 1379
@@ -1138,3 +1390,31 @@ int __init mx51_clocks_init(unsigned long ckil, unsigned long osc,
1138 MX51_MXC_INT_GPT); 1390 MX51_MXC_INT_GPT);
1139 return 0; 1391 return 0;
1140} 1392}
1393
1394int __init mx53_clocks_init(unsigned long ckil, unsigned long osc,
1395 unsigned long ckih1, unsigned long ckih2)
1396{
1397 int i;
1398
1399 external_low_reference = ckil;
1400 external_high_reference = ckih1;
1401 ckih2_reference = ckih2;
1402 oscillator_reference = osc;
1403
1404 for (i = 0; i < ARRAY_SIZE(mx53_lookups); i++)
1405 clkdev_add(&mx53_lookups[i]);
1406
1407 clk_tree_init();
1408
1409 clk_enable(&cpu_clk);
1410 clk_enable(&main_bus_clk);
1411
1412 clk_enable(&iim_clk);
1413 mx53_revision();
1414 clk_disable(&iim_clk);
1415
1416 /* System timer */
1417 mxc_timer_init(&gpt_clk, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
1418 MX53_INT_GPT);
1419 return 0;
1420}
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index eaacb6e9b5d0..d40671da4372 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 5 * License. You may obtain a copy of the GNU General Public License
@@ -20,37 +20,18 @@
20 20
21static int cpu_silicon_rev = -1; 21static int cpu_silicon_rev = -1;
22 22
23#define SI_REV 0x48 23#define IIM_SREV 0x24
24 24
25static void query_silicon_parameter(void) 25static int get_mx51_srev(void)
26{ 26{
27 void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE); 27 void __iomem *iim_base = MX51_IO_ADDRESS(MX51_IIM_BASE_ADDR);
28 u32 rev; 28 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
29 29
30 if (!rom) { 30 if (rev == 0x0)
31 cpu_silicon_rev = -EINVAL; 31 return IMX_CHIP_REVISION_2_0;
32 return; 32 else if (rev == 0x10)
33 } 33 return IMX_CHIP_REVISION_3_0;
34 34 return 0;
35 rev = readl(rom + SI_REV);
36 switch (rev) {
37 case 0x1:
38 cpu_silicon_rev = MX51_CHIP_REV_1_0;
39 break;
40 case 0x2:
41 cpu_silicon_rev = MX51_CHIP_REV_1_1;
42 break;
43 case 0x10:
44 cpu_silicon_rev = MX51_CHIP_REV_2_0;
45 break;
46 case 0x20:
47 cpu_silicon_rev = MX51_CHIP_REV_3_0;
48 break;
49 default:
50 cpu_silicon_rev = 0;
51 }
52
53 iounmap(rom);
54} 35}
55 36
56/* 37/*
@@ -64,7 +45,7 @@ int mx51_revision(void)
64 return -EINVAL; 45 return -EINVAL;
65 46
66 if (cpu_silicon_rev == -1) 47 if (cpu_silicon_rev == -1)
67 query_silicon_parameter(); 48 cpu_silicon_rev = get_mx51_srev();
68 49
69 return cpu_silicon_rev; 50 return cpu_silicon_rev;
70} 51}
@@ -79,7 +60,10 @@ EXPORT_SYMBOL(mx51_revision);
79 */ 60 */
80static int __init mx51_neon_fixup(void) 61static int __init mx51_neon_fixup(void)
81{ 62{
82 if (mx51_revision() < MX51_CHIP_REV_3_0 && (elf_hwcap & HWCAP_NEON)) { 63 if (!cpu_is_mx51())
64 return 0;
65
66 if (mx51_revision() < IMX_CHIP_REVISION_3_0 && (elf_hwcap & HWCAP_NEON)) {
83 elf_hwcap &= ~HWCAP_NEON; 67 elf_hwcap &= ~HWCAP_NEON;
84 pr_info("Turning off NEON support, detected broken NEON implementation\n"); 68 pr_info("Turning off NEON support, detected broken NEON implementation\n");
85 } 69 }
@@ -89,29 +73,65 @@ static int __init mx51_neon_fixup(void)
89late_initcall(mx51_neon_fixup); 73late_initcall(mx51_neon_fixup);
90#endif 74#endif
91 75
76static int get_mx53_srev(void)
77{
78 void __iomem *iim_base = MX51_IO_ADDRESS(MX53_IIM_BASE_ADDR);
79 u32 rev = readl(iim_base + IIM_SREV) & 0xff;
80
81 if (rev == 0x0)
82 return IMX_CHIP_REVISION_1_0;
83 else if (rev == 0x10)
84 return IMX_CHIP_REVISION_2_0;
85 return 0;
86}
87
88/*
89 * Returns:
90 * the silicon revision of the cpu
91 * -EINVAL - not a mx53
92 */
93int mx53_revision(void)
94{
95 if (!cpu_is_mx53())
96 return -EINVAL;
97
98 if (cpu_silicon_rev == -1)
99 cpu_silicon_rev = get_mx53_srev();
100
101 return cpu_silicon_rev;
102}
103EXPORT_SYMBOL(mx53_revision);
104
92static int __init post_cpu_init(void) 105static int __init post_cpu_init(void)
93{ 106{
94 unsigned int reg; 107 unsigned int reg;
95 void __iomem *base; 108 void __iomem *base;
96 109
97 if (!cpu_is_mx51()) 110 if (cpu_is_mx51() || cpu_is_mx53()) {
98 return 0; 111 if (cpu_is_mx51())
99 112 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
100 base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR); 113 else
101 __raw_writel(0x0, base + 0x40); 114 base = MX53_IO_ADDRESS(MX53_AIPS1_BASE_ADDR);
102 __raw_writel(0x0, base + 0x44); 115
103 __raw_writel(0x0, base + 0x48); 116 __raw_writel(0x0, base + 0x40);
104 __raw_writel(0x0, base + 0x4C); 117 __raw_writel(0x0, base + 0x44);
105 reg = __raw_readl(base + 0x50) & 0x00FFFFFF; 118 __raw_writel(0x0, base + 0x48);
106 __raw_writel(reg, base + 0x50); 119 __raw_writel(0x0, base + 0x4C);
107 120 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
108 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR); 121 __raw_writel(reg, base + 0x50);
109 __raw_writel(0x0, base + 0x40); 122
110 __raw_writel(0x0, base + 0x44); 123 if (cpu_is_mx51())
111 __raw_writel(0x0, base + 0x48); 124 base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
112 __raw_writel(0x0, base + 0x4C); 125 else
113 reg = __raw_readl(base + 0x50) & 0x00FFFFFF; 126 base = MX53_IO_ADDRESS(MX53_AIPS2_BASE_ADDR);
114 __raw_writel(reg, base + 0x50); 127
128 __raw_writel(0x0, base + 0x40);
129 __raw_writel(0x0, base + 0x44);
130 __raw_writel(0x0, base + 0x48);
131 __raw_writel(0x0, base + 0x4C);
132 reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
133 __raw_writel(reg, base + 0x50);
134 }
115 135
116 return 0; 136 return 0;
117} 137}
diff --git a/arch/arm/mach-mx5/crm_regs.h b/arch/arm/mach-mx5/crm_regs.h
index c776b9af0624..b462c22f53d8 100644
--- a/arch/arm/mach-mx5/crm_regs.h
+++ b/arch/arm/mach-mx5/crm_regs.h
@@ -18,6 +18,13 @@
18#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR) 18#define MX51_CORTEXA8_BASE MX51_IO_ADDRESS(MX51_ARM_BASE_ADDR)
19#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR) 19#define MX51_GPC_BASE MX51_IO_ADDRESS(MX51_GPC_BASE_ADDR)
20 20
21/*MX53*/
22#define MX53_CCM_BASE MX53_IO_ADDRESS(MX53_CCM_BASE_ADDR)
23#define MX53_DPLL1_BASE MX53_IO_ADDRESS(MX53_PLL1_BASE_ADDR)
24#define MX53_DPLL2_BASE MX53_IO_ADDRESS(MX53_PLL2_BASE_ADDR)
25#define MX53_DPLL3_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
26#define MX53_DPLL4_BASE MX53_IO_ADDRESS(MX53_PLL3_BASE_ADDR)
27
21/* PLL Register Offsets */ 28/* PLL Register Offsets */
22#define MXC_PLL_DP_CTL 0x00 29#define MXC_PLL_DP_CTL 0x00
23#define MXC_PLL_DP_CONFIG 0x04 30#define MXC_PLL_DP_CONFIG 0x04
@@ -380,7 +387,8 @@
380/* Define the bits in register CLPCR */ 387/* Define the bits in register CLPCR */
381#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23) 388#define MXC_CCM_CLPCR_BYPASS_HSC_LPM_HS (0x1 << 23)
382#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22) 389#define MXC_CCM_CLPCR_BYPASS_SCC_LPM_HS (0x1 << 22)
383#define MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21) 390#define MX51_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 21)
391#define MX53_CCM_CLPCR_BYPASS_MAX_LPM_HS (0x1 << 25)
384#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20) 392#define MXC_CCM_CLPCR_BYPASS_SDMA_LPM_HS (0x1 << 20)
385#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19) 393#define MXC_CCM_CLPCR_BYPASS_EMI_LPM_HS (0x1 << 19)
386#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18) 394#define MXC_CCM_CLPCR_BYPASS_IPU_LPM_HS (0x1 << 18)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index 8c50cb5d05f5..6302e4670000 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -31,6 +31,11 @@ extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
31#define imx51_add_mxc_nand(pdata) \ 31#define imx51_add_mxc_nand(pdata) \
32 imx_add_mxc_nand(&imx51_mxc_nand_data, pdata) 32 imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
33 33
34extern const struct imx_sdhci_esdhc_imx_data
35imx51_sdhci_esdhc_imx_data[] __initconst;
36#define imx51_add_sdhci_esdhc_imx(id, pdata) \
37 imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
38
34extern const struct imx_spi_imx_data imx51_cspi_data __initconst; 39extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
35#define imx51_add_cspi(pdata) \ 40#define imx51_add_cspi(pdata) \
36 imx_add_spi_imx(&imx51_cspi_data, pdata) 41 imx_add_spi_imx(&imx51_cspi_data, pdata)
@@ -39,6 +44,6 @@ extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
39#define imx51_add_ecspi(id, pdata) \ 44#define imx51_add_ecspi(id, pdata) \
40 imx_add_spi_imx(&imx51_ecspi_data[id], pdata) 45 imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
41 46
42extern const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst; 47extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst;
43#define imx51_add_esdhc(id, pdata) \ 48#define imx51_add_imx2_wdt(id, pdata) \
44 imx_add_esdhc(&imx51_esdhc_data[id], pdata) 49 imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
new file mode 100644
index 000000000000..9d0ec2507fa6
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -0,0 +1,13 @@
1/*
2 * Copyright (C) 2010 Yong Shen. <Yong.Shen@linaro.org>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8#include <mach/mx53.h>
9#include <mach/devices-common.h>
10
11extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst;
12#define imx53_add_imx_uart(id, pdata) \
13 imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-mx50.h b/arch/arm/mach-mx5/devices-mx50.h
new file mode 100644
index 000000000000..98ab07468a0e
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-mx50.h
@@ -0,0 +1,26 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <mach/mx50.h>
22#include <mach/devices-common.h>
23
24extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
25#define imx50_add_imx_uart(id, pdata) \
26 imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices.c b/arch/arm/mach-mx5/devices.c
index 4c7be87a7c9d..1bda5cb339dc 100644
--- a/arch/arm/mach-mx5/devices.c
+++ b/arch/arm/mach-mx5/devices.c
@@ -97,19 +97,27 @@ struct platform_device mxc_usbh1_device = {
97 }, 97 },
98}; 98};
99 99
100static struct resource mxc_wdt_resources[] = { 100static struct resource usbh2_resources[] = {
101 { 101 {
102 .start = MX51_WDOG_BASE_ADDR, 102 .start = MX51_OTG_BASE_ADDR + 0x400,
103 .end = MX51_WDOG_BASE_ADDR + SZ_16K - 1, 103 .end = MX51_OTG_BASE_ADDR + 0x400 + 0x1ff,
104 .flags = IORESOURCE_MEM, 104 .flags = IORESOURCE_MEM,
105 }, 105 },
106 {
107 .start = MX51_MXC_INT_USB_H2,
108 .flags = IORESOURCE_IRQ,
109 },
106}; 110};
107 111
108struct platform_device mxc_wdt = { 112struct platform_device mxc_usbh2_device = {
109 .name = "imx2-wdt", 113 .name = "mxc-ehci",
110 .id = 0, 114 .id = 2,
111 .num_resources = ARRAY_SIZE(mxc_wdt_resources), 115 .num_resources = ARRAY_SIZE(usbh2_resources),
112 .resource = mxc_wdt_resources, 116 .resource = usbh2_resources,
117 .dev = {
118 .dma_mask = &usb_dma_mask,
119 .coherent_dma_mask = DMA_BIT_MASK(32),
120 },
113}; 121};
114 122
115static struct resource mxc_kpp_resources[] = { 123static struct resource mxc_kpp_resources[] = {
@@ -160,9 +168,36 @@ static struct mxc_gpio_port mxc_gpio_ports[] = {
160 .irq_high = MX51_MXC_INT_GPIO4_HIGH, 168 .irq_high = MX51_MXC_INT_GPIO4_HIGH,
161 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3 169 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 3
162 }, 170 },
171 {
172 .chip.label = "gpio-4",
173 .base = MX53_IO_ADDRESS(MX53_GPIO5_BASE_ADDR),
174 .irq = MX53_INT_GPIO5_LOW,
175 .irq_high = MX53_INT_GPIO5_HIGH,
176 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 4
177 },
178 {
179 .chip.label = "gpio-5",
180 .base = MX53_IO_ADDRESS(MX53_GPIO6_BASE_ADDR),
181 .irq = MX53_INT_GPIO6_LOW,
182 .irq_high = MX53_INT_GPIO6_HIGH,
183 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 5
184 },
185 {
186 .chip.label = "gpio-6",
187 .base = MX53_IO_ADDRESS(MX53_GPIO7_BASE_ADDR),
188 .irq = MX53_INT_GPIO7_LOW,
189 .irq_high = MX53_INT_GPIO7_HIGH,
190 .virtual_irq_start = MXC_GPIO_IRQ_START + 32 * 6
191 },
163}; 192};
164 193
165int __init imx51_register_gpios(void) 194int __init imx51_register_gpios(void)
166{ 195{
196 return mxc_gpio_init(mxc_gpio_ports, 4);
197}
198
199int __init imx53_register_gpios(void)
200{
167 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports)); 201 return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
168} 202}
203
diff --git a/arch/arm/mach-mx5/devices.h b/arch/arm/mach-mx5/devices.h
index af1d07c0bbc1..16891aa3573c 100644
--- a/arch/arm/mach-mx5/devices.h
+++ b/arch/arm/mach-mx5/devices.h
@@ -1,6 +1,6 @@
1extern struct platform_device mxc_usbdr_host_device; 1extern struct platform_device mxc_usbdr_host_device;
2extern struct platform_device mxc_usbh1_device; 2extern struct platform_device mxc_usbh1_device;
3extern struct platform_device mxc_usbh2_device;
3extern struct platform_device mxc_usbdr_udc_device; 4extern struct platform_device mxc_usbdr_udc_device;
4extern struct platform_device mxc_wdt;
5extern struct platform_device mxc_hsi2c_device; 5extern struct platform_device mxc_hsi2c_device;
6extern struct platform_device mxc_keypad_device; 6extern struct platform_device mxc_keypad_device;
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index a2e6e8c39d25..c96d018ff8a2 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -33,12 +33,12 @@
33#include "devices-imx51.h" 33#include "devices-imx51.h"
34#include "devices.h" 34#include "devices.h"
35 35
36#define MBIMX51_TSC2007_GPIO (2*32 + 30) 36#define MBIMX51_TSC2007_GPIO IMX_GPIO_NR(3, 30)
37#define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO) 37#define MBIMX51_TSC2007_IRQ (MXC_INTERNAL_IRQS + MBIMX51_TSC2007_GPIO)
38#define MBIMX51_LED0 (2*32 + 5) 38#define MBIMX51_LED0 IMX_GPIO_NR(3, 5)
39#define MBIMX51_LED1 (2*32 + 6) 39#define MBIMX51_LED1 IMX_GPIO_NR(3, 6)
40#define MBIMX51_LED2 (2*32 + 7) 40#define MBIMX51_LED2 IMX_GPIO_NR(3, 7)
41#define MBIMX51_LED3 (2*32 + 8) 41#define MBIMX51_LED3 IMX_GPIO_NR(3, 8)
42 42
43static struct gpio_led mbimx51_leds[] = { 43static struct gpio_led mbimx51_leds[] = {
44 { 44 {
@@ -84,7 +84,7 @@ static struct platform_device *devices[] __initdata = {
84 &mbimx51_leds_gpio, 84 &mbimx51_leds_gpio,
85}; 85};
86 86
87static struct pad_desc mbimx51_pads[] = { 87static iomux_v3_cfg_t mbimx51_pads[] = {
88 /* UART2 */ 88 /* UART2 */
89 MX51_PAD_UART2_RXD__UART2_RXD, 89 MX51_PAD_UART2_RXD__UART2_RXD,
90 MX51_PAD_UART2_TXD__UART2_TXD, 90 MX51_PAD_UART2_TXD__UART2_TXD,
@@ -96,13 +96,13 @@ static struct pad_desc mbimx51_pads[] = {
96 MX51_PAD_KEY_COL5__UART3_CTS, 96 MX51_PAD_KEY_COL5__UART3_CTS,
97 97
98 /* TSC2007 IRQ */ 98 /* TSC2007 IRQ */
99 MX51_PAD_NANDF_D10__GPIO_3_30, 99 MX51_PAD_NANDF_D10__GPIO3_30,
100 100
101 /* LEDS */ 101 /* LEDS */
102 MX51_PAD_DISPB2_SER_DIN__GPIO_3_5, 102 MX51_PAD_DISPB2_SER_DIN__GPIO3_5,
103 MX51_PAD_DISPB2_SER_DIO__GPIO_3_6, 103 MX51_PAD_DISPB2_SER_DIO__GPIO3_6,
104 MX51_PAD_DISPB2_SER_CLK__GPIO_3_7, 104 MX51_PAD_DISPB2_SER_CLK__GPIO3_7,
105 MX51_PAD_DISPB2_SER_RS__GPIO_3_8, 105 MX51_PAD_DISPB2_SER_RS__GPIO3_8,
106 106
107 /* KPP */ 107 /* KPP */
108 MX51_PAD_KEY_ROW0__KEY_ROW0, 108 MX51_PAD_KEY_ROW0__KEY_ROW0,
@@ -217,6 +217,6 @@ void __init eukrea_mbimx51_baseboard_init(void)
217 i2c_register_board_info(1, mbimx51_i2c_devices, 217 i2c_register_board_info(1, mbimx51_i2c_devices,
218 ARRAY_SIZE(mbimx51_i2c_devices)); 218 ARRAY_SIZE(mbimx51_i2c_devices));
219 219
220 imx51_add_esdhc(0, NULL); 220 imx51_add_sdhci_esdhc_imx(0, NULL);
221 imx51_add_esdhc(1, NULL); 221 imx51_add_sdhci_esdhc_imx(1, NULL);
222} 222}
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
index 2b48f5190830..c372a4373691 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -45,14 +45,13 @@
45#include "devices-imx51.h" 45#include "devices-imx51.h"
46#include "devices.h" 46#include "devices.h"
47 47
48#define MBIMXSD_GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, \ 48static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
49 MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP)
50
51static struct pad_desc eukrea_mbimxsd_pads[] = {
52 /* LED */ 49 /* LED */
53 MX51_PAD_NANDF_D10__GPIO_3_30, 50 MX51_PAD_NANDF_D10__GPIO3_30,
54 /* SWITCH */ 51 /* SWITCH */
55 MBIMXSD_GPIO_3_31, 52 _MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP |
53 PAD_CTL_PKE | PAD_CTL_SRE_FAST |
54 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS),
56 /* UART2 */ 55 /* UART2 */
57 MX51_PAD_UART2_RXD__UART2_RXD, 56 MX51_PAD_UART2_RXD__UART2_RXD,
58 MX51_PAD_UART2_TXD__UART2_TXD, 57 MX51_PAD_UART2_TXD__UART2_TXD,
@@ -70,8 +69,8 @@ static struct pad_desc eukrea_mbimxsd_pads[] = {
70 MX51_PAD_SD1_DATA3__SD1_DATA3, 69 MX51_PAD_SD1_DATA3__SD1_DATA3,
71}; 70};
72 71
73#define GPIO_LED1 (2 * 32 + 30) 72#define GPIO_LED1 IMX_GPIO_NR(3, 30)
74#define GPIO_SWITCH1 (2 * 32 + 31) 73#define GPIO_SWITCH1 IMX_GPIO_NR(3, 31)
75 74
76static struct gpio_led eukrea_mbimxsd_leds[] = { 75static struct gpio_led eukrea_mbimxsd_leds[] = {
77 { 76 {
@@ -149,7 +148,7 @@ void __init eukrea_mbimxsd51_baseboard_init(void)
149 imx51_add_imx_uart(1, NULL); 148 imx51_add_imx_uart(1, NULL);
150 imx51_add_imx_uart(2, &uart_pdata); 149 imx51_add_imx_uart(2, &uart_pdata);
151 150
152 imx51_add_esdhc(0, NULL); 151 imx51_add_sdhci_esdhc_imx(0, NULL);
153 152
154 gpio_request(GPIO_LED1, "LED1"); 153 gpio_request(GPIO_LED1, "LED1");
155 gpio_direction_output(GPIO_LED1, 1); 154 gpio_direction_output(GPIO_LED1, 1);
diff --git a/arch/arm/mach-mx5/mm-mx50.c b/arch/arm/mach-mx5/mm-mx50.c
new file mode 100644
index 000000000000..8c6540e58390
--- /dev/null
+++ b/arch/arm/mach-mx5/mm-mx50.c
@@ -0,0 +1,59 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 * Create static mapping between physical to virtual memory.
19 */
20
21#include <linux/mm.h>
22#include <linux/init.h>
23
24#include <asm/mach/map.h>
25
26#include <mach/hardware.h>
27#include <mach/common.h>
28#include <mach/iomux-v3.h>
29
30/*
31 * Define the MX50 memory map.
32 */
33static struct map_desc mx50_io_desc[] __initdata = {
34 imx_map_entry(MX50, TZIC, MT_DEVICE),
35 imx_map_entry(MX50, SPBA0, MT_DEVICE),
36 imx_map_entry(MX50, AIPS1, MT_DEVICE),
37 imx_map_entry(MX50, AIPS2, MT_DEVICE),
38};
39
40/*
41 * This function initializes the memory map. It is called during the
42 * system startup to create static physical to virtual memory mappings
43 * for the IO modules.
44 */
45void __init mx50_map_io(void)
46{
47 mxc_set_cpu_type(MXC_CPU_MX50);
48 mxc_iomux_v3_init(MX50_IO_ADDRESS(MX50_IOMUXC_BASE_ADDR));
49 mxc_arch_reset_init(MX50_IO_ADDRESS(MX50_WDOG_BASE_ADDR));
50 iotable_init(mx50_io_desc, ARRAY_SIZE(mx50_io_desc));
51}
52
53int imx50_register_gpios(void);
54
55void __init mx50_init_irq(void)
56{
57 tzic_init_irq(MX50_IO_ADDRESS(MX50_TZIC_BASE_ADDR));
58 imx50_register_gpios();
59}
diff --git a/arch/arm/mach-mx5/mm.c b/arch/arm/mach-mx5/mm.c
index bc3f30db8d9a..457f9f95204b 100644
--- a/arch/arm/mach-mx5/mm.c
+++ b/arch/arm/mach-mx5/mm.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * 3 *
4 * The code contained herein is licensed under the GNU General Public 4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License 5 * License. You may obtain a copy of the GNU General Public License
@@ -23,33 +23,21 @@
23/* 23/*
24 * Define the MX51 memory map. 24 * Define the MX51 memory map.
25 */ 25 */
26static struct map_desc mxc_io_desc[] __initdata = { 26static struct map_desc mx51_io_desc[] __initdata = {
27 { 27 imx_map_entry(MX51, IRAM, MT_DEVICE),
28 .virtual = MX51_IRAM_BASE_ADDR_VIRT, 28 imx_map_entry(MX51, DEBUG, MT_DEVICE),
29 .pfn = __phys_to_pfn(MX51_IRAM_BASE_ADDR), 29 imx_map_entry(MX51, AIPS1, MT_DEVICE),
30 .length = MX51_IRAM_SIZE, 30 imx_map_entry(MX51, SPBA0, MT_DEVICE),
31 .type = MT_DEVICE 31 imx_map_entry(MX51, AIPS2, MT_DEVICE),
32 }, { 32};
33 .virtual = MX51_DEBUG_BASE_ADDR_VIRT, 33
34 .pfn = __phys_to_pfn(MX51_DEBUG_BASE_ADDR), 34/*
35 .length = MX51_DEBUG_SIZE, 35 * Define the MX53 memory map.
36 .type = MT_DEVICE 36 */
37 }, { 37static struct map_desc mx53_io_desc[] __initdata = {
38 .virtual = MX51_AIPS1_BASE_ADDR_VIRT, 38 imx_map_entry(MX53, AIPS1, MT_DEVICE),
39 .pfn = __phys_to_pfn(MX51_AIPS1_BASE_ADDR), 39 imx_map_entry(MX53, SPBA0, MT_DEVICE),
40 .length = MX51_AIPS1_SIZE, 40 imx_map_entry(MX53, AIPS2, MT_DEVICE),
41 .type = MT_DEVICE
42 }, {
43 .virtual = MX51_SPBA0_BASE_ADDR_VIRT,
44 .pfn = __phys_to_pfn(MX51_SPBA0_BASE_ADDR),
45 .length = MX51_SPBA0_SIZE,
46 .type = MT_DEVICE
47 }, {
48 .virtual = MX51_AIPS2_BASE_ADDR_VIRT,
49 .pfn = __phys_to_pfn(MX51_AIPS2_BASE_ADDR),
50 .length = MX51_AIPS2_SIZE,
51 .type = MT_DEVICE
52 },
53}; 41};
54 42
55/* 43/*
@@ -61,8 +49,16 @@ void __init mx51_map_io(void)
61{ 49{
62 mxc_set_cpu_type(MXC_CPU_MX51); 50 mxc_set_cpu_type(MXC_CPU_MX51);
63 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR)); 51 mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
64 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG_BASE_ADDR)); 52 mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
65 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 53 iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
54}
55
56void __init mx53_map_io(void)
57{
58 mxc_set_cpu_type(MXC_CPU_MX53);
59 mxc_iomux_v3_init(MX53_IO_ADDRESS(MX53_IOMUXC_BASE_ADDR));
60 mxc_arch_reset_init(MX53_IO_ADDRESS(MX53_WDOG_BASE_ADDR));
61 iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
66} 62}
67 63
68int imx51_register_gpios(void); 64int imx51_register_gpios(void);
@@ -72,7 +68,7 @@ void __init mx51_init_irq(void)
72 unsigned long tzic_addr; 68 unsigned long tzic_addr;
73 void __iomem *tzic_virt; 69 void __iomem *tzic_virt;
74 70
75 if (mx51_revision() < MX51_CHIP_REV_2_0) 71 if (mx51_revision() < IMX_CHIP_REVISION_2_0)
76 tzic_addr = MX51_TZIC_BASE_ADDR_TO1; 72 tzic_addr = MX51_TZIC_BASE_ADDR_TO1;
77 else 73 else
78 tzic_addr = MX51_TZIC_BASE_ADDR; 74 tzic_addr = MX51_TZIC_BASE_ADDR;
@@ -84,3 +80,20 @@ void __init mx51_init_irq(void)
84 tzic_init_irq(tzic_virt); 80 tzic_init_irq(tzic_virt);
85 imx51_register_gpios(); 81 imx51_register_gpios();
86} 82}
83
84int imx53_register_gpios(void);
85
86void __init mx53_init_irq(void)
87{
88 unsigned long tzic_addr;
89 void __iomem *tzic_virt;
90
91 tzic_addr = MX53_TZIC_BASE_ADDR;
92
93 tzic_virt = ioremap(tzic_addr, SZ_16K);
94 if (!tzic_virt)
95 panic("unable to map TZIC interrupt controller\n");
96
97 tzic_init_irq(tzic_virt);
98 imx53_register_gpios();
99}
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
index aeccfd755fee..7652c301da88 100644
--- a/arch/arm/mach-mxc91231/mm.c
+++ b/arch/arm/mach-mxc91231/mm.c
@@ -27,48 +27,15 @@
27/* 27/*
28 * This structure defines the MXC memory map. 28 * This structure defines the MXC memory map.
29 */ 29 */
30static struct map_desc mxc_io_desc[] __initdata = { 30static struct map_desc mxc91231_io_desc[] __initdata = {
31 { 31 imx_map_entry(MXC91231, L2CC, MT_DEVICE),
32 .virtual = MXC91231_L2CC_BASE_ADDR_VIRT, 32 imx_map_entry(MXC91231, X_MEMC, MT_DEVICE),
33 .pfn = __phys_to_pfn(MXC91231_L2CC_BASE_ADDR), 33 imx_map_entry(MXC91231, ROMP, MT_DEVICE),
34 .length = MXC91231_L2CC_SIZE, 34 imx_map_entry(MXC91231, AVIC, MT_DEVICE),
35 .type = MT_DEVICE, 35 imx_map_entry(MXC91231, AIPS1, MT_DEVICE),
36 }, { 36 imx_map_entry(MXC91231, SPBA0, MT_DEVICE),
37 .virtual = MXC91231_X_MEMC_BASE_ADDR_VIRT, 37 imx_map_entry(MXC91231, SPBA1, MT_DEVICE),
38 .pfn = __phys_to_pfn(MXC91231_X_MEMC_BASE_ADDR), 38 imx_map_entry(MXC91231, AIPS2, MT_DEVICE),
39 .length = MXC91231_X_MEMC_SIZE,
40 .type = MT_DEVICE,
41 }, {
42 .virtual = MXC91231_ROMP_BASE_ADDR_VIRT,
43 .pfn = __phys_to_pfn(MXC91231_ROMP_BASE_ADDR),
44 .length = MXC91231_ROMP_SIZE,
45 .type = MT_DEVICE,
46 }, {
47 .virtual = MXC91231_AVIC_BASE_ADDR_VIRT,
48 .pfn = __phys_to_pfn(MXC91231_AVIC_BASE_ADDR),
49 .length = MXC91231_AVIC_SIZE,
50 .type = MT_DEVICE,
51 }, {
52 .virtual = MXC91231_AIPS1_BASE_ADDR_VIRT,
53 .pfn = __phys_to_pfn(MXC91231_AIPS1_BASE_ADDR),
54 .length = MXC91231_AIPS1_SIZE,
55 .type = MT_DEVICE,
56 }, {
57 .virtual = MXC91231_SPBA0_BASE_ADDR_VIRT,
58 .pfn = __phys_to_pfn(MXC91231_SPBA0_BASE_ADDR),
59 .length = MXC91231_SPBA0_SIZE,
60 .type = MT_DEVICE,
61 }, {
62 .virtual = MXC91231_SPBA1_BASE_ADDR_VIRT,
63 .pfn = __phys_to_pfn(MXC91231_SPBA1_BASE_ADDR),
64 .length = MXC91231_SPBA1_SIZE,
65 .type = MT_DEVICE,
66 }, {
67 .virtual = MXC91231_AIPS2_BASE_ADDR_VIRT,
68 .pfn = __phys_to_pfn(MXC91231_AIPS2_BASE_ADDR),
69 .length = MXC91231_AIPS2_SIZE,
70 .type = MT_DEVICE,
71 },
72}; 39};
73 40
74/* 41/*
@@ -80,7 +47,7 @@ void __init mxc91231_map_io(void)
80{ 47{
81 mxc_set_cpu_type(MXC_CPU_MXC91231); 48 mxc_set_cpu_type(MXC_CPU_MXC91231);
82 49
83 iotable_init(mxc_io_desc, ARRAY_SIZE(mxc_io_desc)); 50 iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
84} 51}
85 52
86int mxc91231_register_gpios(void); 53int mxc91231_register_gpios(void);
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
new file mode 100644
index 000000000000..c4ac7b415195
--- /dev/null
+++ b/arch/arm/mach-mxs/Kconfig
@@ -0,0 +1,34 @@
1if ARCH_MXS
2
3source "arch/arm/mach-mxs/devices/Kconfig"
4
5config SOC_IMX23
6 bool
7 select CPU_ARM926T
8
9config SOC_IMX28
10 bool
11 select CPU_ARM926T
12
13comment "MXS platforms:"
14
15config MACH_MX23EVK
16 bool "Support MX23EVK Platform"
17 select SOC_IMX23
18 select MXS_HAVE_PLATFORM_DUART
19 default y
20 help
21 Include support for MX23EVK platform. This includes specific
22 configurations for the board and its peripherals.
23
24config MACH_MX28EVK
25 bool "Support MX28EVK Platform"
26 select SOC_IMX28
27 select MXS_HAVE_PLATFORM_DUART
28 select MXS_HAVE_PLATFORM_FEC
29 default y
30 help
31 Include support for MX28EVK platform. This includes specific
32 configurations for the board and its peripherals.
33
34endif
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
new file mode 100644
index 000000000000..39d3f9c2a841
--- /dev/null
+++ b/arch/arm/mach-mxs/Makefile
@@ -0,0 +1,10 @@
1# Common support
2obj-y := clock.o devices.o gpio.o icoll.o iomux.o system.o timer.o
3
4obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
5obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
6
7obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
8obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
9
10obj-y += devices/
diff --git a/arch/arm/mach-mxs/Makefile.boot b/arch/arm/mach-mxs/Makefile.boot
new file mode 100644
index 000000000000..eb541e0291da
--- /dev/null
+++ b/arch/arm/mach-mxs/Makefile.boot
@@ -0,0 +1 @@
zreladdr-y := 0x40008000
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
new file mode 100644
index 000000000000..8f5a19ab558c
--- /dev/null
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -0,0 +1,526 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/mm.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/jiffies.h>
24
25#include <asm/clkdev.h>
26#include <asm/div64.h>
27
28#include <mach/mx23.h>
29#include <mach/common.h>
30#include <mach/clock.h>
31
32#include "regs-clkctrl-mx23.h"
33
34#define CLKCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
35#define DIGCTRL_BASE_ADDR MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
36
37#define PARENT_RATE_SHIFT 8
38
39static int _raw_clk_enable(struct clk *clk)
40{
41 u32 reg;
42
43 if (clk->enable_reg) {
44 reg = __raw_readl(clk->enable_reg);
45 reg &= ~(1 << clk->enable_shift);
46 __raw_writel(reg, clk->enable_reg);
47 }
48
49 return 0;
50}
51
52static void _raw_clk_disable(struct clk *clk)
53{
54 u32 reg;
55
56 if (clk->enable_reg) {
57 reg = __raw_readl(clk->enable_reg);
58 reg |= 1 << clk->enable_shift;
59 __raw_writel(reg, clk->enable_reg);
60 }
61}
62
63/*
64 * ref_xtal_clk
65 */
66static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
67{
68 return 24000000;
69}
70
71static struct clk ref_xtal_clk = {
72 .get_rate = ref_xtal_clk_get_rate,
73};
74
75/*
76 * pll_clk
77 */
78static unsigned long pll_clk_get_rate(struct clk *clk)
79{
80 return 480000000;
81}
82
83static int pll_clk_enable(struct clk *clk)
84{
85 __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
86 BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
87 CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_SET);
88
89 /* Only a 10us delay is need. PLLCTRL1 LOCK bitfied is only a timer
90 * and is incorrect (excessive). Per definition of the PLLCTRL0
91 * POWER field, waiting at least 10us.
92 */
93 udelay(10);
94
95 return 0;
96}
97
98static void pll_clk_disable(struct clk *clk)
99{
100 __raw_writel(BM_CLKCTRL_PLLCTRL0_POWER |
101 BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS,
102 CLKCTRL_BASE_ADDR + HW_CLKCTRL_PLLCTRL0_CLR);
103}
104
105static struct clk pll_clk = {
106 .get_rate = pll_clk_get_rate,
107 .enable = pll_clk_enable,
108 .disable = pll_clk_disable,
109 .parent = &ref_xtal_clk,
110};
111
112/*
113 * ref_clk
114 */
115#define _CLK_GET_RATE_REF(name, sr, ss) \
116static unsigned long name##_get_rate(struct clk *clk) \
117{ \
118 unsigned long parent_rate; \
119 u32 reg, div; \
120 \
121 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
122 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
123 parent_rate = clk_get_rate(clk->parent); \
124 \
125 return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
126 div, PARENT_RATE_SHIFT); \
127}
128
129_CLK_GET_RATE_REF(ref_cpu_clk, FRAC, CPU)
130_CLK_GET_RATE_REF(ref_emi_clk, FRAC, EMI)
131_CLK_GET_RATE_REF(ref_pix_clk, FRAC, PIX)
132_CLK_GET_RATE_REF(ref_io_clk, FRAC, IO)
133
134#define _DEFINE_CLOCK_REF(name, er, es) \
135 static struct clk name = { \
136 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
137 .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
138 .get_rate = name##_get_rate, \
139 .enable = _raw_clk_enable, \
140 .disable = _raw_clk_disable, \
141 .parent = &pll_clk, \
142 }
143
144_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC, CPU);
145_DEFINE_CLOCK_REF(ref_emi_clk, FRAC, EMI);
146_DEFINE_CLOCK_REF(ref_pix_clk, FRAC, PIX);
147_DEFINE_CLOCK_REF(ref_io_clk, FRAC, IO);
148
149/*
150 * General clocks
151 *
152 * clk_get_rate
153 */
154static unsigned long rtc_clk_get_rate(struct clk *clk)
155{
156 /* ref_xtal_clk is implemented as the only parent */
157 return clk_get_rate(clk->parent) / 768;
158}
159
160static unsigned long clk32k_clk_get_rate(struct clk *clk)
161{
162 return clk->parent->get_rate(clk->parent) / 750;
163}
164
165#define _CLK_GET_RATE(name, rs) \
166static unsigned long name##_get_rate(struct clk *clk) \
167{ \
168 u32 reg, div; \
169 \
170 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
171 \
172 if (clk->parent == &ref_xtal_clk) \
173 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
174 BP_CLKCTRL_##rs##_DIV_XTAL; \
175 else \
176 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
177 BP_CLKCTRL_##rs##_DIV_##rs; \
178 \
179 if (!div) \
180 return -EINVAL; \
181 \
182 return clk_get_rate(clk->parent) / div; \
183}
184
185_CLK_GET_RATE(cpu_clk, CPU)
186_CLK_GET_RATE(emi_clk, EMI)
187
188#define _CLK_GET_RATE1(name, rs) \
189static unsigned long name##_get_rate(struct clk *clk) \
190{ \
191 u32 reg, div; \
192 \
193 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
194 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
195 \
196 if (!div) \
197 return -EINVAL; \
198 \
199 return clk_get_rate(clk->parent) / div; \
200}
201
202_CLK_GET_RATE1(hbus_clk, HBUS)
203_CLK_GET_RATE1(xbus_clk, XBUS)
204_CLK_GET_RATE1(ssp_clk, SSP)
205_CLK_GET_RATE1(gpmi_clk, GPMI)
206_CLK_GET_RATE1(lcdif_clk, PIX)
207
208#define _CLK_GET_RATE_STUB(name) \
209static unsigned long name##_get_rate(struct clk *clk) \
210{ \
211 return clk_get_rate(clk->parent); \
212}
213
214_CLK_GET_RATE_STUB(uart_clk)
215_CLK_GET_RATE_STUB(audio_clk)
216_CLK_GET_RATE_STUB(pwm_clk)
217
218/*
219 * clk_set_rate
220 */
221static int cpu_clk_set_rate(struct clk *clk, unsigned long rate)
222{
223 u32 reg, bm_busy, div_max, d, f, div, frac;
224 unsigned long diff, parent_rate, calc_rate;
225 int i;
226
227 parent_rate = clk_get_rate(clk->parent);
228
229 if (clk->parent == &ref_xtal_clk) {
230 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> BP_CLKCTRL_CPU_DIV_XTAL;
231 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL;
232 div = DIV_ROUND_UP(parent_rate, rate);
233 if (div == 0 || div > div_max)
234 return -EINVAL;
235 } else {
236 div_max = BM_CLKCTRL_CPU_DIV_CPU >> BP_CLKCTRL_CPU_DIV_CPU;
237 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU;
238 rate >>= PARENT_RATE_SHIFT;
239 parent_rate >>= PARENT_RATE_SHIFT;
240 diff = parent_rate;
241 div = frac = 1;
242 for (d = 1; d <= div_max; d++) {
243 f = parent_rate * 18 / d / rate;
244 if ((parent_rate * 18 / d) % rate)
245 f++;
246 if (f < 18 || f > 35)
247 continue;
248
249 calc_rate = parent_rate * 18 / f / d;
250 if (calc_rate > rate)
251 continue;
252
253 if (rate - calc_rate < diff) {
254 frac = f;
255 div = d;
256 diff = rate - calc_rate;
257 }
258
259 if (diff == 0)
260 break;
261 }
262
263 if (diff == parent_rate)
264 return -EINVAL;
265
266 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
267 reg &= ~BM_CLKCTRL_FRAC_CPUFRAC;
268 reg |= frac;
269 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_FRAC);
270 }
271
272 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
273 reg &= ~BM_CLKCTRL_CPU_DIV_CPU;
274 reg |= div << BP_CLKCTRL_CPU_DIV_CPU;
275 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU);
276
277 for (i = 10000; i; i--)
278 if (!(__raw_readl(CLKCTRL_BASE_ADDR +
279 HW_CLKCTRL_CPU) & bm_busy))
280 break;
281 if (!i) {
282 pr_err("%s: divider writing timeout\n", __func__);
283 return -ETIMEDOUT;
284 }
285
286 return 0;
287}
288
289#define _CLK_SET_RATE(name, dr) \
290static int name##_set_rate(struct clk *clk, unsigned long rate) \
291{ \
292 u32 reg, div_max, div; \
293 unsigned long parent_rate; \
294 int i; \
295 \
296 parent_rate = clk_get_rate(clk->parent); \
297 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
298 \
299 div = DIV_ROUND_UP(parent_rate, rate); \
300 if (div == 0 || div > div_max) \
301 return -EINVAL; \
302 \
303 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
304 reg &= ~BM_CLKCTRL_##dr##_DIV; \
305 reg |= div << BP_CLKCTRL_##dr##_DIV; \
306 if (reg | (1 << clk->enable_shift)) { \
307 pr_err("%s: clock is gated\n", __func__); \
308 return -EINVAL; \
309 } \
310 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
311 \
312 for (i = 10000; i; i--) \
313 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
314 HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \
315 break; \
316 if (!i) { \
317 pr_err("%s: divider writing timeout\n", __func__); \
318 return -ETIMEDOUT; \
319 } \
320 \
321 return 0; \
322}
323
324_CLK_SET_RATE(xbus_clk, XBUS)
325_CLK_SET_RATE(ssp_clk, SSP)
326_CLK_SET_RATE(gpmi_clk, GPMI)
327_CLK_SET_RATE(lcdif_clk, PIX)
328
329#define _CLK_SET_RATE_STUB(name) \
330static int name##_set_rate(struct clk *clk, unsigned long rate) \
331{ \
332 return -EINVAL; \
333}
334
335_CLK_SET_RATE_STUB(emi_clk)
336_CLK_SET_RATE_STUB(uart_clk)
337_CLK_SET_RATE_STUB(audio_clk)
338_CLK_SET_RATE_STUB(pwm_clk)
339_CLK_SET_RATE_STUB(clk32k_clk)
340
341/*
342 * clk_set_parent
343 */
344#define _CLK_SET_PARENT(name, bit) \
345static int name##_set_parent(struct clk *clk, struct clk *parent) \
346{ \
347 if (parent != clk->parent) { \
348 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
349 HW_CLKCTRL_CLKSEQ_TOG); \
350 clk->parent = parent; \
351 } \
352 \
353 return 0; \
354}
355
356_CLK_SET_PARENT(cpu_clk, CPU)
357_CLK_SET_PARENT(emi_clk, EMI)
358_CLK_SET_PARENT(ssp_clk, SSP)
359_CLK_SET_PARENT(gpmi_clk, GPMI)
360_CLK_SET_PARENT(lcdif_clk, PIX)
361
362#define _CLK_SET_PARENT_STUB(name) \
363static int name##_set_parent(struct clk *clk, struct clk *parent) \
364{ \
365 if (parent != clk->parent) \
366 return -EINVAL; \
367 else \
368 return 0; \
369}
370
371_CLK_SET_PARENT_STUB(uart_clk)
372_CLK_SET_PARENT_STUB(audio_clk)
373_CLK_SET_PARENT_STUB(pwm_clk)
374_CLK_SET_PARENT_STUB(clk32k_clk)
375
376/*
377 * clk definition
378 */
379static struct clk cpu_clk = {
380 .get_rate = cpu_clk_get_rate,
381 .set_rate = cpu_clk_set_rate,
382 .set_parent = cpu_clk_set_parent,
383 .parent = &ref_cpu_clk,
384};
385
386static struct clk hbus_clk = {
387 .get_rate = hbus_clk_get_rate,
388 .parent = &cpu_clk,
389};
390
391static struct clk xbus_clk = {
392 .get_rate = xbus_clk_get_rate,
393 .set_rate = xbus_clk_set_rate,
394 .parent = &ref_xtal_clk,
395};
396
397static struct clk rtc_clk = {
398 .get_rate = rtc_clk_get_rate,
399 .parent = &ref_xtal_clk,
400};
401
402/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
403static struct clk usb_clk = {
404 .enable_reg = DIGCTRL_BASE_ADDR,
405 .enable_shift = 2,
406 .enable = _raw_clk_enable,
407 .disable = _raw_clk_disable,
408 .parent = &pll_clk,
409};
410
411#define _DEFINE_CLOCK(name, er, es, p) \
412 static struct clk name = { \
413 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
414 .enable_shift = BP_CLKCTRL_##er##_##es, \
415 .get_rate = name##_get_rate, \
416 .set_rate = name##_set_rate, \
417 .set_parent = name##_set_parent, \
418 .enable = _raw_clk_enable, \
419 .disable = _raw_clk_disable, \
420 .parent = p, \
421 }
422
423_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
424_DEFINE_CLOCK(ssp_clk, SSP, CLKGATE, &ref_xtal_clk);
425_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
426_DEFINE_CLOCK(lcdif_clk, PIX, CLKGATE, &ref_xtal_clk);
427_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
428_DEFINE_CLOCK(audio_clk, XTAL, FILT_CLK24M_GATE, &ref_xtal_clk);
429_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
430_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
431
432#define _REGISTER_CLOCK(d, n, c) \
433 { \
434 .dev_id = d, \
435 .con_id = n, \
436 .clk = &c, \
437 },
438
439static struct clk_lookup lookups[] = {
440 _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
441 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
442 _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
443 _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
444 _REGISTER_CLOCK(NULL, "usb", usb_clk)
445 _REGISTER_CLOCK(NULL, "audio", audio_clk)
446 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
447};
448
449static int clk_misc_init(void)
450{
451 u32 reg;
452 int i;
453
454 /* Fix up parent per register setting */
455 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
456 cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
457 &ref_xtal_clk : &ref_cpu_clk;
458 emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
459 &ref_xtal_clk : &ref_emi_clk;
460 ssp_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP) ?
461 &ref_xtal_clk : &ref_io_clk;
462 gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
463 &ref_xtal_clk : &ref_io_clk;
464 lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_PIX) ?
465 &ref_xtal_clk : &ref_pix_clk;
466
467 /* Use int div over frac when both are available */
468 __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
469 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
470 __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
471 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
472 __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
473 CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
474
475 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
476 reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
477 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
478
479 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
480 reg &= ~BM_CLKCTRL_SSP_DIV_FRAC_EN;
481 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP);
482
483 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
484 reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
485 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
486
487 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
488 reg &= ~BM_CLKCTRL_PIX_DIV_FRAC_EN;
489 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_PIX);
490
491 /*
492 * Set safe hbus clock divider. A divider of 3 ensure that
493 * the Vddd voltage required for the cpu clock is sufficiently
494 * high for the hbus clock.
495 */
496 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
497 reg &= BM_CLKCTRL_HBUS_DIV;
498 reg |= 3 << BP_CLKCTRL_HBUS_DIV;
499 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
500
501 for (i = 10000; i; i--)
502 if (!(__raw_readl(CLKCTRL_BASE_ADDR +
503 HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_BUSY))
504 break;
505 if (!i) {
506 pr_err("%s: divider writing timeout\n", __func__);
507 return -ETIMEDOUT;
508 }
509
510 /* Gate off cpu clock in WFI for power saving */
511 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
512 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
513
514 return 0;
515}
516
517int __init mx23_clocks_init(void)
518{
519 clk_misc_init();
520
521 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
522
523 mxs_timer_init(&clk32k_clk, MX23_INT_TIMER0);
524
525 return 0;
526}
diff --git a/arch/arm/mach-mxs/clock-mx28.c b/arch/arm/mach-mxs/clock-mx28.c
new file mode 100644
index 000000000000..74e2103c6011
--- /dev/null
+++ b/arch/arm/mach-mxs/clock-mx28.c
@@ -0,0 +1,734 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/mm.h>
20#include <linux/delay.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/jiffies.h>
24
25#include <asm/clkdev.h>
26#include <asm/div64.h>
27
28#include <mach/mx28.h>
29#include <mach/common.h>
30#include <mach/clock.h>
31
32#include "regs-clkctrl-mx28.h"
33
34#define CLKCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
35#define DIGCTRL_BASE_ADDR MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
36
37#define PARENT_RATE_SHIFT 8
38
39static struct clk pll2_clk;
40static struct clk cpu_clk;
41static struct clk emi_clk;
42static struct clk saif0_clk;
43static struct clk saif1_clk;
44static struct clk clk32k_clk;
45
46static int _raw_clk_enable(struct clk *clk)
47{
48 u32 reg;
49
50 if (clk->enable_reg) {
51 reg = __raw_readl(clk->enable_reg);
52 reg &= ~(1 << clk->enable_shift);
53 __raw_writel(reg, clk->enable_reg);
54 }
55
56 return 0;
57}
58
59static void _raw_clk_disable(struct clk *clk)
60{
61 u32 reg;
62
63 if (clk->enable_reg) {
64 reg = __raw_readl(clk->enable_reg);
65 reg |= 1 << clk->enable_shift;
66 __raw_writel(reg, clk->enable_reg);
67 }
68}
69
70/*
71 * ref_xtal_clk
72 */
73static unsigned long ref_xtal_clk_get_rate(struct clk *clk)
74{
75 return 24000000;
76}
77
78static struct clk ref_xtal_clk = {
79 .get_rate = ref_xtal_clk_get_rate,
80};
81
82/*
83 * pll_clk
84 */
85static unsigned long pll0_clk_get_rate(struct clk *clk)
86{
87 return 480000000;
88}
89
90static unsigned long pll1_clk_get_rate(struct clk *clk)
91{
92 return 480000000;
93}
94
95static unsigned long pll2_clk_get_rate(struct clk *clk)
96{
97 return 50000000;
98}
99
100#define _CLK_ENABLE_PLL(name, r, g) \
101static int name##_enable(struct clk *clk) \
102{ \
103 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
104 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
105 udelay(10); \
106 \
107 if (clk == &pll2_clk) \
108 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
109 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
110 else \
111 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
112 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
113 \
114 return 0; \
115}
116
117_CLK_ENABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
118_CLK_ENABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
119_CLK_ENABLE_PLL(pll2_clk, PLL2, CLKGATE)
120
121#define _CLK_DISABLE_PLL(name, r, g) \
122static void name##_disable(struct clk *clk) \
123{ \
124 __raw_writel(BM_CLKCTRL_##r##CTRL0_POWER, \
125 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
126 \
127 if (clk == &pll2_clk) \
128 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
129 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_SET); \
130 else \
131 __raw_writel(BM_CLKCTRL_##r##CTRL0_##g, \
132 CLKCTRL_BASE_ADDR + HW_CLKCTRL_##r##CTRL0_CLR); \
133 \
134}
135
136_CLK_DISABLE_PLL(pll0_clk, PLL0, EN_USB_CLKS)
137_CLK_DISABLE_PLL(pll1_clk, PLL1, EN_USB_CLKS)
138_CLK_DISABLE_PLL(pll2_clk, PLL2, CLKGATE)
139
140#define _DEFINE_CLOCK_PLL(name) \
141 static struct clk name = { \
142 .get_rate = name##_get_rate, \
143 .enable = name##_enable, \
144 .disable = name##_disable, \
145 .parent = &ref_xtal_clk, \
146 }
147
148_DEFINE_CLOCK_PLL(pll0_clk);
149_DEFINE_CLOCK_PLL(pll1_clk);
150_DEFINE_CLOCK_PLL(pll2_clk);
151
152/*
153 * ref_clk
154 */
155#define _CLK_GET_RATE_REF(name, sr, ss) \
156static unsigned long name##_get_rate(struct clk *clk) \
157{ \
158 unsigned long parent_rate; \
159 u32 reg, div; \
160 \
161 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##sr); \
162 div = (reg >> BP_CLKCTRL_##sr##_##ss##FRAC) & 0x3f; \
163 parent_rate = clk_get_rate(clk->parent); \
164 \
165 return SH_DIV((parent_rate >> PARENT_RATE_SHIFT) * 18, \
166 div, PARENT_RATE_SHIFT); \
167}
168
169_CLK_GET_RATE_REF(ref_cpu_clk, FRAC0, CPU)
170_CLK_GET_RATE_REF(ref_emi_clk, FRAC0, EMI)
171_CLK_GET_RATE_REF(ref_io0_clk, FRAC0, IO0)
172_CLK_GET_RATE_REF(ref_io1_clk, FRAC0, IO1)
173_CLK_GET_RATE_REF(ref_pix_clk, FRAC1, PIX)
174_CLK_GET_RATE_REF(ref_gpmi_clk, FRAC1, GPMI)
175
176#define _DEFINE_CLOCK_REF(name, er, es) \
177 static struct clk name = { \
178 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
179 .enable_shift = BP_CLKCTRL_##er##_CLKGATE##es, \
180 .get_rate = name##_get_rate, \
181 .enable = _raw_clk_enable, \
182 .disable = _raw_clk_disable, \
183 .parent = &pll0_clk, \
184 }
185
186_DEFINE_CLOCK_REF(ref_cpu_clk, FRAC0, CPU);
187_DEFINE_CLOCK_REF(ref_emi_clk, FRAC0, EMI);
188_DEFINE_CLOCK_REF(ref_io0_clk, FRAC0, IO0);
189_DEFINE_CLOCK_REF(ref_io1_clk, FRAC0, IO1);
190_DEFINE_CLOCK_REF(ref_pix_clk, FRAC1, PIX);
191_DEFINE_CLOCK_REF(ref_gpmi_clk, FRAC1, GPMI);
192
193/*
194 * General clocks
195 *
196 * clk_get_rate
197 */
198static unsigned long lradc_clk_get_rate(struct clk *clk)
199{
200 return clk_get_rate(clk->parent) / 16;
201}
202
203static unsigned long rtc_clk_get_rate(struct clk *clk)
204{
205 /* ref_xtal_clk is implemented as the only parent */
206 return clk_get_rate(clk->parent) / 768;
207}
208
209static unsigned long clk32k_clk_get_rate(struct clk *clk)
210{
211 return clk->parent->get_rate(clk->parent) / 750;
212}
213
214static unsigned long spdif_clk_get_rate(struct clk *clk)
215{
216 return clk_get_rate(clk->parent) / 4;
217}
218
219#define _CLK_GET_RATE(name, rs) \
220static unsigned long name##_get_rate(struct clk *clk) \
221{ \
222 u32 reg, div; \
223 \
224 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
225 \
226 if (clk->parent == &ref_xtal_clk) \
227 div = (reg & BM_CLKCTRL_##rs##_DIV_XTAL) >> \
228 BP_CLKCTRL_##rs##_DIV_XTAL; \
229 else \
230 div = (reg & BM_CLKCTRL_##rs##_DIV_##rs) >> \
231 BP_CLKCTRL_##rs##_DIV_##rs; \
232 \
233 if (!div) \
234 return -EINVAL; \
235 \
236 return clk_get_rate(clk->parent) / div; \
237}
238
239_CLK_GET_RATE(cpu_clk, CPU)
240_CLK_GET_RATE(emi_clk, EMI)
241
242#define _CLK_GET_RATE1(name, rs) \
243static unsigned long name##_get_rate(struct clk *clk) \
244{ \
245 u32 reg, div; \
246 \
247 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
248 div = (reg & BM_CLKCTRL_##rs##_DIV) >> BP_CLKCTRL_##rs##_DIV; \
249 \
250 if (!div) \
251 return -EINVAL; \
252 \
253 if (clk == &saif0_clk || clk == &saif1_clk) \
254 return clk_get_rate(clk->parent) >> 16 * div; \
255 else \
256 return clk_get_rate(clk->parent) / div; \
257}
258
259_CLK_GET_RATE1(hbus_clk, HBUS)
260_CLK_GET_RATE1(xbus_clk, XBUS)
261_CLK_GET_RATE1(ssp0_clk, SSP0)
262_CLK_GET_RATE1(ssp1_clk, SSP1)
263_CLK_GET_RATE1(ssp2_clk, SSP2)
264_CLK_GET_RATE1(ssp3_clk, SSP3)
265_CLK_GET_RATE1(gpmi_clk, GPMI)
266_CLK_GET_RATE1(lcdif_clk, DIS_LCDIF)
267_CLK_GET_RATE1(saif0_clk, SAIF0)
268_CLK_GET_RATE1(saif1_clk, SAIF1)
269
270#define _CLK_GET_RATE_STUB(name) \
271static unsigned long name##_get_rate(struct clk *clk) \
272{ \
273 return clk_get_rate(clk->parent); \
274}
275
276_CLK_GET_RATE_STUB(uart_clk)
277_CLK_GET_RATE_STUB(pwm_clk)
278_CLK_GET_RATE_STUB(can0_clk)
279_CLK_GET_RATE_STUB(can1_clk)
280_CLK_GET_RATE_STUB(fec_clk)
281
282/*
283 * clk_set_rate
284 */
285/* fool compiler */
286#define BM_CLKCTRL_CPU_DIV 0
287#define BP_CLKCTRL_CPU_DIV 0
288#define BM_CLKCTRL_CPU_BUSY 0
289
290#define _CLK_SET_RATE(name, dr, fr, fs) \
291static int name##_set_rate(struct clk *clk, unsigned long rate) \
292{ \
293 u32 reg, bm_busy, div_max, d, f, div, frac; \
294 unsigned long diff, parent_rate, calc_rate; \
295 int i; \
296 \
297 parent_rate = clk_get_rate(clk->parent); \
298 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
299 bm_busy = BM_CLKCTRL_##dr##_BUSY; \
300 \
301 if (clk->parent == &ref_xtal_clk) { \
302 div = DIV_ROUND_UP(parent_rate, rate); \
303 if (clk == &cpu_clk) { \
304 div_max = BM_CLKCTRL_CPU_DIV_XTAL >> \
305 BP_CLKCTRL_CPU_DIV_XTAL; \
306 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_XTAL; \
307 } \
308 if (div == 0 || div > div_max) \
309 return -EINVAL; \
310 } else { \
311 rate >>= PARENT_RATE_SHIFT; \
312 parent_rate >>= PARENT_RATE_SHIFT; \
313 diff = parent_rate; \
314 div = frac = 1; \
315 if (clk == &cpu_clk) { \
316 div_max = BM_CLKCTRL_CPU_DIV_CPU >> \
317 BP_CLKCTRL_CPU_DIV_CPU; \
318 bm_busy = BM_CLKCTRL_CPU_BUSY_REF_CPU; \
319 } \
320 for (d = 1; d <= div_max; d++) { \
321 f = parent_rate * 18 / d / rate; \
322 if ((parent_rate * 18 / d) % rate) \
323 f++; \
324 if (f < 18 || f > 35) \
325 continue; \
326 \
327 calc_rate = parent_rate * 18 / f / d; \
328 if (calc_rate > rate) \
329 continue; \
330 \
331 if (rate - calc_rate < diff) { \
332 frac = f; \
333 div = d; \
334 diff = rate - calc_rate; \
335 } \
336 \
337 if (diff == 0) \
338 break; \
339 } \
340 \
341 if (diff == parent_rate) \
342 return -EINVAL; \
343 \
344 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
345 reg &= ~BM_CLKCTRL_##fr##_##fs##FRAC; \
346 reg |= frac; \
347 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##fr); \
348 } \
349 \
350 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
351 if (clk == &cpu_clk) { \
352 reg &= ~BM_CLKCTRL_CPU_DIV_CPU; \
353 reg |= div << BP_CLKCTRL_CPU_DIV_CPU; \
354 } else { \
355 reg &= ~BM_CLKCTRL_##dr##_DIV; \
356 reg |= div << BP_CLKCTRL_##dr##_DIV; \
357 if (reg | (1 << clk->enable_shift)) { \
358 pr_err("%s: clock is gated\n", __func__); \
359 return -EINVAL; \
360 } \
361 } \
362 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU); \
363 \
364 for (i = 10000; i; i--) \
365 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
366 HW_CLKCTRL_##dr) & bm_busy)) \
367 break; \
368 if (!i) { \
369 pr_err("%s: divider writing timeout\n", __func__); \
370 return -ETIMEDOUT; \
371 } \
372 \
373 return 0; \
374}
375
376_CLK_SET_RATE(cpu_clk, CPU, FRAC0, CPU)
377_CLK_SET_RATE(ssp0_clk, SSP0, FRAC0, IO0)
378_CLK_SET_RATE(ssp1_clk, SSP1, FRAC0, IO0)
379_CLK_SET_RATE(ssp2_clk, SSP2, FRAC0, IO1)
380_CLK_SET_RATE(ssp3_clk, SSP3, FRAC0, IO1)
381_CLK_SET_RATE(lcdif_clk, DIS_LCDIF, FRAC1, PIX)
382_CLK_SET_RATE(gpmi_clk, GPMI, FRAC1, GPMI)
383
384#define _CLK_SET_RATE1(name, dr) \
385static int name##_set_rate(struct clk *clk, unsigned long rate) \
386{ \
387 u32 reg, div_max, div; \
388 unsigned long parent_rate; \
389 int i; \
390 \
391 parent_rate = clk_get_rate(clk->parent); \
392 div_max = BM_CLKCTRL_##dr##_DIV >> BP_CLKCTRL_##dr##_DIV; \
393 \
394 div = DIV_ROUND_UP(parent_rate, rate); \
395 if (div == 0 || div > div_max) \
396 return -EINVAL; \
397 \
398 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
399 reg &= ~BM_CLKCTRL_##dr##_DIV; \
400 reg |= div << BP_CLKCTRL_##dr##_DIV; \
401 if (reg | (1 << clk->enable_shift)) { \
402 pr_err("%s: clock is gated\n", __func__); \
403 return -EINVAL; \
404 } \
405 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##dr); \
406 \
407 for (i = 10000; i; i--) \
408 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
409 HW_CLKCTRL_##dr) & BM_CLKCTRL_##dr##_BUSY)) \
410 break; \
411 if (!i) { \
412 pr_err("%s: divider writing timeout\n", __func__); \
413 return -ETIMEDOUT; \
414 } \
415 \
416 return 0; \
417}
418
419_CLK_SET_RATE1(xbus_clk, XBUS)
420
421/* saif clock uses 16 bits frac div */
422#define _CLK_SET_RATE_SAIF(name, rs) \
423static int name##_set_rate(struct clk *clk, unsigned long rate) \
424{ \
425 u16 div; \
426 u32 reg; \
427 u64 lrate; \
428 unsigned long parent_rate; \
429 int i; \
430 \
431 parent_rate = clk_get_rate(clk->parent); \
432 if (rate > parent_rate) \
433 return -EINVAL; \
434 \
435 lrate = (u64)rate << 16; \
436 do_div(lrate, parent_rate); \
437 div = (u16)lrate; \
438 \
439 if (!div) \
440 return -EINVAL; \
441 \
442 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
443 reg &= ~BM_CLKCTRL_##rs##_DIV; \
444 reg |= div << BP_CLKCTRL_##rs##_DIV; \
445 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_##rs); \
446 \
447 for (i = 10000; i; i--) \
448 if (!(__raw_readl(CLKCTRL_BASE_ADDR + \
449 HW_CLKCTRL_##rs) & BM_CLKCTRL_##rs##_BUSY)) \
450 break; \
451 if (!i) { \
452 pr_err("%s: divider writing timeout\n", __func__); \
453 return -ETIMEDOUT; \
454 } \
455 \
456 return 0; \
457}
458
459_CLK_SET_RATE_SAIF(saif0_clk, SAIF0)
460_CLK_SET_RATE_SAIF(saif1_clk, SAIF1)
461
462#define _CLK_SET_RATE_STUB(name) \
463static int name##_set_rate(struct clk *clk, unsigned long rate) \
464{ \
465 return -EINVAL; \
466}
467
468_CLK_SET_RATE_STUB(emi_clk)
469_CLK_SET_RATE_STUB(uart_clk)
470_CLK_SET_RATE_STUB(pwm_clk)
471_CLK_SET_RATE_STUB(spdif_clk)
472_CLK_SET_RATE_STUB(clk32k_clk)
473_CLK_SET_RATE_STUB(can0_clk)
474_CLK_SET_RATE_STUB(can1_clk)
475_CLK_SET_RATE_STUB(fec_clk)
476
477/*
478 * clk_set_parent
479 */
480#define _CLK_SET_PARENT(name, bit) \
481static int name##_set_parent(struct clk *clk, struct clk *parent) \
482{ \
483 if (parent != clk->parent) { \
484 __raw_writel(BM_CLKCTRL_CLKSEQ_BYPASS_##bit, \
485 HW_CLKCTRL_CLKSEQ_TOG); \
486 clk->parent = parent; \
487 } \
488 \
489 return 0; \
490}
491
492_CLK_SET_PARENT(cpu_clk, CPU)
493_CLK_SET_PARENT(emi_clk, EMI)
494_CLK_SET_PARENT(ssp0_clk, SSP0)
495_CLK_SET_PARENT(ssp1_clk, SSP1)
496_CLK_SET_PARENT(ssp2_clk, SSP2)
497_CLK_SET_PARENT(ssp3_clk, SSP3)
498_CLK_SET_PARENT(lcdif_clk, DIS_LCDIF)
499_CLK_SET_PARENT(gpmi_clk, GPMI)
500_CLK_SET_PARENT(saif0_clk, SAIF0)
501_CLK_SET_PARENT(saif1_clk, SAIF1)
502
503#define _CLK_SET_PARENT_STUB(name) \
504static int name##_set_parent(struct clk *clk, struct clk *parent) \
505{ \
506 if (parent != clk->parent) \
507 return -EINVAL; \
508 else \
509 return 0; \
510}
511
512_CLK_SET_PARENT_STUB(pwm_clk)
513_CLK_SET_PARENT_STUB(uart_clk)
514_CLK_SET_PARENT_STUB(clk32k_clk)
515_CLK_SET_PARENT_STUB(spdif_clk)
516_CLK_SET_PARENT_STUB(fec_clk)
517_CLK_SET_PARENT_STUB(can0_clk)
518_CLK_SET_PARENT_STUB(can1_clk)
519
520/*
521 * clk definition
522 */
523static struct clk cpu_clk = {
524 .get_rate = cpu_clk_get_rate,
525 .set_rate = cpu_clk_set_rate,
526 .set_parent = cpu_clk_set_parent,
527 .parent = &ref_cpu_clk,
528};
529
530static struct clk hbus_clk = {
531 .get_rate = hbus_clk_get_rate,
532 .parent = &cpu_clk,
533};
534
535static struct clk xbus_clk = {
536 .get_rate = xbus_clk_get_rate,
537 .set_rate = xbus_clk_set_rate,
538 .parent = &ref_xtal_clk,
539};
540
541static struct clk lradc_clk = {
542 .get_rate = lradc_clk_get_rate,
543 .parent = &clk32k_clk,
544};
545
546static struct clk rtc_clk = {
547 .get_rate = rtc_clk_get_rate,
548 .parent = &ref_xtal_clk,
549};
550
551/* usb_clk gate is controlled in DIGCTRL other than CLKCTRL */
552static struct clk usb0_clk = {
553 .enable_reg = DIGCTRL_BASE_ADDR,
554 .enable_shift = 2,
555 .enable = _raw_clk_enable,
556 .disable = _raw_clk_disable,
557 .parent = &pll0_clk,
558};
559
560static struct clk usb1_clk = {
561 .enable_reg = DIGCTRL_BASE_ADDR,
562 .enable_shift = 16,
563 .enable = _raw_clk_enable,
564 .disable = _raw_clk_disable,
565 .parent = &pll1_clk,
566};
567
568#define _DEFINE_CLOCK(name, er, es, p) \
569 static struct clk name = { \
570 .enable_reg = CLKCTRL_BASE_ADDR + HW_CLKCTRL_##er, \
571 .enable_shift = BP_CLKCTRL_##er##_##es, \
572 .get_rate = name##_get_rate, \
573 .set_rate = name##_set_rate, \
574 .set_parent = name##_set_parent, \
575 .enable = _raw_clk_enable, \
576 .disable = _raw_clk_disable, \
577 .parent = p, \
578 }
579
580_DEFINE_CLOCK(emi_clk, EMI, CLKGATE, &ref_xtal_clk);
581_DEFINE_CLOCK(ssp0_clk, SSP0, CLKGATE, &ref_xtal_clk);
582_DEFINE_CLOCK(ssp1_clk, SSP1, CLKGATE, &ref_xtal_clk);
583_DEFINE_CLOCK(ssp2_clk, SSP2, CLKGATE, &ref_xtal_clk);
584_DEFINE_CLOCK(ssp3_clk, SSP3, CLKGATE, &ref_xtal_clk);
585_DEFINE_CLOCK(lcdif_clk, DIS_LCDIF, CLKGATE, &ref_xtal_clk);
586_DEFINE_CLOCK(gpmi_clk, GPMI, CLKGATE, &ref_xtal_clk);
587_DEFINE_CLOCK(saif0_clk, SAIF0, CLKGATE, &ref_xtal_clk);
588_DEFINE_CLOCK(saif1_clk, SAIF1, CLKGATE, &ref_xtal_clk);
589_DEFINE_CLOCK(can0_clk, FLEXCAN, STOP_CAN0, &ref_xtal_clk);
590_DEFINE_CLOCK(can1_clk, FLEXCAN, STOP_CAN1, &ref_xtal_clk);
591_DEFINE_CLOCK(pwm_clk, XTAL, PWM_CLK24M_GATE, &ref_xtal_clk);
592_DEFINE_CLOCK(uart_clk, XTAL, UART_CLK_GATE, &ref_xtal_clk);
593_DEFINE_CLOCK(clk32k_clk, XTAL, TIMROT_CLK32K_GATE, &ref_xtal_clk);
594_DEFINE_CLOCK(spdif_clk, SPDIF, CLKGATE, &pll0_clk);
595_DEFINE_CLOCK(fec_clk, ENET, DISABLE, &hbus_clk);
596
597#define _REGISTER_CLOCK(d, n, c) \
598 { \
599 .dev_id = d, \
600 .con_id = n, \
601 .clk = &c, \
602 },
603
604static struct clk_lookup lookups[] = {
605 _REGISTER_CLOCK("mxs-duart.0", NULL, uart_clk)
606 _REGISTER_CLOCK("fec.0", NULL, fec_clk)
607 _REGISTER_CLOCK("rtc", NULL, rtc_clk)
608 _REGISTER_CLOCK("pll2", NULL, pll2_clk)
609 _REGISTER_CLOCK(NULL, "hclk", hbus_clk)
610 _REGISTER_CLOCK(NULL, "xclk", xbus_clk)
611 _REGISTER_CLOCK(NULL, "can0", can0_clk)
612 _REGISTER_CLOCK(NULL, "can1", can1_clk)
613 _REGISTER_CLOCK(NULL, "usb0", usb0_clk)
614 _REGISTER_CLOCK(NULL, "usb1", usb1_clk)
615 _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
616 _REGISTER_CLOCK(NULL, "lradc", lradc_clk)
617 _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
618};
619
620static int clk_misc_init(void)
621{
622 u32 reg;
623 int i;
624
625 /* Fix up parent per register setting */
626 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_CLKSEQ);
627 cpu_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_CPU) ?
628 &ref_xtal_clk : &ref_cpu_clk;
629 emi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_EMI) ?
630 &ref_xtal_clk : &ref_emi_clk;
631 ssp0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP0) ?
632 &ref_xtal_clk : &ref_io0_clk;
633 ssp1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP1) ?
634 &ref_xtal_clk : &ref_io0_clk;
635 ssp2_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP2) ?
636 &ref_xtal_clk : &ref_io1_clk;
637 ssp3_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SSP3) ?
638 &ref_xtal_clk : &ref_io1_clk;
639 lcdif_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF) ?
640 &ref_xtal_clk : &ref_pix_clk;
641 gpmi_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_GPMI) ?
642 &ref_xtal_clk : &ref_gpmi_clk;
643 saif0_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0) ?
644 &ref_xtal_clk : &pll0_clk;
645 saif1_clk.parent = (reg & BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1) ?
646 &ref_xtal_clk : &pll0_clk;
647
648 /* Use int div over frac when both are available */
649 __raw_writel(BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN,
650 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
651 __raw_writel(BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN,
652 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_CLR);
653 __raw_writel(BM_CLKCTRL_HBUS_DIV_FRAC_EN,
654 CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS_CLR);
655
656 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
657 reg &= ~BM_CLKCTRL_XBUS_DIV_FRAC_EN;
658 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_XBUS);
659
660 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
661 reg &= ~BM_CLKCTRL_SSP0_DIV_FRAC_EN;
662 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP0);
663
664 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
665 reg &= ~BM_CLKCTRL_SSP1_DIV_FRAC_EN;
666 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP1);
667
668 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
669 reg &= ~BM_CLKCTRL_SSP2_DIV_FRAC_EN;
670 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP2);
671
672 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
673 reg &= ~BM_CLKCTRL_SSP3_DIV_FRAC_EN;
674 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SSP3);
675
676 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
677 reg &= ~BM_CLKCTRL_GPMI_DIV_FRAC_EN;
678 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_GPMI);
679
680 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
681 reg &= ~BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN;
682 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_DIS_LCDIF);
683
684 /* SAIF has to use frac div for functional operation */
685 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
686 reg &= ~BM_CLKCTRL_SAIF0_DIV_FRAC_EN;
687 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF0);
688
689 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
690 reg &= ~BM_CLKCTRL_SAIF1_DIV_FRAC_EN;
691 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_SAIF1);
692
693 /*
694 * Set safe hbus clock divider. A divider of 3 ensure that
695 * the Vddd voltage required for the cpu clock is sufficiently
696 * high for the hbus clock.
697 */
698 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
699 reg &= BM_CLKCTRL_HBUS_DIV;
700 reg |= 3 << BP_CLKCTRL_HBUS_DIV;
701 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_HBUS);
702
703 for (i = 10000; i; i--)
704 if (!(__raw_readl(CLKCTRL_BASE_ADDR +
705 HW_CLKCTRL_HBUS) & BM_CLKCTRL_HBUS_ASM_BUSY))
706 break;
707 if (!i) {
708 pr_err("%s: divider writing timeout\n", __func__);
709 return -ETIMEDOUT;
710 }
711
712 /* Gate off cpu clock in WFI for power saving */
713 __raw_writel(BM_CLKCTRL_CPU_INTERRUPT_WAIT,
714 CLKCTRL_BASE_ADDR + HW_CLKCTRL_CPU_SET);
715
716 /* Extra fec clock setting */
717 reg = __raw_readl(CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
718 reg &= ~BM_CLKCTRL_ENET_SLEEP;
719 reg |= BM_CLKCTRL_ENET_CLK_OUT_EN;
720 __raw_writel(reg, CLKCTRL_BASE_ADDR + HW_CLKCTRL_ENET);
721
722 return 0;
723}
724
725int __init mx28_clocks_init(void)
726{
727 clk_misc_init();
728
729 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
730
731 mxs_timer_init(&clk32k_clk, MX28_INT_TIMER0);
732
733 return 0;
734}
diff --git a/arch/arm/mach-mxs/clock.c b/arch/arm/mach-mxs/clock.c
new file mode 100644
index 000000000000..e7d2269cf70e
--- /dev/null
+++ b/arch/arm/mach-mxs/clock.c
@@ -0,0 +1,200 @@
1/*
2 * Based on arch/arm/plat-omap/clock.c
3 *
4 * Copyright (C) 2004 - 2005 Nokia corporation
5 * Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
6 * Modified for omap shared clock framework by Tony Lindgren <tony@atomide.com>
7 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
8 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version 2
13 * of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
22 * MA 02110-1301, USA.
23 */
24
25/* #define DEBUG */
26
27#include <linux/clk.h>
28#include <linux/err.h>
29#include <linux/errno.h>
30#include <linux/init.h>
31#include <linux/io.h>
32#include <linux/kernel.h>
33#include <linux/list.h>
34#include <linux/module.h>
35#include <linux/mutex.h>
36#include <linux/platform_device.h>
37#include <linux/proc_fs.h>
38#include <linux/semaphore.h>
39#include <linux/string.h>
40
41#include <mach/clock.h>
42
43static LIST_HEAD(clocks);
44static DEFINE_MUTEX(clocks_mutex);
45
46/*-------------------------------------------------------------------------
47 * Standard clock functions defined in include/linux/clk.h
48 *-------------------------------------------------------------------------*/
49
50static void __clk_disable(struct clk *clk)
51{
52 if (clk == NULL || IS_ERR(clk))
53 return;
54 WARN_ON(!clk->usecount);
55
56 if (!(--clk->usecount)) {
57 if (clk->disable)
58 clk->disable(clk);
59 __clk_disable(clk->parent);
60 __clk_disable(clk->secondary);
61 }
62}
63
64static int __clk_enable(struct clk *clk)
65{
66 if (clk == NULL || IS_ERR(clk))
67 return -EINVAL;
68
69 if (clk->usecount++ == 0) {
70 __clk_enable(clk->parent);
71 __clk_enable(clk->secondary);
72
73 if (clk->enable)
74 clk->enable(clk);
75 }
76 return 0;
77}
78
79/* This function increments the reference count on the clock and enables the
80 * clock if not already enabled. The parent clock tree is recursively enabled
81 */
82int clk_enable(struct clk *clk)
83{
84 int ret = 0;
85
86 if (clk == NULL || IS_ERR(clk))
87 return -EINVAL;
88
89 mutex_lock(&clocks_mutex);
90 ret = __clk_enable(clk);
91 mutex_unlock(&clocks_mutex);
92
93 return ret;
94}
95EXPORT_SYMBOL(clk_enable);
96
97/* This function decrements the reference count on the clock and disables
98 * the clock when reference count is 0. The parent clock tree is
99 * recursively disabled
100 */
101void clk_disable(struct clk *clk)
102{
103 if (clk == NULL || IS_ERR(clk))
104 return;
105
106 mutex_lock(&clocks_mutex);
107 __clk_disable(clk);
108 mutex_unlock(&clocks_mutex);
109}
110EXPORT_SYMBOL(clk_disable);
111
112/* Retrieve the *current* clock rate. If the clock itself
113 * does not provide a special calculation routine, ask
114 * its parent and so on, until one is able to return
115 * a valid clock rate
116 */
117unsigned long clk_get_rate(struct clk *clk)
118{
119 if (clk == NULL || IS_ERR(clk))
120 return 0UL;
121
122 if (clk->get_rate)
123 return clk->get_rate(clk);
124
125 return clk_get_rate(clk->parent);
126}
127EXPORT_SYMBOL(clk_get_rate);
128
129/* Round the requested clock rate to the nearest supported
130 * rate that is less than or equal to the requested rate.
131 * This is dependent on the clock's current parent.
132 */
133long clk_round_rate(struct clk *clk, unsigned long rate)
134{
135 if (clk == NULL || IS_ERR(clk) || !clk->round_rate)
136 return 0;
137
138 return clk->round_rate(clk, rate);
139}
140EXPORT_SYMBOL(clk_round_rate);
141
142/* Set the clock to the requested clock rate. The rate must
143 * match a supported rate exactly based on what clk_round_rate returns
144 */
145int clk_set_rate(struct clk *clk, unsigned long rate)
146{
147 int ret = -EINVAL;
148
149 if (clk == NULL || IS_ERR(clk) || clk->set_rate == NULL || rate == 0)
150 return ret;
151
152 mutex_lock(&clocks_mutex);
153 ret = clk->set_rate(clk, rate);
154 mutex_unlock(&clocks_mutex);
155
156 return ret;
157}
158EXPORT_SYMBOL(clk_set_rate);
159
160/* Set the clock's parent to another clock source */
161int clk_set_parent(struct clk *clk, struct clk *parent)
162{
163 int ret = -EINVAL;
164 struct clk *old;
165
166 if (clk == NULL || IS_ERR(clk) || parent == NULL ||
167 IS_ERR(parent) || clk->set_parent == NULL)
168 return ret;
169
170 if (clk->usecount)
171 clk_enable(parent);
172
173 mutex_lock(&clocks_mutex);
174 ret = clk->set_parent(clk, parent);
175 if (ret == 0) {
176 old = clk->parent;
177 clk->parent = parent;
178 } else {
179 old = parent;
180 }
181 mutex_unlock(&clocks_mutex);
182
183 if (clk->usecount)
184 clk_disable(old);
185
186 return ret;
187}
188EXPORT_SYMBOL(clk_set_parent);
189
190/* Retrieve the clock's parent clock source */
191struct clk *clk_get_parent(struct clk *clk)
192{
193 struct clk *ret = NULL;
194
195 if (clk == NULL || IS_ERR(clk))
196 return ret;
197
198 return clk->parent;
199}
200EXPORT_SYMBOL(clk_get_parent);
diff --git a/arch/arm/mach-mxs/devices-mx23.h b/arch/arm/mach-mxs/devices-mx23.h
new file mode 100644
index 000000000000..d0f49fc0abb5
--- /dev/null
+++ b/arch/arm/mach-mxs/devices-mx23.h
@@ -0,0 +1,16 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License version 2 as published by the
9 * Free Software Foundation.
10 */
11#include <mach/mx23.h>
12#include <mach/devices-common.h>
13
14extern const struct mxs_duart_data mx23_duart_data __initconst;
15#define mx23_add_duart() \
16 mxs_add_duart(&mx23_duart_data)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
new file mode 100644
index 000000000000..00b736c434ba
--- /dev/null
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -0,0 +1,20 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License version 2 as published by the
9 * Free Software Foundation.
10 */
11#include <mach/mx28.h>
12#include <mach/devices-common.h>
13
14extern const struct mxs_duart_data mx28_duart_data __initconst;
15#define mx28_add_duart() \
16 mxs_add_duart(&mx28_duart_data)
17
18extern const struct mxs_fec_data mx28_fec_data[] __initconst;
19#define mx28_add_fec(id, pdata) \
20 mxs_add_fec(&mx28_fec_data[id], pdata)
diff --git a/arch/arm/mach-mxs/devices.c b/arch/arm/mach-mxs/devices.c
new file mode 100644
index 000000000000..6b60f02ca2e3
--- /dev/null
+++ b/arch/arm/mach-mxs/devices.c
@@ -0,0 +1,75 @@
1/*
2 * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
16 * Boston, MA 02110-1301, USA.
17 */
18
19#include <linux/kernel.h>
20#include <linux/slab.h>
21#include <linux/init.h>
22#include <linux/err.h>
23#include <linux/platform_device.h>
24#include <mach/common.h>
25
26struct platform_device *__init mxs_add_platform_device_dmamask(
27 const char *name, int id,
28 const struct resource *res, unsigned int num_resources,
29 const void *data, size_t size_data, u64 dmamask)
30{
31 int ret = -ENOMEM;
32 struct platform_device *pdev;
33
34 pdev = platform_device_alloc(name, id);
35 if (!pdev)
36 goto err;
37
38 if (dmamask) {
39 /*
40 * This memory isn't freed when the device is put,
41 * I don't have a nice idea for that though. Conceptually
42 * dma_mask in struct device should not be a pointer.
43 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
44 */
45 pdev->dev.dma_mask =
46 kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
47 if (!pdev->dev.dma_mask)
48 /* ret is still -ENOMEM; */
49 goto err;
50
51 *pdev->dev.dma_mask = dmamask;
52 pdev->dev.coherent_dma_mask = dmamask;
53 }
54
55 if (res) {
56 ret = platform_device_add_resources(pdev, res, num_resources);
57 if (ret)
58 goto err;
59 }
60
61 if (data) {
62 ret = platform_device_add_data(pdev, data, size_data);
63 if (ret)
64 goto err;
65 }
66
67 ret = platform_device_add(pdev);
68 if (ret) {
69err:
70 platform_device_put(pdev);
71 return ERR_PTR(ret);
72 }
73
74 return pdev;
75}
diff --git a/arch/arm/mach-mxs/devices/Kconfig b/arch/arm/mach-mxs/devices/Kconfig
new file mode 100644
index 000000000000..a35a2dc55395
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/Kconfig
@@ -0,0 +1,5 @@
1config MXS_HAVE_PLATFORM_DUART
2 bool
3
4config MXS_HAVE_PLATFORM_FEC
5 bool
diff --git a/arch/arm/mach-mxs/devices/Makefile b/arch/arm/mach-mxs/devices/Makefile
new file mode 100644
index 000000000000..4b5266a3e6d9
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/Makefile
@@ -0,0 +1,2 @@
1obj-$(CONFIG_MXS_HAVE_PLATFORM_DUART) += platform-duart.o
2obj-$(CONFIG_MXS_HAVE_PLATFORM_FEC) += platform-fec.o
diff --git a/arch/arm/mach-mxs/devices/platform-duart.c b/arch/arm/mach-mxs/devices/platform-duart.c
new file mode 100644
index 000000000000..2fe0df5b0aad
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-duart.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
6 *
7 * This program is free software; you can redistribute it and/or modify it under
8 * the terms of the GNU General Public License version 2 as published by the
9 * Free Software Foundation.
10 */
11#include <mach/mx23.h>
12#include <mach/mx28.h>
13#include <mach/devices-common.h>
14
15#define mxs_duart_data_entry(soc) \
16 { \
17 .iobase = soc ## _DUART_BASE_ADDR, \
18 .irq = soc ## _INT_DUART, \
19 }
20
21#ifdef CONFIG_SOC_IMX23
22const struct mxs_duart_data mx23_duart_data __initconst =
23 mxs_duart_data_entry(MX23);
24#endif
25
26#ifdef CONFIG_SOC_IMX28
27const struct mxs_duart_data mx28_duart_data __initconst =
28 mxs_duart_data_entry(MX28);
29#endif
30
31struct platform_device *__init mxs_add_duart(
32 const struct mxs_duart_data *data)
33{
34 struct resource res[] = {
35 {
36 .start = data->iobase,
37 .end = data->iobase + SZ_8K - 1,
38 .flags = IORESOURCE_MEM,
39 }, {
40 .start = data->irq,
41 .end = data->irq,
42 .flags = IORESOURCE_IRQ,
43 },
44 };
45
46 return mxs_add_platform_device("mxs-duart", 0, res, ARRAY_SIZE(res),
47 NULL, 0);
48}
diff --git a/arch/arm/mach-mxs/devices/platform-fec.c b/arch/arm/mach-mxs/devices/platform-fec.c
new file mode 100644
index 000000000000..c08168cf3dec
--- /dev/null
+++ b/arch/arm/mach-mxs/devices/platform-fec.c
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/mx28.h>
11#include <mach/devices-common.h>
12
13#define mxs_fec_data_entry_single(soc, _id) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _ENET_MAC ## _id ## _BASE_ADDR, \
17 .irq = soc ## _INT_ENET_MAC ## _id, \
18 }
19
20#define mxs_fec_data_entry(soc, _id) \
21 [_id] = mxs_fec_data_entry_single(soc, _id)
22
23#ifdef CONFIG_SOC_IMX28
24const struct mxs_fec_data mx28_fec_data[] __initconst = {
25#define mx28_fec_data_entry(_id) \
26 mxs_fec_data_entry(MX28, _id)
27 mx28_fec_data_entry(0),
28 mx28_fec_data_entry(1),
29};
30#endif
31
32struct platform_device *__init mxs_add_fec(
33 const struct mxs_fec_data *data,
34 const struct fec_platform_data *pdata)
35{
36 struct resource res[] = {
37 {
38 .start = data->iobase,
39 .end = data->iobase + SZ_16K - 1,
40 .flags = IORESOURCE_MEM,
41 }, {
42 .start = data->irq,
43 .end = data->irq,
44 .flags = IORESOURCE_IRQ,
45 },
46 };
47
48 return mxs_add_platform_device("fec", data->id,
49 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
50}
diff --git a/arch/arm/mach-mxs/gpio.c b/arch/arm/mach-mxs/gpio.c
new file mode 100644
index 000000000000..d7ad7a61366d
--- /dev/null
+++ b/arch/arm/mach-mxs/gpio.c
@@ -0,0 +1,325 @@
1/*
2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/init.h>
24#include <linux/interrupt.h>
25#include <linux/io.h>
26#include <linux/irq.h>
27#include <linux/gpio.h>
28#include <mach/mx23.h>
29#include <mach/mx28.h>
30#include <asm-generic/bug.h>
31
32#include "gpio.h"
33
34static struct mxs_gpio_port *mxs_gpio_ports;
35static int gpio_table_size;
36
37#define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10)
38#define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10)
39#define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10)
40#define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10)
41#define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10)
42#define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10)
43#define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10)
44#define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10)
45
46#define GPIO_INT_FALL_EDGE 0x0
47#define GPIO_INT_LOW_LEV 0x1
48#define GPIO_INT_RISE_EDGE 0x2
49#define GPIO_INT_HIGH_LEV 0x3
50#define GPIO_INT_LEV_MASK (1 << 0)
51#define GPIO_INT_POL_MASK (1 << 1)
52
53/* Note: This driver assumes 32 GPIOs are handled in one register */
54
55static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index)
56{
57 __mxs_clrl(1 << index, port->base + PINCTRL_IRQSTAT(port->id));
58}
59
60static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index,
61 int enable)
62{
63 if (enable) {
64 __mxs_setl(1 << index, port->base + PINCTRL_IRQEN(port->id));
65 __mxs_setl(1 << index, port->base + PINCTRL_PIN2IRQ(port->id));
66 } else {
67 __mxs_clrl(1 << index, port->base + PINCTRL_IRQEN(port->id));
68 }
69}
70
71static void mxs_gpio_ack_irq(u32 irq)
72{
73 u32 gpio = irq_to_gpio(irq);
74 clear_gpio_irqstatus(&mxs_gpio_ports[gpio / 32], gpio & 0x1f);
75}
76
77static void mxs_gpio_mask_irq(u32 irq)
78{
79 u32 gpio = irq_to_gpio(irq);
80 set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 0);
81}
82
83static void mxs_gpio_unmask_irq(u32 irq)
84{
85 u32 gpio = irq_to_gpio(irq);
86 set_gpio_irqenable(&mxs_gpio_ports[gpio / 32], gpio & 0x1f, 1);
87}
88
89static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset);
90
91static int mxs_gpio_set_irq_type(u32 irq, u32 type)
92{
93 u32 gpio = irq_to_gpio(irq);
94 u32 pin_mask = 1 << (gpio & 31);
95 struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
96 void __iomem *pin_addr;
97 int edge;
98
99 switch (type) {
100 case IRQ_TYPE_EDGE_RISING:
101 edge = GPIO_INT_RISE_EDGE;
102 break;
103 case IRQ_TYPE_EDGE_FALLING:
104 edge = GPIO_INT_FALL_EDGE;
105 break;
106 case IRQ_TYPE_LEVEL_LOW:
107 edge = GPIO_INT_LOW_LEV;
108 break;
109 case IRQ_TYPE_LEVEL_HIGH:
110 edge = GPIO_INT_HIGH_LEV;
111 break;
112 default:
113 return -EINVAL;
114 }
115
116 /* set level or edge */
117 pin_addr = port->base + PINCTRL_IRQLEV(port->id);
118 if (edge & GPIO_INT_LEV_MASK)
119 __mxs_setl(pin_mask, pin_addr);
120 else
121 __mxs_clrl(pin_mask, pin_addr);
122
123 /* set polarity */
124 pin_addr = port->base + PINCTRL_IRQPOL(port->id);
125 if (edge & GPIO_INT_POL_MASK)
126 __mxs_setl(pin_mask, pin_addr);
127 else
128 __mxs_clrl(pin_mask, pin_addr);
129
130 clear_gpio_irqstatus(port, gpio & 0x1f);
131
132 return 0;
133}
134
135/* MXS has one interrupt *per* gpio port */
136static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
137{
138 u32 irq_stat;
139 struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq);
140 u32 gpio_irq_no_base = port->virtual_irq_start;
141
142 irq_stat = __raw_readl(port->base + PINCTRL_IRQSTAT(port->id)) &
143 __raw_readl(port->base + PINCTRL_IRQEN(port->id));
144
145 while (irq_stat != 0) {
146 int irqoffset = fls(irq_stat) - 1;
147 generic_handle_irq(gpio_irq_no_base + irqoffset);
148 irq_stat &= ~(1 << irqoffset);
149 }
150}
151
152/*
153 * Set interrupt number "irq" in the GPIO as a wake-up source.
154 * While system is running, all registered GPIO interrupts need to have
155 * wake-up enabled. When system is suspended, only selected GPIO interrupts
156 * need to have wake-up enabled.
157 * @param irq interrupt source number
158 * @param enable enable as wake-up if equal to non-zero
159 * @return This function returns 0 on success.
160 */
161static int mxs_gpio_set_wake_irq(u32 irq, u32 enable)
162{
163 u32 gpio = irq_to_gpio(irq);
164 u32 gpio_idx = gpio & 0x1f;
165 struct mxs_gpio_port *port = &mxs_gpio_ports[gpio / 32];
166
167 if (enable) {
168 if (port->irq_high && (gpio_idx >= 16))
169 enable_irq_wake(port->irq_high);
170 else
171 enable_irq_wake(port->irq);
172 } else {
173 if (port->irq_high && (gpio_idx >= 16))
174 disable_irq_wake(port->irq_high);
175 else
176 disable_irq_wake(port->irq);
177 }
178
179 return 0;
180}
181
182static struct irq_chip gpio_irq_chip = {
183 .ack = mxs_gpio_ack_irq,
184 .mask = mxs_gpio_mask_irq,
185 .unmask = mxs_gpio_unmask_irq,
186 .set_type = mxs_gpio_set_irq_type,
187 .set_wake = mxs_gpio_set_wake_irq,
188};
189
190static void mxs_set_gpio_direction(struct gpio_chip *chip, unsigned offset,
191 int dir)
192{
193 struct mxs_gpio_port *port =
194 container_of(chip, struct mxs_gpio_port, chip);
195 void __iomem *pin_addr = port->base + PINCTRL_DOE(port->id);
196
197 if (dir)
198 __mxs_setl(1 << offset, pin_addr);
199 else
200 __mxs_clrl(1 << offset, pin_addr);
201}
202
203static int mxs_gpio_get(struct gpio_chip *chip, unsigned offset)
204{
205 struct mxs_gpio_port *port =
206 container_of(chip, struct mxs_gpio_port, chip);
207
208 return (__raw_readl(port->base + PINCTRL_DIN(port->id)) >> offset) & 1;
209}
210
211static void mxs_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
212{
213 struct mxs_gpio_port *port =
214 container_of(chip, struct mxs_gpio_port, chip);
215 void __iomem *pin_addr = port->base + PINCTRL_DOUT(port->id);
216
217 if (value)
218 __mxs_setl(1 << offset, pin_addr);
219 else
220 __mxs_clrl(1 << offset, pin_addr);
221}
222
223static int mxs_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
224{
225 struct mxs_gpio_port *port =
226 container_of(chip, struct mxs_gpio_port, chip);
227
228 return port->virtual_irq_start + offset;
229}
230
231static int mxs_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
232{
233 mxs_set_gpio_direction(chip, offset, 0);
234 return 0;
235}
236
237static int mxs_gpio_direction_output(struct gpio_chip *chip,
238 unsigned offset, int value)
239{
240 mxs_gpio_set(chip, offset, value);
241 mxs_set_gpio_direction(chip, offset, 1);
242 return 0;
243}
244
245int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
246{
247 int i, j;
248
249 /* save for local usage */
250 mxs_gpio_ports = port;
251 gpio_table_size = cnt;
252
253 pr_info("MXS GPIO hardware\n");
254
255 for (i = 0; i < cnt; i++) {
256 /* disable the interrupt and clear the status */
257 __raw_writel(0, port[i].base + PINCTRL_PIN2IRQ(i));
258 __raw_writel(0, port[i].base + PINCTRL_IRQEN(i));
259
260 /* clear address has to be used to clear IRQSTAT bits */
261 __mxs_clrl(~0U, port[i].base + PINCTRL_IRQSTAT(i));
262
263 for (j = port[i].virtual_irq_start;
264 j < port[i].virtual_irq_start + 32; j++) {
265 set_irq_chip(j, &gpio_irq_chip);
266 set_irq_handler(j, handle_level_irq);
267 set_irq_flags(j, IRQF_VALID);
268 }
269
270 /* setup one handler for each entry */
271 set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler);
272 set_irq_data(port[i].irq, &port[i]);
273
274 /* register gpio chip */
275 port[i].chip.direction_input = mxs_gpio_direction_input;
276 port[i].chip.direction_output = mxs_gpio_direction_output;
277 port[i].chip.get = mxs_gpio_get;
278 port[i].chip.set = mxs_gpio_set;
279 port[i].chip.to_irq = mxs_gpio_to_irq;
280 port[i].chip.base = i * 32;
281 port[i].chip.ngpio = 32;
282
283 /* its a serious configuration bug when it fails */
284 BUG_ON(gpiochip_add(&port[i].chip) < 0);
285 }
286
287 return 0;
288}
289
290#define DEFINE_MXS_GPIO_PORT(soc, _id) \
291 { \
292 .chip.label = "gpio-" #_id, \
293 .id = _id, \
294 .irq = soc ## _INT_GPIO ## _id, \
295 .base = soc ## _IO_ADDRESS( \
296 soc ## _PINCTRL ## _BASE_ADDR), \
297 .virtual_irq_start = MXS_GPIO_IRQ_START + (_id) * 32, \
298 }
299
300#define DEFINE_REGISTER_FUNCTION(prefix) \
301int __init prefix ## _register_gpios(void) \
302{ \
303 return mxs_gpio_init(prefix ## _gpio_ports, \
304 ARRAY_SIZE(prefix ## _gpio_ports)); \
305}
306
307#ifdef CONFIG_SOC_IMX23
308static struct mxs_gpio_port mx23_gpio_ports[] = {
309 DEFINE_MXS_GPIO_PORT(MX23, 0),
310 DEFINE_MXS_GPIO_PORT(MX23, 1),
311 DEFINE_MXS_GPIO_PORT(MX23, 2),
312};
313DEFINE_REGISTER_FUNCTION(mx23)
314#endif
315
316#ifdef CONFIG_SOC_IMX28
317static struct mxs_gpio_port mx28_gpio_ports[] = {
318 DEFINE_MXS_GPIO_PORT(MX28, 0),
319 DEFINE_MXS_GPIO_PORT(MX28, 1),
320 DEFINE_MXS_GPIO_PORT(MX28, 2),
321 DEFINE_MXS_GPIO_PORT(MX28, 3),
322 DEFINE_MXS_GPIO_PORT(MX28, 4),
323};
324DEFINE_REGISTER_FUNCTION(mx28)
325#endif
diff --git a/arch/arm/mach-mxs/gpio.h b/arch/arm/mach-mxs/gpio.h
new file mode 100644
index 000000000000..005bb06630b1
--- /dev/null
+++ b/arch/arm/mach-mxs/gpio.h
@@ -0,0 +1,34 @@
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __MXS_GPIO_H__
21#define __MXS_GPIO_H__
22
23struct mxs_gpio_port {
24 void __iomem *base;
25 int id;
26 int irq;
27 int irq_high;
28 int virtual_irq_start;
29 struct gpio_chip chip;
30};
31
32int mxs_gpio_init(struct mxs_gpio_port*, int);
33
34#endif /* __MXS_GPIO_H__ */
diff --git a/arch/arm/mach-mxs/icoll.c b/arch/arm/mach-mxs/icoll.c
new file mode 100644
index 000000000000..5dd43ba70058
--- /dev/null
+++ b/arch/arm/mach-mxs/icoll.c
@@ -0,0 +1,81 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/kernel.h>
20#include <linux/init.h>
21#include <linux/irq.h>
22#include <linux/io.h>
23
24#include <mach/mxs.h>
25#include <mach/common.h>
26
27#define HW_ICOLL_VECTOR 0x0000
28#define HW_ICOLL_LEVELACK 0x0010
29#define HW_ICOLL_CTRL 0x0020
30#define HW_ICOLL_INTERRUPTn_SET(n) (0x0124 + (n) * 0x10)
31#define HW_ICOLL_INTERRUPTn_CLR(n) (0x0128 + (n) * 0x10)
32#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
33#define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1
34
35static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
36
37static void icoll_ack_irq(unsigned int irq)
38{
39 /*
40 * The Interrupt Collector is able to prioritize irqs.
41 * Currently only level 0 is used. So acking can use
42 * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally.
43 */
44 __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0,
45 icoll_base + HW_ICOLL_LEVELACK);
46}
47
48static void icoll_mask_irq(unsigned int irq)
49{
50 __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
51 icoll_base + HW_ICOLL_INTERRUPTn_CLR(irq));
52}
53
54static void icoll_unmask_irq(unsigned int irq)
55{
56 __raw_writel(BM_ICOLL_INTERRUPTn_ENABLE,
57 icoll_base + HW_ICOLL_INTERRUPTn_SET(irq));
58}
59
60static struct irq_chip mxs_icoll_chip = {
61 .ack = icoll_ack_irq,
62 .mask = icoll_mask_irq,
63 .unmask = icoll_unmask_irq,
64};
65
66void __init icoll_init_irq(void)
67{
68 int i;
69
70 /*
71 * Interrupt Collector reset, which initializes the priority
72 * for each irq to level 0.
73 */
74 mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
75
76 for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
77 set_irq_chip(i, &mxs_icoll_chip);
78 set_irq_handler(i, handle_level_irq);
79 set_irq_flags(i, IRQF_VALID);
80 }
81}
diff --git a/arch/arm/mach-mxs/include/mach/clkdev.h b/arch/arm/mach-mxs/include/mach/clkdev.h
new file mode 100644
index 000000000000..3a8f2e3a6309
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/clkdev.h
@@ -0,0 +1,7 @@
1#ifndef __MACH_MXS_CLKDEV_H__
2#define __MACH_MXS_CLKDEV_H__
3
4#define __clk_get(clk) ({ 1; })
5#define __clk_put(clk) do { } while (0)
6
7#endif
diff --git a/arch/arm/mach-mxs/include/mach/clock.h b/arch/arm/mach-mxs/include/mach/clock.h
new file mode 100644
index 000000000000..041e276d8a32
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/clock.h
@@ -0,0 +1,64 @@
1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __MACH_MXS_CLOCK_H__
21#define __MACH_MXS_CLOCK_H__
22
23#ifndef __ASSEMBLY__
24#include <linux/list.h>
25
26struct module;
27
28struct clk {
29 int id;
30 /* Source clock this clk depends on */
31 struct clk *parent;
32 /* Secondary clock to enable/disable with this clock */
33 struct clk *secondary;
34 /* Reference count of clock enable/disable */
35 __s8 usecount;
36 /* Register bit position for clock's enable/disable control. */
37 u8 enable_shift;
38 /* Register address for clock's enable/disable control. */
39 void __iomem *enable_reg;
40 u32 flags;
41 /* get the current clock rate (always a fresh value) */
42 unsigned long (*get_rate) (struct clk *);
43 /* Function ptr to set the clock to a new rate. The rate must match a
44 supported rate returned from round_rate. Leave blank if clock is not
45 programmable */
46 int (*set_rate) (struct clk *, unsigned long);
47 /* Function ptr to round the requested clock rate to the nearest
48 supported rate that is less than or equal to the requested rate. */
49 unsigned long (*round_rate) (struct clk *, unsigned long);
50 /* Function ptr to enable the clock. Leave blank if clock can not
51 be gated. */
52 int (*enable) (struct clk *);
53 /* Function ptr to disable the clock. Leave blank if clock can not
54 be gated. */
55 void (*disable) (struct clk *);
56 /* Function ptr to set the parent clock of the clock. */
57 int (*set_parent) (struct clk *, struct clk *);
58};
59
60int clk_register(struct clk *clk);
61void clk_unregister(struct clk *clk);
62
63#endif /* __ASSEMBLY__ */
64#endif /* __MACH_MXS_CLOCK_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
new file mode 100644
index 000000000000..59133eb3cc96
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/common.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MACH_MXS_COMMON_H__
12#define __MACH_MXS_COMMON_H__
13
14struct clk;
15
16extern int mxs_reset_block(void __iomem *);
17extern void mxs_timer_init(struct clk *, int);
18
19extern int mx23_register_gpios(void);
20extern int mx23_clocks_init(void);
21extern void mx23_map_io(void);
22extern void mx23_init_irq(void);
23
24extern int mx28_register_gpios(void);
25extern int mx28_clocks_init(void);
26extern void mx28_map_io(void);
27extern void mx28_init_irq(void);
28
29extern void icoll_init_irq(void);
30
31#endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S
new file mode 100644
index 000000000000..79650a1ad78d
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/debug-macro.S
@@ -0,0 +1,38 @@
1/* arch/arm/mach-mxs/include/mach/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 */
13
14#include <mach/mx23.h>
15#include <mach/mx28.h>
16
17#ifdef CONFIG_SOC_IMX23
18#ifdef UART_PADDR
19#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
20#endif
21#define UART_PADDR MX23_DUART_BASE_ADDR
22#endif
23
24#ifdef CONFIG_SOC_IMX28
25#ifdef UART_PADDR
26#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
27#endif
28#define UART_PADDR MX28_DUART_BASE_ADDR
29#endif
30
31#define UART_VADDR MXS_IO_ADDRESS(UART_PADDR)
32
33 .macro addruart, rp, rv
34 ldr \rp, =UART_PADDR @ physical
35 ldr \rv, =UART_VADDR @ virtual
36 .endm
37
38#include <asm/hardware/debug-pl01x.S>
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
new file mode 100644
index 000000000000..3da48d4d3273
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -0,0 +1,46 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <linux/kernel.h>
10#include <linux/platform_device.h>
11#include <linux/init.h>
12
13struct platform_device *mxs_add_platform_device_dmamask(
14 const char *name, int id,
15 const struct resource *res, unsigned int num_resources,
16 const void *data, size_t size_data, u64 dmamask);
17
18static inline struct platform_device *mxs_add_platform_device(
19 const char *name, int id,
20 const struct resource *res, unsigned int num_resources,
21 const void *data, size_t size_data)
22{
23 return mxs_add_platform_device_dmamask(
24 name, id, res, num_resources, data, size_data, 0);
25}
26
27/* duart */
28struct mxs_duart_data {
29 resource_size_t iobase;
30 resource_size_t iosize;
31 resource_size_t irq;
32};
33struct platform_device *__init mxs_add_duart(
34 const struct mxs_duart_data *data);
35
36/* fec */
37#include <linux/fec.h>
38struct mxs_fec_data {
39 int id;
40 resource_size_t iobase;
41 resource_size_t iosize;
42 resource_size_t irq;
43};
44struct platform_device *__init mxs_add_fec(
45 const struct mxs_fec_data *data,
46 const struct fec_platform_data *pdata);
diff --git a/arch/arm/mach-mxs/include/mach/entry-macro.S b/arch/arm/mach-mxs/include/mach/entry-macro.S
new file mode 100644
index 000000000000..9f0da12e657a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/entry-macro.S
@@ -0,0 +1,41 @@
1/*
2 * Low-level IRQ helper macros for Freescale MXS-based
3 *
4 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21#include <mach/mxs.h>
22
23#define MXS_ICOLL_VBASE MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR)
24#define HW_ICOLL_STAT_OFFSET 0x70
25
26 .macro disable_fiq
27 .endm
28
29 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
30 ldr \irqnr, [\base, #HW_ICOLL_STAT_OFFSET]
31 cmp \irqnr, #0x7F
32 strne \irqnr, [\base]
33 moveqs \irqnr, #0
34 .endm
35
36 .macro get_irqnr_preamble, base, tmp
37 ldr \base, =MXS_ICOLL_VBASE
38 .endm
39
40 .macro arch_ret_to_user, tmp1, tmp2
41 .endm
diff --git a/arch/arm/mach-mxs/include/mach/gpio.h b/arch/arm/mach-mxs/include/mach/gpio.h
new file mode 100644
index 000000000000..828ccccb6aad
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/gpio.h
@@ -0,0 +1,35 @@
1/*
2 * Copyright 2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __MACH_MXS_GPIO_H__
21#define __MACH_MXS_GPIO_H__
22
23#include <asm-generic/gpio.h>
24
25#define MXS_GPIO_NR(bank, nr) ((bank) * 32 + (nr))
26
27/* use gpiolib dispatchers */
28#define gpio_get_value __gpio_get_value
29#define gpio_set_value __gpio_set_value
30#define gpio_cansleep __gpio_cansleep
31#define gpio_to_irq __gpio_to_irq
32
33#define irq_to_gpio(irq) ((irq) - MXS_GPIO_IRQ_START)
34
35#endif /* __MACH_MXS_GPIO_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/hardware.h b/arch/arm/mach-mxs/include/mach/hardware.h
new file mode 100644
index 000000000000..53e89a09bf0d
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/hardware.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
18 */
19
20#ifndef __MACH_MXS_HARDWARE_H__
21#define __MACH_MXS_HARDWARE_H__
22
23#ifdef __ASSEMBLER__
24#define IOMEM(addr) (addr)
25#else
26#define IOMEM(addr) ((void __force __iomem *)(addr))
27#endif
28
29#endif /* __MACH_MXS_HARDWARE_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/io.h b/arch/arm/mach-mxs/include/mach/io.h
new file mode 100644
index 000000000000..289b7227e072
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/io.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MACH_MXS_IO_H__
12#define __MACH_MXS_IO_H__
13
14/* Allow IO space to be anywhere in the memory */
15#define IO_SPACE_LIMIT 0xffffffff
16
17/* io address mapping macro */
18#define __io(a) __typesafe_io(a)
19
20#define __mem_pci(a) (a)
21
22#endif /* __MACH_MXS_IO_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx23.h b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
new file mode 100644
index 000000000000..94e5dd83cdb8
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx23.h
@@ -0,0 +1,355 @@
1/*
2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#ifndef __MACH_IOMUX_MX23_H__
14#define __MACH_IOMUX_MX23_H__
15
16#include <mach/iomux.h>
17
18/*
19 * The naming convention for the pad modes is MX23_PAD_<padname>__<padmode>
20 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
21 * See also iomux.h
22 *
23 * BANK PIN MUX
24 */
25/* MUXSEL_0 */
26#define MX23_PAD_GPMI_D00__GPMI_D00 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0)
27#define MX23_PAD_GPMI_D01__GPMI_D01 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0)
28#define MX23_PAD_GPMI_D02__GPMI_D02 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0)
29#define MX23_PAD_GPMI_D03__GPMI_D03 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0)
30#define MX23_PAD_GPMI_D04__GPMI_D04 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0)
31#define MX23_PAD_GPMI_D05__GPMI_D05 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0)
32#define MX23_PAD_GPMI_D06__GPMI_D06 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0)
33#define MX23_PAD_GPMI_D07__GPMI_D07 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0)
34#define MX23_PAD_GPMI_D08__GPMI_D08 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_0)
35#define MX23_PAD_GPMI_D09__GPMI_D09 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_0)
36#define MX23_PAD_GPMI_D10__GPMI_D10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_0)
37#define MX23_PAD_GPMI_D11__GPMI_D11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_0)
38#define MX23_PAD_GPMI_D12__GPMI_D12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_0)
39#define MX23_PAD_GPMI_D13__GPMI_D13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_0)
40#define MX23_PAD_GPMI_D14__GPMI_D14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_0)
41#define MX23_PAD_GPMI_D15__GPMI_D15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_0)
42#define MX23_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
43#define MX23_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
44#define MX23_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
45#define MX23_PAD_GPMI_RDY0__GPMI_RDY0 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
46#define MX23_PAD_GPMI_RDY1__GPMI_RDY1 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
47#define MX23_PAD_GPMI_RDY2__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
48#define MX23_PAD_GPMI_RDY3__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
49#define MX23_PAD_GPMI_WPN__GPMI_WPN MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
50#define MX23_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
51#define MX23_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
52#define MX23_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
53#define MX23_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
54#define MX23_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
55#define MX23_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_0)
56#define MX23_PAD_I2C_SCL__I2C_SCL MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_0)
57#define MX23_PAD_I2C_SDA__I2C_SDA MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_0)
58
59#define MX23_PAD_LCD_D00__LCD_D00 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0)
60#define MX23_PAD_LCD_D01__LCD_D01 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0)
61#define MX23_PAD_LCD_D02__LCD_D02 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0)
62#define MX23_PAD_LCD_D03__LCD_D03 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0)
63#define MX23_PAD_LCD_D04__LCD_D04 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0)
64#define MX23_PAD_LCD_D05__LCD_D05 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0)
65#define MX23_PAD_LCD_D06__LCD_D06 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0)
66#define MX23_PAD_LCD_D07__LCD_D07 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0)
67#define MX23_PAD_LCD_D08__LCD_D08 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0)
68#define MX23_PAD_LCD_D09__LCD_D09 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0)
69#define MX23_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
70#define MX23_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
71#define MX23_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
72#define MX23_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
73#define MX23_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
74#define MX23_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
75#define MX23_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
76#define MX23_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
77#define MX23_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
78#define MX23_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
79#define MX23_PAD_LCD_WR__LCD_WR MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
80#define MX23_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
81#define MX23_PAD_LCD_DOTCK__LCD_DOTCK MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
82#define MX23_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
83#define MX23_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
84#define MX23_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
85#define MX23_PAD_PWM0__PWM0 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
86#define MX23_PAD_PWM1__PWM1 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
87#define MX23_PAD_PWM2__PWM2 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
88#define MX23_PAD_PWM3__PWM3 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
89#define MX23_PAD_PWM4__PWM4 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
90
91#define MX23_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0)
92#define MX23_PAD_SSP1_DETECT__SSP1_DETECT MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0)
93#define MX23_PAD_SSP1_DATA0__SSP1_DATA0 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0)
94#define MX23_PAD_SSP1_DATA1__SSP1_DATA1 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0)
95#define MX23_PAD_SSP1_DATA2__SSP1_DATA2 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0)
96#define MX23_PAD_SSP1_DATA3__SSP1_DATA3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0)
97#define MX23_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0)
98#define MX23_PAD_ROTARYA__ROTARYA MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0)
99#define MX23_PAD_ROTARYB__ROTARYB MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0)
100#define MX23_PAD_EMI_A00__EMI_A00 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0)
101#define MX23_PAD_EMI_A01__EMI_A01 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
102#define MX23_PAD_EMI_A02__EMI_A02 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_0)
103#define MX23_PAD_EMI_A03__EMI_A03 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
104#define MX23_PAD_EMI_A04__EMI_A04 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
105#define MX23_PAD_EMI_A05__EMI_A05 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
106#define MX23_PAD_EMI_A06__EMI_A06 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
107#define MX23_PAD_EMI_A07__EMI_A07 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
108#define MX23_PAD_EMI_A08__EMI_A08 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
109#define MX23_PAD_EMI_A09__EMI_A09 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
110#define MX23_PAD_EMI_A10__EMI_A10 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
111#define MX23_PAD_EMI_A11__EMI_A11 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
112#define MX23_PAD_EMI_A12__EMI_A12 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
113#define MX23_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_0)
114#define MX23_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_0)
115#define MX23_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
116#define MX23_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
117#define MX23_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
118#define MX23_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
119#define MX23_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_0)
120#define MX23_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_0)
121#define MX23_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_0)
122#define MX23_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_0)
123
124#define MX23_PAD_EMI_D00__EMI_D00 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0)
125#define MX23_PAD_EMI_D01__EMI_D01 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0)
126#define MX23_PAD_EMI_D02__EMI_D02 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0)
127#define MX23_PAD_EMI_D03__EMI_D03 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0)
128#define MX23_PAD_EMI_D04__EMI_D04 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0)
129#define MX23_PAD_EMI_D05__EMI_D05 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0)
130#define MX23_PAD_EMI_D06__EMI_D06 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0)
131#define MX23_PAD_EMI_D07__EMI_D07 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0)
132#define MX23_PAD_EMI_D08__EMI_D08 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0)
133#define MX23_PAD_EMI_D09__EMI_D09 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0)
134#define MX23_PAD_EMI_D10__EMI_D10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
135#define MX23_PAD_EMI_D11__EMI_D11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
136#define MX23_PAD_EMI_D12__EMI_D12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
137#define MX23_PAD_EMI_D13__EMI_D13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
138#define MX23_PAD_EMI_D14__EMI_D14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
139#define MX23_PAD_EMI_D15__EMI_D15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
140#define MX23_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
141#define MX23_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
142#define MX23_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
143#define MX23_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(3, 19, PAD_MUXSEL_0)
144#define MX23_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
145#define MX23_PAD_EMI_CLKN__EMI_CLKN MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
146
147/* MUXSEL_1 */
148#define MX23_PAD_GPMI_D00__LCD_D8 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1)
149#define MX23_PAD_GPMI_D01__LCD_D9 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1)
150#define MX23_PAD_GPMI_D02__LCD_D10 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1)
151#define MX23_PAD_GPMI_D03__LCD_D11 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1)
152#define MX23_PAD_GPMI_D04__LCD_D12 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1)
153#define MX23_PAD_GPMI_D05__LCD_D13 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1)
154#define MX23_PAD_GPMI_D06__LCD_D14 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1)
155#define MX23_PAD_GPMI_D07__LCD_D15 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1)
156#define MX23_PAD_GPMI_D08__LCD_D18 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_1)
157#define MX23_PAD_GPMI_D09__LCD_D19 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_1)
158#define MX23_PAD_GPMI_D10__LCD_D20 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_1)
159#define MX23_PAD_GPMI_D11__LCD_D21 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_1)
160#define MX23_PAD_GPMI_D12__LCD_D22 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_1)
161#define MX23_PAD_GPMI_D13__LCD_D23 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_1)
162#define MX23_PAD_GPMI_D14__AUART2_RX MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_1)
163#define MX23_PAD_GPMI_D15__AUART2_TX MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_1)
164#define MX23_PAD_GPMI_CLE__LCD_D16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
165#define MX23_PAD_GPMI_ALE__LCD_D17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
166#define MX23_PAD_GPMI_CE2N__ATA_A2 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
167#define MX23_PAD_AUART1_RTS__IR_CLK MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
168#define MX23_PAD_AUART1_RX__IR_RX MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
169#define MX23_PAD_AUART1_TX__IR_TX MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_1)
170#define MX23_PAD_I2C_SCL__GPMI_RDY2 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_1)
171#define MX23_PAD_I2C_SDA__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_1)
172
173#define MX23_PAD_LCD_D00__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_1)
174#define MX23_PAD_LCD_D01__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_1)
175#define MX23_PAD_LCD_D02__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_1)
176#define MX23_PAD_LCD_D03__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1)
177#define MX23_PAD_LCD_D04__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1)
178#define MX23_PAD_LCD_D05__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_1)
179#define MX23_PAD_LCD_D06__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_1)
180#define MX23_PAD_LCD_D07__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_1)
181#define MX23_PAD_LCD_D08__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1)
182#define MX23_PAD_LCD_D09__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1)
183#define MX23_PAD_LCD_D10__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_1)
184#define MX23_PAD_LCD_D11__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_1)
185#define MX23_PAD_LCD_D12__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_1)
186#define MX23_PAD_LCD_D13__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_1)
187#define MX23_PAD_LCD_D14__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_1)
188#define MX23_PAD_LCD_D15__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_1)
189#define MX23_PAD_LCD_RESET__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_1)
190#define MX23_PAD_LCD_RS__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_1)
191#define MX23_PAD_LCD_DOTCK__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
192#define MX23_PAD_LCD_ENABLE__I2C_SCL MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
193#define MX23_PAD_LCD_HSYNC__I2C_SDA MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
194#define MX23_PAD_LCD_VSYNC__LCD_BUSY MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
195#define MX23_PAD_PWM0__ROTARYA MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
196#define MX23_PAD_PWM1__ROTARYB MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
197#define MX23_PAD_PWM2__GPMI_RDY3 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
198#define MX23_PAD_PWM3__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
199#define MX23_PAD_PWM4__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
200
201#define MX23_PAD_SSP1_DETECT__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_1)
202#define MX23_PAD_SSP1_DATA1__I2C_SCL MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_1)
203#define MX23_PAD_SSP1_DATA2__I2C_SDA MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1)
204#define MX23_PAD_ROTARYA__AUART2_RTS MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1)
205#define MX23_PAD_ROTARYB__AUART2_CTS MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_1)
206
207/* MUXSEL_2 */
208#define MX23_PAD_GPMI_D00__SSP2_DATA0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_2)
209#define MX23_PAD_GPMI_D01__SSP2_DATA1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_2)
210#define MX23_PAD_GPMI_D02__SSP2_DATA2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_2)
211#define MX23_PAD_GPMI_D03__SSP2_DATA3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_2)
212#define MX23_PAD_GPMI_D04__SSP2_DATA4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_2)
213#define MX23_PAD_GPMI_D05__SSP2_DATA5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_2)
214#define MX23_PAD_GPMI_D06__SSP2_DATA6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_2)
215#define MX23_PAD_GPMI_D07__SSP2_DATA7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_2)
216#define MX23_PAD_GPMI_D08__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_2)
217#define MX23_PAD_GPMI_D09__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_2)
218#define MX23_PAD_GPMI_D10__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_2)
219#define MX23_PAD_GPMI_D11__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_2)
220#define MX23_PAD_GPMI_D15__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_2)
221#define MX23_PAD_GPMI_RDY0__SSP2_DETECT MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
222#define MX23_PAD_GPMI_RDY1__SSP2_CMD MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
223#define MX23_PAD_GPMI_WRN__SSP2_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_2)
224#define MX23_PAD_AUART1_CTS__SSP1_DATA4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
225#define MX23_PAD_AUART1_RTS__SSP1_DATA5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
226#define MX23_PAD_AUART1_RX__SSP1_DATA6 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_2)
227#define MX23_PAD_AUART1_TX__SSP1_DATA7 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_2)
228#define MX23_PAD_I2C_SCL__AUART1_TX MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_2)
229#define MX23_PAD_I2C_SDA__AUART1_RX MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_2)
230
231#define MX23_PAD_LCD_D08__SAIF2_SDATA0 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2)
232#define MX23_PAD_LCD_D09__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2)
233#define MX23_PAD_LCD_D10__SAIF_MCLK_BITCLK MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
234#define MX23_PAD_LCD_D11__SAIF_LRCLK MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
235#define MX23_PAD_LCD_D12__SAIF2_SDATA1 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
236#define MX23_PAD_LCD_D13__SAIF2_SDATA2 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
237#define MX23_PAD_LCD_D14__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
238#define MX23_PAD_LCD_D15__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
239#define MX23_PAD_LCD_D16__SAIF_ALT_BITCLK MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
240#define MX23_PAD_LCD_RESET__GPMI_CE3N MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
241#define MX23_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_2)
242#define MX23_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_2)
243#define MX23_PAD_PWM3__AUART1_CTS MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
244#define MX23_PAD_PWM4__AUART1_RTS MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
245
246#define MX23_PAD_SSP1_CMD__JTAG_TDO MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_2)
247#define MX23_PAD_SSP1_DETECT__USB_OTG_ID MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_2)
248#define MX23_PAD_SSP1_DATA0__JTAG_TDI MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_2)
249#define MX23_PAD_SSP1_DATA1__JTAG_TCLK MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_2)
250#define MX23_PAD_SSP1_DATA2__JTAG_RTCK MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_2)
251#define MX23_PAD_SSP1_DATA3__JTAG_TMS MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_2)
252#define MX23_PAD_SSP1_SCK__JTAG_TRST MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_2)
253#define MX23_PAD_ROTARYA__SPDIF MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_2)
254#define MX23_PAD_ROTARYB__GPMI_CE3N MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_2)
255
256/* MUXSEL_GPIO */
257#define MX23_PAD_GPMI_D00__GPO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO)
258#define MX23_PAD_GPMI_D01__GPO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO)
259#define MX23_PAD_GPMI_D02__GPO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO)
260#define MX23_PAD_GPMI_D03__GPO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO)
261#define MX23_PAD_GPMI_D04__GPO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO)
262#define MX23_PAD_GPMI_D05__GPO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO)
263#define MX23_PAD_GPMI_D06__GPO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO)
264#define MX23_PAD_GPMI_D07__GPO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO)
265#define MX23_PAD_GPMI_D08__GPO_0_8 MXS_IOMUX_PAD_NAKED(0, 8, PAD_MUXSEL_GPIO)
266#define MX23_PAD_GPMI_D09__GPO_0_9 MXS_IOMUX_PAD_NAKED(0, 9, PAD_MUXSEL_GPIO)
267#define MX23_PAD_GPMI_D10__GPO_0_10 MXS_IOMUX_PAD_NAKED(0, 10, PAD_MUXSEL_GPIO)
268#define MX23_PAD_GPMI_D11__GPO_0_11 MXS_IOMUX_PAD_NAKED(0, 11, PAD_MUXSEL_GPIO)
269#define MX23_PAD_GPMI_D12__GPO_0_12 MXS_IOMUX_PAD_NAKED(0, 12, PAD_MUXSEL_GPIO)
270#define MX23_PAD_GPMI_D13__GPO_0_13 MXS_IOMUX_PAD_NAKED(0, 13, PAD_MUXSEL_GPIO)
271#define MX23_PAD_GPMI_D14__GPO_0_14 MXS_IOMUX_PAD_NAKED(0, 14, PAD_MUXSEL_GPIO)
272#define MX23_PAD_GPMI_D15__GPO_0_15 MXS_IOMUX_PAD_NAKED(0, 15, PAD_MUXSEL_GPIO)
273#define MX23_PAD_GPMI_CLE__GPO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
274#define MX23_PAD_GPMI_ALE__GPO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
275#define MX23_PAD_GPMI_CE2N__GPO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
276#define MX23_PAD_GPMI_RDY0__GPO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
277#define MX23_PAD_GPMI_RDY1__GPO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
278#define MX23_PAD_GPMI_RDY2__GPO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
279#define MX23_PAD_GPMI_RDY3__GPO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
280#define MX23_PAD_GPMI_WPN__GPO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
281#define MX23_PAD_GPMI_WRN__GPO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
282#define MX23_PAD_GPMI_RDN__GPO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
283#define MX23_PAD_AUART1_CTS__GPO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
284#define MX23_PAD_AUART1_RTS__GPO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
285#define MX23_PAD_AUART1_RX__GPO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
286#define MX23_PAD_AUART1_TX__GPO_0_29 MXS_IOMUX_PAD_NAKED(0, 29, PAD_MUXSEL_GPIO)
287#define MX23_PAD_I2C_SCL__GPO_0_30 MXS_IOMUX_PAD_NAKED(0, 30, PAD_MUXSEL_GPIO)
288#define MX23_PAD_I2C_SDA__GPO_0_31 MXS_IOMUX_PAD_NAKED(0, 31, PAD_MUXSEL_GPIO)
289
290#define MX23_PAD_LCD_D00__GPO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO)
291#define MX23_PAD_LCD_D01__GPO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO)
292#define MX23_PAD_LCD_D02__GPO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO)
293#define MX23_PAD_LCD_D03__GPO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO)
294#define MX23_PAD_LCD_D04__GPO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO)
295#define MX23_PAD_LCD_D05__GPO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO)
296#define MX23_PAD_LCD_D06__GPO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO)
297#define MX23_PAD_LCD_D07__GPO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO)
298#define MX23_PAD_LCD_D08__GPO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO)
299#define MX23_PAD_LCD_D09__GPO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO)
300#define MX23_PAD_LCD_D10__GPO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
301#define MX23_PAD_LCD_D11__GPO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
302#define MX23_PAD_LCD_D12__GPO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
303#define MX23_PAD_LCD_D13__GPO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
304#define MX23_PAD_LCD_D14__GPO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
305#define MX23_PAD_LCD_D15__GPO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
306#define MX23_PAD_LCD_D16__GPO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
307#define MX23_PAD_LCD_D17__GPO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
308#define MX23_PAD_LCD_RESET__GPO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
309#define MX23_PAD_LCD_RS__GPO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
310#define MX23_PAD_LCD_WR__GPO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
311#define MX23_PAD_LCD_CS__GPO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
312#define MX23_PAD_LCD_DOTCK__GPO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
313#define MX23_PAD_LCD_ENABLE__GPO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
314#define MX23_PAD_LCD_HSYNC__GPO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
315#define MX23_PAD_LCD_VSYNC__GPO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
316#define MX23_PAD_PWM0__GPO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
317#define MX23_PAD_PWM1__GPO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
318#define MX23_PAD_PWM2__GPO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
319#define MX23_PAD_PWM3__GPO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
320#define MX23_PAD_PWM4__GPO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
321
322#define MX23_PAD_SSP1_CMD__GPO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO)
323#define MX23_PAD_SSP1_DETECT__GPO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO)
324#define MX23_PAD_SSP1_DATA0__GPO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO)
325#define MX23_PAD_SSP1_DATA1__GPO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO)
326#define MX23_PAD_SSP1_DATA2__GPO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO)
327#define MX23_PAD_SSP1_DATA3__GPO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO)
328#define MX23_PAD_SSP1_SCK__GPO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO)
329#define MX23_PAD_ROTARYA__GPO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO)
330#define MX23_PAD_ROTARYB__GPO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO)
331#define MX23_PAD_EMI_A00__GPO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO)
332#define MX23_PAD_EMI_A01__GPO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
333#define MX23_PAD_EMI_A02__GPO_2_11 MXS_IOMUX_PAD_NAKED(2, 11, PAD_MUXSEL_GPIO)
334#define MX23_PAD_EMI_A03__GPO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
335#define MX23_PAD_EMI_A04__GPO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
336#define MX23_PAD_EMI_A05__GPO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
337#define MX23_PAD_EMI_A06__GPO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
338#define MX23_PAD_EMI_A07__GPO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
339#define MX23_PAD_EMI_A08__GPO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
340#define MX23_PAD_EMI_A09__GPO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
341#define MX23_PAD_EMI_A10__GPO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
342#define MX23_PAD_EMI_A11__GPO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
343#define MX23_PAD_EMI_A12__GPO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
344#define MX23_PAD_EMI_BA0__GPO_2_22 MXS_IOMUX_PAD_NAKED(2, 22, PAD_MUXSEL_GPIO)
345#define MX23_PAD_EMI_BA1__GPO_2_23 MXS_IOMUX_PAD_NAKED(2, 23, PAD_MUXSEL_GPIO)
346#define MX23_PAD_EMI_CASN__GPO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
347#define MX23_PAD_EMI_CE0N__GPO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
348#define MX23_PAD_EMI_CE1N__GPO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
349#define MX23_PAD_GPMI_CE1N__GPO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
350#define MX23_PAD_GPMI_CE0N__GPO_2_28 MXS_IOMUX_PAD_NAKED(2, 28, PAD_MUXSEL_GPIO)
351#define MX23_PAD_EMI_CKE__GPO_2_29 MXS_IOMUX_PAD_NAKED(2, 29, PAD_MUXSEL_GPIO)
352#define MX23_PAD_EMI_RASN__GPO_2_30 MXS_IOMUX_PAD_NAKED(2, 30, PAD_MUXSEL_GPIO)
353#define MX23_PAD_EMI_WEN__GPO_2_31 MXS_IOMUX_PAD_NAKED(2, 31, PAD_MUXSEL_GPIO)
354
355#endif /* __MACH_IOMUX_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux-mx28.h b/arch/arm/mach-mxs/include/mach/iomux-mx28.h
new file mode 100644
index 000000000000..f50fefd10520
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/iomux-mx28.h
@@ -0,0 +1,537 @@
1/*
2 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13#ifndef __MACH_IOMUX_MX28_H__
14#define __MACH_IOMUX_MX28_H__
15
16#include <mach/iomux.h>
17
18/*
19 * The naming convention for the pad modes is MX28_PAD_<padname>__<padmode>
20 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num>
21 * See also iomux.h
22 *
23 * BANK PIN MUX
24 */
25/* MUXSEL_0 */
26#define MX28_PAD_GPMI_D00__GPMI_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_0)
27#define MX28_PAD_GPMI_D01__GPMI_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_0)
28#define MX28_PAD_GPMI_D02__GPMI_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_0)
29#define MX28_PAD_GPMI_D03__GPMI_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_0)
30#define MX28_PAD_GPMI_D04__GPMI_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_0)
31#define MX28_PAD_GPMI_D05__GPMI_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_0)
32#define MX28_PAD_GPMI_D06__GPMI_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_0)
33#define MX28_PAD_GPMI_D07__GPMI_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_0)
34#define MX28_PAD_GPMI_CE0N__GPMI_CE0N MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_0)
35#define MX28_PAD_GPMI_CE1N__GPMI_CE1N MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_0)
36#define MX28_PAD_GPMI_CE2N__GPMI_CE2N MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_0)
37#define MX28_PAD_GPMI_CE3N__GPMI_CE3N MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_0)
38#define MX28_PAD_GPMI_RDY0__GPMI_READY0 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_0)
39#define MX28_PAD_GPMI_RDY1__GPMI_READY1 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_0)
40#define MX28_PAD_GPMI_RDY2__GPMI_READY2 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_0)
41#define MX28_PAD_GPMI_RDY3__GPMI_READY3 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_0)
42#define MX28_PAD_GPMI_RDN__GPMI_RDN MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_0)
43#define MX28_PAD_GPMI_WRN__GPMI_WRN MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_0)
44#define MX28_PAD_GPMI_ALE__GPMI_ALE MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_0)
45#define MX28_PAD_GPMI_CLE__GPMI_CLE MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_0)
46#define MX28_PAD_GPMI_RESETN__GPMI_RESETN MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_0)
47
48#define MX28_PAD_LCD_D00__LCD_D0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_0)
49#define MX28_PAD_LCD_D01__LCD_D1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_0)
50#define MX28_PAD_LCD_D02__LCD_D2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_0)
51#define MX28_PAD_LCD_D03__LCD_D3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_0)
52#define MX28_PAD_LCD_D04__LCD_D4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_0)
53#define MX28_PAD_LCD_D05__LCD_D5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_0)
54#define MX28_PAD_LCD_D06__LCD_D6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_0)
55#define MX28_PAD_LCD_D07__LCD_D7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_0)
56#define MX28_PAD_LCD_D08__LCD_D8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_0)
57#define MX28_PAD_LCD_D09__LCD_D9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_0)
58#define MX28_PAD_LCD_D10__LCD_D10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_0)
59#define MX28_PAD_LCD_D11__LCD_D11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_0)
60#define MX28_PAD_LCD_D12__LCD_D12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_0)
61#define MX28_PAD_LCD_D13__LCD_D13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_0)
62#define MX28_PAD_LCD_D14__LCD_D14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_0)
63#define MX28_PAD_LCD_D15__LCD_D15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_0)
64#define MX28_PAD_LCD_D16__LCD_D16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_0)
65#define MX28_PAD_LCD_D17__LCD_D17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_0)
66#define MX28_PAD_LCD_D18__LCD_D18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_0)
67#define MX28_PAD_LCD_D19__LCD_D19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_0)
68#define MX28_PAD_LCD_D20__LCD_D20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_0)
69#define MX28_PAD_LCD_D21__LCD_D21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_0)
70#define MX28_PAD_LCD_D22__LCD_D22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_0)
71#define MX28_PAD_LCD_D23__LCD_D23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_0)
72#define MX28_PAD_LCD_RD_E__LCD_RD_E MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_0)
73#define MX28_PAD_LCD_WR_RWN__LCD_WR_RWN MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_0)
74#define MX28_PAD_LCD_RS__LCD_RS MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_0)
75#define MX28_PAD_LCD_CS__LCD_CS MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_0)
76#define MX28_PAD_LCD_VSYNC__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_0)
77#define MX28_PAD_LCD_HSYNC__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_0)
78#define MX28_PAD_LCD_DOTCLK__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_0)
79#define MX28_PAD_LCD_ENABLE__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_0)
80
81#define MX28_PAD_SSP0_DATA0__SSP0_D0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_0)
82#define MX28_PAD_SSP0_DATA1__SSP0_D1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_0)
83#define MX28_PAD_SSP0_DATA2__SSP0_D2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_0)
84#define MX28_PAD_SSP0_DATA3__SSP0_D3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_0)
85#define MX28_PAD_SSP0_DATA4__SSP0_D4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_0)
86#define MX28_PAD_SSP0_DATA5__SSP0_D5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_0)
87#define MX28_PAD_SSP0_DATA6__SSP0_D6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_0)
88#define MX28_PAD_SSP0_DATA7__SSP0_D7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_0)
89#define MX28_PAD_SSP0_CMD__SSP0_CMD MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_0)
90#define MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_0)
91#define MX28_PAD_SSP0_SCK__SSP0_SCK MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_0)
92#define MX28_PAD_SSP1_SCK__SSP1_SCK MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_0)
93#define MX28_PAD_SSP1_CMD__SSP1_CMD MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_0)
94#define MX28_PAD_SSP1_DATA0__SSP1_D0 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_0)
95#define MX28_PAD_SSP1_DATA3__SSP1_D3 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_0)
96#define MX28_PAD_SSP2_SCK__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_0)
97#define MX28_PAD_SSP2_MOSI__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_0)
98#define MX28_PAD_SSP2_MISO__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_0)
99#define MX28_PAD_SSP2_SS0__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_0)
100#define MX28_PAD_SSP2_SS1__SSP2_D4 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_0)
101#define MX28_PAD_SSP2_SS2__SSP2_D5 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_0)
102#define MX28_PAD_SSP3_SCK__SSP3_SCK MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_0)
103#define MX28_PAD_SSP3_MOSI__SSP3_CMD MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_0)
104#define MX28_PAD_SSP3_MISO__SSP3_D0 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_0)
105#define MX28_PAD_SSP3_SS0__SSP3_D3 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_0)
106
107#define MX28_PAD_AUART0_RX__AUART0_RX MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_0)
108#define MX28_PAD_AUART0_TX__AUART0_TX MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_0)
109#define MX28_PAD_AUART0_CTS__AUART0_CTS MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_0)
110#define MX28_PAD_AUART0_RTS__AUART0_RTS MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_0)
111#define MX28_PAD_AUART1_RX__AUART1_RX MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_0)
112#define MX28_PAD_AUART1_TX__AUART1_TX MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_0)
113#define MX28_PAD_AUART1_CTS__AUART1_CTS MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_0)
114#define MX28_PAD_AUART1_RTS__AUART1_RTS MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_0)
115#define MX28_PAD_AUART2_RX__AUART2_RX MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_0)
116#define MX28_PAD_AUART2_TX__AUART2_TX MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_0)
117#define MX28_PAD_AUART2_CTS__AUART2_CTS MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_0)
118#define MX28_PAD_AUART2_RTS__AUART2_RTS MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_0)
119#define MX28_PAD_AUART3_RX__AUART3_RX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_0)
120#define MX28_PAD_AUART3_TX__AUART3_TX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_0)
121#define MX28_PAD_AUART3_CTS__AUART3_CTS MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_0)
122#define MX28_PAD_AUART3_RTS__AUART3_RTS MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_0)
123#define MX28_PAD_PWM0__PWM_0 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_0)
124#define MX28_PAD_PWM1__PWM_1 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_0)
125#define MX28_PAD_PWM2__PWM_2 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_0)
126#define MX28_PAD_SAIF0_MCLK__SAIF0_MCLK MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_0)
127#define MX28_PAD_SAIF0_LRCLK__SAIF0_LRCLK MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_0)
128#define MX28_PAD_SAIF0_BITCLK__SAIF0_BITCLK MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_0)
129#define MX28_PAD_SAIF0_SDATA0__SAIF0_SDATA0 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_0)
130#define MX28_PAD_I2C0_SCL__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_0)
131#define MX28_PAD_I2C0_SDA__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_0)
132#define MX28_PAD_SAIF1_SDATA0__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_0)
133#define MX28_PAD_SPDIF__SPDIF_TX MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_0)
134#define MX28_PAD_PWM3__PWM_3 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_0)
135#define MX28_PAD_PWM4__PWM_4 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_0)
136#define MX28_PAD_LCD_RESET__LCD_RESET MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_0)
137
138#define MX28_PAD_ENET0_MDC__ENET0_MDC MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_0)
139#define MX28_PAD_ENET0_MDIO__ENET0_MDIO MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_0)
140#define MX28_PAD_ENET0_RX_EN__ENET0_RX_EN MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_0)
141#define MX28_PAD_ENET0_RXD0__ENET0_RXD0 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_0)
142#define MX28_PAD_ENET0_RXD1__ENET0_RXD1 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_0)
143#define MX28_PAD_ENET0_TX_CLK__ENET0_TX_CLK MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_0)
144#define MX28_PAD_ENET0_TX_EN__ENET0_TX_EN MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_0)
145#define MX28_PAD_ENET0_TXD0__ENET0_TXD0 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_0)
146#define MX28_PAD_ENET0_TXD1__ENET0_TXD1 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_0)
147#define MX28_PAD_ENET0_RXD2__ENET0_RXD2 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_0)
148#define MX28_PAD_ENET0_RXD3__ENET0_RXD3 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_0)
149#define MX28_PAD_ENET0_TXD2__ENET0_TXD2 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_0)
150#define MX28_PAD_ENET0_TXD3__ENET0_TXD3 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_0)
151#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_CLK MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_0)
152#define MX28_PAD_ENET0_COL__ENET0_COL MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_0)
153#define MX28_PAD_ENET0_CRS__ENET0_CRS MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_0)
154#define MX28_PAD_ENET_CLK__CLKCTRL_ENET MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_0)
155#define MX28_PAD_JTAG_RTCK__JTAG_RTCK MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_0)
156
157#define MX28_PAD_EMI_D00__EMI_DATA0 MXS_IOMUX_PAD_NAKED(5, 0, PAD_MUXSEL_0)
158#define MX28_PAD_EMI_D01__EMI_DATA1 MXS_IOMUX_PAD_NAKED(5, 1, PAD_MUXSEL_0)
159#define MX28_PAD_EMI_D02__EMI_DATA2 MXS_IOMUX_PAD_NAKED(5, 2, PAD_MUXSEL_0)
160#define MX28_PAD_EMI_D03__EMI_DATA3 MXS_IOMUX_PAD_NAKED(5, 3, PAD_MUXSEL_0)
161#define MX28_PAD_EMI_D04__EMI_DATA4 MXS_IOMUX_PAD_NAKED(5, 4, PAD_MUXSEL_0)
162#define MX28_PAD_EMI_D05__EMI_DATA5 MXS_IOMUX_PAD_NAKED(5, 5, PAD_MUXSEL_0)
163#define MX28_PAD_EMI_D06__EMI_DATA6 MXS_IOMUX_PAD_NAKED(5, 6, PAD_MUXSEL_0)
164#define MX28_PAD_EMI_D07__EMI_DATA7 MXS_IOMUX_PAD_NAKED(5, 7, PAD_MUXSEL_0)
165#define MX28_PAD_EMI_D08__EMI_DATA8 MXS_IOMUX_PAD_NAKED(5, 8, PAD_MUXSEL_0)
166#define MX28_PAD_EMI_D09__EMI_DATA9 MXS_IOMUX_PAD_NAKED(5, 9, PAD_MUXSEL_0)
167#define MX28_PAD_EMI_D10__EMI_DATA10 MXS_IOMUX_PAD_NAKED(5, 10, PAD_MUXSEL_0)
168#define MX28_PAD_EMI_D11__EMI_DATA11 MXS_IOMUX_PAD_NAKED(5, 11, PAD_MUXSEL_0)
169#define MX28_PAD_EMI_D12__EMI_DATA12 MXS_IOMUX_PAD_NAKED(5, 12, PAD_MUXSEL_0)
170#define MX28_PAD_EMI_D13__EMI_DATA13 MXS_IOMUX_PAD_NAKED(5, 13, PAD_MUXSEL_0)
171#define MX28_PAD_EMI_D14__EMI_DATA14 MXS_IOMUX_PAD_NAKED(5, 14, PAD_MUXSEL_0)
172#define MX28_PAD_EMI_D15__EMI_DATA15 MXS_IOMUX_PAD_NAKED(5, 15, PAD_MUXSEL_0)
173#define MX28_PAD_EMI_ODT0__EMI_ODT0 MXS_IOMUX_PAD_NAKED(5, 16, PAD_MUXSEL_0)
174#define MX28_PAD_EMI_DQM0__EMI_DQM0 MXS_IOMUX_PAD_NAKED(5, 17, PAD_MUXSEL_0)
175#define MX28_PAD_EMI_ODT1__EMI_ODT1 MXS_IOMUX_PAD_NAKED(5, 18, PAD_MUXSEL_0)
176#define MX28_PAD_EMI_DQM1__EMI_DQM1 MXS_IOMUX_PAD_NAKED(5, 19, PAD_MUXSEL_0)
177#define MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK MXS_IOMUX_PAD_NAKED(5, 20, PAD_MUXSEL_0)
178#define MX28_PAD_EMI_CLK__EMI_CLK MXS_IOMUX_PAD_NAKED(5, 21, PAD_MUXSEL_0)
179#define MX28_PAD_EMI_DQS0__EMI_DQS0 MXS_IOMUX_PAD_NAKED(5, 22, PAD_MUXSEL_0)
180#define MX28_PAD_EMI_DQS1__EMI_DQS1 MXS_IOMUX_PAD_NAKED(5, 23, PAD_MUXSEL_0)
181#define MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN MXS_IOMUX_PAD_NAKED(5, 26, PAD_MUXSEL_0)
182
183#define MX28_PAD_EMI_A00__EMI_ADDR0 MXS_IOMUX_PAD_NAKED(6, 0, PAD_MUXSEL_0)
184#define MX28_PAD_EMI_A01__EMI_ADDR1 MXS_IOMUX_PAD_NAKED(6, 1, PAD_MUXSEL_0)
185#define MX28_PAD_EMI_A02__EMI_ADDR2 MXS_IOMUX_PAD_NAKED(6, 2, PAD_MUXSEL_0)
186#define MX28_PAD_EMI_A03__EMI_ADDR3 MXS_IOMUX_PAD_NAKED(6, 3, PAD_MUXSEL_0)
187#define MX28_PAD_EMI_A04__EMI_ADDR4 MXS_IOMUX_PAD_NAKED(6, 4, PAD_MUXSEL_0)
188#define MX28_PAD_EMI_A05__EMI_ADDR5 MXS_IOMUX_PAD_NAKED(6, 5, PAD_MUXSEL_0)
189#define MX28_PAD_EMI_A06__EMI_ADDR6 MXS_IOMUX_PAD_NAKED(6, 6, PAD_MUXSEL_0)
190#define MX28_PAD_EMI_A07__EMI_ADDR7 MXS_IOMUX_PAD_NAKED(6, 7, PAD_MUXSEL_0)
191#define MX28_PAD_EMI_A08__EMI_ADDR8 MXS_IOMUX_PAD_NAKED(6, 8, PAD_MUXSEL_0)
192#define MX28_PAD_EMI_A09__EMI_ADDR9 MXS_IOMUX_PAD_NAKED(6, 9, PAD_MUXSEL_0)
193#define MX28_PAD_EMI_A10__EMI_ADDR10 MXS_IOMUX_PAD_NAKED(6, 10, PAD_MUXSEL_0)
194#define MX28_PAD_EMI_A11__EMI_ADDR11 MXS_IOMUX_PAD_NAKED(6, 11, PAD_MUXSEL_0)
195#define MX28_PAD_EMI_A12__EMI_ADDR12 MXS_IOMUX_PAD_NAKED(6, 12, PAD_MUXSEL_0)
196#define MX28_PAD_EMI_A13__EMI_ADDR13 MXS_IOMUX_PAD_NAKED(6, 13, PAD_MUXSEL_0)
197#define MX28_PAD_EMI_A14__EMI_ADDR14 MXS_IOMUX_PAD_NAKED(6, 14, PAD_MUXSEL_0)
198#define MX28_PAD_EMI_BA0__EMI_BA0 MXS_IOMUX_PAD_NAKED(6, 16, PAD_MUXSEL_0)
199#define MX28_PAD_EMI_BA1__EMI_BA1 MXS_IOMUX_PAD_NAKED(6, 17, PAD_MUXSEL_0)
200#define MX28_PAD_EMI_BA2__EMI_BA2 MXS_IOMUX_PAD_NAKED(6, 18, PAD_MUXSEL_0)
201#define MX28_PAD_EMI_CASN__EMI_CASN MXS_IOMUX_PAD_NAKED(6, 19, PAD_MUXSEL_0)
202#define MX28_PAD_EMI_RASN__EMI_RASN MXS_IOMUX_PAD_NAKED(6, 20, PAD_MUXSEL_0)
203#define MX28_PAD_EMI_WEN__EMI_WEN MXS_IOMUX_PAD_NAKED(6, 21, PAD_MUXSEL_0)
204#define MX28_PAD_EMI_CE0N__EMI_CE0N MXS_IOMUX_PAD_NAKED(6, 22, PAD_MUXSEL_0)
205#define MX28_PAD_EMI_CE1N__EMI_CE1N MXS_IOMUX_PAD_NAKED(6, 23, PAD_MUXSEL_0)
206#define MX28_PAD_EMI_CKE__EMI_CKE MXS_IOMUX_PAD_NAKED(6, 24, PAD_MUXSEL_0)
207
208/* MUXSEL_1 */
209#define MX28_PAD_GPMI_D00__SSP1_D0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_1)
210#define MX28_PAD_GPMI_D01__SSP1_D1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_1)
211#define MX28_PAD_GPMI_D02__SSP1_D2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_1)
212#define MX28_PAD_GPMI_D03__SSP1_D3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_1)
213#define MX28_PAD_GPMI_D04__SSP1_D4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_1)
214#define MX28_PAD_GPMI_D05__SSP1_D5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_1)
215#define MX28_PAD_GPMI_D06__SSP1_D6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_1)
216#define MX28_PAD_GPMI_D07__SSP1_D7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_1)
217#define MX28_PAD_GPMI_CE0N__SSP3_D0 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_1)
218#define MX28_PAD_GPMI_CE1N__SSP3_D3 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_1)
219#define MX28_PAD_GPMI_CE2N__CAN1_TX MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_1)
220#define MX28_PAD_GPMI_CE3N__CAN1_RX MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_1)
221#define MX28_PAD_GPMI_RDY0__SSP1_CARD_DETECT MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_1)
222#define MX28_PAD_GPMI_RDY1__SSP1_CMD MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_1)
223#define MX28_PAD_GPMI_RDY2__CAN0_TX MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_1)
224#define MX28_PAD_GPMI_RDY3__CAN0_RX MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_1)
225#define MX28_PAD_GPMI_RDN__SSP3_SCK MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_1)
226#define MX28_PAD_GPMI_WRN__SSP1_SCK MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_1)
227#define MX28_PAD_GPMI_ALE__SSP3_D1 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_1)
228#define MX28_PAD_GPMI_CLE__SSP3_D2 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_1)
229#define MX28_PAD_GPMI_RESETN__SSP3_CMD MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_1)
230
231#define MX28_PAD_LCD_D03__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_1)
232#define MX28_PAD_LCD_D04__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_1)
233#define MX28_PAD_LCD_D08__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_1)
234#define MX28_PAD_LCD_D09__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_1)
235#define MX28_PAD_LCD_D20__ENET1_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_1)
236#define MX28_PAD_LCD_D21__ENET1_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_1)
237#define MX28_PAD_LCD_D22__ENET1_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_1)
238#define MX28_PAD_LCD_D23__ENET1_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_1)
239#define MX28_PAD_LCD_RD_E__LCD_VSYNC MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_1)
240#define MX28_PAD_LCD_WR_RWN__LCD_HSYNC MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_1)
241#define MX28_PAD_LCD_RS__LCD_DOTCLK MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_1)
242#define MX28_PAD_LCD_CS__LCD_ENABLE MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_1)
243#define MX28_PAD_LCD_VSYNC__SAIF1_SDATA0 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_1)
244#define MX28_PAD_LCD_HSYNC__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_1)
245#define MX28_PAD_LCD_DOTCLK__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_1)
246
247#define MX28_PAD_SSP0_DATA4__SSP2_D0 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_1)
248#define MX28_PAD_SSP0_DATA5__SSP2_D3 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_1)
249#define MX28_PAD_SSP0_DATA6__SSP2_CMD MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_1)
250#define MX28_PAD_SSP0_DATA7__SSP2_SCK MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_1)
251#define MX28_PAD_SSP1_SCK__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_1)
252#define MX28_PAD_SSP1_CMD__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_1)
253#define MX28_PAD_SSP1_DATA0__SSP2_D6 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_1)
254#define MX28_PAD_SSP1_DATA3__SSP2_D7 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_1)
255#define MX28_PAD_SSP2_SCK__AUART2_RX MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_1)
256#define MX28_PAD_SSP2_MOSI__AUART2_TX MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_1)
257#define MX28_PAD_SSP2_MISO__AUART3_RX MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_1)
258#define MX28_PAD_SSP2_SS0__AUART3_TX MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_1)
259#define MX28_PAD_SSP2_SS1__SSP2_D1 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_1)
260#define MX28_PAD_SSP2_SS2__SSP2_D2 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_1)
261#define MX28_PAD_SSP3_SCK__AUART4_TX MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_1)
262#define MX28_PAD_SSP3_MOSI__AUART4_RX MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_1)
263#define MX28_PAD_SSP3_MISO__AUART4_RTS MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_1)
264#define MX28_PAD_SSP3_SS0__AUART4_CTS MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_1)
265
266#define MX28_PAD_AUART0_RX__I2C0_SCL MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_1)
267#define MX28_PAD_AUART0_TX__I2C0_SDA MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_1)
268#define MX28_PAD_AUART0_CTS__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_1)
269#define MX28_PAD_AUART0_RTS__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_1)
270#define MX28_PAD_AUART1_RX__SSP2_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_1)
271#define MX28_PAD_AUART1_TX__SSP3_CARD_DETECT MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_1)
272#define MX28_PAD_AUART1_CTS__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_1)
273#define MX28_PAD_AUART1_RTS__USB0_ID MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_1)
274#define MX28_PAD_AUART2_RX__SSP3_D1 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_1)
275#define MX28_PAD_AUART2_TX__SSP3_D2 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_1)
276#define MX28_PAD_AUART2_CTS__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_1)
277#define MX28_PAD_AUART2_RTS__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_1)
278#define MX28_PAD_AUART3_RX__CAN0_TX MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_1)
279#define MX28_PAD_AUART3_TX__CAN0_RX MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_1)
280#define MX28_PAD_AUART3_CTS__CAN1_TX MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_1)
281#define MX28_PAD_AUART3_RTS__CAN1_RX MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_1)
282#define MX28_PAD_PWM0__I2C1_SCL MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_1)
283#define MX28_PAD_PWM1__I2C1_SDA MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_1)
284#define MX28_PAD_PWM2__USB0_ID MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_1)
285#define MX28_PAD_SAIF0_MCLK__PWM_3 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_1)
286#define MX28_PAD_SAIF0_LRCLK__PWM_4 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_1)
287#define MX28_PAD_SAIF0_BITCLK__PWM_5 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_1)
288#define MX28_PAD_SAIF0_SDATA0__PWM_6 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_1)
289#define MX28_PAD_I2C0_SCL__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_1)
290#define MX28_PAD_I2C0_SDA__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_1)
291#define MX28_PAD_SAIF1_SDATA0__PWM_7 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_1)
292#define MX28_PAD_LCD_RESET__LCD_VSYNC MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_1)
293
294#define MX28_PAD_ENET0_MDC__GPMI_CE4N MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_1)
295#define MX28_PAD_ENET0_MDIO__GPMI_CE5N MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_1)
296#define MX28_PAD_ENET0_RX_EN__GPMI_CE6N MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_1)
297#define MX28_PAD_ENET0_RXD0__GPMI_CE7N MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_1)
298#define MX28_PAD_ENET0_RXD1__GPMI_READY4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_1)
299#define MX28_PAD_ENET0_TX_CLK__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_1)
300#define MX28_PAD_ENET0_TX_EN__GPMI_READY5 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_1)
301#define MX28_PAD_ENET0_TXD0__GPMI_READY6 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_1)
302#define MX28_PAD_ENET0_TXD1__GPMI_READY7 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_1)
303#define MX28_PAD_ENET0_RXD2__ENET1_RXD0 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_1)
304#define MX28_PAD_ENET0_RXD3__ENET1_RXD1 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_1)
305#define MX28_PAD_ENET0_TXD2__ENET1_TXD0 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_1)
306#define MX28_PAD_ENET0_TXD3__ENET1_TXD1 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_1)
307#define MX28_PAD_ENET0_RX_CLK__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_1)
308#define MX28_PAD_ENET0_COL__ENET1_TX_EN MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_1)
309#define MX28_PAD_ENET0_CRS__ENET1_RX_EN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_1)
310
311/* MUXSEL_2 */
312#define MX28_PAD_GPMI_CE2N__ENET0_RX_ER MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_2)
313#define MX28_PAD_GPMI_CE3N__SAIF1_MCLK MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_2)
314#define MX28_PAD_GPMI_RDY0__USB0_ID MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_2)
315#define MX28_PAD_GPMI_RDY2__ENET0_TX_ER MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_2)
316#define MX28_PAD_GPMI_RDY3__HSADC_TRIGGER MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_2)
317#define MX28_PAD_GPMI_ALE__SSP3_D4 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_2)
318#define MX28_PAD_GPMI_CLE__SSP3_D5 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_2)
319
320#define MX28_PAD_LCD_D00__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_2)
321#define MX28_PAD_LCD_D01__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_2)
322#define MX28_PAD_LCD_D02__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_2)
323#define MX28_PAD_LCD_D03__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_2)
324#define MX28_PAD_LCD_D04__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_2)
325#define MX28_PAD_LCD_D05__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_2)
326#define MX28_PAD_LCD_D06__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_2)
327#define MX28_PAD_LCD_D07__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_2)
328#define MX28_PAD_LCD_D08__ETM_DA8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_2)
329#define MX28_PAD_LCD_D09__ETM_DA9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_2)
330#define MX28_PAD_LCD_D10__ETM_DA10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_2)
331#define MX28_PAD_LCD_D11__ETM_DA11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_2)
332#define MX28_PAD_LCD_D12__ETM_DA12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_2)
333#define MX28_PAD_LCD_D13__ETM_DA13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_2)
334#define MX28_PAD_LCD_D14__ETM_DA14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_2)
335#define MX28_PAD_LCD_D15__ETM_DA15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_2)
336#define MX28_PAD_LCD_D16__ETM_DA7 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_2)
337#define MX28_PAD_LCD_D17__ETM_DA6 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_2)
338#define MX28_PAD_LCD_D18__ETM_DA5 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_2)
339#define MX28_PAD_LCD_D19__ETM_DA4 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_2)
340#define MX28_PAD_LCD_D20__ETM_DA3 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_2)
341#define MX28_PAD_LCD_D21__ETM_DA2 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_2)
342#define MX28_PAD_LCD_D22__ETM_DA1 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_2)
343#define MX28_PAD_LCD_D23__ETM_DA0 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_2)
344#define MX28_PAD_LCD_RD_E__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_2)
345#define MX28_PAD_LCD_WR_RWN__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_2)
346#define MX28_PAD_LCD_HSYNC__ETM_TCTL MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_2)
347#define MX28_PAD_LCD_DOTCLK__ETM_TCLK MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_2)
348
349#define MX28_PAD_SSP1_SCK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_2)
350#define MX28_PAD_SSP1_CMD__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_2)
351#define MX28_PAD_SSP1_DATA0__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_2)
352#define MX28_PAD_SSP1_DATA3__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_2)
353#define MX28_PAD_SSP2_SCK__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_2)
354#define MX28_PAD_SSP2_MOSI__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_2)
355#define MX28_PAD_SSP2_MISO__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_2)
356#define MX28_PAD_SSP2_SS0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_2)
357#define MX28_PAD_SSP2_SS1__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_2)
358#define MX28_PAD_SSP2_SS2__USB0_OVERCURRENT MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_2)
359#define MX28_PAD_SSP3_SCK__ENET1_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_2)
360#define MX28_PAD_SSP3_MOSI__ENET1_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_2)
361#define MX28_PAD_SSP3_MISO__ENET1_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_2)
362#define MX28_PAD_SSP3_SS0__ENET1_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_2)
363
364#define MX28_PAD_AUART0_RX__DUART_CTS MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_2)
365#define MX28_PAD_AUART0_TX__DUART_RTS MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_2)
366#define MX28_PAD_AUART0_CTS__DUART_RX MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_2)
367#define MX28_PAD_AUART0_RTS__DUART_TX MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_2)
368#define MX28_PAD_AUART1_RX__PWM_0 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_2)
369#define MX28_PAD_AUART1_TX__PWM_1 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_2)
370#define MX28_PAD_AUART1_CTS__TIMROT_ROTARYA MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_2)
371#define MX28_PAD_AUART1_RTS__TIMROT_ROTARYB MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_2)
372#define MX28_PAD_AUART2_RX__SSP3_D4 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_2)
373#define MX28_PAD_AUART2_TX__SSP3_D5 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_2)
374#define MX28_PAD_AUART2_CTS__SAIF1_BITCLK MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_2)
375#define MX28_PAD_AUART2_RTS__SAIF1_LRCLK MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_2)
376#define MX28_PAD_AUART3_RX__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_2)
377#define MX28_PAD_AUART3_TX__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_2)
378#define MX28_PAD_AUART3_CTS__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_2)
379#define MX28_PAD_AUART3_RTS__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_2)
380#define MX28_PAD_PWM0__DUART_RX MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_2)
381#define MX28_PAD_PWM1__DUART_TX MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_2)
382#define MX28_PAD_PWM2__USB1_OVERCURRENT MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_2)
383#define MX28_PAD_SAIF0_MCLK__AUART4_CTS MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_2)
384#define MX28_PAD_SAIF0_LRCLK__AUART4_RTS MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_2)
385#define MX28_PAD_SAIF0_BITCLK__AUART4_RX MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_2)
386#define MX28_PAD_SAIF0_SDATA0__AUART4_TX MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_2)
387#define MX28_PAD_I2C0_SCL__DUART_RX MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_2)
388#define MX28_PAD_I2C0_SDA__DUART_TX MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_2)
389#define MX28_PAD_SAIF1_SDATA0__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_2)
390#define MX28_PAD_SPDIF__ENET1_RX_ER MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_2)
391
392#define MX28_PAD_ENET0_MDC__SAIF0_SDATA1 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_2)
393#define MX28_PAD_ENET0_MDIO__SAIF0_SDATA2 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_2)
394#define MX28_PAD_ENET0_RX_EN__SAIF1_SDATA1 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_2)
395#define MX28_PAD_ENET0_RXD0__SAIF1_SDATA2 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_2)
396#define MX28_PAD_ENET0_TX_CLK__ENET0_1588_EVENT2_OUT MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_2)
397#define MX28_PAD_ENET0_RXD2__ENET0_1588_EVENT0_OUT MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_2)
398#define MX28_PAD_ENET0_RXD3__ENET0_1588_EVENT0_IN MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_2)
399#define MX28_PAD_ENET0_TXD2__ENET0_1588_EVENT1_OUT MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_2)
400#define MX28_PAD_ENET0_TXD3__ENET0_1588_EVENT1_IN MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_2)
401#define MX28_PAD_ENET0_RX_CLK__ENET0_1588_EVENT2_IN MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_2)
402#define MX28_PAD_ENET0_COL__ENET0_1588_EVENT3_OUT MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_2)
403#define MX28_PAD_ENET0_CRS__ENET0_1588_EVENT3_IN MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_2)
404
405/* MUXSEL_GPIO */
406#define MX28_PAD_GPMI_D00__GPIO_0_0 MXS_IOMUX_PAD_NAKED(0, 0, PAD_MUXSEL_GPIO)
407#define MX28_PAD_GPMI_D01__GPIO_0_1 MXS_IOMUX_PAD_NAKED(0, 1, PAD_MUXSEL_GPIO)
408#define MX28_PAD_GPMI_D02__GPIO_0_2 MXS_IOMUX_PAD_NAKED(0, 2, PAD_MUXSEL_GPIO)
409#define MX28_PAD_GPMI_D03__GPIO_0_3 MXS_IOMUX_PAD_NAKED(0, 3, PAD_MUXSEL_GPIO)
410#define MX28_PAD_GPMI_D04__GPIO_0_4 MXS_IOMUX_PAD_NAKED(0, 4, PAD_MUXSEL_GPIO)
411#define MX28_PAD_GPMI_D05__GPIO_0_5 MXS_IOMUX_PAD_NAKED(0, 5, PAD_MUXSEL_GPIO)
412#define MX28_PAD_GPMI_D06__GPIO_0_6 MXS_IOMUX_PAD_NAKED(0, 6, PAD_MUXSEL_GPIO)
413#define MX28_PAD_GPMI_D07__GPIO_0_7 MXS_IOMUX_PAD_NAKED(0, 7, PAD_MUXSEL_GPIO)
414#define MX28_PAD_GPMI_CE0N__GPIO_0_16 MXS_IOMUX_PAD_NAKED(0, 16, PAD_MUXSEL_GPIO)
415#define MX28_PAD_GPMI_CE1N__GPIO_0_17 MXS_IOMUX_PAD_NAKED(0, 17, PAD_MUXSEL_GPIO)
416#define MX28_PAD_GPMI_CE2N__GPIO_0_18 MXS_IOMUX_PAD_NAKED(0, 18, PAD_MUXSEL_GPIO)
417#define MX28_PAD_GPMI_CE3N__GPIO_0_19 MXS_IOMUX_PAD_NAKED(0, 19, PAD_MUXSEL_GPIO)
418#define MX28_PAD_GPMI_RDY0__GPIO_0_20 MXS_IOMUX_PAD_NAKED(0, 20, PAD_MUXSEL_GPIO)
419#define MX28_PAD_GPMI_RDY1__GPIO_0_21 MXS_IOMUX_PAD_NAKED(0, 21, PAD_MUXSEL_GPIO)
420#define MX28_PAD_GPMI_RDY2__GPIO_0_22 MXS_IOMUX_PAD_NAKED(0, 22, PAD_MUXSEL_GPIO)
421#define MX28_PAD_GPMI_RDY3__GPIO_0_23 MXS_IOMUX_PAD_NAKED(0, 23, PAD_MUXSEL_GPIO)
422#define MX28_PAD_GPMI_RDN__GPIO_0_24 MXS_IOMUX_PAD_NAKED(0, 24, PAD_MUXSEL_GPIO)
423#define MX28_PAD_GPMI_WRN__GPIO_0_25 MXS_IOMUX_PAD_NAKED(0, 25, PAD_MUXSEL_GPIO)
424#define MX28_PAD_GPMI_ALE__GPIO_0_26 MXS_IOMUX_PAD_NAKED(0, 26, PAD_MUXSEL_GPIO)
425#define MX28_PAD_GPMI_CLE__GPIO_0_27 MXS_IOMUX_PAD_NAKED(0, 27, PAD_MUXSEL_GPIO)
426#define MX28_PAD_GPMI_RESETN__GPIO_0_28 MXS_IOMUX_PAD_NAKED(0, 28, PAD_MUXSEL_GPIO)
427
428#define MX28_PAD_LCD_D00__GPIO_1_0 MXS_IOMUX_PAD_NAKED(1, 0, PAD_MUXSEL_GPIO)
429#define MX28_PAD_LCD_D01__GPIO_1_1 MXS_IOMUX_PAD_NAKED(1, 1, PAD_MUXSEL_GPIO)
430#define MX28_PAD_LCD_D02__GPIO_1_2 MXS_IOMUX_PAD_NAKED(1, 2, PAD_MUXSEL_GPIO)
431#define MX28_PAD_LCD_D03__GPIO_1_3 MXS_IOMUX_PAD_NAKED(1, 3, PAD_MUXSEL_GPIO)
432#define MX28_PAD_LCD_D04__GPIO_1_4 MXS_IOMUX_PAD_NAKED(1, 4, PAD_MUXSEL_GPIO)
433#define MX28_PAD_LCD_D05__GPIO_1_5 MXS_IOMUX_PAD_NAKED(1, 5, PAD_MUXSEL_GPIO)
434#define MX28_PAD_LCD_D06__GPIO_1_6 MXS_IOMUX_PAD_NAKED(1, 6, PAD_MUXSEL_GPIO)
435#define MX28_PAD_LCD_D07__GPIO_1_7 MXS_IOMUX_PAD_NAKED(1, 7, PAD_MUXSEL_GPIO)
436#define MX28_PAD_LCD_D08__GPIO_1_8 MXS_IOMUX_PAD_NAKED(1, 8, PAD_MUXSEL_GPIO)
437#define MX28_PAD_LCD_D09__GPIO_1_9 MXS_IOMUX_PAD_NAKED(1, 9, PAD_MUXSEL_GPIO)
438#define MX28_PAD_LCD_D10__GPIO_1_10 MXS_IOMUX_PAD_NAKED(1, 10, PAD_MUXSEL_GPIO)
439#define MX28_PAD_LCD_D11__GPIO_1_11 MXS_IOMUX_PAD_NAKED(1, 11, PAD_MUXSEL_GPIO)
440#define MX28_PAD_LCD_D12__GPIO_1_12 MXS_IOMUX_PAD_NAKED(1, 12, PAD_MUXSEL_GPIO)
441#define MX28_PAD_LCD_D13__GPIO_1_13 MXS_IOMUX_PAD_NAKED(1, 13, PAD_MUXSEL_GPIO)
442#define MX28_PAD_LCD_D14__GPIO_1_14 MXS_IOMUX_PAD_NAKED(1, 14, PAD_MUXSEL_GPIO)
443#define MX28_PAD_LCD_D15__GPIO_1_15 MXS_IOMUX_PAD_NAKED(1, 15, PAD_MUXSEL_GPIO)
444#define MX28_PAD_LCD_D16__GPIO_1_16 MXS_IOMUX_PAD_NAKED(1, 16, PAD_MUXSEL_GPIO)
445#define MX28_PAD_LCD_D17__GPIO_1_17 MXS_IOMUX_PAD_NAKED(1, 17, PAD_MUXSEL_GPIO)
446#define MX28_PAD_LCD_D18__GPIO_1_18 MXS_IOMUX_PAD_NAKED(1, 18, PAD_MUXSEL_GPIO)
447#define MX28_PAD_LCD_D19__GPIO_1_19 MXS_IOMUX_PAD_NAKED(1, 19, PAD_MUXSEL_GPIO)
448#define MX28_PAD_LCD_D20__GPIO_1_20 MXS_IOMUX_PAD_NAKED(1, 20, PAD_MUXSEL_GPIO)
449#define MX28_PAD_LCD_D21__GPIO_1_21 MXS_IOMUX_PAD_NAKED(1, 21, PAD_MUXSEL_GPIO)
450#define MX28_PAD_LCD_D22__GPIO_1_22 MXS_IOMUX_PAD_NAKED(1, 22, PAD_MUXSEL_GPIO)
451#define MX28_PAD_LCD_D23__GPIO_1_23 MXS_IOMUX_PAD_NAKED(1, 23, PAD_MUXSEL_GPIO)
452#define MX28_PAD_LCD_RD_E__GPIO_1_24 MXS_IOMUX_PAD_NAKED(1, 24, PAD_MUXSEL_GPIO)
453#define MX28_PAD_LCD_WR_RWN__GPIO_1_25 MXS_IOMUX_PAD_NAKED(1, 25, PAD_MUXSEL_GPIO)
454#define MX28_PAD_LCD_RS__GPIO_1_26 MXS_IOMUX_PAD_NAKED(1, 26, PAD_MUXSEL_GPIO)
455#define MX28_PAD_LCD_CS__GPIO_1_27 MXS_IOMUX_PAD_NAKED(1, 27, PAD_MUXSEL_GPIO)
456#define MX28_PAD_LCD_VSYNC__GPIO_1_28 MXS_IOMUX_PAD_NAKED(1, 28, PAD_MUXSEL_GPIO)
457#define MX28_PAD_LCD_HSYNC__GPIO_1_29 MXS_IOMUX_PAD_NAKED(1, 29, PAD_MUXSEL_GPIO)
458#define MX28_PAD_LCD_DOTCLK__GPIO_1_30 MXS_IOMUX_PAD_NAKED(1, 30, PAD_MUXSEL_GPIO)
459#define MX28_PAD_LCD_ENABLE__GPIO_1_31 MXS_IOMUX_PAD_NAKED(1, 31, PAD_MUXSEL_GPIO)
460
461#define MX28_PAD_SSP0_DATA0__GPIO_2_0 MXS_IOMUX_PAD_NAKED(2, 0, PAD_MUXSEL_GPIO)
462#define MX28_PAD_SSP0_DATA1__GPIO_2_1 MXS_IOMUX_PAD_NAKED(2, 1, PAD_MUXSEL_GPIO)
463#define MX28_PAD_SSP0_DATA2__GPIO_2_2 MXS_IOMUX_PAD_NAKED(2, 2, PAD_MUXSEL_GPIO)
464#define MX28_PAD_SSP0_DATA3__GPIO_2_3 MXS_IOMUX_PAD_NAKED(2, 3, PAD_MUXSEL_GPIO)
465#define MX28_PAD_SSP0_DATA4__GPIO_2_4 MXS_IOMUX_PAD_NAKED(2, 4, PAD_MUXSEL_GPIO)
466#define MX28_PAD_SSP0_DATA5__GPIO_2_5 MXS_IOMUX_PAD_NAKED(2, 5, PAD_MUXSEL_GPIO)
467#define MX28_PAD_SSP0_DATA6__GPIO_2_6 MXS_IOMUX_PAD_NAKED(2, 6, PAD_MUXSEL_GPIO)
468#define MX28_PAD_SSP0_DATA7__GPIO_2_7 MXS_IOMUX_PAD_NAKED(2, 7, PAD_MUXSEL_GPIO)
469#define MX28_PAD_SSP0_CMD__GPIO_2_8 MXS_IOMUX_PAD_NAKED(2, 8, PAD_MUXSEL_GPIO)
470#define MX28_PAD_SSP0_DETECT__GPIO_2_9 MXS_IOMUX_PAD_NAKED(2, 9, PAD_MUXSEL_GPIO)
471#define MX28_PAD_SSP0_SCK__GPIO_2_10 MXS_IOMUX_PAD_NAKED(2, 10, PAD_MUXSEL_GPIO)
472#define MX28_PAD_SSP1_SCK__GPIO_2_12 MXS_IOMUX_PAD_NAKED(2, 12, PAD_MUXSEL_GPIO)
473#define MX28_PAD_SSP1_CMD__GPIO_2_13 MXS_IOMUX_PAD_NAKED(2, 13, PAD_MUXSEL_GPIO)
474#define MX28_PAD_SSP1_DATA0__GPIO_2_14 MXS_IOMUX_PAD_NAKED(2, 14, PAD_MUXSEL_GPIO)
475#define MX28_PAD_SSP1_DATA3__GPIO_2_15 MXS_IOMUX_PAD_NAKED(2, 15, PAD_MUXSEL_GPIO)
476#define MX28_PAD_SSP2_SCK__GPIO_2_16 MXS_IOMUX_PAD_NAKED(2, 16, PAD_MUXSEL_GPIO)
477#define MX28_PAD_SSP2_MOSI__GPIO_2_17 MXS_IOMUX_PAD_NAKED(2, 17, PAD_MUXSEL_GPIO)
478#define MX28_PAD_SSP2_MISO__GPIO_2_18 MXS_IOMUX_PAD_NAKED(2, 18, PAD_MUXSEL_GPIO)
479#define MX28_PAD_SSP2_SS0__GPIO_2_19 MXS_IOMUX_PAD_NAKED(2, 19, PAD_MUXSEL_GPIO)
480#define MX28_PAD_SSP2_SS1__GPIO_2_20 MXS_IOMUX_PAD_NAKED(2, 20, PAD_MUXSEL_GPIO)
481#define MX28_PAD_SSP2_SS2__GPIO_2_21 MXS_IOMUX_PAD_NAKED(2, 21, PAD_MUXSEL_GPIO)
482#define MX28_PAD_SSP3_SCK__GPIO_2_24 MXS_IOMUX_PAD_NAKED(2, 24, PAD_MUXSEL_GPIO)
483#define MX28_PAD_SSP3_MOSI__GPIO_2_25 MXS_IOMUX_PAD_NAKED(2, 25, PAD_MUXSEL_GPIO)
484#define MX28_PAD_SSP3_MISO__GPIO_2_26 MXS_IOMUX_PAD_NAKED(2, 26, PAD_MUXSEL_GPIO)
485#define MX28_PAD_SSP3_SS0__GPIO_2_27 MXS_IOMUX_PAD_NAKED(2, 27, PAD_MUXSEL_GPIO)
486
487#define MX28_PAD_AUART0_RX__GPIO_3_0 MXS_IOMUX_PAD_NAKED(3, 0, PAD_MUXSEL_GPIO)
488#define MX28_PAD_AUART0_TX__GPIO_3_1 MXS_IOMUX_PAD_NAKED(3, 1, PAD_MUXSEL_GPIO)
489#define MX28_PAD_AUART0_CTS__GPIO_3_2 MXS_IOMUX_PAD_NAKED(3, 2, PAD_MUXSEL_GPIO)
490#define MX28_PAD_AUART0_RTS__GPIO_3_3 MXS_IOMUX_PAD_NAKED(3, 3, PAD_MUXSEL_GPIO)
491#define MX28_PAD_AUART1_RX__GPIO_3_4 MXS_IOMUX_PAD_NAKED(3, 4, PAD_MUXSEL_GPIO)
492#define MX28_PAD_AUART1_TX__GPIO_3_5 MXS_IOMUX_PAD_NAKED(3, 5, PAD_MUXSEL_GPIO)
493#define MX28_PAD_AUART1_CTS__GPIO_3_6 MXS_IOMUX_PAD_NAKED(3, 6, PAD_MUXSEL_GPIO)
494#define MX28_PAD_AUART1_RTS__GPIO_3_7 MXS_IOMUX_PAD_NAKED(3, 7, PAD_MUXSEL_GPIO)
495#define MX28_PAD_AUART2_RX__GPIO_3_8 MXS_IOMUX_PAD_NAKED(3, 8, PAD_MUXSEL_GPIO)
496#define MX28_PAD_AUART2_TX__GPIO_3_9 MXS_IOMUX_PAD_NAKED(3, 9, PAD_MUXSEL_GPIO)
497#define MX28_PAD_AUART2_CTS__GPIO_3_10 MXS_IOMUX_PAD_NAKED(3, 10, PAD_MUXSEL_GPIO)
498#define MX28_PAD_AUART2_RTS__GPIO_3_11 MXS_IOMUX_PAD_NAKED(3, 11, PAD_MUXSEL_GPIO)
499#define MX28_PAD_AUART3_RX__GPIO_3_12 MXS_IOMUX_PAD_NAKED(3, 12, PAD_MUXSEL_GPIO)
500#define MX28_PAD_AUART3_TX__GPIO_3_13 MXS_IOMUX_PAD_NAKED(3, 13, PAD_MUXSEL_GPIO)
501#define MX28_PAD_AUART3_CTS__GPIO_3_14 MXS_IOMUX_PAD_NAKED(3, 14, PAD_MUXSEL_GPIO)
502#define MX28_PAD_AUART3_RTS__GPIO_3_15 MXS_IOMUX_PAD_NAKED(3, 15, PAD_MUXSEL_GPIO)
503#define MX28_PAD_PWM0__GPIO_3_16 MXS_IOMUX_PAD_NAKED(3, 16, PAD_MUXSEL_GPIO)
504#define MX28_PAD_PWM1__GPIO_3_17 MXS_IOMUX_PAD_NAKED(3, 17, PAD_MUXSEL_GPIO)
505#define MX28_PAD_PWM2__GPIO_3_18 MXS_IOMUX_PAD_NAKED(3, 18, PAD_MUXSEL_GPIO)
506#define MX28_PAD_SAIF0_MCLK__GPIO_3_20 MXS_IOMUX_PAD_NAKED(3, 20, PAD_MUXSEL_GPIO)
507#define MX28_PAD_SAIF0_LRCLK__GPIO_3_21 MXS_IOMUX_PAD_NAKED(3, 21, PAD_MUXSEL_GPIO)
508#define MX28_PAD_SAIF0_BITCLK__GPIO_3_22 MXS_IOMUX_PAD_NAKED(3, 22, PAD_MUXSEL_GPIO)
509#define MX28_PAD_SAIF0_SDATA0__GPIO_3_23 MXS_IOMUX_PAD_NAKED(3, 23, PAD_MUXSEL_GPIO)
510#define MX28_PAD_I2C0_SCL__GPIO_3_24 MXS_IOMUX_PAD_NAKED(3, 24, PAD_MUXSEL_GPIO)
511#define MX28_PAD_I2C0_SDA__GPIO_3_25 MXS_IOMUX_PAD_NAKED(3, 25, PAD_MUXSEL_GPIO)
512#define MX28_PAD_SAIF1_SDATA0__GPIO_3_26 MXS_IOMUX_PAD_NAKED(3, 26, PAD_MUXSEL_GPIO)
513#define MX28_PAD_SPDIF__GPIO_3_27 MXS_IOMUX_PAD_NAKED(3, 27, PAD_MUXSEL_GPIO)
514#define MX28_PAD_PWM3__GPIO_3_28 MXS_IOMUX_PAD_NAKED(3, 28, PAD_MUXSEL_GPIO)
515#define MX28_PAD_PWM4__GPIO_3_29 MXS_IOMUX_PAD_NAKED(3, 29, PAD_MUXSEL_GPIO)
516#define MX28_PAD_LCD_RESET__GPIO_3_30 MXS_IOMUX_PAD_NAKED(3, 30, PAD_MUXSEL_GPIO)
517
518#define MX28_PAD_ENET0_MDC__GPIO_4_0 MXS_IOMUX_PAD_NAKED(4, 0, PAD_MUXSEL_GPIO)
519#define MX28_PAD_ENET0_MDIO__GPIO_4_1 MXS_IOMUX_PAD_NAKED(4, 1, PAD_MUXSEL_GPIO)
520#define MX28_PAD_ENET0_RX_EN__GPIO_4_2 MXS_IOMUX_PAD_NAKED(4, 2, PAD_MUXSEL_GPIO)
521#define MX28_PAD_ENET0_RXD0__GPIO_4_3 MXS_IOMUX_PAD_NAKED(4, 3, PAD_MUXSEL_GPIO)
522#define MX28_PAD_ENET0_RXD1__GPIO_4_4 MXS_IOMUX_PAD_NAKED(4, 4, PAD_MUXSEL_GPIO)
523#define MX28_PAD_ENET0_TX_CLK__GPIO_4_5 MXS_IOMUX_PAD_NAKED(4, 5, PAD_MUXSEL_GPIO)
524#define MX28_PAD_ENET0_TX_EN__GPIO_4_6 MXS_IOMUX_PAD_NAKED(4, 6, PAD_MUXSEL_GPIO)
525#define MX28_PAD_ENET0_TXD0__GPIO_4_7 MXS_IOMUX_PAD_NAKED(4, 7, PAD_MUXSEL_GPIO)
526#define MX28_PAD_ENET0_TXD1__GPIO_4_8 MXS_IOMUX_PAD_NAKED(4, 8, PAD_MUXSEL_GPIO)
527#define MX28_PAD_ENET0_RXD2__GPIO_4_9 MXS_IOMUX_PAD_NAKED(4, 9, PAD_MUXSEL_GPIO)
528#define MX28_PAD_ENET0_RXD3__GPIO_4_10 MXS_IOMUX_PAD_NAKED(4, 10, PAD_MUXSEL_GPIO)
529#define MX28_PAD_ENET0_TXD2__GPIO_4_11 MXS_IOMUX_PAD_NAKED(4, 11, PAD_MUXSEL_GPIO)
530#define MX28_PAD_ENET0_TXD3__GPIO_4_12 MXS_IOMUX_PAD_NAKED(4, 12, PAD_MUXSEL_GPIO)
531#define MX28_PAD_ENET0_RX_CLK__GPIO_4_13 MXS_IOMUX_PAD_NAKED(4, 13, PAD_MUXSEL_GPIO)
532#define MX28_PAD_ENET0_COL__GPIO_4_14 MXS_IOMUX_PAD_NAKED(4, 14, PAD_MUXSEL_GPIO)
533#define MX28_PAD_ENET0_CRS__GPIO_4_15 MXS_IOMUX_PAD_NAKED(4, 15, PAD_MUXSEL_GPIO)
534#define MX28_PAD_ENET_CLK__GPIO_4_16 MXS_IOMUX_PAD_NAKED(4, 16, PAD_MUXSEL_GPIO)
535#define MX28_PAD_JTAG_RTCK__GPIO_4_20 MXS_IOMUX_PAD_NAKED(4, 20, PAD_MUXSEL_GPIO)
536
537#endif /* __MACH_IOMUX_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/iomux.h b/arch/arm/mach-mxs/include/mach/iomux.h
new file mode 100644
index 000000000000..fe558e3c5a9a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/iomux.h
@@ -0,0 +1,165 @@
1/*
2 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
3 * <armlinux@phytec.de>
4 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#ifndef __MACH_MXS_IOMUX_H__
22#define __MACH_MXS_IOMUX_H__
23
24/*
25 * IOMUX/PAD Bit field definitions
26 *
27 * PAD_BANK: 0..2 (3)
28 * PAD_PIN: 3..7 (5)
29 * PAD_MUXSEL: 8..9 (2)
30 * PAD_MA: 10..11 (2)
31 * PAD_MA_VALID: 12 (1)
32 * PAD_VOL: 13 (1)
33 * PAD_VOL_VALID: 14 (1)
34 * PAD_PULL: 15 (1)
35 * PAD_PULL_VALID: 16 (1)
36 * RESERVED: 17..31 (15)
37 */
38typedef u32 iomux_cfg_t;
39
40#define MXS_PAD_BANK_SHIFT 0
41#define MXS_PAD_BANK_MASK ((iomux_cfg_t)0x7 << MXS_PAD_BANK_SHIFT)
42#define MXS_PAD_PIN_SHIFT 3
43#define MXS_PAD_PIN_MASK ((iomux_cfg_t)0x1f << MXS_PAD_PIN_SHIFT)
44#define MXS_PAD_MUXSEL_SHIFT 8
45#define MXS_PAD_MUXSEL_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MUXSEL_SHIFT)
46#define MXS_PAD_MA_SHIFT 10
47#define MXS_PAD_MA_MASK ((iomux_cfg_t)0x3 << MXS_PAD_MA_SHIFT)
48#define MXS_PAD_MA_VALID_SHIFT 12
49#define MXS_PAD_MA_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_MA_VALID_SHIFT)
50#define MXS_PAD_VOL_SHIFT 13
51#define MXS_PAD_VOL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_SHIFT)
52#define MXS_PAD_VOL_VALID_SHIFT 14
53#define MXS_PAD_VOL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_VOL_VALID_SHIFT)
54#define MXS_PAD_PULL_SHIFT 15
55#define MXS_PAD_PULL_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_SHIFT)
56#define MXS_PAD_PULL_VALID_SHIFT 16
57#define MXS_PAD_PULL_VALID_MASK ((iomux_cfg_t)0x1 << MXS_PAD_PULL_VALID_SHIFT)
58
59#define PAD_MUXSEL_0 0
60#define PAD_MUXSEL_1 1
61#define PAD_MUXSEL_2 2
62#define PAD_MUXSEL_GPIO 3
63
64#define PAD_4MA 0
65#define PAD_8MA 1
66#define PAD_12MA 2
67#define PAD_16MA 3
68
69#define PAD_1V8 0
70#define PAD_3V3 1
71
72#define PAD_NOPULL 0
73#define PAD_PULLUP 1
74
75#define MXS_PAD_4MA ((PAD_4MA << MXS_PAD_MA_SHIFT) | \
76 MXS_PAD_MA_VALID_MASK)
77#define MXS_PAD_8MA ((PAD_8MA << MXS_PAD_MA_SHIFT) | \
78 MXS_PAD_MA_VALID_MASK)
79#define MXS_PAD_12MA ((PAD_12MA << MXS_PAD_MA_SHIFT) | \
80 MXS_PAD_MA_VALID_MASK)
81#define MXS_PAD_16MA ((PAD_16MA << MXS_PAD_MA_SHIFT) | \
82 MXS_PAD_MA_VALID_MASK)
83
84#define MXS_PAD_1V8 ((PAD_1V8 << MXS_PAD_VOL_SHIFT) | \
85 MXS_PAD_VOL_VALID_MASK)
86#define MXS_PAD_3V3 ((PAD_3V3 << MXS_PAD_VOL_SHIFT) | \
87 MXS_PAD_VOL_VALID_MASK)
88
89#define MXS_PAD_NOPULL ((PAD_NOPULL << MXS_PAD_PULL_SHIFT) | \
90 MXS_PAD_PULL_VALID_MASK)
91#define MXS_PAD_PULLUP ((PAD_PULLUP << MXS_PAD_PULL_SHIFT) | \
92 MXS_PAD_PULL_VALID_MASK)
93
94#define MXS_IOMUX_PAD(_bank, _pin, _muxsel, _ma, _vol, _pull) \
95 (((iomux_cfg_t)(_bank) << MXS_PAD_BANK_SHIFT) | \
96 ((iomux_cfg_t)(_pin) << MXS_PAD_PIN_SHIFT) | \
97 ((iomux_cfg_t)(_muxsel) << MXS_PAD_MUXSEL_SHIFT) | \
98 ((iomux_cfg_t)(_ma) << MXS_PAD_MA_SHIFT) | \
99 ((iomux_cfg_t)(_vol) << MXS_PAD_VOL_SHIFT) | \
100 ((iomux_cfg_t)(_pull) << MXS_PAD_PULL_SHIFT))
101
102/*
103 * A pad becomes naked, when none of mA, vol or pull
104 * validity bits is set.
105 */
106#define MXS_IOMUX_PAD_NAKED(_bank, _pin, _muxsel) \
107 MXS_IOMUX_PAD(_bank, _pin, _muxsel, 0, 0, 0)
108
109static inline unsigned int PAD_BANK(iomux_cfg_t pad)
110{
111 return (pad & MXS_PAD_BANK_MASK) >> MXS_PAD_BANK_SHIFT;
112}
113
114static inline unsigned int PAD_PIN(iomux_cfg_t pad)
115{
116 return (pad & MXS_PAD_PIN_MASK) >> MXS_PAD_PIN_SHIFT;
117}
118
119static inline unsigned int PAD_MUXSEL(iomux_cfg_t pad)
120{
121 return (pad & MXS_PAD_MUXSEL_MASK) >> MXS_PAD_MUXSEL_SHIFT;
122}
123
124static inline unsigned int PAD_MA(iomux_cfg_t pad)
125{
126 return (pad & MXS_PAD_MA_MASK) >> MXS_PAD_MA_SHIFT;
127}
128
129static inline unsigned int PAD_MA_VALID(iomux_cfg_t pad)
130{
131 return (pad & MXS_PAD_MA_VALID_MASK) >> MXS_PAD_MA_VALID_SHIFT;
132}
133
134static inline unsigned int PAD_VOL(iomux_cfg_t pad)
135{
136 return (pad & MXS_PAD_VOL_MASK) >> MXS_PAD_VOL_SHIFT;
137}
138
139static inline unsigned int PAD_VOL_VALID(iomux_cfg_t pad)
140{
141 return (pad & MXS_PAD_VOL_VALID_MASK) >> MXS_PAD_VOL_VALID_SHIFT;
142}
143
144static inline unsigned int PAD_PULL(iomux_cfg_t pad)
145{
146 return (pad & MXS_PAD_PULL_MASK) >> MXS_PAD_PULL_SHIFT;
147}
148
149static inline unsigned int PAD_PULL_VALID(iomux_cfg_t pad)
150{
151 return (pad & MXS_PAD_PULL_VALID_MASK) >> MXS_PAD_PULL_VALID_SHIFT;
152}
153
154/*
155 * configures a single pad in the iomuxer
156 */
157int mxs_iomux_setup_pad(iomux_cfg_t pad);
158
159/*
160 * configures multiple pads
161 * convenient way to call the above function with tables
162 */
163int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count);
164
165#endif /* __MACH_MXS_IOMUX_H__*/
diff --git a/arch/arm/mach-mxs/include/mach/irqs.h b/arch/arm/mach-mxs/include/mach/irqs.h
new file mode 100644
index 000000000000..f771039b814a
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/irqs.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __MACH_MXS_IRQS_H__
12#define __MACH_MXS_IRQS_H__
13
14#define MXS_INTERNAL_IRQS 128
15
16#define MXS_GPIO_IRQ_START MXS_INTERNAL_IRQS
17
18/* the maximum for MXS-based */
19#define MXS_GPIO_IRQS (32 * 5)
20
21/*
22 * The next 16 interrupts are for board specific purposes. Since
23 * the kernel can only run on one machine at a time, we can re-use
24 * these. If you need more, increase MXS_BOARD_IRQS, but keep it
25 * within sensible limits.
26 */
27#define MXS_BOARD_IRQ_START (MXS_GPIO_IRQ_START + MXS_GPIO_IRQS)
28#define MXS_BOARD_IRQS 16
29
30#define NR_IRQS (MXS_BOARD_IRQ_START + MXS_BOARD_IRQS)
31
32#endif /* __MACH_MXS_IRQS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/memory.h b/arch/arm/mach-mxs/include/mach/memory.h
new file mode 100644
index 000000000000..b5420a5c2d4b
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/memory.h
@@ -0,0 +1,24 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_MXS_MEMORY_H__
20#define __MACH_MXS_MEMORY_H__
21
22#define PHYS_OFFSET UL(0x40000000)
23
24#endif /* __MACH_MXS_MEMORY_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
new file mode 100644
index 000000000000..9edd02ec8e30
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -0,0 +1,145 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_MX23_H__
20#define __MACH_MX23_H__
21
22#include <mach/mxs.h>
23
24/*
25 * OCRAM
26 */
27#define MX23_OCRAM_BASE_ADDR 0x00000000
28#define MX23_OCRAM_SIZE SZ_32K
29
30/*
31 * IO
32 */
33#define MX23_IO_BASE_ADDR 0x80000000
34#define MX23_IO_SIZE SZ_1M
35
36#define MX23_ICOLL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x000000)
37#define MX23_APBH_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x004000)
38#define MX23_BCH_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00a000)
39#define MX23_GPMI_BASE_ADDR (MX23_IO_BASE_ADDR + 0x00c000)
40#define MX23_SSP1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x010000)
41#define MX23_PINCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x018000)
42#define MX23_DIGCTL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x01c000)
43#define MX23_ETM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x020000)
44#define MX23_APBX_DMA_BASE_ADDR (MX23_IO_BASE_ADDR + 0x024000)
45#define MX23_DCP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x028000)
46#define MX23_PXP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02a000)
47#define MX23_OCOTP_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02c000)
48#define MX23_AXI_AHB0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x02e000)
49#define MX23_LCDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x030000)
50#define MX23_SSP2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x034000)
51#define MX23_TVENC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x038000)
52#define MX23_CLKCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x040000)
53#define MX23_SAIF0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x042000)
54#define MX23_POWER_BASE_ADDR (MX23_IO_BASE_ADDR + 0x044000)
55#define MX23_SAIF1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x046000)
56#define MX23_AUDIOOUT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x048000)
57#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000)
58#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000)
59#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000)
60#define MX23_I2C0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
61#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000)
62#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000)
63#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000)
64#define MX23_AUART1_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06c000)
65#define MX23_AUART2_BASE_ADDR (MX23_IO_BASE_ADDR + 0x06e000)
66#define MX23_DUART_BASE_ADDR (MX23_IO_BASE_ADDR + 0x070000)
67#define MX23_USBPHY_BASE_ADDR (MX23_IO_BASE_ADDR + 0x07c000)
68#define MX23_USBCTRL_BASE_ADDR (MX23_IO_BASE_ADDR + 0x080000)
69#define MX23_DRAM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x0e0000)
70
71#define MX23_IO_P2V(x) MXS_IO_P2V(x)
72#define MX23_IO_ADDRESS(x) IOMEM(MX23_IO_P2V(x))
73
74/*
75 * IRQ
76 */
77#define MX23_INT_DUART 0
78#define MX23_INT_COMMS_RX 1
79#define MX23_INT_COMMS_TX 1
80#define MX23_INT_SSP2_ERROR 2
81#define MX23_INT_VDD5V 3
82#define MX23_INT_HEADPHONE_SHORT 4
83#define MX23_INT_DAC_DMA 5
84#define MX23_INT_DAC_ERROR 6
85#define MX23_INT_ADC_DMA 7
86#define MX23_INT_ADC_ERROR 8
87#define MX23_INT_SPDIF_DMA 9
88#define MX23_INT_SAIF2_DMA 9
89#define MX23_INT_SPDIF_ERROR 10
90#define MX23_INT_SAIF1_IRQ 10
91#define MX23_INT_SAIF2_IRQ 10
92#define MX23_INT_USB_CTRL 11
93#define MX23_INT_USB_WAKEUP 12
94#define MX23_INT_GPMI_DMA 13
95#define MX23_INT_SSP1_DMA 14
96#define MX23_INT_SSP_ERROR 15
97#define MX23_INT_GPIO0 16
98#define MX23_INT_GPIO1 17
99#define MX23_INT_GPIO2 18
100#define MX23_INT_SAIF1_DMA 19
101#define MX23_INT_SSP2_DMA 20
102#define MX23_INT_ECC8_IRQ 21
103#define MX23_INT_RTC_ALARM 22
104#define MX23_INT_UARTAPP_TX_DMA 23
105#define MX23_INT_UARTAPP_INTERNAL 24
106#define MX23_INT_UARTAPP_RX_DMA 25
107#define MX23_INT_I2C_DMA 26
108#define MX23_INT_I2C_ERROR 27
109#define MX23_INT_TIMER0 28
110#define MX23_INT_TIMER1 29
111#define MX23_INT_TIMER2 30
112#define MX23_INT_TIMER3 31
113#define MX23_INT_BATT_BRNOUT 32
114#define MX23_INT_VDDD_BRNOUT 33
115#define MX23_INT_VDDIO_BRNOUT 34
116#define MX23_INT_VDD18_BRNOUT 35
117#define MX23_INT_TOUCH_DETECT 36
118#define MX23_INT_LRADC_CH0 37
119#define MX23_INT_LRADC_CH1 38
120#define MX23_INT_LRADC_CH2 39
121#define MX23_INT_LRADC_CH3 40
122#define MX23_INT_LRADC_CH4 41
123#define MX23_INT_LRADC_CH5 42
124#define MX23_INT_LRADC_CH6 43
125#define MX23_INT_LRADC_CH7 44
126#define MX23_INT_LCDIF_DMA 45
127#define MX23_INT_LCDIF_ERROR 46
128#define MX23_INT_DIGCTL_DEBUG_TRAP 47
129#define MX23_INT_RTC_1MSEC 48
130#define MX23_INT_DRI_DMA 49
131#define MX23_INT_DRI_ATTENTION 50
132#define MX23_INT_GPMI_ATTENTION 51
133#define MX23_INT_IR 52
134#define MX23_INT_DCP_VMI 53
135#define MX23_INT_DCP 54
136#define MX23_INT_BCH 56
137#define MX23_INT_PXP 57
138#define MX23_INT_UARTAPP2_TX_DMA 58
139#define MX23_INT_UARTAPP2_INTERNAL 59
140#define MX23_INT_UARTAPP2_RX_DMA 60
141#define MX23_INT_VDAC_DETECT 61
142#define MX23_INT_VDD5V_DROOP 64
143#define MX23_INT_DCDC4P2_BO 65
144
145#endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
new file mode 100644
index 000000000000..0716745267ad
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mx28.h
@@ -0,0 +1,188 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_MX28_H__
20#define __MACH_MX28_H__
21
22#include <mach/mxs.h>
23
24/*
25 * OCRAM
26 */
27#define MX28_OCRAM_BASE_ADDR 0x00000000
28#define MX28_OCRAM_SIZE SZ_128K
29
30/*
31 * IO
32 */
33#define MX28_IO_BASE_ADDR 0x80000000
34#define MX28_IO_SIZE SZ_1M
35
36#define MX28_ICOLL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x000000)
37#define MX28_HSADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x002000)
38#define MX28_APBH_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x004000)
39#define MX28_PERFMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x006000)
40#define MX28_BCH_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00a000)
41#define MX28_GPMI_BASE_ADDR (MX28_IO_BASE_ADDR + 0x00c000)
42#define MX28_SSP0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x010000)
43#define MX28_SSP1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x012000)
44#define MX28_SSP2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x014000)
45#define MX28_SSP3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x016000)
46#define MX28_PINCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x018000)
47#define MX28_DIGCTL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x01c000)
48#define MX28_ETM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x022000)
49#define MX28_APBX_DMA_BASE_ADDR (MX28_IO_BASE_ADDR + 0x024000)
50#define MX28_DCP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x028000)
51#define MX28_PXP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02a000)
52#define MX28_OCOTP_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02c000)
53#define MX28_AXI_AHB0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x02e000)
54#define MX28_LCDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x030000)
55#define MX28_CAN0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x032000)
56#define MX28_CAN1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x034000)
57#define MX28_SIMDBG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c000)
58#define MX28_SIMGPMISEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c200)
59#define MX28_SIMSSPSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c300)
60#define MX28_SIMMEMSEL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c400)
61#define MX28_GPIOMON_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c500)
62#define MX28_SIMENET_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c700)
63#define MX28_ARMJTAG_BASE_ADDR (MX28_IO_BASE_ADDR + 0x03c800)
64#define MX28_CLKCTRL_BASE_ADDR (MX28_IO_BASE_ADDR + 0x040000)
65#define MX28_SAIF0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x042000)
66#define MX28_POWER_BASE_ADDR (MX28_IO_BASE_ADDR + 0x044000)
67#define MX28_SAIF1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x046000)
68#define MX28_LRADC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x050000)
69#define MX28_SPDIF_BASE_ADDR (MX28_IO_BASE_ADDR + 0x054000)
70#define MX28_RTC_BASE_ADDR (MX28_IO_BASE_ADDR + 0x056000)
71#define MX28_I2C0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x058000)
72#define MX28_I2C1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x05a000)
73#define MX28_PWM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x064000)
74#define MX28_TIMROT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x068000)
75#define MX28_AUART0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06a000)
76#define MX28_AUART1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06c000)
77#define MX28_AUART2_BASE_ADDR (MX28_IO_BASE_ADDR + 0x06e000)
78#define MX28_AUART3_BASE_ADDR (MX28_IO_BASE_ADDR + 0x070000)
79#define MX28_AUART4_BASE_ADDR (MX28_IO_BASE_ADDR + 0x072000)
80#define MX28_DUART_BASE_ADDR (MX28_IO_BASE_ADDR + 0x074000)
81#define MX28_USBPHY0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07C000)
82#define MX28_USBPHY1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x07e000)
83#define MX28_USBCTRL0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x080000)
84#define MX28_USBCTRL1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x090000)
85#define MX28_DFLPT_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0c0000)
86#define MX28_DRAM_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0e0000)
87#define MX28_ENET_MAC0_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f0000)
88#define MX28_ENET_MAC1_BASE_ADDR (MX28_IO_BASE_ADDR + 0x0f4000)
89
90#define MX28_IO_P2V(x) MXS_IO_P2V(x)
91#define MX28_IO_ADDRESS(x) IOMEM(MX28_IO_P2V(x))
92
93/*
94 * IRQ
95 */
96#define MX28_INT_BATT_BRNOUT 0
97#define MX28_INT_VDDD_BRNOUT 1
98#define MX28_INT_VDDIO_BRNOUT 2
99#define MX28_INT_VDDA_BRNOUT 3
100#define MX28_INT_VDD5V_DROOP 4
101#define MX28_INT_DCDC4P2_BRNOUT 5
102#define MX28_INT_VDD5V 6
103#define MX28_INT_CAN0 8
104#define MX28_INT_CAN1 9
105#define MX28_INT_LRADC_TOUCH 10
106#define MX28_INT_HSADC 13
107#define MX28_INT_IRADC_THRESH0 14
108#define MX28_INT_IRADC_THRESH1 15
109#define MX28_INT_LRADC_CH0 16
110#define MX28_INT_LRADC_CH1 17
111#define MX28_INT_LRADC_CH2 18
112#define MX28_INT_LRADC_CH3 19
113#define MX28_INT_LRADC_CH4 20
114#define MX28_INT_LRADC_CH5 21
115#define MX28_INT_LRADC_CH6 22
116#define MX28_INT_LRADC_CH7 23
117#define MX28_INT_LRADC_BUTTON0 24
118#define MX28_INT_LRADC_BUTTON1 25
119#define MX28_INT_PERFMON 27
120#define MX28_INT_RTC_1MSEC 28
121#define MX28_INT_RTC_ALARM 29
122#define MX28_INT_COMMS 31
123#define MX28_INT_EMI_ERR 32
124#define MX28_INT_LCDIF 38
125#define MX28_INT_PXP 39
126#define MX28_INT_BCH 41
127#define MX28_INT_GPMI 42
128#define MX28_INT_SPDIF_ERROR 45
129#define MX28_INT_DUART 47
130#define MX28_INT_TIMER0 48
131#define MX28_INT_TIMER1 49
132#define MX28_INT_TIMER2 50
133#define MX28_INT_TIMER3 51
134#define MX28_INT_DCP_VMI 52
135#define MX28_INT_DCP 53
136#define MX28_INT_DCP_SECURE 54
137#define MX28_INT_SAIF1 58
138#define MX28_INT_SAIF0 59
139#define MX28_INT_SPDIF_DMA 66
140#define MX28_INT_I2C0_DMA 68
141#define MX28_INT_I2C1_DMA 69
142#define MX28_INT_AUART0_RX_DMA 70
143#define MX28_INT_AUART0_TX_DMA 71
144#define MX28_INT_AUART1_RX_DMA 72
145#define MX28_INT_AUART1_TX_DMA 73
146#define MX28_INT_AUART2_RX_DMA 74
147#define MX28_INT_AUART2_TX_DMA 75
148#define MX28_INT_AUART3_RX_DMA 76
149#define MX28_INT_AUART3_TX_DMA 77
150#define MX28_INT_AUART4_RX_DMA 78
151#define MX28_INT_AUART4_TX_DMA 79
152#define MX28_INT_SAIF0_DMA 80
153#define MX28_INT_SAIF1_DMA 81
154#define MX28_INT_SSP0_DMA 82
155#define MX28_INT_SSP1_DMA 83
156#define MX28_INT_SSP2_DMA 84
157#define MX28_INT_SSP3_DMA 85
158#define MX28_INT_LCDIF_DMA 86
159#define MX28_INT_HSADC_DMA 87
160#define MX28_INT_GPMI_DMA 88
161#define MX28_INT_DIGCTL_DEBUG_TRAP 89
162#define MX28_INT_USB1 92
163#define MX28_INT_USB0 93
164#define MX28_INT_USB1_WAKEUP 94
165#define MX28_INT_USB0_WAKEUP 95
166#define MX28_INT_SSP0 96
167#define MX28_INT_SSP1 97
168#define MX28_INT_SSP2 98
169#define MX28_INT_SSP3 99
170#define MX28_INT_ENET_SWI 100
171#define MX28_INT_ENET_MAC0 101
172#define MX28_INT_ENET_MAC1 102
173#define MX28_INT_ENET_MAC0_1588 103
174#define MX28_INT_ENET_MAC1_1588 104
175#define MX28_INT_I2C1_ERROR 110
176#define MX28_INT_I2C0_ERROR 111
177#define MX28_INT_AUART0 112
178#define MX28_INT_AUART1 113
179#define MX28_INT_AUART2 114
180#define MX28_INT_AUART3 115
181#define MX28_INT_AUART4 116
182#define MX28_INT_GPIO4 123
183#define MX28_INT_GPIO3 124
184#define MX28_INT_GPIO2 125
185#define MX28_INT_GPIO1 126
186#define MX28_INT_GPIO0 127
187
188#endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
new file mode 100644
index 000000000000..f186c08c2911
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/mxs.h
@@ -0,0 +1,105 @@
1/*
2 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_MXS_H__
20#define __MACH_MXS_H__
21
22#ifndef __ASSEMBLER__
23#include <linux/io.h>
24#endif
25#include <asm/mach-types.h>
26#include <mach/hardware.h>
27
28/*
29 * MXS CPU types
30 */
31#define cpu_is_mx23() (machine_is_mx23evk())
32#define cpu_is_mx28() (machine_is_mx28evk())
33
34/*
35 * IO addresses common to MXS-based
36 */
37#define MXS_IO_BASE_ADDR 0x80000000
38#define MXS_IO_SIZE SZ_1M
39
40#define MXS_ICOLL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x000000)
41#define MXS_APBH_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x004000)
42#define MXS_BCH_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00a000)
43#define MXS_GPMI_BASE_ADDR (MXS_IO_BASE_ADDR + 0x00c000)
44#define MXS_PINCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x018000)
45#define MXS_DIGCTL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x01c000)
46#define MXS_APBX_DMA_BASE_ADDR (MXS_IO_BASE_ADDR + 0x024000)
47#define MXS_DCP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x028000)
48#define MXS_PXP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02a000)
49#define MXS_OCOTP_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02c000)
50#define MXS_AXI_AHB0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x02e000)
51#define MXS_LCDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x030000)
52#define MXS_CLKCTRL_BASE_ADDR (MXS_IO_BASE_ADDR + 0x040000)
53#define MXS_SAIF0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x042000)
54#define MXS_POWER_BASE_ADDR (MXS_IO_BASE_ADDR + 0x044000)
55#define MXS_SAIF1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x046000)
56#define MXS_LRADC_BASE_ADDR (MXS_IO_BASE_ADDR + 0x050000)
57#define MXS_SPDIF_BASE_ADDR (MXS_IO_BASE_ADDR + 0x054000)
58#define MXS_I2C0_BASE_ADDR (MXS_IO_BASE_ADDR + 0x058000)
59#define MXS_PWM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x064000)
60#define MXS_TIMROT_BASE_ADDR (MXS_IO_BASE_ADDR + 0x068000)
61#define MXS_AUART1_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06c000)
62#define MXS_AUART2_BASE_ADDR (MXS_IO_BASE_ADDR + 0x06e000)
63#define MXS_DRAM_BASE_ADDR (MXS_IO_BASE_ADDR + 0x0e0000)
64
65/*
66 * It maps the whole address space to [0xf4000000, 0xf50fffff].
67 *
68 * OCRAM 0x00000000+0x020000 -> 0xf4000000+0x020000
69 * IO 0x80000000+0x100000 -> 0xf5000000+0x100000
70 */
71#define MXS_IO_P2V(x) (0xf4000000 + \
72 (((x) & 0x80000000) >> 7) + \
73 (((x) & 0x000fffff)))
74
75#define MXS_IO_ADDRESS(x) IOMEM(MXS_IO_P2V(x))
76
77#define mxs_map_entry(soc, name, _type) { \
78 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
79 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
80 .length = soc ## _ ## name ## _SIZE, \
81 .type = _type, \
82}
83
84#define MXS_SET_ADDR 0x4
85#define MXS_CLR_ADDR 0x8
86#define MXS_TOG_ADDR 0xc
87
88#ifndef __ASSEMBLER__
89static inline void __mxs_setl(u32 mask, void __iomem *reg)
90{
91 __raw_writel(mask, reg + MXS_SET_ADDR);
92}
93
94static inline void __mxs_clrl(u32 mask, void __iomem *reg)
95{
96 __raw_writel(mask, reg + MXS_CLR_ADDR);
97}
98
99static inline void __mxs_togl(u32 mask, void __iomem *reg)
100{
101 __raw_writel(mask, reg + MXS_TOG_ADDR);
102}
103#endif
104
105#endif /* __MACH_MXS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/system.h b/arch/arm/mach-mxs/include/mach/system.h
new file mode 100644
index 000000000000..0e428239b433
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/system.h
@@ -0,0 +1,27 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2004-2008 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#ifndef __MACH_MXS_SYSTEM_H__
18#define __MACH_MXS_SYSTEM_H__
19
20static inline void arch_idle(void)
21{
22 cpu_do_idle();
23}
24
25void arch_reset(char mode, const char *cmd);
26
27#endif /* __MACH_MXS_SYSTEM_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/timex.h b/arch/arm/mach-mxs/include/mach/timex.h
new file mode 100644
index 000000000000..734ce8984a64
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/timex.h
@@ -0,0 +1,21 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __MACH_MXS_TIMEX_H__
17#define __MACH_MXS_TIMEX_H__
18
19#define CLOCK_TICK_RATE 32000 /* 32K */
20
21#endif /* __MACH_MXS_TIMEX_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
new file mode 100644
index 000000000000..a005e76f34f9
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -0,0 +1,76 @@
1/*
2 * arch/arm/mach-mxs/include/mach/uncompress.h
3 *
4 * Copyright (C) 1999 ARM Limited
5 * Copyright (C) Shane Nay (shane@minirl.com)
6 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18#ifndef __MACH_MXS_UNCOMPRESS_H__
19#define __MACH_MXS_UNCOMPRESS_H__
20
21#include <asm/mach-types.h>
22
23static unsigned long mxs_duart_base;
24
25#define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x)))
26
27#define MXS_DUART_DR 0x00
28#define MXS_DUART_FR 0x18
29#define MXS_DUART_FR_TXFE (1 << 7)
30#define MXS_DUART_CR 0x30
31#define MXS_DUART_CR_UARTEN (1 << 0)
32
33/*
34 * The following code assumes the serial port has already been
35 * initialized by the bootloader. If it's not, the output is
36 * simply discarded.
37 */
38
39static void putc(int ch)
40{
41 if (!mxs_duart_base)
42 return;
43 if (!(MXS_DUART(MXS_DUART_CR) & MXS_DUART_CR_UARTEN))
44 return;
45
46 while (!(MXS_DUART(MXS_DUART_FR) & MXS_DUART_FR_TXFE))
47 barrier();
48
49 MXS_DUART(MXS_DUART_DR) = ch;
50}
51
52static inline void flush(void)
53{
54}
55
56#define MX23_DUART_BASE_ADDR 0x80070000
57#define MX28_DUART_BASE_ADDR 0x80074000
58
59static inline void __arch_decomp_setup(unsigned long arch_id)
60{
61 switch (arch_id) {
62 case MACH_TYPE_MX23EVK:
63 mxs_duart_base = MX23_DUART_BASE_ADDR;
64 break;
65 case MACH_TYPE_MX28EVK:
66 mxs_duart_base = MX28_DUART_BASE_ADDR;
67 break;
68 default:
69 break;
70 }
71}
72
73#define arch_decomp_setup() __arch_decomp_setup(arch_id)
74#define arch_decomp_wdog()
75
76#endif /* __MACH_MXS_UNCOMPRESS_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/vmalloc.h b/arch/arm/mach-mxs/include/mach/vmalloc.h
new file mode 100644
index 000000000000..103b0165ed0b
--- /dev/null
+++ b/arch/arm/mach-mxs/include/mach/vmalloc.h
@@ -0,0 +1,22 @@
1/*
2 * Copyright (C) 2000 Russell King.
3 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#ifndef __MACH_MXS_VMALLOC_H__
17#define __MACH_MXS_VMALLOC_H__
18
19/* vmalloc ending address */
20#define VMALLOC_END 0xf4000000UL
21
22#endif /* __MACH_MXS_VMALLOC_H__ */
diff --git a/arch/arm/mach-mxs/iomux.c b/arch/arm/mach-mxs/iomux.c
new file mode 100644
index 000000000000..0e804e2f11f4
--- /dev/null
+++ b/arch/arm/mach-mxs/iomux.c
@@ -0,0 +1,101 @@
1/*
2 * Copyright 2004-2006,2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
4 * Copyright (C) 2009 by Jan Weitzel Phytec Messtechnik GmbH,
5 * <armlinux@phytec.de>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
19 * MA 02110-1301, USA.
20 */
21
22#include <linux/errno.h>
23#include <linux/init.h>
24#include <linux/kernel.h>
25#include <linux/module.h>
26#include <linux/string.h>
27#include <linux/gpio.h>
28
29#include <asm/mach/map.h>
30
31#include <mach/mxs.h>
32#include <mach/iomux.h>
33
34/*
35 * configures a single pad in the iomuxer
36 */
37int mxs_iomux_setup_pad(iomux_cfg_t pad)
38{
39 u32 reg, ofs, bp, bm;
40 void __iomem *iomux_base = MXS_IO_ADDRESS(MXS_PINCTRL_BASE_ADDR);
41
42 /* muxsel */
43 ofs = 0x100;
44 ofs += PAD_BANK(pad) * 0x20 + PAD_PIN(pad) / 16 * 0x10;
45 bp = PAD_PIN(pad) % 16 * 2;
46 bm = 0x3 << bp;
47 reg = __raw_readl(iomux_base + ofs);
48 reg &= ~bm;
49 reg |= PAD_MUXSEL(pad) << bp;
50 __raw_writel(reg, iomux_base + ofs);
51
52 /* drive */
53 ofs = cpu_is_mx23() ? 0x200 : 0x300;
54 ofs += PAD_BANK(pad) * 0x40 + PAD_PIN(pad) / 8 * 0x10;
55 /* mA */
56 if (PAD_MA_VALID(pad)) {
57 bp = PAD_PIN(pad) % 8 * 4;
58 bm = 0x3 << bp;
59 reg = __raw_readl(iomux_base + ofs);
60 reg &= ~bm;
61 reg |= PAD_MA(pad) << bp;
62 __raw_writel(reg, iomux_base + ofs);
63 }
64 /* vol */
65 if (PAD_VOL_VALID(pad)) {
66 bp = PAD_PIN(pad) % 8 * 4 + 2;
67 if (PAD_VOL(pad))
68 __mxs_setl(1 << bp, iomux_base + ofs);
69 else
70 __mxs_clrl(1 << bp, iomux_base + ofs);
71 }
72
73 /* pull */
74 if (PAD_PULL_VALID(pad)) {
75 ofs = cpu_is_mx23() ? 0x400 : 0x600;
76 ofs += PAD_BANK(pad) * 0x10;
77 bp = PAD_PIN(pad);
78 if (PAD_PULL(pad))
79 __mxs_setl(1 << bp, iomux_base + ofs);
80 else
81 __mxs_clrl(1 << bp, iomux_base + ofs);
82 }
83
84 return 0;
85}
86
87int mxs_iomux_setup_multiple_pads(const iomux_cfg_t *pad_list, unsigned count)
88{
89 const iomux_cfg_t *p = pad_list;
90 int i;
91 int ret;
92
93 for (i = 0; i < count; i++) {
94 ret = mxs_iomux_setup_pad(*p);
95 if (ret)
96 return ret;
97 p++;
98 }
99
100 return 0;
101}
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
new file mode 100644
index 000000000000..aa0640052f58
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -0,0 +1,57 @@
1/*
2 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/delay.h>
16#include <linux/platform_device.h>
17#include <linux/gpio.h>
18#include <linux/irq.h>
19
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/time.h>
23
24#include <mach/common.h>
25#include <mach/iomux-mx23.h>
26
27#include "devices-mx23.h"
28
29static const iomux_cfg_t mx23evk_pads[] __initconst = {
30 /* duart */
31 MX23_PAD_PWM0__DUART_RX | MXS_PAD_4MA,
32 MX23_PAD_PWM1__DUART_TX | MXS_PAD_4MA,
33};
34
35static void __init mx23evk_init(void)
36{
37 mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
38
39 mx23_add_duart();
40}
41
42static void __init mx23evk_timer_init(void)
43{
44 mx23_clocks_init();
45}
46
47static struct sys_timer mx23evk_timer = {
48 .init = mx23evk_timer_init,
49};
50
51MACHINE_START(MX23EVK, "Freescale MX23 EVK")
52 /* Maintainer: Freescale Semiconductor, Inc. */
53 .map_io = mx23_map_io,
54 .init_irq = mx23_init_irq,
55 .init_machine = mx23evk_init,
56 .timer = &mx23evk_timer,
57MACHINE_END
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
new file mode 100644
index 000000000000..d162e95910f3
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -0,0 +1,138 @@
1/*
2 * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/delay.h>
16#include <linux/platform_device.h>
17#include <linux/gpio.h>
18#include <linux/irq.h>
19#include <linux/clk.h>
20
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23#include <asm/mach/time.h>
24
25#include <mach/common.h>
26#include <mach/iomux-mx28.h>
27
28#include "devices-mx28.h"
29#include "gpio.h"
30
31#define MX28EVK_FEC_PHY_POWER MXS_GPIO_NR(2, 15)
32#define MX28EVK_FEC_PHY_RESET MXS_GPIO_NR(4, 13)
33
34static const iomux_cfg_t mx28evk_pads[] __initconst = {
35 /* duart */
36 MX28_PAD_PWM0__DUART_RX |
37 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
38 MX28_PAD_PWM1__DUART_TX |
39 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
40
41 /* fec0 */
42 MX28_PAD_ENET0_MDC__ENET0_MDC |
43 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
44 MX28_PAD_ENET0_MDIO__ENET0_MDIO |
45 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
46 MX28_PAD_ENET0_RX_EN__ENET0_RX_EN |
47 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
48 MX28_PAD_ENET0_RXD0__ENET0_RXD0 |
49 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
50 MX28_PAD_ENET0_RXD1__ENET0_RXD1 |
51 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
52 MX28_PAD_ENET0_TX_EN__ENET0_TX_EN |
53 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
54 MX28_PAD_ENET0_TXD0__ENET0_TXD0 |
55 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
56 MX28_PAD_ENET0_TXD1__ENET0_TXD1 |
57 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
58 MX28_PAD_ENET_CLK__CLKCTRL_ENET |
59 (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
60 /* phy power line */
61 MX28_PAD_SSP1_DATA3__GPIO_2_15 |
62 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
63 /* phy reset line */
64 MX28_PAD_ENET0_RX_CLK__GPIO_4_13 |
65 (MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
66};
67
68/* fec */
69static void __init mx28evk_fec_reset(void)
70{
71 int ret;
72 struct clk *clk;
73
74 /* Enable fec phy clock */
75 clk = clk_get_sys("pll2", NULL);
76 if (!IS_ERR(clk))
77 clk_enable(clk);
78
79 /* Power up fec phy */
80 ret = gpio_request(MX28EVK_FEC_PHY_POWER, "fec-phy-power");
81 if (ret) {
82 pr_err("Failed to request gpio fec-phy-%s: %d\n", "power", ret);
83 return;
84 }
85
86 ret = gpio_direction_output(MX28EVK_FEC_PHY_POWER, 0);
87 if (ret) {
88 pr_err("Failed to drive gpio fec-phy-%s: %d\n", "power", ret);
89 return;
90 }
91
92 /* Reset fec phy */
93 ret = gpio_request(MX28EVK_FEC_PHY_RESET, "fec-phy-reset");
94 if (ret) {
95 pr_err("Failed to request gpio fec-phy-%s: %d\n", "reset", ret);
96 return;
97 }
98
99 gpio_direction_output(MX28EVK_FEC_PHY_RESET, 0);
100 if (ret) {
101 pr_err("Failed to drive gpio fec-phy-%s: %d\n", "reset", ret);
102 return;
103 }
104
105 mdelay(1);
106 gpio_set_value(MX28EVK_FEC_PHY_RESET, 1);
107}
108
109static const struct fec_platform_data mx28_fec_pdata __initconst = {
110 .phy = PHY_INTERFACE_MODE_RMII,
111};
112
113static void __init mx28evk_init(void)
114{
115 mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
116
117 mx28_add_duart();
118
119 mx28evk_fec_reset();
120 mx28_add_fec(0, &mx28_fec_pdata);
121}
122
123static void __init mx28evk_timer_init(void)
124{
125 mx28_clocks_init();
126}
127
128static struct sys_timer mx28evk_timer = {
129 .init = mx28evk_timer_init,
130};
131
132MACHINE_START(MX28EVK, "Freescale MX28 EVK")
133 /* Maintainer: Freescale Semiconductor, Inc. */
134 .map_io = mx28_map_io,
135 .init_irq = mx28_init_irq,
136 .init_machine = mx28evk_init,
137 .timer = &mx28evk_timer,
138MACHINE_END
diff --git a/arch/arm/mach-mxs/mm-mx23.c b/arch/arm/mach-mxs/mm-mx23.c
new file mode 100644
index 000000000000..5148cd64a6b7
--- /dev/null
+++ b/arch/arm/mach-mxs/mm-mx23.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Create static mapping between physical to virtual memory.
12 */
13
14#include <linux/mm.h>
15#include <linux/init.h>
16
17#include <asm/mach/map.h>
18
19#include <mach/mx23.h>
20#include <mach/common.h>
21#include <mach/iomux.h>
22
23/*
24 * Define the MX23 memory map.
25 */
26static struct map_desc mx23_io_desc[] __initdata = {
27 mxs_map_entry(MX23, OCRAM, MT_DEVICE),
28 mxs_map_entry(MX23, IO, MT_DEVICE),
29};
30
31/*
32 * This function initializes the memory map. It is called during the
33 * system startup to create static physical to virtual memory mappings
34 * for the IO modules.
35 */
36void __init mx23_map_io(void)
37{
38 iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
39}
40
41void __init mx23_init_irq(void)
42{
43 icoll_init_irq();
44 mx23_register_gpios();
45}
diff --git a/arch/arm/mach-mxs/mm-mx28.c b/arch/arm/mach-mxs/mm-mx28.c
new file mode 100644
index 000000000000..7e4cea32ebc6
--- /dev/null
+++ b/arch/arm/mach-mxs/mm-mx28.c
@@ -0,0 +1,45 @@
1/*
2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 *
11 * Create static mapping between physical to virtual memory.
12 */
13
14#include <linux/mm.h>
15#include <linux/init.h>
16
17#include <asm/mach/map.h>
18
19#include <mach/mx28.h>
20#include <mach/common.h>
21#include <mach/iomux.h>
22
23/*
24 * Define the MX28 memory map.
25 */
26static struct map_desc mx28_io_desc[] __initdata = {
27 mxs_map_entry(MX28, OCRAM, MT_DEVICE),
28 mxs_map_entry(MX28, IO, MT_DEVICE),
29};
30
31/*
32 * This function initializes the memory map. It is called during the
33 * system startup to create static physical to virtual memory mappings
34 * for the IO modules.
35 */
36void __init mx28_map_io(void)
37{
38 iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
39}
40
41void __init mx28_init_irq(void)
42{
43 icoll_init_irq();
44 mx28_register_gpios();
45}
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx23.h b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
new file mode 100644
index 000000000000..dbc04747b691
--- /dev/null
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx23.h
@@ -0,0 +1,455 @@
1/*
2 * Freescale CLKCTRL Register Definitions
3 *
4 * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
5 * Copyright 2008-2010 Freescale Semiconductor, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 *
21 * This file is created by xml file. Don't Edit it.
22 *
23 * Xml Revision: 1.48
24 * Template revision: 26195
25 */
26
27#ifndef __REGS_CLKCTRL_MX23_H__
28#define __REGS_CLKCTRL_MX23_H__
29
30
31#define HW_CLKCTRL_PLLCTRL0 (0x00000000)
32#define HW_CLKCTRL_PLLCTRL0_SET (0x00000004)
33#define HW_CLKCTRL_PLLCTRL0_CLR (0x00000008)
34#define HW_CLKCTRL_PLLCTRL0_TOG (0x0000000c)
35
36#define BP_CLKCTRL_PLLCTRL0_RSRVD6 30
37#define BM_CLKCTRL_PLLCTRL0_RSRVD6 0xC0000000
38#define BF_CLKCTRL_PLLCTRL0_RSRVD6(v) \
39 (((v) << 30) & BM_CLKCTRL_PLLCTRL0_RSRVD6)
40#define BP_CLKCTRL_PLLCTRL0_LFR_SEL 28
41#define BM_CLKCTRL_PLLCTRL0_LFR_SEL 0x30000000
42#define BF_CLKCTRL_PLLCTRL0_LFR_SEL(v) \
43 (((v) << 28) & BM_CLKCTRL_PLLCTRL0_LFR_SEL)
44#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__DEFAULT 0x0
45#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_2 0x1
46#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__TIMES_05 0x2
47#define BV_CLKCTRL_PLLCTRL0_LFR_SEL__UNDEFINED 0x3
48#define BP_CLKCTRL_PLLCTRL0_RSRVD5 26
49#define BM_CLKCTRL_PLLCTRL0_RSRVD5 0x0C000000
50#define BF_CLKCTRL_PLLCTRL0_RSRVD5(v) \
51 (((v) << 26) & BM_CLKCTRL_PLLCTRL0_RSRVD5)
52#define BP_CLKCTRL_PLLCTRL0_CP_SEL 24
53#define BM_CLKCTRL_PLLCTRL0_CP_SEL 0x03000000
54#define BF_CLKCTRL_PLLCTRL0_CP_SEL(v) \
55 (((v) << 24) & BM_CLKCTRL_PLLCTRL0_CP_SEL)
56#define BV_CLKCTRL_PLLCTRL0_CP_SEL__DEFAULT 0x0
57#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_2 0x1
58#define BV_CLKCTRL_PLLCTRL0_CP_SEL__TIMES_05 0x2
59#define BV_CLKCTRL_PLLCTRL0_CP_SEL__UNDEFINED 0x3
60#define BP_CLKCTRL_PLLCTRL0_RSRVD4 22
61#define BM_CLKCTRL_PLLCTRL0_RSRVD4 0x00C00000
62#define BF_CLKCTRL_PLLCTRL0_RSRVD4(v) \
63 (((v) << 22) & BM_CLKCTRL_PLLCTRL0_RSRVD4)
64#define BP_CLKCTRL_PLLCTRL0_DIV_SEL 20
65#define BM_CLKCTRL_PLLCTRL0_DIV_SEL 0x00300000
66#define BF_CLKCTRL_PLLCTRL0_DIV_SEL(v) \
67 (((v) << 20) & BM_CLKCTRL_PLLCTRL0_DIV_SEL)
68#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__DEFAULT 0x0
69#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWER 0x1
70#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__LOWEST 0x2
71#define BV_CLKCTRL_PLLCTRL0_DIV_SEL__UNDEFINED 0x3
72#define BM_CLKCTRL_PLLCTRL0_RSRVD3 0x00080000
73#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
74#define BM_CLKCTRL_PLLCTRL0_RSRVD2 0x00020000
75#define BM_CLKCTRL_PLLCTRL0_POWER 0x00010000
76#define BP_CLKCTRL_PLLCTRL0_RSRVD1 0
77#define BM_CLKCTRL_PLLCTRL0_RSRVD1 0x0000FFFF
78#define BF_CLKCTRL_PLLCTRL0_RSRVD1(v) \
79 (((v) << 0) & BM_CLKCTRL_PLLCTRL0_RSRVD1)
80
81#define HW_CLKCTRL_PLLCTRL1 (0x00000010)
82
83#define BM_CLKCTRL_PLLCTRL1_LOCK 0x80000000
84#define BM_CLKCTRL_PLLCTRL1_FORCE_LOCK 0x40000000
85#define BP_CLKCTRL_PLLCTRL1_RSRVD1 16
86#define BM_CLKCTRL_PLLCTRL1_RSRVD1 0x3FFF0000
87#define BF_CLKCTRL_PLLCTRL1_RSRVD1(v) \
88 (((v) << 16) & BM_CLKCTRL_PLLCTRL1_RSRVD1)
89#define BP_CLKCTRL_PLLCTRL1_LOCK_COUNT 0
90#define BM_CLKCTRL_PLLCTRL1_LOCK_COUNT 0x0000FFFF
91#define BF_CLKCTRL_PLLCTRL1_LOCK_COUNT(v) \
92 (((v) << 0) & BM_CLKCTRL_PLLCTRL1_LOCK_COUNT)
93
94#define HW_CLKCTRL_CPU (0x00000020)
95#define HW_CLKCTRL_CPU_SET (0x00000024)
96#define HW_CLKCTRL_CPU_CLR (0x00000028)
97#define HW_CLKCTRL_CPU_TOG (0x0000002c)
98
99#define BP_CLKCTRL_CPU_RSRVD5 30
100#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
101#define BF_CLKCTRL_CPU_RSRVD5(v) \
102 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
103#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
104#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
105#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
106#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
107#define BP_CLKCTRL_CPU_DIV_XTAL 16
108#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
109#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
110 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
111#define BP_CLKCTRL_CPU_RSRVD3 13
112#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
113#define BF_CLKCTRL_CPU_RSRVD3(v) \
114 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
115#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
116#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
117#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
118#define BP_CLKCTRL_CPU_RSRVD1 6
119#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
120#define BF_CLKCTRL_CPU_RSRVD1(v) \
121 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
122#define BP_CLKCTRL_CPU_DIV_CPU 0
123#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
124#define BF_CLKCTRL_CPU_DIV_CPU(v) \
125 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
126
127#define HW_CLKCTRL_HBUS (0x00000030)
128#define HW_CLKCTRL_HBUS_SET (0x00000034)
129#define HW_CLKCTRL_HBUS_CLR (0x00000038)
130#define HW_CLKCTRL_HBUS_TOG (0x0000003c)
131
132#define BP_CLKCTRL_HBUS_RSRVD4 30
133#define BM_CLKCTRL_HBUS_RSRVD4 0xC0000000
134#define BF_CLKCTRL_HBUS_RSRVD4(v) \
135 (((v) << 30) & BM_CLKCTRL_HBUS_RSRVD4)
136#define BM_CLKCTRL_HBUS_BUSY 0x20000000
137#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x10000000
138#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x08000000
139#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
140#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
141#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
142#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
143#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
144#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
145#define BM_CLKCTRL_HBUS_AUTO_SLOW_MODE 0x00100000
146#define BM_CLKCTRL_HBUS_RSRVD2 0x00080000
147#define BP_CLKCTRL_HBUS_SLOW_DIV 16
148#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
149#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
150 (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
151#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
152#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
153#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
154#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
155#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
156#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
157#define BP_CLKCTRL_HBUS_RSRVD1 6
158#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
159#define BF_CLKCTRL_HBUS_RSRVD1(v) \
160 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
161#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
162#define BP_CLKCTRL_HBUS_DIV 0
163#define BM_CLKCTRL_HBUS_DIV 0x0000001F
164#define BF_CLKCTRL_HBUS_DIV(v) \
165 (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
166
167#define HW_CLKCTRL_XBUS (0x00000040)
168
169#define BM_CLKCTRL_XBUS_BUSY 0x80000000
170#define BP_CLKCTRL_XBUS_RSRVD1 11
171#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF800
172#define BF_CLKCTRL_XBUS_RSRVD1(v) \
173 (((v) << 11) & BM_CLKCTRL_XBUS_RSRVD1)
174#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
175#define BP_CLKCTRL_XBUS_DIV 0
176#define BM_CLKCTRL_XBUS_DIV 0x000003FF
177#define BF_CLKCTRL_XBUS_DIV(v) \
178 (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
179
180#define HW_CLKCTRL_XTAL (0x00000050)
181#define HW_CLKCTRL_XTAL_SET (0x00000054)
182#define HW_CLKCTRL_XTAL_CLR (0x00000058)
183#define HW_CLKCTRL_XTAL_TOG (0x0000005c)
184
185#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
186#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
187#define BP_CLKCTRL_XTAL_FILT_CLK24M_GATE 30
188#define BM_CLKCTRL_XTAL_FILT_CLK24M_GATE 0x40000000
189#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
190#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
191#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
192#define BM_CLKCTRL_XTAL_DIGCTRL_CLK1M_GATE 0x08000000
193#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
194#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
195#define BP_CLKCTRL_XTAL_RSRVD1 2
196#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
197#define BF_CLKCTRL_XTAL_RSRVD1(v) \
198 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
199#define BP_CLKCTRL_XTAL_DIV_UART 0
200#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
201#define BF_CLKCTRL_XTAL_DIV_UART(v) \
202 (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
203
204#define HW_CLKCTRL_PIX (0x00000060)
205
206#define BP_CLKCTRL_PIX_CLKGATE 31
207#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
208#define BM_CLKCTRL_PIX_RSRVD2 0x40000000
209#define BM_CLKCTRL_PIX_BUSY 0x20000000
210#define BP_CLKCTRL_PIX_RSRVD1 13
211#define BM_CLKCTRL_PIX_RSRVD1 0x1FFFE000
212#define BF_CLKCTRL_PIX_RSRVD1(v) \
213 (((v) << 13) & BM_CLKCTRL_PIX_RSRVD1)
214#define BM_CLKCTRL_PIX_DIV_FRAC_EN 0x00001000
215#define BP_CLKCTRL_PIX_DIV 0
216#define BM_CLKCTRL_PIX_DIV 0x00000FFF
217#define BF_CLKCTRL_PIX_DIV(v) \
218 (((v) << 0) & BM_CLKCTRL_PIX_DIV)
219
220#define HW_CLKCTRL_SSP (0x00000070)
221
222#define BP_CLKCTRL_SSP_CLKGATE 31
223#define BM_CLKCTRL_SSP_CLKGATE 0x80000000
224#define BM_CLKCTRL_SSP_RSRVD2 0x40000000
225#define BM_CLKCTRL_SSP_BUSY 0x20000000
226#define BP_CLKCTRL_SSP_RSRVD1 10
227#define BM_CLKCTRL_SSP_RSRVD1 0x1FFFFC00
228#define BF_CLKCTRL_SSP_RSRVD1(v) \
229 (((v) << 10) & BM_CLKCTRL_SSP_RSRVD1)
230#define BM_CLKCTRL_SSP_DIV_FRAC_EN 0x00000200
231#define BP_CLKCTRL_SSP_DIV 0
232#define BM_CLKCTRL_SSP_DIV 0x000001FF
233#define BF_CLKCTRL_SSP_DIV(v) \
234 (((v) << 0) & BM_CLKCTRL_SSP_DIV)
235
236#define HW_CLKCTRL_GPMI (0x00000080)
237
238#define BP_CLKCTRL_GPMI_CLKGATE 31
239#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
240#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
241#define BM_CLKCTRL_GPMI_BUSY 0x20000000
242#define BP_CLKCTRL_GPMI_RSRVD1 11
243#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
244#define BF_CLKCTRL_GPMI_RSRVD1(v) \
245 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
246#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
247#define BP_CLKCTRL_GPMI_DIV 0
248#define BM_CLKCTRL_GPMI_DIV 0x000003FF
249#define BF_CLKCTRL_GPMI_DIV(v) \
250 (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
251
252#define HW_CLKCTRL_SPDIF (0x00000090)
253
254#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
255#define BP_CLKCTRL_SPDIF_RSRVD 0
256#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
257#define BF_CLKCTRL_SPDIF_RSRVD(v) \
258 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
259
260#define HW_CLKCTRL_EMI (0x000000a0)
261
262#define BP_CLKCTRL_EMI_CLKGATE 31
263#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
264#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
265#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
266#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
267#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
268#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
269#define BP_CLKCTRL_EMI_RSRVD3 18
270#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
271#define BF_CLKCTRL_EMI_RSRVD3(v) \
272 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
273#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
274#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
275#define BP_CLKCTRL_EMI_RSRVD2 12
276#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
277#define BF_CLKCTRL_EMI_RSRVD2(v) \
278 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
279#define BP_CLKCTRL_EMI_DIV_XTAL 8
280#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
281#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
282 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
283#define BP_CLKCTRL_EMI_RSRVD1 6
284#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
285#define BF_CLKCTRL_EMI_RSRVD1(v) \
286 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
287#define BP_CLKCTRL_EMI_DIV_EMI 0
288#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
289#define BF_CLKCTRL_EMI_DIV_EMI(v) \
290 (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
291
292#define HW_CLKCTRL_IR (0x000000b0)
293
294#define BM_CLKCTRL_IR_CLKGATE 0x80000000
295#define BM_CLKCTRL_IR_RSRVD3 0x40000000
296#define BM_CLKCTRL_IR_AUTO_DIV 0x20000000
297#define BM_CLKCTRL_IR_IR_BUSY 0x10000000
298#define BM_CLKCTRL_IR_IROV_BUSY 0x08000000
299#define BP_CLKCTRL_IR_RSRVD2 25
300#define BM_CLKCTRL_IR_RSRVD2 0x06000000
301#define BF_CLKCTRL_IR_RSRVD2(v) \
302 (((v) << 25) & BM_CLKCTRL_IR_RSRVD2)
303#define BP_CLKCTRL_IR_IROV_DIV 16
304#define BM_CLKCTRL_IR_IROV_DIV 0x01FF0000
305#define BF_CLKCTRL_IR_IROV_DIV(v) \
306 (((v) << 16) & BM_CLKCTRL_IR_IROV_DIV)
307#define BP_CLKCTRL_IR_RSRVD1 10
308#define BM_CLKCTRL_IR_RSRVD1 0x0000FC00
309#define BF_CLKCTRL_IR_RSRVD1(v) \
310 (((v) << 10) & BM_CLKCTRL_IR_RSRVD1)
311#define BP_CLKCTRL_IR_IR_DIV 0
312#define BM_CLKCTRL_IR_IR_DIV 0x000003FF
313#define BF_CLKCTRL_IR_IR_DIV(v) \
314 (((v) << 0) & BM_CLKCTRL_IR_IR_DIV)
315
316#define HW_CLKCTRL_SAIF (0x000000c0)
317
318#define BM_CLKCTRL_SAIF_CLKGATE 0x80000000
319#define BM_CLKCTRL_SAIF_RSRVD2 0x40000000
320#define BM_CLKCTRL_SAIF_BUSY 0x20000000
321#define BP_CLKCTRL_SAIF_RSRVD1 17
322#define BM_CLKCTRL_SAIF_RSRVD1 0x1FFE0000
323#define BF_CLKCTRL_SAIF_RSRVD1(v) \
324 (((v) << 17) & BM_CLKCTRL_SAIF_RSRVD1)
325#define BM_CLKCTRL_SAIF_DIV_FRAC_EN 0x00010000
326#define BP_CLKCTRL_SAIF_DIV 0
327#define BM_CLKCTRL_SAIF_DIV 0x0000FFFF
328#define BF_CLKCTRL_SAIF_DIV(v) \
329 (((v) << 0) & BM_CLKCTRL_SAIF_DIV)
330
331#define HW_CLKCTRL_TV (0x000000d0)
332
333#define BM_CLKCTRL_TV_CLK_TV108M_GATE 0x80000000
334#define BM_CLKCTRL_TV_CLK_TV_GATE 0x40000000
335#define BP_CLKCTRL_TV_RSRVD 0
336#define BM_CLKCTRL_TV_RSRVD 0x3FFFFFFF
337#define BF_CLKCTRL_TV_RSRVD(v) \
338 (((v) << 0) & BM_CLKCTRL_TV_RSRVD)
339
340#define HW_CLKCTRL_ETM (0x000000e0)
341
342#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
343#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
344#define BM_CLKCTRL_ETM_BUSY 0x20000000
345#define BP_CLKCTRL_ETM_RSRVD1 7
346#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF80
347#define BF_CLKCTRL_ETM_RSRVD1(v) \
348 (((v) << 7) & BM_CLKCTRL_ETM_RSRVD1)
349#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000040
350#define BP_CLKCTRL_ETM_DIV 0
351#define BM_CLKCTRL_ETM_DIV 0x0000003F
352#define BF_CLKCTRL_ETM_DIV(v) \
353 (((v) << 0) & BM_CLKCTRL_ETM_DIV)
354
355#define HW_CLKCTRL_FRAC (0x000000f0)
356#define HW_CLKCTRL_FRAC_SET (0x000000f4)
357#define HW_CLKCTRL_FRAC_CLR (0x000000f8)
358#define HW_CLKCTRL_FRAC_TOG (0x000000fc)
359
360#define BP_CLKCTRL_FRAC_CLKGATEIO 31
361#define BM_CLKCTRL_FRAC_CLKGATEIO 0x80000000
362#define BM_CLKCTRL_FRAC_IO_STABLE 0x40000000
363#define BP_CLKCTRL_FRAC_IOFRAC 24
364#define BM_CLKCTRL_FRAC_IOFRAC 0x3F000000
365#define BF_CLKCTRL_FRAC_IOFRAC(v) \
366 (((v) << 24) & BM_CLKCTRL_FRAC_IOFRAC)
367#define BP_CLKCTRL_FRAC_CLKGATEPIX 23
368#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
369#define BM_CLKCTRL_FRAC_PIX_STABLE 0x00400000
370#define BP_CLKCTRL_FRAC_PIXFRAC 16
371#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
372#define BF_CLKCTRL_FRAC_PIXFRAC(v) \
373 (((v) << 16) & BM_CLKCTRL_FRAC_PIXFRAC)
374#define BP_CLKCTRL_FRAC_CLKGATEEMI 15
375#define BM_CLKCTRL_FRAC_CLKGATEEMI 0x00008000
376#define BM_CLKCTRL_FRAC_EMI_STABLE 0x00004000
377#define BP_CLKCTRL_FRAC_EMIFRAC 8
378#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
379#define BF_CLKCTRL_FRAC_EMIFRAC(v) \
380 (((v) << 8) & BM_CLKCTRL_FRAC_EMIFRAC)
381#define BP_CLKCTRL_FRAC_CLKGATECPU 7
382#define BM_CLKCTRL_FRAC_CLKGATECPU 0x00000080
383#define BM_CLKCTRL_FRAC_CPU_STABLE 0x00000040
384#define BP_CLKCTRL_FRAC_CPUFRAC 0
385#define BM_CLKCTRL_FRAC_CPUFRAC 0x0000003F
386#define BF_CLKCTRL_FRAC_CPUFRAC(v) \
387 (((v) << 0) & BM_CLKCTRL_FRAC_CPUFRAC)
388
389#define HW_CLKCTRL_FRAC1 (0x00000100)
390#define HW_CLKCTRL_FRAC1_SET (0x00000104)
391#define HW_CLKCTRL_FRAC1_CLR (0x00000108)
392#define HW_CLKCTRL_FRAC1_TOG (0x0000010c)
393
394#define BM_CLKCTRL_FRAC1_CLKGATEVID 0x80000000
395#define BM_CLKCTRL_FRAC1_VID_STABLE 0x40000000
396#define BP_CLKCTRL_FRAC1_RSRVD1 0
397#define BM_CLKCTRL_FRAC1_RSRVD1 0x3FFFFFFF
398#define BF_CLKCTRL_FRAC1_RSRVD1(v) \
399 (((v) << 0) & BM_CLKCTRL_FRAC1_RSRVD1)
400
401#define HW_CLKCTRL_CLKSEQ (0x00000110)
402#define HW_CLKCTRL_CLKSEQ_SET (0x00000114)
403#define HW_CLKCTRL_CLKSEQ_CLR (0x00000118)
404#define HW_CLKCTRL_CLKSEQ_TOG (0x0000011c)
405
406#define BP_CLKCTRL_CLKSEQ_RSRVD1 9
407#define BM_CLKCTRL_CLKSEQ_RSRVD1 0xFFFFFE00
408#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
409 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD1)
410#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
411#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00000080
412#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000040
413#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP 0x00000020
414#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000010
415#define BM_CLKCTRL_CLKSEQ_BYPASS_IR 0x00000008
416#define BM_CLKCTRL_CLKSEQ_RSRVD0 0x00000004
417#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
418#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF 0x00000001
419
420#define HW_CLKCTRL_RESET (0x00000120)
421
422#define BP_CLKCTRL_RESET_RSRVD 2
423#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFFC
424#define BF_CLKCTRL_RESET_RSRVD(v) \
425 (((v) << 2) & BM_CLKCTRL_RESET_RSRVD)
426#define BM_CLKCTRL_RESET_CHIP 0x00000002
427#define BM_CLKCTRL_RESET_DIG 0x00000001
428
429#define HW_CLKCTRL_STATUS (0x00000130)
430
431#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
432#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
433#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
434 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
435#define BP_CLKCTRL_STATUS_RSRVD 0
436#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
437#define BF_CLKCTRL_STATUS_RSRVD(v) \
438 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
439
440#define HW_CLKCTRL_VERSION (0x00000140)
441
442#define BP_CLKCTRL_VERSION_MAJOR 24
443#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
444#define BF_CLKCTRL_VERSION_MAJOR(v) \
445 (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
446#define BP_CLKCTRL_VERSION_MINOR 16
447#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
448#define BF_CLKCTRL_VERSION_MINOR(v) \
449 (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
450#define BP_CLKCTRL_VERSION_STEP 0
451#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
452#define BF_CLKCTRL_VERSION_STEP(v) \
453 (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
454
455#endif /* __REGS_CLKCTRL_MX23_H__ */
diff --git a/arch/arm/mach-mxs/regs-clkctrl-mx28.h b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
new file mode 100644
index 000000000000..661df18755f7
--- /dev/null
+++ b/arch/arm/mach-mxs/regs-clkctrl-mx28.h
@@ -0,0 +1,663 @@
1/*
2 * Freescale CLKCTRL Register Definitions
3 *
4 * Copyright 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 * This file is created by xml file. Don't Edit it.
21 *
22 * Xml Revision: 1.48
23 * Template revision: 26195
24 */
25
26#ifndef __REGS_CLKCTRL_MX28_H__
27#define __REGS_CLKCTRL_MX28_H__
28
29#define HW_CLKCTRL_PLL0CTRL0 (0x00000000)
30#define HW_CLKCTRL_PLL0CTRL0_SET (0x00000004)
31#define HW_CLKCTRL_PLL0CTRL0_CLR (0x00000008)
32#define HW_CLKCTRL_PLL0CTRL0_TOG (0x0000000c)
33
34#define BP_CLKCTRL_PLL0CTRL0_RSRVD6 30
35#define BM_CLKCTRL_PLL0CTRL0_RSRVD6 0xC0000000
36#define BF_CLKCTRL_PLL0CTRL0_RSRVD6(v) \
37 (((v) << 30) & BM_CLKCTRL_PLL0CTRL0_RSRVD6)
38#define BP_CLKCTRL_PLL0CTRL0_LFR_SEL 28
39#define BM_CLKCTRL_PLL0CTRL0_LFR_SEL 0x30000000
40#define BF_CLKCTRL_PLL0CTRL0_LFR_SEL(v) \
41 (((v) << 28) & BM_CLKCTRL_PLL0CTRL0_LFR_SEL)
42#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__DEFAULT 0x0
43#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_2 0x1
44#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__TIMES_05 0x2
45#define BV_CLKCTRL_PLL0CTRL0_LFR_SEL__UNDEFINED 0x3
46#define BP_CLKCTRL_PLL0CTRL0_RSRVD5 26
47#define BM_CLKCTRL_PLL0CTRL0_RSRVD5 0x0C000000
48#define BF_CLKCTRL_PLL0CTRL0_RSRVD5(v) \
49 (((v) << 26) & BM_CLKCTRL_PLL0CTRL0_RSRVD5)
50#define BP_CLKCTRL_PLL0CTRL0_CP_SEL 24
51#define BM_CLKCTRL_PLL0CTRL0_CP_SEL 0x03000000
52#define BF_CLKCTRL_PLL0CTRL0_CP_SEL(v) \
53 (((v) << 24) & BM_CLKCTRL_PLL0CTRL0_CP_SEL)
54#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__DEFAULT 0x0
55#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_2 0x1
56#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__TIMES_05 0x2
57#define BV_CLKCTRL_PLL0CTRL0_CP_SEL__UNDEFINED 0x3
58#define BP_CLKCTRL_PLL0CTRL0_RSRVD4 22
59#define BM_CLKCTRL_PLL0CTRL0_RSRVD4 0x00C00000
60#define BF_CLKCTRL_PLL0CTRL0_RSRVD4(v) \
61 (((v) << 22) & BM_CLKCTRL_PLL0CTRL0_RSRVD4)
62#define BP_CLKCTRL_PLL0CTRL0_DIV_SEL 20
63#define BM_CLKCTRL_PLL0CTRL0_DIV_SEL 0x00300000
64#define BF_CLKCTRL_PLL0CTRL0_DIV_SEL(v) \
65 (((v) << 20) & BM_CLKCTRL_PLL0CTRL0_DIV_SEL)
66#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__DEFAULT 0x0
67#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWER 0x1
68#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__LOWEST 0x2
69#define BV_CLKCTRL_PLL0CTRL0_DIV_SEL__UNDEFINED 0x3
70#define BM_CLKCTRL_PLL0CTRL0_RSRVD3 0x00080000
71#define BM_CLKCTRL_PLL0CTRL0_EN_USB_CLKS 0x00040000
72#define BM_CLKCTRL_PLL0CTRL0_POWER 0x00020000
73#define BP_CLKCTRL_PLL0CTRL0_RSRVD1 0
74#define BM_CLKCTRL_PLL0CTRL0_RSRVD1 0x0001FFFF
75#define BF_CLKCTRL_PLL0CTRL0_RSRVD1(v) \
76 (((v) << 0) & BM_CLKCTRL_PLL0CTRL0_RSRVD1)
77
78#define HW_CLKCTRL_PLL0CTRL1 (0x00000010)
79
80#define BM_CLKCTRL_PLL0CTRL1_LOCK 0x80000000
81#define BM_CLKCTRL_PLL0CTRL1_FORCE_LOCK 0x40000000
82#define BP_CLKCTRL_PLL0CTRL1_RSRVD1 16
83#define BM_CLKCTRL_PLL0CTRL1_RSRVD1 0x3FFF0000
84#define BF_CLKCTRL_PLL0CTRL1_RSRVD1(v) \
85 (((v) << 16) & BM_CLKCTRL_PLL0CTRL1_RSRVD1)
86#define BP_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0
87#define BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT 0x0000FFFF
88#define BF_CLKCTRL_PLL0CTRL1_LOCK_COUNT(v) \
89 (((v) << 0) & BM_CLKCTRL_PLL0CTRL1_LOCK_COUNT)
90
91#define HW_CLKCTRL_PLL1CTRL0 (0x00000020)
92#define HW_CLKCTRL_PLL1CTRL0_SET (0x00000024)
93#define HW_CLKCTRL_PLL1CTRL0_CLR (0x00000028)
94#define HW_CLKCTRL_PLL1CTRL0_TOG (0x0000002c)
95
96#define BM_CLKCTRL_PLL1CTRL0_CLKGATEEMI 0x80000000
97#define BM_CLKCTRL_PLL1CTRL0_RSRVD6 0x40000000
98#define BP_CLKCTRL_PLL1CTRL0_LFR_SEL 28
99#define BM_CLKCTRL_PLL1CTRL0_LFR_SEL 0x30000000
100#define BF_CLKCTRL_PLL1CTRL0_LFR_SEL(v) \
101 (((v) << 28) & BM_CLKCTRL_PLL1CTRL0_LFR_SEL)
102#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__DEFAULT 0x0
103#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_2 0x1
104#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__TIMES_05 0x2
105#define BV_CLKCTRL_PLL1CTRL0_LFR_SEL__UNDEFINED 0x3
106#define BP_CLKCTRL_PLL1CTRL0_RSRVD5 26
107#define BM_CLKCTRL_PLL1CTRL0_RSRVD5 0x0C000000
108#define BF_CLKCTRL_PLL1CTRL0_RSRVD5(v) \
109 (((v) << 26) & BM_CLKCTRL_PLL1CTRL0_RSRVD5)
110#define BP_CLKCTRL_PLL1CTRL0_CP_SEL 24
111#define BM_CLKCTRL_PLL1CTRL0_CP_SEL 0x03000000
112#define BF_CLKCTRL_PLL1CTRL0_CP_SEL(v) \
113 (((v) << 24) & BM_CLKCTRL_PLL1CTRL0_CP_SEL)
114#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__DEFAULT 0x0
115#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_2 0x1
116#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__TIMES_05 0x2
117#define BV_CLKCTRL_PLL1CTRL0_CP_SEL__UNDEFINED 0x3
118#define BP_CLKCTRL_PLL1CTRL0_RSRVD4 22
119#define BM_CLKCTRL_PLL1CTRL0_RSRVD4 0x00C00000
120#define BF_CLKCTRL_PLL1CTRL0_RSRVD4(v) \
121 (((v) << 22) & BM_CLKCTRL_PLL1CTRL0_RSRVD4)
122#define BP_CLKCTRL_PLL1CTRL0_DIV_SEL 20
123#define BM_CLKCTRL_PLL1CTRL0_DIV_SEL 0x00300000
124#define BF_CLKCTRL_PLL1CTRL0_DIV_SEL(v) \
125 (((v) << 20) & BM_CLKCTRL_PLL1CTRL0_DIV_SEL)
126#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__DEFAULT 0x0
127#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWER 0x1
128#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__LOWEST 0x2
129#define BV_CLKCTRL_PLL1CTRL0_DIV_SEL__UNDEFINED 0x3
130#define BM_CLKCTRL_PLL1CTRL0_RSRVD3 0x00080000
131#define BM_CLKCTRL_PLL1CTRL0_EN_USB_CLKS 0x00040000
132#define BM_CLKCTRL_PLL1CTRL0_POWER 0x00020000
133#define BP_CLKCTRL_PLL1CTRL0_RSRVD1 0
134#define BM_CLKCTRL_PLL1CTRL0_RSRVD1 0x0001FFFF
135#define BF_CLKCTRL_PLL1CTRL0_RSRVD1(v) \
136 (((v) << 0) & BM_CLKCTRL_PLL1CTRL0_RSRVD1)
137
138#define HW_CLKCTRL_PLL1CTRL1 (0x00000030)
139
140#define BM_CLKCTRL_PLL1CTRL1_LOCK 0x80000000
141#define BM_CLKCTRL_PLL1CTRL1_FORCE_LOCK 0x40000000
142#define BP_CLKCTRL_PLL1CTRL1_RSRVD1 16
143#define BM_CLKCTRL_PLL1CTRL1_RSRVD1 0x3FFF0000
144#define BF_CLKCTRL_PLL1CTRL1_RSRVD1(v) \
145 (((v) << 16) & BM_CLKCTRL_PLL1CTRL1_RSRVD1)
146#define BP_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0
147#define BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT 0x0000FFFF
148#define BF_CLKCTRL_PLL1CTRL1_LOCK_COUNT(v) \
149 (((v) << 0) & BM_CLKCTRL_PLL1CTRL1_LOCK_COUNT)
150
151#define HW_CLKCTRL_PLL2CTRL0 (0x00000040)
152#define HW_CLKCTRL_PLL2CTRL0_SET (0x00000044)
153#define HW_CLKCTRL_PLL2CTRL0_CLR (0x00000048)
154#define HW_CLKCTRL_PLL2CTRL0_TOG (0x0000004c)
155
156#define BM_CLKCTRL_PLL2CTRL0_CLKGATE 0x80000000
157#define BM_CLKCTRL_PLL2CTRL0_RSRVD3 0x40000000
158#define BP_CLKCTRL_PLL2CTRL0_LFR_SEL 28
159#define BM_CLKCTRL_PLL2CTRL0_LFR_SEL 0x30000000
160#define BF_CLKCTRL_PLL2CTRL0_LFR_SEL(v) \
161 (((v) << 28) & BM_CLKCTRL_PLL2CTRL0_LFR_SEL)
162#define BM_CLKCTRL_PLL2CTRL0_RSRVD2 0x08000000
163#define BM_CLKCTRL_PLL2CTRL0_HOLD_RING_OFF_B 0x04000000
164#define BP_CLKCTRL_PLL2CTRL0_CP_SEL 24
165#define BM_CLKCTRL_PLL2CTRL0_CP_SEL 0x03000000
166#define BF_CLKCTRL_PLL2CTRL0_CP_SEL(v) \
167 (((v) << 24) & BM_CLKCTRL_PLL2CTRL0_CP_SEL)
168#define BM_CLKCTRL_PLL2CTRL0_POWER 0x00800000
169#define BP_CLKCTRL_PLL2CTRL0_RSRVD1 0
170#define BM_CLKCTRL_PLL2CTRL0_RSRVD1 0x007FFFFF
171#define BF_CLKCTRL_PLL2CTRL0_RSRVD1(v) \
172 (((v) << 0) & BM_CLKCTRL_PLL2CTRL0_RSRVD1)
173
174#define HW_CLKCTRL_CPU (0x00000050)
175#define HW_CLKCTRL_CPU_SET (0x00000054)
176#define HW_CLKCTRL_CPU_CLR (0x00000058)
177#define HW_CLKCTRL_CPU_TOG (0x0000005c)
178
179#define BP_CLKCTRL_CPU_RSRVD5 30
180#define BM_CLKCTRL_CPU_RSRVD5 0xC0000000
181#define BF_CLKCTRL_CPU_RSRVD5(v) \
182 (((v) << 30) & BM_CLKCTRL_CPU_RSRVD5)
183#define BM_CLKCTRL_CPU_BUSY_REF_XTAL 0x20000000
184#define BM_CLKCTRL_CPU_BUSY_REF_CPU 0x10000000
185#define BM_CLKCTRL_CPU_RSRVD4 0x08000000
186#define BM_CLKCTRL_CPU_DIV_XTAL_FRAC_EN 0x04000000
187#define BP_CLKCTRL_CPU_DIV_XTAL 16
188#define BM_CLKCTRL_CPU_DIV_XTAL 0x03FF0000
189#define BF_CLKCTRL_CPU_DIV_XTAL(v) \
190 (((v) << 16) & BM_CLKCTRL_CPU_DIV_XTAL)
191#define BP_CLKCTRL_CPU_RSRVD3 13
192#define BM_CLKCTRL_CPU_RSRVD3 0x0000E000
193#define BF_CLKCTRL_CPU_RSRVD3(v) \
194 (((v) << 13) & BM_CLKCTRL_CPU_RSRVD3)
195#define BM_CLKCTRL_CPU_INTERRUPT_WAIT 0x00001000
196#define BM_CLKCTRL_CPU_RSRVD2 0x00000800
197#define BM_CLKCTRL_CPU_DIV_CPU_FRAC_EN 0x00000400
198#define BP_CLKCTRL_CPU_RSRVD1 6
199#define BM_CLKCTRL_CPU_RSRVD1 0x000003C0
200#define BF_CLKCTRL_CPU_RSRVD1(v) \
201 (((v) << 6) & BM_CLKCTRL_CPU_RSRVD1)
202#define BP_CLKCTRL_CPU_DIV_CPU 0
203#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
204#define BF_CLKCTRL_CPU_DIV_CPU(v) \
205 (((v) << 0) & BM_CLKCTRL_CPU_DIV_CPU)
206
207#define HW_CLKCTRL_HBUS (0x00000060)
208#define HW_CLKCTRL_HBUS_SET (0x00000064)
209#define HW_CLKCTRL_HBUS_CLR (0x00000068)
210#define HW_CLKCTRL_HBUS_TOG (0x0000006c)
211
212#define BM_CLKCTRL_HBUS_ASM_BUSY 0x80000000
213#define BM_CLKCTRL_HBUS_DCP_AS_ENABLE 0x40000000
214#define BM_CLKCTRL_HBUS_PXP_AS_ENABLE 0x20000000
215#define BM_CLKCTRL_HBUS_RSRVD2 0x10000000
216#define BM_CLKCTRL_HBUS_ASM_EMIPORT_AS_ENABLE 0x08000000
217#define BM_CLKCTRL_HBUS_APBHDMA_AS_ENABLE 0x04000000
218#define BM_CLKCTRL_HBUS_APBXDMA_AS_ENABLE 0x02000000
219#define BM_CLKCTRL_HBUS_TRAFFIC_JAM_AS_ENABLE 0x01000000
220#define BM_CLKCTRL_HBUS_TRAFFIC_AS_ENABLE 0x00800000
221#define BM_CLKCTRL_HBUS_CPU_DATA_AS_ENABLE 0x00400000
222#define BM_CLKCTRL_HBUS_CPU_INSTR_AS_ENABLE 0x00200000
223#define BM_CLKCTRL_HBUS_ASM_ENABLE 0x00100000
224#define BM_CLKCTRL_HBUS_AUTO_CLEAR_DIV_ENABLE 0x00080000
225#define BP_CLKCTRL_HBUS_SLOW_DIV 16
226#define BM_CLKCTRL_HBUS_SLOW_DIV 0x00070000
227#define BF_CLKCTRL_HBUS_SLOW_DIV(v) \
228 (((v) << 16) & BM_CLKCTRL_HBUS_SLOW_DIV)
229#define BV_CLKCTRL_HBUS_SLOW_DIV__BY1 0x0
230#define BV_CLKCTRL_HBUS_SLOW_DIV__BY2 0x1
231#define BV_CLKCTRL_HBUS_SLOW_DIV__BY4 0x2
232#define BV_CLKCTRL_HBUS_SLOW_DIV__BY8 0x3
233#define BV_CLKCTRL_HBUS_SLOW_DIV__BY16 0x4
234#define BV_CLKCTRL_HBUS_SLOW_DIV__BY32 0x5
235#define BP_CLKCTRL_HBUS_RSRVD1 6
236#define BM_CLKCTRL_HBUS_RSRVD1 0x0000FFC0
237#define BF_CLKCTRL_HBUS_RSRVD1(v) \
238 (((v) << 6) & BM_CLKCTRL_HBUS_RSRVD1)
239#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
240#define BP_CLKCTRL_HBUS_DIV 0
241#define BM_CLKCTRL_HBUS_DIV 0x0000001F
242#define BF_CLKCTRL_HBUS_DIV(v) \
243 (((v) << 0) & BM_CLKCTRL_HBUS_DIV)
244
245#define HW_CLKCTRL_XBUS (0x00000070)
246
247#define BM_CLKCTRL_XBUS_BUSY 0x80000000
248#define BP_CLKCTRL_XBUS_RSRVD1 12
249#define BM_CLKCTRL_XBUS_RSRVD1 0x7FFFF000
250#define BF_CLKCTRL_XBUS_RSRVD1(v) \
251 (((v) << 12) & BM_CLKCTRL_XBUS_RSRVD1)
252#define BM_CLKCTRL_XBUS_AUTO_CLEAR_DIV_ENABLE 0x00000800
253#define BM_CLKCTRL_XBUS_DIV_FRAC_EN 0x00000400
254#define BP_CLKCTRL_XBUS_DIV 0
255#define BM_CLKCTRL_XBUS_DIV 0x000003FF
256#define BF_CLKCTRL_XBUS_DIV(v) \
257 (((v) << 0) & BM_CLKCTRL_XBUS_DIV)
258
259#define HW_CLKCTRL_XTAL (0x00000080)
260#define HW_CLKCTRL_XTAL_SET (0x00000084)
261#define HW_CLKCTRL_XTAL_CLR (0x00000088)
262#define HW_CLKCTRL_XTAL_TOG (0x0000008c)
263
264#define BP_CLKCTRL_XTAL_UART_CLK_GATE 31
265#define BM_CLKCTRL_XTAL_UART_CLK_GATE 0x80000000
266#define BM_CLKCTRL_XTAL_RSRVD3 0x40000000
267#define BP_CLKCTRL_XTAL_PWM_CLK24M_GATE 29
268#define BM_CLKCTRL_XTAL_PWM_CLK24M_GATE 0x20000000
269#define BP_CLKCTRL_XTAL_RSRVD2 27
270#define BM_CLKCTRL_XTAL_RSRVD2 0x18000000
271#define BF_CLKCTRL_XTAL_RSRVD2(v) \
272 (((v) << 27) & BM_CLKCTRL_XTAL_RSRVD2)
273#define BP_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 26
274#define BM_CLKCTRL_XTAL_TIMROT_CLK32K_GATE 0x04000000
275#define BP_CLKCTRL_XTAL_RSRVD1 2
276#define BM_CLKCTRL_XTAL_RSRVD1 0x03FFFFFC
277#define BF_CLKCTRL_XTAL_RSRVD1(v) \
278 (((v) << 2) & BM_CLKCTRL_XTAL_RSRVD1)
279#define BP_CLKCTRL_XTAL_DIV_UART 0
280#define BM_CLKCTRL_XTAL_DIV_UART 0x00000003
281#define BF_CLKCTRL_XTAL_DIV_UART(v) \
282 (((v) << 0) & BM_CLKCTRL_XTAL_DIV_UART)
283
284#define HW_CLKCTRL_SSP0 (0x00000090)
285
286#define BP_CLKCTRL_SSP0_CLKGATE 31
287#define BM_CLKCTRL_SSP0_CLKGATE 0x80000000
288#define BM_CLKCTRL_SSP0_RSRVD2 0x40000000
289#define BM_CLKCTRL_SSP0_BUSY 0x20000000
290#define BP_CLKCTRL_SSP0_RSRVD1 10
291#define BM_CLKCTRL_SSP0_RSRVD1 0x1FFFFC00
292#define BF_CLKCTRL_SSP0_RSRVD1(v) \
293 (((v) << 10) & BM_CLKCTRL_SSP0_RSRVD1)
294#define BM_CLKCTRL_SSP0_DIV_FRAC_EN 0x00000200
295#define BP_CLKCTRL_SSP0_DIV 0
296#define BM_CLKCTRL_SSP0_DIV 0x000001FF
297#define BF_CLKCTRL_SSP0_DIV(v) \
298 (((v) << 0) & BM_CLKCTRL_SSP0_DIV)
299
300#define HW_CLKCTRL_SSP1 (0x000000a0)
301
302#define BP_CLKCTRL_SSP1_CLKGATE 31
303#define BM_CLKCTRL_SSP1_CLKGATE 0x80000000
304#define BM_CLKCTRL_SSP1_RSRVD2 0x40000000
305#define BM_CLKCTRL_SSP1_BUSY 0x20000000
306#define BP_CLKCTRL_SSP1_RSRVD1 10
307#define BM_CLKCTRL_SSP1_RSRVD1 0x1FFFFC00
308#define BF_CLKCTRL_SSP1_RSRVD1(v) \
309 (((v) << 10) & BM_CLKCTRL_SSP1_RSRVD1)
310#define BM_CLKCTRL_SSP1_DIV_FRAC_EN 0x00000200
311#define BP_CLKCTRL_SSP1_DIV 0
312#define BM_CLKCTRL_SSP1_DIV 0x000001FF
313#define BF_CLKCTRL_SSP1_DIV(v) \
314 (((v) << 0) & BM_CLKCTRL_SSP1_DIV)
315
316#define HW_CLKCTRL_SSP2 (0x000000b0)
317
318#define BP_CLKCTRL_SSP2_CLKGATE 31
319#define BM_CLKCTRL_SSP2_CLKGATE 0x80000000
320#define BM_CLKCTRL_SSP2_RSRVD2 0x40000000
321#define BM_CLKCTRL_SSP2_BUSY 0x20000000
322#define BP_CLKCTRL_SSP2_RSRVD1 10
323#define BM_CLKCTRL_SSP2_RSRVD1 0x1FFFFC00
324#define BF_CLKCTRL_SSP2_RSRVD1(v) \
325 (((v) << 10) & BM_CLKCTRL_SSP2_RSRVD1)
326#define BM_CLKCTRL_SSP2_DIV_FRAC_EN 0x00000200
327#define BP_CLKCTRL_SSP2_DIV 0
328#define BM_CLKCTRL_SSP2_DIV 0x000001FF
329#define BF_CLKCTRL_SSP2_DIV(v) \
330 (((v) << 0) & BM_CLKCTRL_SSP2_DIV)
331
332#define HW_CLKCTRL_SSP3 (0x000000c0)
333
334#define BP_CLKCTRL_SSP3_CLKGATE 31
335#define BM_CLKCTRL_SSP3_CLKGATE 0x80000000
336#define BM_CLKCTRL_SSP3_RSRVD2 0x40000000
337#define BM_CLKCTRL_SSP3_BUSY 0x20000000
338#define BP_CLKCTRL_SSP3_RSRVD1 10
339#define BM_CLKCTRL_SSP3_RSRVD1 0x1FFFFC00
340#define BF_CLKCTRL_SSP3_RSRVD1(v) \
341 (((v) << 10) & BM_CLKCTRL_SSP3_RSRVD1)
342#define BM_CLKCTRL_SSP3_DIV_FRAC_EN 0x00000200
343#define BP_CLKCTRL_SSP3_DIV 0
344#define BM_CLKCTRL_SSP3_DIV 0x000001FF
345#define BF_CLKCTRL_SSP3_DIV(v) \
346 (((v) << 0) & BM_CLKCTRL_SSP3_DIV)
347
348#define HW_CLKCTRL_GPMI (0x000000d0)
349
350#define BP_CLKCTRL_GPMI_CLKGATE 31
351#define BM_CLKCTRL_GPMI_CLKGATE 0x80000000
352#define BM_CLKCTRL_GPMI_RSRVD2 0x40000000
353#define BM_CLKCTRL_GPMI_BUSY 0x20000000
354#define BP_CLKCTRL_GPMI_RSRVD1 11
355#define BM_CLKCTRL_GPMI_RSRVD1 0x1FFFF800
356#define BF_CLKCTRL_GPMI_RSRVD1(v) \
357 (((v) << 11) & BM_CLKCTRL_GPMI_RSRVD1)
358#define BM_CLKCTRL_GPMI_DIV_FRAC_EN 0x00000400
359#define BP_CLKCTRL_GPMI_DIV 0
360#define BM_CLKCTRL_GPMI_DIV 0x000003FF
361#define BF_CLKCTRL_GPMI_DIV(v) \
362 (((v) << 0) & BM_CLKCTRL_GPMI_DIV)
363
364#define HW_CLKCTRL_SPDIF (0x000000e0)
365
366#define BP_CLKCTRL_SPDIF_CLKGATE 31
367#define BM_CLKCTRL_SPDIF_CLKGATE 0x80000000
368#define BP_CLKCTRL_SPDIF_RSRVD 0
369#define BM_CLKCTRL_SPDIF_RSRVD 0x7FFFFFFF
370#define BF_CLKCTRL_SPDIF_RSRVD(v) \
371 (((v) << 0) & BM_CLKCTRL_SPDIF_RSRVD)
372
373#define HW_CLKCTRL_EMI (0x000000f0)
374
375#define BP_CLKCTRL_EMI_CLKGATE 31
376#define BM_CLKCTRL_EMI_CLKGATE 0x80000000
377#define BM_CLKCTRL_EMI_SYNC_MODE_EN 0x40000000
378#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
379#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
380#define BM_CLKCTRL_EMI_BUSY_REF_CPU 0x08000000
381#define BM_CLKCTRL_EMI_BUSY_SYNC_MODE 0x04000000
382#define BP_CLKCTRL_EMI_RSRVD3 18
383#define BM_CLKCTRL_EMI_RSRVD3 0x03FC0000
384#define BF_CLKCTRL_EMI_RSRVD3(v) \
385 (((v) << 18) & BM_CLKCTRL_EMI_RSRVD3)
386#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
387#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
388#define BP_CLKCTRL_EMI_RSRVD2 12
389#define BM_CLKCTRL_EMI_RSRVD2 0x0000F000
390#define BF_CLKCTRL_EMI_RSRVD2(v) \
391 (((v) << 12) & BM_CLKCTRL_EMI_RSRVD2)
392#define BP_CLKCTRL_EMI_DIV_XTAL 8
393#define BM_CLKCTRL_EMI_DIV_XTAL 0x00000F00
394#define BF_CLKCTRL_EMI_DIV_XTAL(v) \
395 (((v) << 8) & BM_CLKCTRL_EMI_DIV_XTAL)
396#define BP_CLKCTRL_EMI_RSRVD1 6
397#define BM_CLKCTRL_EMI_RSRVD1 0x000000C0
398#define BF_CLKCTRL_EMI_RSRVD1(v) \
399 (((v) << 6) & BM_CLKCTRL_EMI_RSRVD1)
400#define BP_CLKCTRL_EMI_DIV_EMI 0
401#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
402#define BF_CLKCTRL_EMI_DIV_EMI(v) \
403 (((v) << 0) & BM_CLKCTRL_EMI_DIV_EMI)
404
405#define HW_CLKCTRL_SAIF0 (0x00000100)
406
407#define BP_CLKCTRL_SAIF0_CLKGATE 31
408#define BM_CLKCTRL_SAIF0_CLKGATE 0x80000000
409#define BM_CLKCTRL_SAIF0_RSRVD2 0x40000000
410#define BM_CLKCTRL_SAIF0_BUSY 0x20000000
411#define BP_CLKCTRL_SAIF0_RSRVD1 17
412#define BM_CLKCTRL_SAIF0_RSRVD1 0x1FFE0000
413#define BF_CLKCTRL_SAIF0_RSRVD1(v) \
414 (((v) << 17) & BM_CLKCTRL_SAIF0_RSRVD1)
415#define BM_CLKCTRL_SAIF0_DIV_FRAC_EN 0x00010000
416#define BP_CLKCTRL_SAIF0_DIV 0
417#define BM_CLKCTRL_SAIF0_DIV 0x0000FFFF
418#define BF_CLKCTRL_SAIF0_DIV(v) \
419 (((v) << 0) & BM_CLKCTRL_SAIF0_DIV)
420
421#define HW_CLKCTRL_SAIF1 (0x00000110)
422
423#define BP_CLKCTRL_SAIF1_CLKGATE 31
424#define BM_CLKCTRL_SAIF1_CLKGATE 0x80000000
425#define BM_CLKCTRL_SAIF1_RSRVD2 0x40000000
426#define BM_CLKCTRL_SAIF1_BUSY 0x20000000
427#define BP_CLKCTRL_SAIF1_RSRVD1 17
428#define BM_CLKCTRL_SAIF1_RSRVD1 0x1FFE0000
429#define BF_CLKCTRL_SAIF1_RSRVD1(v) \
430 (((v) << 17) & BM_CLKCTRL_SAIF1_RSRVD1)
431#define BM_CLKCTRL_SAIF1_DIV_FRAC_EN 0x00010000
432#define BP_CLKCTRL_SAIF1_DIV 0
433#define BM_CLKCTRL_SAIF1_DIV 0x0000FFFF
434#define BF_CLKCTRL_SAIF1_DIV(v) \
435 (((v) << 0) & BM_CLKCTRL_SAIF1_DIV)
436
437#define HW_CLKCTRL_DIS_LCDIF (0x00000120)
438
439#define BP_CLKCTRL_DIS_LCDIF_CLKGATE 31
440#define BM_CLKCTRL_DIS_LCDIF_CLKGATE 0x80000000
441#define BM_CLKCTRL_DIS_LCDIF_RSRVD2 0x40000000
442#define BM_CLKCTRL_DIS_LCDIF_BUSY 0x20000000
443#define BP_CLKCTRL_DIS_LCDIF_RSRVD1 14
444#define BM_CLKCTRL_DIS_LCDIF_RSRVD1 0x1FFFC000
445#define BF_CLKCTRL_DIS_LCDIF_RSRVD1(v) \
446 (((v) << 14) & BM_CLKCTRL_DIS_LCDIF_RSRVD1)
447#define BM_CLKCTRL_DIS_LCDIF_DIV_FRAC_EN 0x00002000
448#define BP_CLKCTRL_DIS_LCDIF_DIV 0
449#define BM_CLKCTRL_DIS_LCDIF_DIV 0x00001FFF
450#define BF_CLKCTRL_DIS_LCDIF_DIV(v) \
451 (((v) << 0) & BM_CLKCTRL_DIS_LCDIF_DIV)
452
453#define HW_CLKCTRL_ETM (0x00000130)
454
455#define BM_CLKCTRL_ETM_CLKGATE 0x80000000
456#define BM_CLKCTRL_ETM_RSRVD2 0x40000000
457#define BM_CLKCTRL_ETM_BUSY 0x20000000
458#define BP_CLKCTRL_ETM_RSRVD1 8
459#define BM_CLKCTRL_ETM_RSRVD1 0x1FFFFF00
460#define BF_CLKCTRL_ETM_RSRVD1(v) \
461 (((v) << 8) & BM_CLKCTRL_ETM_RSRVD1)
462#define BM_CLKCTRL_ETM_DIV_FRAC_EN 0x00000080
463#define BP_CLKCTRL_ETM_DIV 0
464#define BM_CLKCTRL_ETM_DIV 0x0000007F
465#define BF_CLKCTRL_ETM_DIV(v) \
466 (((v) << 0) & BM_CLKCTRL_ETM_DIV)
467
468#define HW_CLKCTRL_ENET (0x00000140)
469
470#define BM_CLKCTRL_ENET_SLEEP 0x80000000
471#define BP_CLKCTRL_ENET_DISABLE 30
472#define BM_CLKCTRL_ENET_DISABLE 0x40000000
473#define BM_CLKCTRL_ENET_STATUS 0x20000000
474#define BM_CLKCTRL_ENET_RSRVD1 0x10000000
475#define BM_CLKCTRL_ENET_BUSY_TIME 0x08000000
476#define BP_CLKCTRL_ENET_DIV_TIME 21
477#define BM_CLKCTRL_ENET_DIV_TIME 0x07E00000
478#define BF_CLKCTRL_ENET_DIV_TIME(v) \
479 (((v) << 21) & BM_CLKCTRL_ENET_DIV_TIME)
480#define BM_CLKCTRL_ENET_BUSY 0x08000000
481#define BP_CLKCTRL_ENET_DIV 21
482#define BM_CLKCTRL_ENET_DIV 0x07E00000
483#define BF_CLKCTRL_ENET_DIV(v) \
484 (((v) << 21) & BM_CLKCTRL_ENET_DIV)
485#define BP_CLKCTRL_ENET_TIME_SEL 19
486#define BM_CLKCTRL_ENET_TIME_SEL 0x00180000
487#define BF_CLKCTRL_ENET_TIME_SEL(v) \
488 (((v) << 19) & BM_CLKCTRL_ENET_TIME_SEL)
489#define BV_CLKCTRL_ENET_TIME_SEL__XTAL 0x0
490#define BV_CLKCTRL_ENET_TIME_SEL__PLL 0x1
491#define BV_CLKCTRL_ENET_TIME_SEL__RMII_CLK 0x2
492#define BV_CLKCTRL_ENET_TIME_SEL__UNDEFINED 0x3
493#define BM_CLKCTRL_ENET_CLK_OUT_EN 0x00040000
494#define BM_CLKCTRL_ENET_RESET_BY_SW_CHIP 0x00020000
495#define BM_CLKCTRL_ENET_RESET_BY_SW 0x00010000
496#define BP_CLKCTRL_ENET_RSRVD0 0
497#define BM_CLKCTRL_ENET_RSRVD0 0x0000FFFF
498#define BF_CLKCTRL_ENET_RSRVD0(v) \
499 (((v) << 0) & BM_CLKCTRL_ENET_RSRVD0)
500
501#define HW_CLKCTRL_HSADC (0x00000150)
502
503#define BM_CLKCTRL_HSADC_RSRVD2 0x80000000
504#define BM_CLKCTRL_HSADC_RESETB 0x40000000
505#define BP_CLKCTRL_HSADC_FREQDIV 28
506#define BM_CLKCTRL_HSADC_FREQDIV 0x30000000
507#define BF_CLKCTRL_HSADC_FREQDIV(v) \
508 (((v) << 28) & BM_CLKCTRL_HSADC_FREQDIV)
509#define BP_CLKCTRL_HSADC_RSRVD1 0
510#define BM_CLKCTRL_HSADC_RSRVD1 0x0FFFFFFF
511#define BF_CLKCTRL_HSADC_RSRVD1(v) \
512 (((v) << 0) & BM_CLKCTRL_HSADC_RSRVD1)
513
514#define HW_CLKCTRL_FLEXCAN (0x00000160)
515
516#define BM_CLKCTRL_FLEXCAN_RSRVD2 0x80000000
517#define BP_CLKCTRL_FLEXCAN_STOP_CAN0 30
518#define BM_CLKCTRL_FLEXCAN_STOP_CAN0 0x40000000
519#define BM_CLKCTRL_FLEXCAN_CAN0_STATUS 0x20000000
520#define BP_CLKCTRL_FLEXCAN_STOP_CAN1 28
521#define BM_CLKCTRL_FLEXCAN_STOP_CAN1 0x10000000
522#define BM_CLKCTRL_FLEXCAN_CAN1_STATUS 0x08000000
523#define BP_CLKCTRL_FLEXCAN_RSRVD1 0
524#define BM_CLKCTRL_FLEXCAN_RSRVD1 0x07FFFFFF
525#define BF_CLKCTRL_FLEXCAN_RSRVD1(v) \
526 (((v) << 0) & BM_CLKCTRL_FLEXCAN_RSRVD1)
527
528#define HW_CLKCTRL_FRAC0 (0x000001b0)
529#define HW_CLKCTRL_FRAC0_SET (0x000001b4)
530#define HW_CLKCTRL_FRAC0_CLR (0x000001b8)
531#define HW_CLKCTRL_FRAC0_TOG (0x000001bc)
532
533#define BP_CLKCTRL_FRAC0_CLKGATEIO0 31
534#define BM_CLKCTRL_FRAC0_CLKGATEIO0 0x80000000
535#define BM_CLKCTRL_FRAC0_IO0_STABLE 0x40000000
536#define BP_CLKCTRL_FRAC0_IO0FRAC 24
537#define BM_CLKCTRL_FRAC0_IO0FRAC 0x3F000000
538#define BF_CLKCTRL_FRAC0_IO0FRAC(v) \
539 (((v) << 24) & BM_CLKCTRL_FRAC0_IO0FRAC)
540#define BP_CLKCTRL_FRAC0_CLKGATEIO1 23
541#define BM_CLKCTRL_FRAC0_CLKGATEIO1 0x00800000
542#define BM_CLKCTRL_FRAC0_IO1_STABLE 0x00400000
543#define BP_CLKCTRL_FRAC0_IO1FRAC 16
544#define BM_CLKCTRL_FRAC0_IO1FRAC 0x003F0000
545#define BF_CLKCTRL_FRAC0_IO1FRAC(v) \
546 (((v) << 16) & BM_CLKCTRL_FRAC0_IO1FRAC)
547#define BP_CLKCTRL_FRAC0_CLKGATEEMI 15
548#define BM_CLKCTRL_FRAC0_CLKGATEEMI 0x00008000
549#define BM_CLKCTRL_FRAC0_EMI_STABLE 0x00004000
550#define BP_CLKCTRL_FRAC0_EMIFRAC 8
551#define BM_CLKCTRL_FRAC0_EMIFRAC 0x00003F00
552#define BF_CLKCTRL_FRAC0_EMIFRAC(v) \
553 (((v) << 8) & BM_CLKCTRL_FRAC0_EMIFRAC)
554#define BP_CLKCTRL_FRAC0_CLKGATECPU 7
555#define BM_CLKCTRL_FRAC0_CLKGATECPU 0x00000080
556#define BM_CLKCTRL_FRAC0_CPU_STABLE 0x00000040
557#define BP_CLKCTRL_FRAC0_CPUFRAC 0
558#define BM_CLKCTRL_FRAC0_CPUFRAC 0x0000003F
559#define BF_CLKCTRL_FRAC0_CPUFRAC(v) \
560 (((v) << 0) & BM_CLKCTRL_FRAC0_CPUFRAC)
561
562#define HW_CLKCTRL_FRAC1 (0x000001c0)
563#define HW_CLKCTRL_FRAC1_SET (0x000001c4)
564#define HW_CLKCTRL_FRAC1_CLR (0x000001c8)
565#define HW_CLKCTRL_FRAC1_TOG (0x000001cc)
566
567#define BP_CLKCTRL_FRAC1_RSRVD2 24
568#define BM_CLKCTRL_FRAC1_RSRVD2 0xFF000000
569#define BF_CLKCTRL_FRAC1_RSRVD2(v) \
570 (((v) << 24) & BM_CLKCTRL_FRAC1_RSRVD2)
571#define BP_CLKCTRL_FRAC1_CLKGATEGPMI 23
572#define BM_CLKCTRL_FRAC1_CLKGATEGPMI 0x00800000
573#define BM_CLKCTRL_FRAC1_GPMI_STABLE 0x00400000
574#define BP_CLKCTRL_FRAC1_GPMIFRAC 16
575#define BM_CLKCTRL_FRAC1_GPMIFRAC 0x003F0000
576#define BF_CLKCTRL_FRAC1_GPMIFRAC(v) \
577 (((v) << 16) & BM_CLKCTRL_FRAC1_GPMIFRAC)
578#define BP_CLKCTRL_FRAC1_CLKGATEHSADC 15
579#define BM_CLKCTRL_FRAC1_CLKGATEHSADC 0x00008000
580#define BM_CLKCTRL_FRAC1_HSADC_STABLE 0x00004000
581#define BP_CLKCTRL_FRAC1_HSADCFRAC 8
582#define BM_CLKCTRL_FRAC1_HSADCFRAC 0x00003F00
583#define BF_CLKCTRL_FRAC1_HSADCFRAC(v) \
584 (((v) << 8) & BM_CLKCTRL_FRAC1_HSADCFRAC)
585#define BP_CLKCTRL_FRAC1_CLKGATEPIX 7
586#define BM_CLKCTRL_FRAC1_CLKGATEPIX 0x00000080
587#define BM_CLKCTRL_FRAC1_PIX_STABLE 0x00000040
588#define BP_CLKCTRL_FRAC1_PIXFRAC 0
589#define BM_CLKCTRL_FRAC1_PIXFRAC 0x0000003F
590#define BF_CLKCTRL_FRAC1_PIXFRAC(v) \
591 (((v) << 0) & BM_CLKCTRL_FRAC1_PIXFRAC)
592
593#define HW_CLKCTRL_CLKSEQ (0x000001d0)
594#define HW_CLKCTRL_CLKSEQ_SET (0x000001d4)
595#define HW_CLKCTRL_CLKSEQ_CLR (0x000001d8)
596#define HW_CLKCTRL_CLKSEQ_TOG (0x000001dc)
597
598#define BP_CLKCTRL_CLKSEQ_RSRVD0 19
599#define BM_CLKCTRL_CLKSEQ_RSRVD0 0xFFF80000
600#define BF_CLKCTRL_CLKSEQ_RSRVD0(v) \
601 (((v) << 19) & BM_CLKCTRL_CLKSEQ_RSRVD0)
602#define BM_CLKCTRL_CLKSEQ_BYPASS_CPU 0x00040000
603#define BP_CLKCTRL_CLKSEQ_RSRVD1 15
604#define BM_CLKCTRL_CLKSEQ_RSRVD1 0x00038000
605#define BF_CLKCTRL_CLKSEQ_RSRVD1(v) \
606 (((v) << 15) & BM_CLKCTRL_CLKSEQ_RSRVD1)
607#define BM_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF 0x00004000
608#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__BYPASS 0x1
609#define BV_CLKCTRL_CLKSEQ_BYPASS_DIS_LCDIF__PFD 0x0
610#define BP_CLKCTRL_CLKSEQ_RSRVD2 9
611#define BM_CLKCTRL_CLKSEQ_RSRVD2 0x00003E00
612#define BF_CLKCTRL_CLKSEQ_RSRVD2(v) \
613 (((v) << 9) & BM_CLKCTRL_CLKSEQ_RSRVD2)
614#define BM_CLKCTRL_CLKSEQ_BYPASS_ETM 0x00000100
615#define BM_CLKCTRL_CLKSEQ_BYPASS_EMI 0x00000080
616#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP3 0x00000040
617#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP2 0x00000020
618#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP1 0x00000010
619#define BM_CLKCTRL_CLKSEQ_BYPASS_SSP0 0x00000008
620#define BM_CLKCTRL_CLKSEQ_BYPASS_GPMI 0x00000004
621#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF1 0x00000002
622#define BM_CLKCTRL_CLKSEQ_BYPASS_SAIF0 0x00000001
623
624#define HW_CLKCTRL_RESET (0x000001e0)
625
626#define BP_CLKCTRL_RESET_RSRVD 6
627#define BM_CLKCTRL_RESET_RSRVD 0xFFFFFFC0
628#define BF_CLKCTRL_RESET_RSRVD(v) \
629 (((v) << 6) & BM_CLKCTRL_RESET_RSRVD)
630#define BM_CLKCTRL_RESET_WDOG_POR_DISABLE 0x00000020
631#define BM_CLKCTRL_RESET_EXTERNAL_RESET_ENABLE 0x00000010
632#define BM_CLKCTRL_RESET_THERMAL_RESET_ENABLE 0x00000008
633#define BM_CLKCTRL_RESET_THERMAL_RESET_DEFAULT 0x00000004
634#define BM_CLKCTRL_RESET_CHIP 0x00000002
635#define BM_CLKCTRL_RESET_DIG 0x00000001
636
637#define HW_CLKCTRL_STATUS (0x000001f0)
638
639#define BP_CLKCTRL_STATUS_CPU_LIMIT 30
640#define BM_CLKCTRL_STATUS_CPU_LIMIT 0xC0000000
641#define BF_CLKCTRL_STATUS_CPU_LIMIT(v) \
642 (((v) << 30) & BM_CLKCTRL_STATUS_CPU_LIMIT)
643#define BP_CLKCTRL_STATUS_RSRVD 0
644#define BM_CLKCTRL_STATUS_RSRVD 0x3FFFFFFF
645#define BF_CLKCTRL_STATUS_RSRVD(v) \
646 (((v) << 0) & BM_CLKCTRL_STATUS_RSRVD)
647
648#define HW_CLKCTRL_VERSION (0x00000200)
649
650#define BP_CLKCTRL_VERSION_MAJOR 24
651#define BM_CLKCTRL_VERSION_MAJOR 0xFF000000
652#define BF_CLKCTRL_VERSION_MAJOR(v) \
653 (((v) << 24) & BM_CLKCTRL_VERSION_MAJOR)
654#define BP_CLKCTRL_VERSION_MINOR 16
655#define BM_CLKCTRL_VERSION_MINOR 0x00FF0000
656#define BF_CLKCTRL_VERSION_MINOR(v) \
657 (((v) << 16) & BM_CLKCTRL_VERSION_MINOR)
658#define BP_CLKCTRL_VERSION_STEP 0
659#define BM_CLKCTRL_VERSION_STEP 0x0000FFFF
660#define BF_CLKCTRL_VERSION_STEP(v) \
661 (((v) << 0) & BM_CLKCTRL_VERSION_STEP)
662
663#endif /* __REGS_CLKCTRL_MX28_H__ */
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
new file mode 100644
index 000000000000..9343d7edd4f6
--- /dev/null
+++ b/arch/arm/mach-mxs/system.c
@@ -0,0 +1,137 @@
1/*
2 * Copyright (C) 1999 ARM Limited
3 * Copyright (C) 2000 Deep Blue Solutions Ltd
4 * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
5 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
6 * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/kernel.h>
20#include <linux/clk.h>
21#include <linux/io.h>
22#include <linux/err.h>
23#include <linux/delay.h>
24#include <linux/init.h>
25
26#include <asm/proc-fns.h>
27#include <asm/system.h>
28
29#include <mach/mxs.h>
30#include <mach/common.h>
31
32#define MX23_CLKCTRL_RESET_OFFSET 0x120
33#define MX28_CLKCTRL_RESET_OFFSET 0x1e0
34#define MXS_CLKCTRL_RESET_CHIP (1 << 1)
35
36#define MXS_MODULE_CLKGATE (1 << 30)
37#define MXS_MODULE_SFTRST (1 << 31)
38
39static void __iomem *mxs_clkctrl_reset_addr;
40
41/*
42 * Reset the system. It is called by machine_restart().
43 */
44void arch_reset(char mode, const char *cmd)
45{
46 /* reset the chip */
47 __mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr);
48
49 pr_err("Failed to assert the chip reset\n");
50
51 /* Delay to allow the serial port to show the message */
52 mdelay(50);
53
54 /* We'll take a jump through zero as a poor second */
55 cpu_reset(0);
56}
57
58static int __init mxs_arch_reset_init(void)
59{
60 struct clk *clk;
61
62 mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) +
63 (cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET :
64 MX28_CLKCTRL_RESET_OFFSET);
65
66 clk = clk_get_sys("rtc", NULL);
67 if (!IS_ERR(clk))
68 clk_enable(clk);
69
70 return 0;
71}
72core_initcall(mxs_arch_reset_init);
73
74/*
75 * Clear the bit and poll it cleared. This is usually called with
76 * a reset address and mask being either SFTRST(bit 31) or CLKGATE
77 * (bit 30).
78 */
79static int clear_poll_bit(void __iomem *addr, u32 mask)
80{
81 int timeout = 0x400;
82
83 /* clear the bit */
84 __mxs_clrl(mask, addr);
85
86 /*
87 * SFTRST needs 3 GPMI clocks to settle, the reference manual
88 * recommends to wait 1us.
89 */
90 udelay(1);
91
92 /* poll the bit becoming clear */
93 while ((__raw_readl(addr) & mask) && --timeout)
94 /* nothing */;
95
96 return !timeout;
97}
98
99int mxs_reset_block(void __iomem *reset_addr)
100{
101 int ret;
102 int timeout = 0x400;
103
104 /* clear and poll SFTRST */
105 ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
106 if (unlikely(ret))
107 goto error;
108
109 /* clear CLKGATE */
110 __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr);
111
112 /* set SFTRST to reset the block */
113 __mxs_setl(MXS_MODULE_SFTRST, reset_addr);
114 udelay(1);
115
116 /* poll CLKGATE becoming set */
117 while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout)
118 /* nothing */;
119 if (unlikely(!timeout))
120 goto error;
121
122 /* clear and poll SFTRST */
123 ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
124 if (unlikely(ret))
125 goto error;
126
127 /* clear and poll CLKGATE */
128 ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE);
129 if (unlikely(ret))
130 goto error;
131
132 return 0;
133
134error:
135 pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
136 return -ETIMEDOUT;
137}
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
new file mode 100644
index 000000000000..13647f301860
--- /dev/null
+++ b/arch/arm/mach-mxs/timer.c
@@ -0,0 +1,296 @@
1/*
2 * Copyright (C) 2000-2001 Deep Blue Solutions
3 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
4 * Copyright (C) 2006-2007 Pavel Pisa (ppisa@pikron.com)
5 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
6 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
20 * MA 02110-1301, USA.
21 */
22
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/clockchips.h>
26#include <linux/clk.h>
27
28#include <asm/mach/time.h>
29#include <mach/mxs.h>
30#include <mach/common.h>
31
32/*
33 * There are 2 versions of the timrot on Freescale MXS-based SoCs.
34 * The v1 on MX23 only gets 16 bits counter, while v2 on MX28
35 * extends the counter to 32 bits.
36 *
37 * The implementation uses two timers, one for clock_event and
38 * another for clocksource. MX28 uses timrot 0 and 1, while MX23
39 * uses 0 and 2.
40 */
41
42#define MX23_TIMROT_VERSION_OFFSET 0x0a0
43#define MX28_TIMROT_VERSION_OFFSET 0x120
44#define BP_TIMROT_MAJOR_VERSION 24
45#define BV_TIMROT_VERSION_1 0x01
46#define BV_TIMROT_VERSION_2 0x02
47#define timrot_is_v1() (timrot_major_version == BV_TIMROT_VERSION_1)
48
49/*
50 * There are 4 registers for each timrotv2 instance, and 2 registers
51 * for each timrotv1. So address step 0x40 in macros below strides
52 * one instance of timrotv2 while two instances of timrotv1.
53 *
54 * As the result, HW_TIMROT_XXXn(1) defines the address of timrot1
55 * on MX28 while timrot2 on MX23.
56 */
57/* common between v1 and v2 */
58#define HW_TIMROT_ROTCTRL 0x00
59#define HW_TIMROT_TIMCTRLn(n) (0x20 + (n) * 0x40)
60/* v1 only */
61#define HW_TIMROT_TIMCOUNTn(n) (0x30 + (n) * 0x40)
62/* v2 only */
63#define HW_TIMROT_RUNNING_COUNTn(n) (0x30 + (n) * 0x40)
64#define HW_TIMROT_FIXED_COUNTn(n) (0x40 + (n) * 0x40)
65
66#define BM_TIMROT_TIMCTRLn_RELOAD (1 << 6)
67#define BM_TIMROT_TIMCTRLn_UPDATE (1 << 7)
68#define BM_TIMROT_TIMCTRLn_IRQ_EN (1 << 14)
69#define BM_TIMROT_TIMCTRLn_IRQ (1 << 15)
70#define BP_TIMROT_TIMCTRLn_SELECT 0
71#define BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL 0x8
72#define BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL 0xb
73
74static struct clock_event_device mxs_clockevent_device;
75static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
76
77static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
78static u32 timrot_major_version;
79
80static inline void timrot_irq_disable(void)
81{
82 __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
83 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
84}
85
86static inline void timrot_irq_enable(void)
87{
88 __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
89 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
90}
91
92static void timrot_irq_acknowledge(void)
93{
94 __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
95 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
96}
97
98static cycle_t timrotv1_get_cycles(struct clocksource *cs)
99{
100 return ~((__raw_readl(mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1))
101 & 0xffff0000) >> 16);
102}
103
104static cycle_t timrotv2_get_cycles(struct clocksource *cs)
105{
106 return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
107}
108
109static int timrotv1_set_next_event(unsigned long evt,
110 struct clock_event_device *dev)
111{
112 /* timrot decrements the count */
113 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_TIMCOUNTn(0));
114
115 return 0;
116}
117
118static int timrotv2_set_next_event(unsigned long evt,
119 struct clock_event_device *dev)
120{
121 /* timrot decrements the count */
122 __raw_writel(evt, mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(0));
123
124 return 0;
125}
126
127static irqreturn_t mxs_timer_interrupt(int irq, void *dev_id)
128{
129 struct clock_event_device *evt = dev_id;
130
131 timrot_irq_acknowledge();
132 evt->event_handler(evt);
133
134 return IRQ_HANDLED;
135}
136
137static struct irqaction mxs_timer_irq = {
138 .name = "MXS Timer Tick",
139 .dev_id = &mxs_clockevent_device,
140 .flags = IRQF_TIMER | IRQF_IRQPOLL,
141 .handler = mxs_timer_interrupt,
142};
143
144#ifdef DEBUG
145static const char *clock_event_mode_label[] const = {
146 [CLOCK_EVT_MODE_PERIODIC] = "CLOCK_EVT_MODE_PERIODIC",
147 [CLOCK_EVT_MODE_ONESHOT] = "CLOCK_EVT_MODE_ONESHOT",
148 [CLOCK_EVT_MODE_SHUTDOWN] = "CLOCK_EVT_MODE_SHUTDOWN",
149 [CLOCK_EVT_MODE_UNUSED] = "CLOCK_EVT_MODE_UNUSED"
150};
151#endif /* DEBUG */
152
153static void mxs_set_mode(enum clock_event_mode mode,
154 struct clock_event_device *evt)
155{
156 /* Disable interrupt in timer module */
157 timrot_irq_disable();
158
159 if (mode != mxs_clockevent_mode) {
160 /* Set event time into the furthest future */
161 if (timrot_is_v1())
162 __raw_writel(0xffff,
163 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
164 else
165 __raw_writel(0xffffffff,
166 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
167
168 /* Clear pending interrupt */
169 timrot_irq_acknowledge();
170 }
171
172#ifdef DEBUG
173 pr_info("%s: changing mode from %s to %s\n", __func__,
174 clock_event_mode_label[mxs_clockevent_mode],
175 clock_event_mode_label[mode]);
176#endif /* DEBUG */
177
178 /* Remember timer mode */
179 mxs_clockevent_mode = mode;
180
181 switch (mode) {
182 case CLOCK_EVT_MODE_PERIODIC:
183 pr_err("%s: Periodic mode is not implemented\n", __func__);
184 break;
185 case CLOCK_EVT_MODE_ONESHOT:
186 timrot_irq_enable();
187 break;
188 case CLOCK_EVT_MODE_SHUTDOWN:
189 case CLOCK_EVT_MODE_UNUSED:
190 case CLOCK_EVT_MODE_RESUME:
191 /* Left event sources disabled, no more interrupts appear */
192 break;
193 }
194}
195
196static struct clock_event_device mxs_clockevent_device = {
197 .name = "mxs_timrot",
198 .features = CLOCK_EVT_FEAT_ONESHOT,
199 .shift = 32,
200 .set_mode = mxs_set_mode,
201 .set_next_event = timrotv2_set_next_event,
202 .rating = 200,
203};
204
205static int __init mxs_clockevent_init(struct clk *timer_clk)
206{
207 unsigned int c = clk_get_rate(timer_clk);
208
209 mxs_clockevent_device.mult =
210 div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
211 mxs_clockevent_device.cpumask = cpumask_of(0);
212 if (timrot_is_v1()) {
213 mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
214 mxs_clockevent_device.max_delta_ns =
215 clockevent_delta2ns(0xfffe, &mxs_clockevent_device);
216 mxs_clockevent_device.min_delta_ns =
217 clockevent_delta2ns(0xf, &mxs_clockevent_device);
218 } else {
219 mxs_clockevent_device.max_delta_ns =
220 clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
221 mxs_clockevent_device.min_delta_ns =
222 clockevent_delta2ns(0xf, &mxs_clockevent_device);
223 }
224
225 clockevents_register_device(&mxs_clockevent_device);
226
227 return 0;
228}
229
230static struct clocksource clocksource_mxs = {
231 .name = "mxs_timer",
232 .rating = 200,
233 .read = timrotv2_get_cycles,
234 .mask = CLOCKSOURCE_MASK(32),
235 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
236};
237
238static int __init mxs_clocksource_init(struct clk *timer_clk)
239{
240 unsigned int c = clk_get_rate(timer_clk);
241
242 if (timrot_is_v1()) {
243 clocksource_mxs.read = timrotv1_get_cycles;
244 clocksource_mxs.mask = CLOCKSOURCE_MASK(16);
245 }
246
247 clocksource_register_hz(&clocksource_mxs, c);
248
249 return 0;
250}
251
252void __init mxs_timer_init(struct clk *timer_clk, int irq)
253{
254 clk_enable(timer_clk);
255
256 /*
257 * Initialize timers to a known state
258 */
259 mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
260
261 /* get timrot version */
262 timrot_major_version = __raw_readl(mxs_timrot_base +
263 (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
264 MX28_TIMROT_VERSION_OFFSET));
265 timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
266
267 /* one for clock_event */
268 __raw_writel((timrot_is_v1() ?
269 BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
270 BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
271 BM_TIMROT_TIMCTRLn_UPDATE |
272 BM_TIMROT_TIMCTRLn_IRQ_EN,
273 mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
274
275 /* another for clocksource */
276 __raw_writel((timrot_is_v1() ?
277 BV_TIMROTv1_TIMCTRLn_SELECT__32KHZ_XTAL :
278 BV_TIMROTv2_TIMCTRLn_SELECT__32KHZ_XTAL) |
279 BM_TIMROT_TIMCTRLn_RELOAD,
280 mxs_timrot_base + HW_TIMROT_TIMCTRLn(1));
281
282 /* set clocksource timer fixed count to the maximum */
283 if (timrot_is_v1())
284 __raw_writel(0xffff,
285 mxs_timrot_base + HW_TIMROT_TIMCOUNTn(1));
286 else
287 __raw_writel(0xffffffff,
288 mxs_timrot_base + HW_TIMROT_FIXED_COUNTn(1));
289
290 /* init and register the timer to the framework */
291 mxs_clocksource_init(timer_clk);
292 mxs_clockevent_init(timer_clk);
293
294 /* Make irqs happen */
295 setup_irq(irq, &mxs_timer_irq);
296}
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index 64e3a64520e0..389f21795015 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -21,10 +21,6 @@ config ARCH_MX2
21 21
22config ARCH_MX25 22config ARCH_MX25
23 bool "MX25-based" 23 bool "MX25-based"
24 select CPU_ARM926T
25 select ARCH_MXC_IOMUX_V3
26 select HAVE_FB_IMX
27 select ARCH_MXC_AUDMUX_V2
28 help 24 help
29 This enables support for systems based on the Freescale i.MX25 family 25 This enables support for systems based on the Freescale i.MX25 family
30 26
@@ -51,7 +47,6 @@ endchoice
51 47
52source "arch/arm/mach-imx/Kconfig" 48source "arch/arm/mach-imx/Kconfig"
53source "arch/arm/mach-mx3/Kconfig" 49source "arch/arm/mach-mx3/Kconfig"
54source "arch/arm/mach-mx25/Kconfig"
55source "arch/arm/mach-mxc91231/Kconfig" 50source "arch/arm/mach-mxc91231/Kconfig"
56source "arch/arm/mach-mx5/Kconfig" 51source "arch/arm/mach-mx5/Kconfig"
57 52
@@ -68,12 +63,10 @@ config MXC_IRQ_PRIOR
68 Say N here, unless you have a specialized requirement. 63 Say N here, unless you have a specialized requirement.
69 64
70config MXC_TZIC 65config MXC_TZIC
71 bool "Enable TrustZone Interrupt Controller" 66 bool
72 depends on ARCH_MX51 67
73 help 68config MXC_AVIC
74 This will be automatically selected for all processors 69 bool
75 containing this interrupt controller.
76 Say N here only if you are really sure.
77 70
78config MXC_PWM 71config MXC_PWM
79 tristate "Enable PWM driver" 72 tristate "Enable PWM driver"
diff --git a/arch/arm/plat-mxc/Makefile b/arch/arm/plat-mxc/Makefile
index 372670952789..5fd20e96876c 100644
--- a/arch/arm/plat-mxc/Makefile
+++ b/arch/arm/plat-mxc/Makefile
@@ -3,10 +3,11 @@
3# 3#
4 4
5# Common support 5# Common support
6obj-y := irq.o clock.o gpio.o time.o devices.o cpu.o system.o 6obj-y := clock.o gpio.o time.o devices.o cpu.o system.o irq-common.o
7 7
8# MX51 uses the TZIC interrupt controller, older platforms use AVIC (irq.o) 8# MX51 uses the TZIC interrupt controller, older platforms use AVIC
9obj-$(CONFIG_MXC_TZIC) += tzic.o 9obj-$(CONFIG_MXC_TZIC) += tzic.o
10obj-$(CONFIG_MXC_AVIC) += avic.o
10 11
11obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o 12obj-$(CONFIG_IMX_HAVE_IOMUX_V1) += iomux-v1.o
12obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o 13obj-$(CONFIG_ARCH_MXC_IOMUX_V3) += iomux-v3.o
diff --git a/arch/arm/plat-mxc/audmux-v2.c b/arch/arm/plat-mxc/audmux-v2.c
index 0be1ac7f421b..175e3647bb27 100644
--- a/arch/arm/plat-mxc/audmux-v2.c
+++ b/arch/arm/plat-mxc/audmux-v2.c
@@ -209,7 +209,7 @@ static int mxc_audmux_v2_init(void)
209 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR); 209 audmux_base = MX35_IO_ADDRESS(MX35_AUDMUX_BASE_ADDR);
210 } 210 }
211#endif 211#endif
212#if defined(CONFIG_ARCH_MX25) 212#if defined(CONFIG_SOC_IMX25)
213 if (cpu_is_mx25()) { 213 if (cpu_is_mx25()) {
214 audmux_clk = clk_get(NULL, "audmux"); 214 audmux_clk = clk_get(NULL, "audmux");
215 if (IS_ERR(audmux_clk)) { 215 if (IS_ERR(audmux_clk)) {
@@ -220,7 +220,7 @@ static int mxc_audmux_v2_init(void)
220 } 220 }
221 audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR); 221 audmux_base = MX25_IO_ADDRESS(MX25_AUDMUX_BASE_ADDR);
222 } 222 }
223#endif 223#endif /* if defined(CONFIG_SOC_IMX25) */
224 audmux_debugfs_init(); 224 audmux_debugfs_init();
225 225
226 return 0; 226 return 0;
diff --git a/arch/arm/plat-mxc/irq.c b/arch/arm/plat-mxc/avic.c
index 7331f2ace5fe..9a4e8a22dd0a 100644
--- a/arch/arm/plat-mxc/irq.c
+++ b/arch/arm/plat-mxc/avic.c
@@ -24,6 +24,8 @@
24#include <asm/mach/irq.h> 24#include <asm/mach/irq.h>
25#include <mach/hardware.h> 25#include <mach/hardware.h>
26 26
27#include "irq-common.h"
28
27#define AVIC_INTCNTL 0x00 /* int control reg */ 29#define AVIC_INTCNTL 0x00 /* int control reg */
28#define AVIC_NIMASK 0x04 /* int mask reg */ 30#define AVIC_NIMASK 0x04 /* int mask reg */
29#define AVIC_INTENNUM 0x08 /* int enable number reg */ 31#define AVIC_INTENNUM 0x08 /* int enable number reg */
@@ -46,9 +48,9 @@
46 48
47void __iomem *avic_base; 49void __iomem *avic_base;
48 50
49int imx_irq_set_priority(unsigned char irq, unsigned char prio)
50{
51#ifdef CONFIG_MXC_IRQ_PRIOR 51#ifdef CONFIG_MXC_IRQ_PRIOR
52static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
53{
52 unsigned int temp; 54 unsigned int temp;
53 unsigned int mask = 0x0F << irq % 8 * 4; 55 unsigned int mask = 0x0F << irq % 8 * 4;
54 56
@@ -62,14 +64,11 @@ int imx_irq_set_priority(unsigned char irq, unsigned char prio)
62 __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8)); 64 __raw_writel(temp, avic_base + AVIC_NIPRIORITY(irq / 8));
63 65
64 return 0; 66 return 0;
65#else
66 return -ENOSYS;
67#endif
68} 67}
69EXPORT_SYMBOL(imx_irq_set_priority); 68#endif
70 69
71#ifdef CONFIG_FIQ 70#ifdef CONFIG_FIQ
72int mxc_set_irq_fiq(unsigned int irq, unsigned int type) 71static int avic_set_irq_fiq(unsigned int irq, unsigned int type)
73{ 72{
74 unsigned int irqt; 73 unsigned int irqt;
75 74
@@ -87,7 +86,6 @@ int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
87 86
88 return 0; 87 return 0;
89} 88}
90EXPORT_SYMBOL(mxc_set_irq_fiq);
91#endif /* CONFIG_FIQ */ 89#endif /* CONFIG_FIQ */
92 90
93/* Disable interrupt number "irq" in the AVIC */ 91/* Disable interrupt number "irq" in the AVIC */
@@ -102,10 +100,18 @@ static void mxc_unmask_irq(unsigned int irq)
102 __raw_writel(irq, avic_base + AVIC_INTENNUM); 100 __raw_writel(irq, avic_base + AVIC_INTENNUM);
103} 101}
104 102
105static struct irq_chip mxc_avic_chip = { 103static struct mxc_irq_chip mxc_avic_chip = {
106 .ack = mxc_mask_irq, 104 .base = {
107 .mask = mxc_mask_irq, 105 .ack = mxc_mask_irq,
108 .unmask = mxc_unmask_irq, 106 .mask = mxc_mask_irq,
107 .unmask = mxc_unmask_irq,
108 },
109#ifdef CONFIG_MXC_IRQ_PRIOR
110 .set_priority = avic_irq_set_priority,
111#endif
112#ifdef CONFIG_FIQ
113 .set_irq_fiq = avic_set_irq_fiq,
114#endif
109}; 115};
110 116
111/* 117/*
@@ -133,7 +139,7 @@ void __init mxc_init_irq(void __iomem *irqbase)
133 __raw_writel(0, avic_base + AVIC_INTTYPEH); 139 __raw_writel(0, avic_base + AVIC_INTTYPEH);
134 __raw_writel(0, avic_base + AVIC_INTTYPEL); 140 __raw_writel(0, avic_base + AVIC_INTTYPEL);
135 for (i = 0; i < MXC_INTERNAL_IRQS; i++) { 141 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
136 set_irq_chip(i, &mxc_avic_chip); 142 set_irq_chip(i, &mxc_avic_chip.base);
137 set_irq_handler(i, handle_level_irq); 143 set_irq_handler(i, handle_level_irq);
138 set_irq_flags(i, IRQF_VALID); 144 set_irq_flags(i, IRQF_VALID);
139 } 145 }
diff --git a/arch/arm/plat-mxc/cpufreq.c b/arch/arm/plat-mxc/cpufreq.c
index 039538e68793..ce81481becf1 100644
--- a/arch/arm/plat-mxc/cpufreq.c
+++ b/arch/arm/plat-mxc/cpufreq.c
@@ -144,7 +144,6 @@ static int __init mxc_cpufreq_init(struct cpufreq_policy *policy)
144 imx_freq_table[i].frequency = CPUFREQ_TABLE_END; 144 imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
145 145
146 policy->cur = clk_get_rate(cpu_clk) / 1000; 146 policy->cur = clk_get_rate(cpu_clk) / 1000;
147 policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
148 policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min; 147 policy->min = policy->cpuinfo.min_freq = cpu_freq_khz_min;
149 policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max; 148 policy->max = policy->cpuinfo.max_freq = cpu_freq_khz_max;
150 149
diff --git a/arch/arm/plat-mxc/devices.c b/arch/arm/plat-mxc/devices.c
index 735776d84956..e9bcefe79a43 100644
--- a/arch/arm/plat-mxc/devices.c
+++ b/arch/arm/plat-mxc/devices.c
@@ -17,6 +17,7 @@
17 */ 17 */
18 18
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/slab.h>
20#include <linux/init.h> 21#include <linux/init.h>
21#include <linux/err.h> 22#include <linux/err.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
@@ -36,9 +37,10 @@ int __init mxc_register_device(struct platform_device *pdev, void *data)
36 return ret; 37 return ret;
37} 38}
38 39
39struct platform_device *__init imx_add_platform_device(const char *name, int id, 40struct platform_device *__init imx_add_platform_device_dmamask(
41 const char *name, int id,
40 const struct resource *res, unsigned int num_resources, 42 const struct resource *res, unsigned int num_resources,
41 const void *data, size_t size_data) 43 const void *data, size_t size_data, u64 dmamask)
42{ 44{
43 int ret = -ENOMEM; 45 int ret = -ENOMEM;
44 struct platform_device *pdev; 46 struct platform_device *pdev;
@@ -47,6 +49,23 @@ struct platform_device *__init imx_add_platform_device(const char *name, int id,
47 if (!pdev) 49 if (!pdev)
48 goto err; 50 goto err;
49 51
52 if (dmamask) {
53 /*
54 * This memory isn't freed when the device is put,
55 * I don't have a nice idea for that though. Conceptually
56 * dma_mask in struct device should not be a pointer.
57 * See http://thread.gmane.org/gmane.linux.kernel.pci/9081
58 */
59 pdev->dev.dma_mask =
60 kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
61 if (!pdev->dev.dma_mask)
62 /* ret is still -ENOMEM; */
63 goto err;
64
65 *pdev->dev.dma_mask = dmamask;
66 pdev->dev.coherent_dma_mask = dmamask;
67 }
68
50 if (res) { 69 if (res) {
51 ret = platform_device_add_resources(pdev, res, num_resources); 70 ret = platform_device_add_resources(pdev, res, num_resources);
52 if (ret) 71 if (ret)
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index 9aa6f3ea9012..2537166468ac 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -1,29 +1,73 @@
1config IMX_HAVE_PLATFORM_ESDHC
2 bool
3
4config IMX_HAVE_PLATFORM_FEC 1config IMX_HAVE_PLATFORM_FEC
5 bool 2 bool
6 default y if ARCH_MX25 || SOC_IMX27 || ARCH_MX35 || ARCH_MX51 3 default y if ARCH_MX25 || SOC_IMX27 || SOC_IMX35 || SOC_IMX51
7 4
8config IMX_HAVE_PLATFORM_FLEXCAN 5config IMX_HAVE_PLATFORM_FLEXCAN
9 select HAVE_CAN_FLEXCAN if CAN 6 select HAVE_CAN_FLEXCAN if CAN
10 bool 7 bool
11 8
9config IMX_HAVE_PLATFORM_FSL_USB2_UDC
10 bool
11
12config IMX_HAVE_PLATFORM_GPIO_KEYS 12config IMX_HAVE_PLATFORM_GPIO_KEYS
13 bool 13 bool
14 default y if ARCH_MX51 14 default y if SOC_IMX51
15
16config IMX_HAVE_PLATFORM_IMX21_HCD
17 bool
15 18
19config IMX_HAVE_PLATFORM_IMX2_WDT
20 bool
21
22config IMX_HAVE_PLATFORM_IMXDI_RTC
23 bool
24
25config IMX_HAVE_PLATFORM_IMX_FB
26 bool
27 select HAVE_FB_IMX
28
16config IMX_HAVE_PLATFORM_IMX_I2C 29config IMX_HAVE_PLATFORM_IMX_I2C
17 bool 30 bool
18 31
32config IMX_HAVE_PLATFORM_IMX_KEYPAD
33 bool
34
19config IMX_HAVE_PLATFORM_IMX_SSI 35config IMX_HAVE_PLATFORM_IMX_SSI
20 bool 36 bool
21 37
22config IMX_HAVE_PLATFORM_IMX_UART 38config IMX_HAVE_PLATFORM_IMX_UART
23 bool 39 bool
24 40
41config IMX_HAVE_PLATFORM_IMX_UDC
42 bool
43
44config IMX_HAVE_PLATFORM_MX1_CAMERA
45 bool
46
47config IMX_HAVE_PLATFORM_MX2_CAMERA
48 bool
49
50config IMX_HAVE_PLATFORM_MXC_EHCI
51 bool
52
53config IMX_HAVE_PLATFORM_MXC_MMC
54 bool
55
25config IMX_HAVE_PLATFORM_MXC_NAND 56config IMX_HAVE_PLATFORM_MXC_NAND
26 bool 57 bool
27 58
59config IMX_HAVE_PLATFORM_MXC_PWM
60 bool
61
62config IMX_HAVE_PLATFORM_MXC_RNGA
63 bool
64 select ARCH_HAS_RNGA
65
66config IMX_HAVE_PLATFORM_MXC_W1
67 bool
68
69config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
70 bool
71
28config IMX_HAVE_PLATFORM_SPI_IMX 72config IMX_HAVE_PLATFORM_SPI_IMX
29 bool 73 bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 45aefeb283ba..75cd2ece9053 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -1,10 +1,24 @@
1obj-$(CONFIG_IMX_HAVE_PLATFORM_ESDHC) += platform-esdhc.o
2obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o 1obj-$(CONFIG_IMX_HAVE_PLATFORM_FEC) += platform-fec.o
3obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o 2obj-$(CONFIG_IMX_HAVE_PLATFORM_FLEXCAN) += platform-flexcan.o
3obj-$(CONFIG_IMX_HAVE_PLATFORM_FSL_USB2_UDC) += platform-fsl-usb2-udc.o
4obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o 4obj-$(CONFIG_IMX_HAVE_PLATFORM_GPIO_KEYS) += platform-gpio_keys.o
5obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX21_HCD) += platform-imx21-hcd.o
6obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX2_WDT) += platform-imx2-wdt.o
7obj-$(CONFIG_IMX_HAVE_PLATFORM_IMXDI_RTC) += platform-imxdi_rtc.o
5obj-y += platform-imx-dma.o 8obj-y += platform-imx-dma.o
9obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_FB) += platform-imx-fb.o
6obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o 10obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_I2C) += platform-imx-i2c.o
11obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_KEYPAD) += platform-imx-keypad.o
7obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o 12obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
8obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o 13obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
14obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
15obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
16obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
17obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
18obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_MMC) += platform-mxc-mmc.o
9obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o 19obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
20obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
21obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
22obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
23obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
10obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o 24obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-esdhc.c b/arch/arm/plat-mxc/devices/platform-esdhc.c
deleted file mode 100644
index 2605bfa0dfb0..000000000000
--- a/arch/arm/plat-mxc/devices/platform-esdhc.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/*
2 * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11#include <mach/esdhc.h>
12
13#define imx_esdhc_imx_data_entry_single(soc, _id, hwid) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \
17 .irq = soc ## _INT_ESDHC ## hwid, \
18 }
19
20#define imx_esdhc_imx_data_entry(soc, id, hwid) \
21 [id] = imx_esdhc_imx_data_entry_single(soc, id, hwid)
22
23#ifdef CONFIG_ARCH_MX25
24const struct imx_esdhc_imx_data imx25_esdhc_data[] __initconst = {
25#define imx25_esdhc_data_entry(_id, _hwid) \
26 imx_esdhc_imx_data_entry(MX25, _id, _hwid)
27 imx25_esdhc_data_entry(0, 1),
28 imx25_esdhc_data_entry(1, 2),
29};
30#endif /* ifdef CONFIG_ARCH_MX25 */
31
32#ifdef CONFIG_ARCH_MX35
33const struct imx_esdhc_imx_data imx35_esdhc_data[] __initconst = {
34#define imx35_esdhc_data_entry(_id, _hwid) \
35 imx_esdhc_imx_data_entry(MX35, _id, _hwid)
36 imx35_esdhc_data_entry(0, 1),
37 imx35_esdhc_data_entry(1, 2),
38 imx35_esdhc_data_entry(2, 3),
39};
40#endif /* ifdef CONFIG_ARCH_MX35 */
41
42#ifdef CONFIG_ARCH_MX51
43const struct imx_esdhc_imx_data imx51_esdhc_data[] __initconst = {
44#define imx51_esdhc_data_entry(_id, _hwid) \
45 imx_esdhc_imx_data_entry(MX51, _id, _hwid)
46 imx51_esdhc_data_entry(0, 1),
47 imx51_esdhc_data_entry(1, 2),
48 imx51_esdhc_data_entry(2, 3),
49 imx51_esdhc_data_entry(3, 4),
50};
51#endif /* ifdef CONFIG_ARCH_MX51 */
52
53struct platform_device *__init imx_add_esdhc(
54 const struct imx_esdhc_imx_data *data,
55 const struct esdhc_platform_data *pdata)
56{
57 struct resource res[] = {
58 {
59 .start = data->iobase,
60 .end = data->iobase + SZ_16K - 1,
61 .flags = IORESOURCE_MEM,
62 }, {
63 .start = data->irq,
64 .end = data->irq,
65 .flags = IORESOURCE_IRQ,
66 },
67 };
68
69 return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
70 ARRAY_SIZE(res), pdata, sizeof(*pdata));
71}
diff --git a/arch/arm/plat-mxc/devices/platform-fec.c b/arch/arm/plat-mxc/devices/platform-fec.c
index 11d087f4e219..269ec78aba77 100644
--- a/arch/arm/plat-mxc/devices/platform-fec.c
+++ b/arch/arm/plat-mxc/devices/platform-fec.c
@@ -16,22 +16,22 @@
16 .irq = soc ## _INT_FEC, \ 16 .irq = soc ## _INT_FEC, \
17 } 17 }
18 18
19#ifdef CONFIG_ARCH_MX25 19#ifdef CONFIG_SOC_IMX25
20const struct imx_fec_data imx25_fec_data __initconst = 20const struct imx_fec_data imx25_fec_data __initconst =
21 imx_fec_data_entry_single(MX25); 21 imx_fec_data_entry_single(MX25);
22#endif /* ifdef CONFIG_ARCH_MX25 */ 22#endif /* ifdef CONFIG_SOC_IMX25 */
23 23
24#ifdef CONFIG_SOC_IMX27 24#ifdef CONFIG_SOC_IMX27
25const struct imx_fec_data imx27_fec_data __initconst = 25const struct imx_fec_data imx27_fec_data __initconst =
26 imx_fec_data_entry_single(MX27); 26 imx_fec_data_entry_single(MX27);
27#endif /* ifdef CONFIG_SOC_IMX27 */ 27#endif /* ifdef CONFIG_SOC_IMX27 */
28 28
29#ifdef CONFIG_ARCH_MX35 29#ifdef CONFIG_SOC_IMX35
30const struct imx_fec_data imx35_fec_data __initconst = 30const struct imx_fec_data imx35_fec_data __initconst =
31 imx_fec_data_entry_single(MX35); 31 imx_fec_data_entry_single(MX35);
32#endif 32#endif
33 33
34#ifdef CONFIG_ARCH_MX51 34#ifdef CONFIG_SOC_IMX51
35const struct imx_fec_data imx51_fec_data __initconst = 35const struct imx_fec_data imx51_fec_data __initconst =
36 imx_fec_data_entry_single(MX51); 36 imx_fec_data_entry_single(MX51);
37#endif 37#endif
diff --git a/arch/arm/plat-mxc/devices/platform-flexcan.c b/arch/arm/plat-mxc/devices/platform-flexcan.c
index 5e97a01f14f3..4e8497af2eb1 100644
--- a/arch/arm/plat-mxc/devices/platform-flexcan.c
+++ b/arch/arm/plat-mxc/devices/platform-flexcan.c
@@ -5,26 +5,54 @@
5 * the terms of the GNU General Public License version 2 as published by the 5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation. 6 * Free Software Foundation.
7 */ 7 */
8 8#include <mach/hardware.h>
9#include <mach/devices-common.h> 9#include <mach/devices-common.h>
10 10
11struct platform_device *__init imx_add_flexcan(int id, 11#define imx_flexcan_data_entry_single(soc, _id, _hwid, _size) \
12 resource_size_t iobase, resource_size_t iosize, 12 { \
13 resource_size_t irq, 13 .id = _id, \
14 .iobase = soc ## _CAN ## _hwid ## _BASE_ADDR, \
15 .iosize = _size, \
16 .irq = soc ## _INT_CAN ## _hwid, \
17 }
18
19#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \
20 [_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size)
21
22#ifdef CONFIG_SOC_IMX25
23const struct imx_flexcan_data imx25_flexcan_data[] __initconst = {
24#define imx25_flexcan_data_entry(_id, _hwid) \
25 imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K)
26 imx25_flexcan_data_entry(0, 1),
27 imx25_flexcan_data_entry(1, 2),
28};
29#endif /* ifdef CONFIG_SOC_IMX25 */
30
31#ifdef CONFIG_SOC_IMX35
32const struct imx_flexcan_data imx35_flexcan_data[] __initconst = {
33#define imx35_flexcan_data_entry(_id, _hwid) \
34 imx_flexcan_data_entry(MX35, _id, _hwid, SZ_16K)
35 imx35_flexcan_data_entry(0, 1),
36 imx35_flexcan_data_entry(1, 2),
37};
38#endif /* ifdef CONFIG_SOC_IMX35 */
39
40struct platform_device *__init imx_add_flexcan(
41 const struct imx_flexcan_data *data,
14 const struct flexcan_platform_data *pdata) 42 const struct flexcan_platform_data *pdata)
15{ 43{
16 struct resource res[] = { 44 struct resource res[] = {
17 { 45 {
18 .start = iobase, 46 .start = data->iobase,
19 .end = iobase + iosize - 1, 47 .end = data->iobase + data->iosize - 1,
20 .flags = IORESOURCE_MEM, 48 .flags = IORESOURCE_MEM,
21 }, { 49 }, {
22 .start = irq, 50 .start = data->irq,
23 .end = irq, 51 .end = data->irq,
24 .flags = IORESOURCE_IRQ, 52 .flags = IORESOURCE_IRQ,
25 }, 53 },
26 }; 54 };
27 55
28 return imx_add_platform_device("flexcan", id, res, ARRAY_SIZE(res), 56 return imx_add_platform_device("flexcan", data->id,
29 pdata, sizeof(*pdata)); 57 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
30} 58}
diff --git a/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
new file mode 100644
index 000000000000..59c33f6e401c
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-fsl-usb2-udc.c
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_fsl_usb2_udc_data_entry_single(soc) \
13 { \
14 .iobase = soc ## _USB_OTG_BASE_ADDR, \
15 .irq = soc ## _INT_USB_OTG, \
16 }
17
18#ifdef CONFIG_SOC_IMX25
19const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst =
20 imx_fsl_usb2_udc_data_entry_single(MX25);
21#endif /* ifdef CONFIG_SOC_IMX25 */
22
23#ifdef CONFIG_SOC_IMX27
24const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst =
25 imx_fsl_usb2_udc_data_entry_single(MX27);
26#endif /* ifdef CONFIG_SOC_IMX27 */
27
28#ifdef CONFIG_SOC_IMX31
29const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst =
30 imx_fsl_usb2_udc_data_entry_single(MX31);
31#endif /* ifdef CONFIG_SOC_IMX31 */
32
33#ifdef CONFIG_SOC_IMX35
34const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst =
35 imx_fsl_usb2_udc_data_entry_single(MX35);
36#endif /* ifdef CONFIG_SOC_IMX35 */
37
38struct platform_device *__init imx_add_fsl_usb2_udc(
39 const struct imx_fsl_usb2_udc_data *data,
40 const struct fsl_usb2_platform_data *pdata)
41{
42 struct resource res[] = {
43 {
44 .start = data->iobase,
45 .end = data->iobase + SZ_512 - 1,
46 .flags = IORESOURCE_MEM,
47 }, {
48 .start = data->irq,
49 .end = data->irq,
50 .flags = IORESOURCE_IRQ,
51 },
52 };
53 return imx_add_platform_device_dmamask("fsl-usb2-udc", -1,
54 res, ARRAY_SIZE(res),
55 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
56}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-dma.c b/arch/arm/plat-mxc/devices/platform-imx-dma.c
index 3a705c7877dd..33530d2d5ed1 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-dma.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-dma.c
@@ -31,25 +31,25 @@ struct imx_imx_sdma_data {
31 }, \ 31 }, \
32 } 32 }
33 33
34#ifdef CONFIG_ARCH_MX25 34#ifdef CONFIG_SOC_IMX25
35const struct imx_imx_sdma_data imx25_imx_sdma_data __initconst = 35struct imx_imx_sdma_data imx25_imx_sdma_data __initconst =
36 imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0); 36 imx_imx_sdma_data_entry_single(MX25, 1, "imx25", 0);
37#endif /* ifdef CONFIG_ARCH_MX25 */ 37#endif /* ifdef CONFIG_SOC_IMX25 */
38 38
39#ifdef CONFIG_ARCH_MX31 39#ifdef CONFIG_SOC_IMX31
40struct imx_imx_sdma_data imx31_imx_sdma_data __initdata = 40struct imx_imx_sdma_data imx31_imx_sdma_data __initdata =
41 imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0); 41 imx_imx_sdma_data_entry_single(MX31, 1, "imx31", 0);
42#endif /* ifdef CONFIG_ARCH_MX31 */ 42#endif /* ifdef CONFIG_SOC_IMX31 */
43 43
44#ifdef CONFIG_ARCH_MX35 44#ifdef CONFIG_SOC_IMX35
45struct imx_imx_sdma_data imx35_imx_sdma_data __initdata = 45struct imx_imx_sdma_data imx35_imx_sdma_data __initdata =
46 imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0); 46 imx_imx_sdma_data_entry_single(MX35, 2, "imx35", 0);
47#endif /* ifdef CONFIG_ARCH_MX35 */ 47#endif /* ifdef CONFIG_SOC_IMX35 */
48 48
49#ifdef CONFIG_ARCH_MX51 49#ifdef CONFIG_SOC_IMX51
50const struct imx_imx_sdma_data imx51_imx_sdma_data __initconst = 50struct imx_imx_sdma_data imx51_imx_sdma_data __initconst =
51 imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0); 51 imx_imx_sdma_data_entry_single(MX51, 2, "imx51", 0);
52#endif /* ifdef CONFIG_ARCH_MX51 */ 52#endif /* ifdef CONFIG_SOC_IMX51 */
53 53
54static struct platform_device __init __maybe_unused *imx_add_imx_sdma( 54static struct platform_device __init __maybe_unused *imx_add_imx_sdma(
55 const struct imx_imx_sdma_data *data) 55 const struct imx_imx_sdma_data *data)
@@ -76,6 +76,83 @@ static struct platform_device __init __maybe_unused *imx_add_imx_dma(void)
76 return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0); 76 return imx_add_platform_device("imx-dma", -1, NULL, 0, NULL, 0);
77} 77}
78 78
79#ifdef CONFIG_ARCH_MX25
80static struct sdma_script_start_addrs addr_imx25_to1 = {
81 .ap_2_ap_addr = 729,
82 .uart_2_mcu_addr = 904,
83 .per_2_app_addr = 1255,
84 .mcu_2_app_addr = 834,
85 .uartsh_2_mcu_addr = 1120,
86 .per_2_shp_addr = 1329,
87 .mcu_2_shp_addr = 1048,
88 .ata_2_mcu_addr = 1560,
89 .mcu_2_ata_addr = 1479,
90 .app_2_per_addr = 1189,
91 .app_2_mcu_addr = 770,
92 .shp_2_per_addr = 1407,
93 .shp_2_mcu_addr = 979,
94};
95#endif
96
97#ifdef CONFIG_ARCH_MX31
98static struct sdma_script_start_addrs addr_imx31_to1 = {
99 .per_2_per_addr = 1677,
100};
101
102static struct sdma_script_start_addrs addr_imx31_to2 = {
103 .ap_2_ap_addr = 423,
104 .ap_2_bp_addr = 829,
105 .bp_2_ap_addr = 1029,
106};
107#endif
108
109#ifdef CONFIG_ARCH_MX35
110static struct sdma_script_start_addrs addr_imx35_to1 = {
111 .ap_2_ap_addr = 642,
112 .uart_2_mcu_addr = 817,
113 .mcu_2_app_addr = 747,
114 .uartsh_2_mcu_addr = 1183,
115 .per_2_shp_addr = 1033,
116 .mcu_2_shp_addr = 961,
117 .ata_2_mcu_addr = 1333,
118 .mcu_2_ata_addr = 1252,
119 .app_2_mcu_addr = 683,
120 .shp_2_per_addr = 1111,
121 .shp_2_mcu_addr = 892,
122};
123
124static struct sdma_script_start_addrs addr_imx35_to2 = {
125 .ap_2_ap_addr = 729,
126 .uart_2_mcu_addr = 904,
127 .per_2_app_addr = 1597,
128 .mcu_2_app_addr = 834,
129 .uartsh_2_mcu_addr = 1270,
130 .per_2_shp_addr = 1120,
131 .mcu_2_shp_addr = 1048,
132 .ata_2_mcu_addr = 1429,
133 .mcu_2_ata_addr = 1339,
134 .app_2_per_addr = 1531,
135 .app_2_mcu_addr = 770,
136 .shp_2_per_addr = 1198,
137 .shp_2_mcu_addr = 979,
138};
139#endif
140
141#ifdef CONFIG_SOC_IMX51
142static struct sdma_script_start_addrs addr_imx51_to1 = {
143 .ap_2_ap_addr = 642,
144 .uart_2_mcu_addr = 817,
145 .mcu_2_app_addr = 747,
146 .mcu_2_shp_addr = 961,
147 .ata_2_mcu_addr = 1473,
148 .mcu_2_ata_addr = 1392,
149 .app_2_per_addr = 1033,
150 .app_2_mcu_addr = 683,
151 .shp_2_per_addr = 1251,
152 .shp_2_mcu_addr = 892,
153};
154#endif
155
79static int __init imxXX_add_imx_dma(void) 156static int __init imxXX_add_imx_dma(void)
80{ 157{
81 struct platform_device *ret; 158 struct platform_device *ret;
@@ -86,30 +163,42 @@ static int __init imxXX_add_imx_dma(void)
86 else 163 else
87#endif 164#endif
88 165
89#if defined(CONFIG_ARCH_MX25) 166#if defined(CONFIG_SOC_IMX25)
90 if (cpu_is_mx25()) 167 if (cpu_is_mx25()) {
168 imx25_imx_sdma_data.pdata.script_addrs = &addr_imx25_to1;
91 ret = imx_add_imx_sdma(&imx25_imx_sdma_data); 169 ret = imx_add_imx_sdma(&imx25_imx_sdma_data);
92 else 170 } else
93#endif 171#endif
94 172
95#if defined(CONFIG_ARCH_MX31) 173#if defined(CONFIG_SOC_IMX31)
96 if (cpu_is_mx31()) { 174 if (cpu_is_mx31()) {
97 imx31_imx_sdma_data.pdata.to_version = mx31_revision() >> 4; 175 int to_version = mx31_revision() >> 4;
176 imx31_imx_sdma_data.pdata.to_version = to_version;
177 if (to_version == 1)
178 imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to1;
179 else
180 imx31_imx_sdma_data.pdata.script_addrs = &addr_imx31_to2;
98 ret = imx_add_imx_sdma(&imx31_imx_sdma_data); 181 ret = imx_add_imx_sdma(&imx31_imx_sdma_data);
99 } else 182 } else
100#endif 183#endif
101 184
102#if defined(CONFIG_ARCH_MX35) 185#if defined(CONFIG_SOC_IMX35)
103 if (cpu_is_mx35()) { 186 if (cpu_is_mx35()) {
104 imx35_imx_sdma_data.pdata.to_version = mx35_revision() >> 4; 187 int to_version = mx35_revision() >> 4;
188 imx35_imx_sdma_data.pdata.to_version = to_version;
189 if (to_version == 1)
190 imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to1;
191 else
192 imx35_imx_sdma_data.pdata.script_addrs = &addr_imx35_to2;
105 ret = imx_add_imx_sdma(&imx35_imx_sdma_data); 193 ret = imx_add_imx_sdma(&imx35_imx_sdma_data);
106 } else 194 } else
107#endif 195#endif
108 196
109#if defined(CONFIG_ARCH_MX51) 197#if defined(CONFIG_ARCH_MX51)
110 if (cpu_is_mx51()) 198 if (cpu_is_mx51()) {
199 imx51_imx_sdma_data.pdata.script_addrs = &addr_imx51_to1;
111 ret = imx_add_imx_sdma(&imx51_imx_sdma_data); 200 ret = imx_add_imx_sdma(&imx51_imx_sdma_data);
112 else 201 } else
113#endif 202#endif
114 ret = ERR_PTR(-ENODEV); 203 ret = ERR_PTR(-ENODEV);
115 204
diff --git a/arch/arm/plat-mxc/devices/platform-imx-fb.c b/arch/arm/plat-mxc/devices/platform-imx-fb.c
new file mode 100644
index 000000000000..6100a7d824dd
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-fb.c
@@ -0,0 +1,52 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_imx_fb_data_entry_single(soc, _size) \
13 { \
14 .iobase = soc ## _LCDC_BASE_ADDR, \
15 .iosize = _size, \
16 .irq = soc ## _INT_LCDC, \
17 }
18
19#ifdef CONFIG_SOC_IMX21
20const struct imx_imx_fb_data imx21_imx_fb_data __initconst =
21 imx_imx_fb_data_entry_single(MX21, SZ_4K);
22#endif /* ifdef CONFIG_SOC_IMX21 */
23
24#ifdef CONFIG_SOC_IMX25
25const struct imx_imx_fb_data imx25_imx_fb_data __initconst =
26 imx_imx_fb_data_entry_single(MX25, SZ_16K);
27#endif /* ifdef CONFIG_SOC_IMX25 */
28
29#ifdef CONFIG_SOC_IMX27
30const struct imx_imx_fb_data imx27_imx_fb_data __initconst =
31 imx_imx_fb_data_entry_single(MX27, SZ_4K);
32#endif /* ifdef CONFIG_SOC_IMX27 */
33
34struct platform_device *__init imx_add_imx_fb(
35 const struct imx_imx_fb_data *data,
36 const struct imx_fb_platform_data *pdata)
37{
38 struct resource res[] = {
39 {
40 .start = data->iobase,
41 .end = data->iobase + data->iosize - 1,
42 .flags = IORESOURCE_MEM,
43 }, {
44 .start = data->irq,
45 .end = data->irq,
46 .flags = IORESOURCE_IRQ,
47 },
48 };
49 return imx_add_platform_device_dmamask("imx-fb", 0,
50 res, ARRAY_SIZE(res),
51 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
52}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-i2c.c b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
index 679588453aad..72ba880c75af 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-i2c.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-i2c.c
@@ -30,7 +30,7 @@ const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst =
30 imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K); 30 imx_imx_i2c_data_entry_single(MX21, 0, , SZ_4K);
31#endif /* ifdef CONFIG_SOC_IMX21 */ 31#endif /* ifdef CONFIG_SOC_IMX21 */
32 32
33#ifdef CONFIG_ARCH_MX25 33#ifdef CONFIG_SOC_IMX25
34const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = { 34const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
35#define imx25_imx_i2c_data_entry(_id, _hwid) \ 35#define imx25_imx_i2c_data_entry(_id, _hwid) \
36 imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K) 36 imx_imx_i2c_data_entry(MX25, _id, _hwid, SZ_16K)
@@ -38,7 +38,7 @@ const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst = {
38 imx25_imx_i2c_data_entry(1, 2), 38 imx25_imx_i2c_data_entry(1, 2),
39 imx25_imx_i2c_data_entry(2, 3), 39 imx25_imx_i2c_data_entry(2, 3),
40}; 40};
41#endif /* ifdef CONFIG_ARCH_MX25 */ 41#endif /* ifdef CONFIG_SOC_IMX25 */
42 42
43#ifdef CONFIG_SOC_IMX27 43#ifdef CONFIG_SOC_IMX27
44const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = { 44const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
@@ -49,7 +49,7 @@ const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst = {
49}; 49};
50#endif /* ifdef CONFIG_SOC_IMX27 */ 50#endif /* ifdef CONFIG_SOC_IMX27 */
51 51
52#ifdef CONFIG_ARCH_MX31 52#ifdef CONFIG_SOC_IMX31
53const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = { 53const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
54#define imx31_imx_i2c_data_entry(_id, _hwid) \ 54#define imx31_imx_i2c_data_entry(_id, _hwid) \
55 imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K) 55 imx_imx_i2c_data_entry(MX31, _id, _hwid, SZ_4K)
@@ -57,9 +57,9 @@ const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst = {
57 imx31_imx_i2c_data_entry(1, 2), 57 imx31_imx_i2c_data_entry(1, 2),
58 imx31_imx_i2c_data_entry(2, 3), 58 imx31_imx_i2c_data_entry(2, 3),
59}; 59};
60#endif /* ifdef CONFIG_ARCH_MX31 */ 60#endif /* ifdef CONFIG_SOC_IMX31 */
61 61
62#ifdef CONFIG_ARCH_MX35 62#ifdef CONFIG_SOC_IMX35
63const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = { 63const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
64#define imx35_imx_i2c_data_entry(_id, _hwid) \ 64#define imx35_imx_i2c_data_entry(_id, _hwid) \
65 imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K) 65 imx_imx_i2c_data_entry(MX35, _id, _hwid, SZ_4K)
@@ -67,16 +67,16 @@ const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst = {
67 imx35_imx_i2c_data_entry(1, 2), 67 imx35_imx_i2c_data_entry(1, 2),
68 imx35_imx_i2c_data_entry(2, 3), 68 imx35_imx_i2c_data_entry(2, 3),
69}; 69};
70#endif /* ifdef CONFIG_ARCH_MX35 */ 70#endif /* ifdef CONFIG_SOC_IMX35 */
71 71
72#ifdef CONFIG_ARCH_MX51 72#ifdef CONFIG_SOC_IMX51
73const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = { 73const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst = {
74#define imx51_imx_i2c_data_entry(_id, _hwid) \ 74#define imx51_imx_i2c_data_entry(_id, _hwid) \
75 imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K) 75 imx_imx_i2c_data_entry(MX51, _id, _hwid, SZ_4K)
76 imx51_imx_i2c_data_entry(0, 1), 76 imx51_imx_i2c_data_entry(0, 1),
77 imx51_imx_i2c_data_entry(1, 2), 77 imx51_imx_i2c_data_entry(1, 2),
78}; 78};
79#endif /* ifdef CONFIG_ARCH_MX51 */ 79#endif /* ifdef CONFIG_SOC_IMX51 */
80 80
81struct platform_device *__init imx_add_imx_i2c( 81struct platform_device *__init imx_add_imx_i2c(
82 const struct imx_imx_i2c_data *data, 82 const struct imx_imx_i2c_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx-keypad.c b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
new file mode 100644
index 000000000000..40238f0b8643
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx-keypad.c
@@ -0,0 +1,62 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_imx_keypad_data_entry_single(soc, _size) \
13 { \
14 .iobase = soc ## _KPP_BASE_ADDR, \
15 .iosize = _size, \
16 .irq = soc ## _INT_KPP, \
17 }
18
19#ifdef CONFIG_SOC_IMX21
20const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst =
21 imx_imx_keypad_data_entry_single(MX21, SZ_16);
22#endif /* ifdef CONFIG_SOC_IMX21 */
23
24#ifdef CONFIG_SOC_IMX25
25const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst =
26 imx_imx_keypad_data_entry_single(MX25, SZ_16K);
27#endif /* ifdef CONFIG_SOC_IMX25 */
28
29#ifdef CONFIG_SOC_IMX27
30const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst =
31 imx_imx_keypad_data_entry_single(MX27, SZ_16);
32#endif /* ifdef CONFIG_SOC_IMX27 */
33
34#ifdef CONFIG_SOC_IMX31
35const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst =
36 imx_imx_keypad_data_entry_single(MX31, SZ_16);
37#endif /* ifdef CONFIG_SOC_IMX31 */
38
39#ifdef CONFIG_SOC_IMX35
40const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst =
41 imx_imx_keypad_data_entry_single(MX35, SZ_16);
42#endif /* ifdef CONFIG_SOC_IMX35 */
43
44struct platform_device *__init imx_add_imx_keypad(
45 const struct imx_imx_keypad_data *data,
46 const struct matrix_keymap_data *pdata)
47{
48 struct resource res[] = {
49 {
50 .start = data->iobase,
51 .end = data->iobase + data->iosize - 1,
52 .flags = IORESOURCE_MEM,
53 }, {
54 .start = data->irq,
55 .end = data->irq,
56 .flags = IORESOURCE_IRQ,
57 },
58 };
59
60 return imx_add_platform_device("imx-keypad", -1,
61 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
62}
diff --git a/arch/arm/plat-mxc/devices/platform-imx-ssi.c b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
index 38a7a0b8f2f1..2569c8d8a2ef 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-ssi.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-ssi.c
@@ -30,14 +30,14 @@ const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst = {
30}; 30};
31#endif /* ifdef CONFIG_SOC_IMX21 */ 31#endif /* ifdef CONFIG_SOC_IMX21 */
32 32
33#ifdef CONFIG_ARCH_MX25 33#ifdef CONFIG_SOC_IMX25
34const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = { 34const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst = {
35#define imx25_imx_ssi_data_entry(_id, _hwid) \ 35#define imx25_imx_ssi_data_entry(_id, _hwid) \
36 imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K) 36 imx_imx_ssi_data_entry(MX25, _id, _hwid, SZ_4K)
37 imx25_imx_ssi_data_entry(0, 1), 37 imx25_imx_ssi_data_entry(0, 1),
38 imx25_imx_ssi_data_entry(1, 2), 38 imx25_imx_ssi_data_entry(1, 2),
39}; 39};
40#endif /* ifdef CONFIG_ARCH_MX25 */ 40#endif /* ifdef CONFIG_SOC_IMX25 */
41 41
42#ifdef CONFIG_SOC_IMX27 42#ifdef CONFIG_SOC_IMX27
43const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = { 43const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
@@ -48,32 +48,33 @@ const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst = {
48}; 48};
49#endif /* ifdef CONFIG_SOC_IMX27 */ 49#endif /* ifdef CONFIG_SOC_IMX27 */
50 50
51#ifdef CONFIG_ARCH_MX31 51#ifdef CONFIG_SOC_IMX31
52const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = { 52const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst = {
53#define imx31_imx_ssi_data_entry(_id, _hwid) \ 53#define imx31_imx_ssi_data_entry(_id, _hwid) \
54 imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K) 54 imx_imx_ssi_data_entry(MX31, _id, _hwid, SZ_4K)
55 imx31_imx_ssi_data_entry(0, 1), 55 imx31_imx_ssi_data_entry(0, 1),
56 imx31_imx_ssi_data_entry(1, 2), 56 imx31_imx_ssi_data_entry(1, 2),
57}; 57};
58#endif /* ifdef CONFIG_ARCH_MX31 */ 58#endif /* ifdef CONFIG_SOC_IMX31 */
59 59
60#ifdef CONFIG_ARCH_MX35 60#ifdef CONFIG_SOC_IMX35
61const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = { 61const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst = {
62#define imx35_imx_ssi_data_entry(_id, _hwid) \ 62#define imx35_imx_ssi_data_entry(_id, _hwid) \
63 imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K) 63 imx_imx_ssi_data_entry(MX35, _id, _hwid, SZ_4K)
64 imx35_imx_ssi_data_entry(0, 1), 64 imx35_imx_ssi_data_entry(0, 1),
65 imx35_imx_ssi_data_entry(1, 2), 65 imx35_imx_ssi_data_entry(1, 2),
66}; 66};
67#endif /* ifdef CONFIG_ARCH_MX35 */ 67#endif /* ifdef CONFIG_SOC_IMX35 */
68 68
69#ifdef CONFIG_ARCH_MX51 69#ifdef CONFIG_SOC_IMX51
70const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = { 70const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst = {
71#define imx51_imx_ssi_data_entry(_id, _hwid) \ 71#define imx51_imx_ssi_data_entry(_id, _hwid) \
72 imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K) 72 imx_imx_ssi_data_entry(MX51, _id, _hwid, SZ_4K)
73 imx51_imx_ssi_data_entry(0, 1), 73 imx51_imx_ssi_data_entry(0, 1),
74 imx51_imx_ssi_data_entry(1, 2), 74 imx51_imx_ssi_data_entry(1, 2),
75 imx51_imx_ssi_data_entry(2, 3),
75}; 76};
76#endif /* ifdef CONFIG_ARCH_MX51 */ 77#endif /* ifdef CONFIG_SOC_IMX51 */
77 78
78struct platform_device *__init imx_add_imx_ssi( 79struct platform_device *__init imx_add_imx_ssi(
79 const struct imx_imx_ssi_data *data, 80 const struct imx_imx_ssi_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx-uart.c b/arch/arm/plat-mxc/devices/platform-imx-uart.c
index 2039640adf27..3c854c2cc6dd 100644
--- a/arch/arm/plat-mxc/devices/platform-imx-uart.c
+++ b/arch/arm/plat-mxc/devices/platform-imx-uart.c
@@ -47,7 +47,7 @@ const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst = {
47}; 47};
48#endif 48#endif
49 49
50#ifdef CONFIG_ARCH_MX25 50#ifdef CONFIG_SOC_IMX25
51const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = { 51const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
52#define imx25_imx_uart_data_entry(_id, _hwid) \ 52#define imx25_imx_uart_data_entry(_id, _hwid) \
53 imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K) 53 imx_imx_uart_1irq_data_entry(MX25, _id, _hwid, SZ_16K)
@@ -57,7 +57,7 @@ const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst = {
57 imx25_imx_uart_data_entry(3, 4), 57 imx25_imx_uart_data_entry(3, 4),
58 imx25_imx_uart_data_entry(4, 5), 58 imx25_imx_uart_data_entry(4, 5),
59}; 59};
60#endif /* ifdef CONFIG_ARCH_MX25 */ 60#endif /* ifdef CONFIG_SOC_IMX25 */
61 61
62#ifdef CONFIG_SOC_IMX27 62#ifdef CONFIG_SOC_IMX27
63const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = { 63const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
@@ -72,7 +72,7 @@ const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst = {
72}; 72};
73#endif /* ifdef CONFIG_SOC_IMX27 */ 73#endif /* ifdef CONFIG_SOC_IMX27 */
74 74
75#ifdef CONFIG_ARCH_MX31 75#ifdef CONFIG_SOC_IMX31
76const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = { 76const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
77#define imx31_imx_uart_data_entry(_id, _hwid) \ 77#define imx31_imx_uart_data_entry(_id, _hwid) \
78 imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K) 78 imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_4K)
@@ -82,9 +82,9 @@ const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst = {
82 imx31_imx_uart_data_entry(3, 4), 82 imx31_imx_uart_data_entry(3, 4),
83 imx31_imx_uart_data_entry(4, 5), 83 imx31_imx_uart_data_entry(4, 5),
84}; 84};
85#endif /* ifdef CONFIG_ARCH_MX31 */ 85#endif /* ifdef CONFIG_SOC_IMX31 */
86 86
87#ifdef CONFIG_ARCH_MX35 87#ifdef CONFIG_SOC_IMX35
88const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = { 88const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
89#define imx35_imx_uart_data_entry(_id, _hwid) \ 89#define imx35_imx_uart_data_entry(_id, _hwid) \
90 imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K) 90 imx_imx_uart_1irq_data_entry(MX31, _id, _hwid, SZ_16K)
@@ -92,9 +92,21 @@ const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst = {
92 imx35_imx_uart_data_entry(1, 2), 92 imx35_imx_uart_data_entry(1, 2),
93 imx35_imx_uart_data_entry(2, 3), 93 imx35_imx_uart_data_entry(2, 3),
94}; 94};
95#endif /* ifdef CONFIG_ARCH_MX35 */ 95#endif /* ifdef CONFIG_SOC_IMX35 */
96 96
97#ifdef CONFIG_ARCH_MX51 97#ifdef CONFIG_SOC_IMX50
98const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst = {
99#define imx50_imx_uart_data_entry(_id, _hwid) \
100 imx_imx_uart_1irq_data_entry(MX50, _id, _hwid, SZ_4K)
101 imx50_imx_uart_data_entry(0, 1),
102 imx50_imx_uart_data_entry(1, 2),
103 imx50_imx_uart_data_entry(2, 3),
104 imx50_imx_uart_data_entry(3, 4),
105 imx50_imx_uart_data_entry(4, 5),
106};
107#endif /* ifdef CONFIG_SOC_IMX50 */
108
109#ifdef CONFIG_SOC_IMX51
98const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = { 110const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
99#define imx51_imx_uart_data_entry(_id, _hwid) \ 111#define imx51_imx_uart_data_entry(_id, _hwid) \
100 imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K) 112 imx_imx_uart_1irq_data_entry(MX51, _id, _hwid, SZ_4K)
@@ -102,7 +114,17 @@ const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst = {
102 imx51_imx_uart_data_entry(1, 2), 114 imx51_imx_uart_data_entry(1, 2),
103 imx51_imx_uart_data_entry(2, 3), 115 imx51_imx_uart_data_entry(2, 3),
104}; 116};
105#endif /* ifdef CONFIG_ARCH_MX51 */ 117#endif /* ifdef CONFIG_SOC_IMX51 */
118
119#ifdef CONFIG_SOC_IMX53
120const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst = {
121#define imx53_imx_uart_data_entry(_id, _hwid) \
122 imx_imx_uart_1irq_data_entry(MX53, _id, _hwid, SZ_4K)
123 imx53_imx_uart_data_entry(0, 1),
124 imx53_imx_uart_data_entry(1, 2),
125 imx53_imx_uart_data_entry(2, 3),
126};
127#endif /* ifdef CONFIG_SOC_IMX53 */
106 128
107struct platform_device *__init imx_add_imx_uart_3irq( 129struct platform_device *__init imx_add_imx_uart_3irq(
108 const struct imx_imx_uart_3irq_data *data, 130 const struct imx_imx_uart_3irq_data *data,
diff --git a/arch/arm/plat-mxc/devices/platform-imx2-wdt.c b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
new file mode 100644
index 000000000000..e0aec61177f4
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx2-wdt.c
@@ -0,0 +1,68 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/hardware.h>
11#include <mach/devices-common.h>
12
13#define imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _WDOG ## _hwid ## _BASE_ADDR, \
17 .iosize = _size, \
18 }
19#define imx_imx2_wdt_data_entry(soc, _id, _hwid, _size) \
20 [_id] = imx_imx2_wdt_data_entry_single(soc, _id, _hwid, _size)
21
22#ifdef CONFIG_SOC_IMX21
23const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst =
24 imx_imx2_wdt_data_entry_single(MX21, 0, , SZ_4K);
25#endif /* ifdef CONFIG_SOC_IMX21 */
26
27#ifdef CONFIG_SOC_IMX25
28const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst =
29 imx_imx2_wdt_data_entry_single(MX25, 0, , SZ_16K);
30#endif /* ifdef CONFIG_SOC_IMX25 */
31
32#ifdef CONFIG_SOC_IMX27
33const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst =
34 imx_imx2_wdt_data_entry_single(MX27, 0, , SZ_4K);
35#endif /* ifdef CONFIG_SOC_IMX27 */
36
37#ifdef CONFIG_SOC_IMX31
38const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst =
39 imx_imx2_wdt_data_entry_single(MX31, 0, , SZ_16K);
40#endif /* ifdef CONFIG_SOC_IMX31 */
41
42#ifdef CONFIG_SOC_IMX35
43const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst =
44 imx_imx2_wdt_data_entry_single(MX35, 0, , SZ_16K);
45#endif /* ifdef CONFIG_SOC_IMX35 */
46
47#ifdef CONFIG_SOC_IMX51
48const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst = {
49#define imx51_imx2_wdt_data_entry(_id, _hwid) \
50 imx_imx2_wdt_data_entry(MX51, _id, _hwid, SZ_16K)
51 imx51_imx2_wdt_data_entry(0, 1),
52 imx51_imx2_wdt_data_entry(1, 2),
53};
54#endif /* ifdef CONFIG_SOC_IMX51 */
55
56struct platform_device *__init imx_add_imx2_wdt(
57 const struct imx_imx2_wdt_data *data)
58{
59 struct resource res[] = {
60 {
61 .start = data->iobase,
62 .end = data->iobase + data->iosize - 1,
63 .flags = IORESOURCE_MEM,
64 },
65 };
66 return imx_add_platform_device("imx2-wdt", data->id,
67 res, ARRAY_SIZE(res), NULL, 0);
68}
diff --git a/arch/arm/plat-mxc/devices/platform-imx21-hcd.c b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c
new file mode 100644
index 000000000000..5770a42f33bf
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx21-hcd.c
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_imx21_hcd_data_entry_single(soc) \
13 { \
14 .iobase = soc ## _USBOTG_BASE_ADDR, \
15 .irq = soc ## _INT_USBHOST, \
16 }
17
18#ifdef CONFIG_SOC_IMX21
19const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst =
20 imx_imx21_hcd_data_entry_single(MX21);
21#endif /* ifdef CONFIG_SOC_IMX21 */
22
23struct platform_device *__init imx_add_imx21_hcd(
24 const struct imx_imx21_hcd_data *data,
25 const struct mx21_usbh_platform_data *pdata)
26{
27 struct resource res[] = {
28 {
29 .start = data->iobase,
30 .end = data->iobase + SZ_8K - 1,
31 .flags = IORESOURCE_MEM,
32 }, {
33 .start = data->irq,
34 .end = data->irq,
35 .flags = IORESOURCE_IRQ,
36 },
37 };
38 return imx_add_platform_device_dmamask("imx21-hcd", 0,
39 res, ARRAY_SIZE(res),
40 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
41}
diff --git a/arch/arm/plat-mxc/devices/platform-imx_udc.c b/arch/arm/plat-mxc/devices/platform-imx_udc.c
new file mode 100644
index 000000000000..6fd675dfce14
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imx_udc.c
@@ -0,0 +1,75 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_imx_udc_data_entry_single(soc, _size) \
13 { \
14 .iobase = soc ## _USBD_BASE_ADDR, \
15 .iosize = _size, \
16 .irq0 = soc ## _INT_USBD0, \
17 .irq1 = soc ## _INT_USBD1, \
18 .irq2 = soc ## _INT_USBD2, \
19 .irq3 = soc ## _INT_USBD3, \
20 .irq4 = soc ## _INT_USBD4, \
21 .irq5 = soc ## _INT_USBD5, \
22 .irq6 = soc ## _INT_USBD6, \
23 }
24
25#define imx_imx_udc_data_entry(soc, _size) \
26 [_id] = imx_imx_udc_data_entry_single(soc, _size)
27
28#ifdef CONFIG_SOC_IMX1
29const struct imx_imx_udc_data imx1_imx_udc_data __initconst =
30 imx_imx_udc_data_entry_single(MX1, SZ_4K);
31#endif /* ifdef CONFIG_SOC_IMX1 */
32
33struct platform_device *__init imx_add_imx_udc(
34 const struct imx_imx_udc_data *data,
35 const struct imxusb_platform_data *pdata)
36{
37 struct resource res[] = {
38 {
39 .start = data->iobase,
40 .end = data->iobase + data->iosize - 1,
41 .flags = IORESOURCE_MEM,
42 }, {
43 .start = data->irq0,
44 .end = data->irq0,
45 .flags = IORESOURCE_IRQ,
46 }, {
47 .start = data->irq1,
48 .end = data->irq1,
49 .flags = IORESOURCE_IRQ,
50 }, {
51 .start = data->irq2,
52 .end = data->irq2,
53 .flags = IORESOURCE_IRQ,
54 }, {
55 .start = data->irq3,
56 .end = data->irq3,
57 .flags = IORESOURCE_IRQ,
58 }, {
59 .start = data->irq4,
60 .end = data->irq4,
61 .flags = IORESOURCE_IRQ,
62 }, {
63 .start = data->irq5,
64 .end = data->irq5,
65 .flags = IORESOURCE_IRQ,
66 }, {
67 .start = data->irq6,
68 .end = data->irq6,
69 .flags = IORESOURCE_IRQ,
70 },
71 };
72
73 return imx_add_platform_device("imx_udc", 0,
74 res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
75}
diff --git a/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
new file mode 100644
index 000000000000..10653cc8d1fa
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-imxdi_rtc.c
@@ -0,0 +1,41 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <asm/sizes.h>
10#include <mach/hardware.h>
11#include <mach/devices-common.h>
12
13#define imx_imxdi_rtc_data_entry_single(soc) \
14 { \
15 .iobase = soc ## _DRYICE_BASE_ADDR, \
16 .irq = soc ## _INT_DRYICE, \
17 }
18
19#ifdef CONFIG_SOC_IMX25
20const struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst =
21 imx_imxdi_rtc_data_entry_single(MX25);
22#endif /* ifdef CONFIG_SOC_IMX25 */
23
24struct platform_device *__init imx_add_imxdi_rtc(
25 const struct imx_imxdi_rtc_data *data)
26{
27 struct resource res[] = {
28 {
29 .start = data->iobase,
30 .end = data->iobase + SZ_16K,
31 .flags = IORESOURCE_MEM,
32 }, {
33 .start = data->irq,
34 .end = data->irq,
35 .flags = IORESOURCE_IRQ,
36 },
37 };
38
39 return imx_add_platform_device("imxdi_rtc", 0,
40 res, ARRAY_SIZE(res), NULL, 0);
41}
diff --git a/arch/arm/plat-mxc/devices/platform-mx1-camera.c b/arch/arm/plat-mxc/devices/platform-mx1-camera.c
new file mode 100644
index 000000000000..edcc581a30a9
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mx1-camera.c
@@ -0,0 +1,42 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mx1_camera_data_entry_single(soc, _size) \
13 { \
14 .iobase = soc ## _CSI ## _BASE_ADDR, \
15 .iosize = _size, \
16 .irq = soc ## _INT_CSI, \
17 }
18
19#ifdef CONFIG_SOC_IMX1
20const struct imx_mx1_camera_data imx1_mx1_camera_data __initconst =
21 imx_mx1_camera_data_entry_single(MX1, 10);
22#endif /* ifdef CONFIG_SOC_IMX1 */
23
24struct platform_device *__init imx_add_mx1_camera(
25 const struct imx_mx1_camera_data *data,
26 const struct mx1_camera_pdata *pdata)
27{
28 struct resource res[] = {
29 {
30 .start = data->iobase,
31 .end = data->iobase + data->iosize - 1,
32 .flags = IORESOURCE_MEM,
33 }, {
34 .start = data->irq,
35 .end = data->irq,
36 .flags = IORESOURCE_IRQ,
37 },
38 };
39 return imx_add_platform_device_dmamask("mx1-camera", 0,
40 res, ARRAY_SIZE(res),
41 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
42}
diff --git a/arch/arm/plat-mxc/devices/platform-mx2-camera.c b/arch/arm/plat-mxc/devices/platform-mx2-camera.c
new file mode 100644
index 000000000000..b3f4828dc447
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mx2-camera.c
@@ -0,0 +1,64 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mx2_camera_data_entry_single(soc) \
13 { \
14 .iobasecsi = soc ## _CSI_BASE_ADDR, \
15 .iosizecsi = SZ_4K, \
16 .irqcsi = soc ## _INT_CSI, \
17 }
18#define imx_mx2_camera_data_entry_single_emma(soc) \
19 { \
20 .iobasecsi = soc ## _CSI_BASE_ADDR, \
21 .iosizecsi = SZ_32, \
22 .irqcsi = soc ## _INT_CSI, \
23 .iobaseemmaprp = soc ## _EMMAPRP_BASE_ADDR, \
24 .iosizeemmaprp = SZ_32, \
25 .irqemmaprp = soc ## _INT_EMMAPRP, \
26 }
27
28#ifdef CONFIG_SOC_IMX25
29const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst =
30 imx_mx2_camera_data_entry_single(MX25);
31#endif /* ifdef CONFIG_SOC_IMX25 */
32
33#ifdef CONFIG_SOC_IMX27
34const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst =
35 imx_mx2_camera_data_entry_single_emma(MX27);
36#endif /* ifdef CONFIG_SOC_IMX27 */
37
38struct platform_device *__init imx_add_mx2_camera(
39 const struct imx_mx2_camera_data *data,
40 const struct mx2_camera_platform_data *pdata)
41{
42 struct resource res[] = {
43 {
44 .start = data->iobasecsi,
45 .end = data->iobasecsi + data->iosizecsi - 1,
46 .flags = IORESOURCE_MEM,
47 }, {
48 .start = data->irqcsi,
49 .end = data->irqcsi,
50 .flags = IORESOURCE_IRQ,
51 }, {
52 .start = data->iobaseemmaprp,
53 .end = data->iobaseemmaprp + data->iosizeemmaprp - 1,
54 .flags = IORESOURCE_MEM,
55 }, {
56 .start = data->irqemmaprp,
57 .end = data->irqemmaprp,
58 .flags = IORESOURCE_IRQ,
59 },
60 };
61 return imx_add_platform_device_dmamask("mx2-camera", 0,
62 res, data->iobaseemmaprp ? 4 : 2,
63 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
64}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-ehci.c b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
new file mode 100644
index 000000000000..cc488f4b6204
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc-ehci.c
@@ -0,0 +1,69 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mxc_ehci_data_entry_single(soc, _id, hs) \
13 { \
14 .id = _id, \
15 .iobase = soc ## _USB_ ## hs ## _BASE_ADDR, \
16 .irq = soc ## _INT_USB_ ## hs, \
17 }
18
19#ifdef CONFIG_SOC_IMX25
20const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst =
21 imx_mxc_ehci_data_entry_single(MX25, 0, OTG);
22const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst =
23 imx_mxc_ehci_data_entry_single(MX25, 1, HS);
24#endif /* ifdef CONFIG_SOC_IMX25 */
25
26#ifdef CONFIG_SOC_IMX27
27const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst =
28 imx_mxc_ehci_data_entry_single(MX27, 0, OTG);
29const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst = {
30 imx_mxc_ehci_data_entry_single(MX27, 1, HS1),
31 imx_mxc_ehci_data_entry_single(MX27, 2, HS2),
32};
33#endif /* ifdef CONFIG_SOC_IMX27 */
34
35#ifdef CONFIG_SOC_IMX31
36const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst =
37 imx_mxc_ehci_data_entry_single(MX31, 0, OTG);
38const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst = {
39 imx_mxc_ehci_data_entry_single(MX31, 1, HS1),
40 imx_mxc_ehci_data_entry_single(MX31, 2, HS2),
41};
42#endif /* ifdef CONFIG_SOC_IMX31 */
43
44#ifdef CONFIG_SOC_IMX35
45const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst =
46 imx_mxc_ehci_data_entry_single(MX35, 0, OTG);
47const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst =
48 imx_mxc_ehci_data_entry_single(MX35, 1, HS);
49#endif /* ifdef CONFIG_SOC_IMX35 */
50
51struct platform_device *__init imx_add_mxc_ehci(
52 const struct imx_mxc_ehci_data *data,
53 const struct mxc_usbh_platform_data *pdata)
54{
55 struct resource res[] = {
56 {
57 .start = data->iobase,
58 .end = data->iobase + SZ_512 - 1,
59 .flags = IORESOURCE_MEM,
60 }, {
61 .start = data->irq,
62 .end = data->irq,
63 .flags = IORESOURCE_IRQ,
64 },
65 };
66 return imx_add_platform_device_dmamask("mxc-ehci", data->id,
67 res, ARRAY_SIZE(res),
68 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
69}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc-mmc.c b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c
new file mode 100644
index 000000000000..90d762f6f93b
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc-mmc.c
@@ -0,0 +1,72 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size) \
13 { \
14 .id = _id, \
15 .iobase = soc ## _SDHC ## _hwid ## _BASE_ADDR, \
16 .iosize = _size, \
17 .irq = soc ## _INT_SDHC ## _hwid, \
18 .dmareq = soc ## _DMA_REQ_SDHC ## _hwid, \
19 }
20#define imx_mxc_mmc_data_entry(soc, _id, _hwid, _size) \
21 [_id] = imx_mxc_mmc_data_entry_single(soc, _id, _hwid, _size)
22
23#ifdef CONFIG_SOC_IMX21
24const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst = {
25#define imx21_mxc_mmc_data_entry(_id, _hwid) \
26 imx_mxc_mmc_data_entry(MX21, _id, _hwid, SZ_4K)
27 imx21_mxc_mmc_data_entry(0, 1),
28 imx21_mxc_mmc_data_entry(1, 2),
29};
30#endif /* ifdef CONFIG_SOC_IMX21 */
31
32#ifdef CONFIG_SOC_IMX27
33const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst = {
34#define imx27_mxc_mmc_data_entry(_id, _hwid) \
35 imx_mxc_mmc_data_entry(MX27, _id, _hwid, SZ_4K)
36 imx27_mxc_mmc_data_entry(0, 1),
37 imx27_mxc_mmc_data_entry(1, 2),
38};
39#endif /* ifdef CONFIG_SOC_IMX27 */
40
41#ifdef CONFIG_SOC_IMX31
42const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst = {
43#define imx31_mxc_mmc_data_entry(_id, _hwid) \
44 imx_mxc_mmc_data_entry(MX31, _id, _hwid, SZ_16K)
45 imx31_mxc_mmc_data_entry(0, 1),
46 imx31_mxc_mmc_data_entry(1, 2),
47};
48#endif /* ifdef CONFIG_SOC_IMX31 */
49
50struct platform_device *__init imx_add_mxc_mmc(
51 const struct imx_mxc_mmc_data *data,
52 const struct imxmmc_platform_data *pdata)
53{
54 struct resource res[] = {
55 {
56 .start = data->iobase,
57 .end = data->iobase + SZ_4K - 1,
58 .flags = IORESOURCE_MEM,
59 }, {
60 .start = data->irq,
61 .end = data->irq,
62 .flags = IORESOURCE_IRQ,
63 }, {
64 .start = data->dmareq,
65 .end = data->dmareq,
66 .flags = IORESOURCE_DMA,
67 },
68 };
69 return imx_add_platform_device_dmamask("mxc-mmc", data->id,
70 res, ARRAY_SIZE(res),
71 pdata, sizeof(*pdata), DMA_BIT_MASK(32));
72}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_nand.c b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
index 3fdcc32e3d67..1568f39fba8b 100644
--- a/arch/arm/plat-mxc/devices/platform-mxc_nand.c
+++ b/arch/arm/plat-mxc/devices/platform-mxc_nand.c
@@ -31,27 +31,27 @@ const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst =
31 imx_mxc_nand_data_entry_single(MX21, SZ_4K); 31 imx_mxc_nand_data_entry_single(MX21, SZ_4K);
32#endif /* ifdef CONFIG_SOC_IMX21 */ 32#endif /* ifdef CONFIG_SOC_IMX21 */
33 33
34#ifdef CONFIG_ARCH_MX25 34#ifdef CONFIG_SOC_IMX25
35const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst = 35const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst =
36 imx_mxc_nand_data_entry_single(MX25, SZ_8K); 36 imx_mxc_nand_data_entry_single(MX25, SZ_8K);
37#endif /* ifdef CONFIG_ARCH_MX25 */ 37#endif /* ifdef CONFIG_SOC_IMX25 */
38 38
39#ifdef CONFIG_SOC_IMX27 39#ifdef CONFIG_SOC_IMX27
40const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst = 40const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst =
41 imx_mxc_nand_data_entry_single(MX27, SZ_4K); 41 imx_mxc_nand_data_entry_single(MX27, SZ_4K);
42#endif /* ifdef CONFIG_SOC_IMX27 */ 42#endif /* ifdef CONFIG_SOC_IMX27 */
43 43
44#ifdef CONFIG_ARCH_MX31 44#ifdef CONFIG_SOC_IMX31
45const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst = 45const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst =
46 imx_mxc_nand_data_entry_single(MX31, SZ_4K); 46 imx_mxc_nand_data_entry_single(MX31, SZ_4K);
47#endif 47#endif
48 48
49#ifdef CONFIG_ARCH_MX35 49#ifdef CONFIG_SOC_IMX35
50const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst = 50const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst =
51 imx_mxc_nand_data_entry_single(MX35, SZ_8K); 51 imx_mxc_nand_data_entry_single(MX35, SZ_8K);
52#endif 52#endif
53 53
54#ifdef CONFIG_ARCH_MX51 54#ifdef CONFIG_SOC_IMX51
55const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst = 55const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst =
56 imx_mxc_nandv3_data_entry_single(MX51, SZ_16K); 56 imx_mxc_nandv3_data_entry_single(MX51, SZ_16K);
57#endif 57#endif
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_pwm.c b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
new file mode 100644
index 000000000000..3d8ebdba38ee
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_pwm.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright (C) 2009-2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size) \
13 { \
14 .id = _id, \
15 .iobase = soc ## _PWM ## _hwid ## _BASE_ADDR, \
16 .iosize = _size, \
17 .irq = soc ## _INT_PWM ## _hwid, \
18 }
19#define imx_mxc_pwm_data_entry(soc, _id, _hwid, _size) \
20 [_id] = imx_mxc_pwm_data_entry_single(soc, _id, _hwid, _size)
21
22#ifdef CONFIG_SOC_IMX21
23const struct imx_mxc_pwm_data imx21_mxc_pwm_data __initconst =
24 imx_mxc_pwm_data_entry_single(MX21, 0, , SZ_4K);
25#endif /* ifdef CONFIG_SOC_IMX21 */
26
27#ifdef CONFIG_SOC_IMX25
28const struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst = {
29#define imx25_mxc_pwm_data_entry(_id, _hwid) \
30 imx_mxc_pwm_data_entry(MX25, _id, _hwid, SZ_16K)
31 imx25_mxc_pwm_data_entry(0, 1),
32 imx25_mxc_pwm_data_entry(1, 2),
33 imx25_mxc_pwm_data_entry(2, 3),
34 imx25_mxc_pwm_data_entry(3, 4),
35};
36#endif /* ifdef CONFIG_SOC_IMX25 */
37
38#ifdef CONFIG_SOC_IMX27
39const struct imx_mxc_pwm_data imx27_mxc_pwm_data __initconst =
40 imx_mxc_pwm_data_entry_single(MX27, 0, , SZ_4K);
41#endif /* ifdef CONFIG_SOC_IMX27 */
42
43struct platform_device *__init imx_add_mxc_pwm(
44 const struct imx_mxc_pwm_data *data)
45{
46 struct resource res[] = {
47 {
48 .start = data->iobase,
49 .end = data->iobase + data->iosize - 1,
50 .flags = IORESOURCE_MEM,
51 }, {
52 .start = data->irq,
53 .end = data->irq,
54 .flags = IORESOURCE_IRQ,
55 },
56 };
57
58 return imx_add_platform_device("mxc_pwm", data->id,
59 res, ARRAY_SIZE(res), NULL, 0);
60}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rnga.c b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c
new file mode 100644
index 000000000000..b4b7612b6e17
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_rnga.c
@@ -0,0 +1,56 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12struct imx_mxc_rnga_data {
13 resource_size_t iobase;
14};
15
16#define imx_mxc_rnga_data_entry_single(soc) \
17 { \
18 .iobase = soc ## _RNGA_BASE_ADDR, \
19 }
20
21#ifdef CONFIG_SOC_IMX31
22static const struct imx_mxc_rnga_data imx31_mxc_rnga_data __initconst =
23 imx_mxc_rnga_data_entry_single(MX31);
24#endif /* ifdef CONFIG_SOC_IMX31 */
25
26static struct platform_device *__init imx_add_mxc_rnga(
27 const struct imx_mxc_rnga_data *data)
28{
29 struct resource res[] = {
30 {
31 .start = data->iobase,
32 .end = data->iobase + SZ_16K - 1,
33 .flags = IORESOURCE_MEM,
34 },
35 };
36 return imx_add_platform_device("mxc_rnga", -1,
37 res, ARRAY_SIZE(res), NULL, 0);
38}
39
40static int __init imxXX_add_mxc_rnga(void)
41{
42 struct platform_device *ret;
43
44#if defined(CONFIG_SOC_IMX31)
45 if (cpu_is_mx31())
46 ret = imx_add_mxc_rnga(&imx31_mxc_rnga_data);
47 else
48#endif /* if defined(CONFIG_SOC_IMX31) */
49 ret = ERR_PTR(-ENODEV);
50
51 if (IS_ERR(ret))
52 return PTR_ERR(ret);
53
54 return 0;
55}
56arch_initcall(imxXX_add_mxc_rnga);
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_w1.c b/arch/arm/plat-mxc/devices/platform-mxc_w1.c
new file mode 100644
index 000000000000..96fa5ea91fe8
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_w1.c
@@ -0,0 +1,50 @@
1/*
2 * Copyright (C) 2010 Pengutronix
3 * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
4 *
5 * This program is free software; you can redistribute it and/or modify it under
6 * the terms of the GNU General Public License version 2 as published by the
7 * Free Software Foundation.
8 */
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11
12#define imx_mxc_w1_data_entry_single(soc) \
13 { \
14 .iobase = soc ## _OWIRE_BASE_ADDR, \
15 }
16
17#ifdef CONFIG_SOC_IMX21
18const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst =
19 imx_mxc_w1_data_entry_single(MX21);
20#endif /* ifdef CONFIG_SOC_IMX21 */
21
22#ifdef CONFIG_SOC_IMX27
23const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst =
24 imx_mxc_w1_data_entry_single(MX27);
25#endif /* ifdef CONFIG_SOC_IMX27 */
26
27#ifdef CONFIG_SOC_IMX31
28const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst =
29 imx_mxc_w1_data_entry_single(MX31);
30#endif /* ifdef CONFIG_SOC_IMX31 */
31
32#ifdef CONFIG_SOC_IMX35
33const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst =
34 imx_mxc_w1_data_entry_single(MX35);
35#endif /* ifdef CONFIG_SOC_IMX35 */
36
37struct platform_device *__init imx_add_mxc_w1(
38 const struct imx_mxc_w1_data *data)
39{
40 struct resource res[] = {
41 {
42 .start = data->iobase,
43 .end = data->iobase + SZ_4K - 1,
44 .flags = IORESOURCE_MEM,
45 },
46 };
47
48 return imx_add_platform_device("mxc_w1", 0,
49 res, ARRAY_SIZE(res), NULL, 0);
50}
diff --git a/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
new file mode 100644
index 000000000000..b3525648a01d
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-sdhci-esdhc-imx.c
@@ -0,0 +1,74 @@
1/*
2 * Copyright (C) 2010 Pengutronix, Wolfram Sang <w.sang@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify it under
5 * the terms of the GNU General Public License version 2 as published by the
6 * Free Software Foundation.
7 */
8
9#include <mach/hardware.h>
10#include <mach/devices-common.h>
11#include <mach/esdhc.h>
12
13#define imx_sdhci_esdhc_imx_data_entry_single(soc, _id, hwid) \
14 { \
15 .id = _id, \
16 .iobase = soc ## _ESDHC ## hwid ## _BASE_ADDR, \
17 .irq = soc ## _INT_ESDHC ## hwid, \
18 }
19
20#define imx_sdhci_esdhc_imx_data_entry(soc, id, hwid) \
21 [id] = imx_sdhci_esdhc_imx_data_entry_single(soc, id, hwid)
22
23#ifdef CONFIG_SOC_IMX25
24const struct imx_sdhci_esdhc_imx_data
25imx25_sdhci_esdhc_imx_data[] __initconst = {
26#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \
27 imx_sdhci_esdhc_imx_data_entry(MX25, _id, _hwid)
28 imx25_sdhci_esdhc_imx_data_entry(0, 1),
29 imx25_sdhci_esdhc_imx_data_entry(1, 2),
30};
31#endif /* ifdef CONFIG_SOC_IMX25 */
32
33#ifdef CONFIG_SOC_IMX35
34const struct imx_sdhci_esdhc_imx_data
35imx35_sdhci_esdhc_imx_data[] __initconst = {
36#define imx35_sdhci_esdhc_imx_data_entry(_id, _hwid) \
37 imx_sdhci_esdhc_imx_data_entry(MX35, _id, _hwid)
38 imx35_sdhci_esdhc_imx_data_entry(0, 1),
39 imx35_sdhci_esdhc_imx_data_entry(1, 2),
40 imx35_sdhci_esdhc_imx_data_entry(2, 3),
41};
42#endif /* ifdef CONFIG_SOC_IMX35 */
43
44#ifdef CONFIG_SOC_IMX51
45const struct imx_sdhci_esdhc_imx_data
46imx51_sdhci_esdhc_imx_data[] __initconst = {
47#define imx51_sdhci_esdhc_imx_data_entry(_id, _hwid) \
48 imx_sdhci_esdhc_imx_data_entry(MX51, _id, _hwid)
49 imx51_sdhci_esdhc_imx_data_entry(0, 1),
50 imx51_sdhci_esdhc_imx_data_entry(1, 2),
51 imx51_sdhci_esdhc_imx_data_entry(2, 3),
52 imx51_sdhci_esdhc_imx_data_entry(3, 4),
53};
54#endif /* ifdef CONFIG_SOC_IMX51 */
55
56struct platform_device *__init imx_add_sdhci_esdhc_imx(
57 const struct imx_sdhci_esdhc_imx_data *data,
58 const struct esdhc_platform_data *pdata)
59{
60 struct resource res[] = {
61 {
62 .start = data->iobase,
63 .end = data->iobase + SZ_16K - 1,
64 .flags = IORESOURCE_MEM,
65 }, {
66 .start = data->irq,
67 .end = data->irq,
68 .flags = IORESOURCE_IRQ,
69 },
70 };
71
72 return imx_add_platform_device("sdhci-esdhc-imx", data->id, res,
73 ARRAY_SIZE(res), pdata, sizeof(*pdata));
74}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 17f724c9452d..8ea49adcdfc1 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -30,7 +30,7 @@ const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
30}; 30};
31#endif 31#endif
32 32
33#ifdef CONFIG_ARCH_MX25 33#ifdef CONFIG_SOC_IMX25
34const struct imx_spi_imx_data imx25_cspi_data[] __initconst = { 34const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
35#define imx25_cspi_data_entry(_id, _hwid) \ 35#define imx25_cspi_data_entry(_id, _hwid) \
36 imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K) 36 imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
@@ -38,7 +38,7 @@ const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
38 imx25_cspi_data_entry(1, 2), 38 imx25_cspi_data_entry(1, 2),
39 imx25_cspi_data_entry(2, 3), 39 imx25_cspi_data_entry(2, 3),
40}; 40};
41#endif /* ifdef CONFIG_ARCH_MX25 */ 41#endif /* ifdef CONFIG_SOC_IMX25 */
42 42
43#ifdef CONFIG_SOC_IMX27 43#ifdef CONFIG_SOC_IMX27
44const struct imx_spi_imx_data imx27_cspi_data[] __initconst = { 44const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
@@ -50,7 +50,7 @@ const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
50}; 50};
51#endif /* ifdef CONFIG_SOC_IMX27 */ 51#endif /* ifdef CONFIG_SOC_IMX27 */
52 52
53#ifdef CONFIG_ARCH_MX31 53#ifdef CONFIG_SOC_IMX31
54const struct imx_spi_imx_data imx31_cspi_data[] __initconst = { 54const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
55#define imx31_cspi_data_entry(_id, _hwid) \ 55#define imx31_cspi_data_entry(_id, _hwid) \
56 imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K) 56 imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
@@ -58,18 +58,18 @@ const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
58 imx31_cspi_data_entry(1, 2), 58 imx31_cspi_data_entry(1, 2),
59 imx31_cspi_data_entry(2, 3), 59 imx31_cspi_data_entry(2, 3),
60}; 60};
61#endif /* ifdef CONFIG_ARCH_MX31 */ 61#endif /* ifdef CONFIG_SOC_IMX31 */
62 62
63#ifdef CONFIG_ARCH_MX35 63#ifdef CONFIG_SOC_IMX35
64const struct imx_spi_imx_data imx35_cspi_data[] __initconst = { 64const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
65#define imx35_cspi_data_entry(_id, _hwid) \ 65#define imx35_cspi_data_entry(_id, _hwid) \
66 imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K) 66 imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
67 imx35_cspi_data_entry(0, 1), 67 imx35_cspi_data_entry(0, 1),
68 imx35_cspi_data_entry(1, 2), 68 imx35_cspi_data_entry(1, 2),
69}; 69};
70#endif /* ifdef CONFIG_ARCH_MX35 */ 70#endif /* ifdef CONFIG_SOC_IMX35 */
71 71
72#ifdef CONFIG_ARCH_MX51 72#ifdef CONFIG_SOC_IMX51
73const struct imx_spi_imx_data imx51_cspi_data __initconst = 73const struct imx_spi_imx_data imx51_cspi_data __initconst =
74 imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K); 74 imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K);
75 75
@@ -79,7 +79,7 @@ const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
79 imx51_ecspi_data_entry(0, 1), 79 imx51_ecspi_data_entry(0, 1),
80 imx51_ecspi_data_entry(1, 2), 80 imx51_ecspi_data_entry(1, 2),
81}; 81};
82#endif /* ifdef CONFIG_ARCH_MX51 */ 82#endif /* ifdef CONFIG_SOC_IMX51 */
83 83
84struct platform_device *__init imx_add_spi_imx( 84struct platform_device *__init imx_add_spi_imx(
85 const struct imx_spi_imx_data *data, 85 const struct imx_spi_imx_data *data,
diff --git a/arch/arm/plat-mxc/ehci.c b/arch/arm/plat-mxc/ehci.c
index 9915607683de..8772ce346a58 100644
--- a/arch/arm/plat-mxc/ehci.c
+++ b/arch/arm/plat-mxc/ehci.c
@@ -49,6 +49,7 @@
49 49
50#define MXC_OTG_OFFSET 0 50#define MXC_OTG_OFFSET 0
51#define MXC_H1_OFFSET 0x200 51#define MXC_H1_OFFSET 0x200
52#define MXC_H2_OFFSET 0x400
52 53
53/* USB_CTRL */ 54/* USB_CTRL */
54#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */ 55#define MXC_OTG_UCTRL_OWIE_BIT (1 << 27) /* OTG wakeup intr enable */
@@ -61,6 +62,11 @@
61#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */ 62#define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8) /* OTG Disable Overcurrent Event */
62#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */ 63#define MXC_H1_OC_DIS_BIT (1 << 5) /* UH1 Disable Overcurrent Event */
63 64
65/* USBH2CTRL */
66#define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
67#define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
68#define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
69
64#define MXC_USBCMD_OFFSET 0x140 70#define MXC_USBCMD_OFFSET 0x140
65 71
66/* USBCMD */ 72/* USBCMD */
@@ -69,9 +75,9 @@
69int mxc_initialize_usb_hw(int port, unsigned int flags) 75int mxc_initialize_usb_hw(int port, unsigned int flags)
70{ 76{
71 unsigned int v; 77 unsigned int v;
72#if defined(CONFIG_ARCH_MX25) 78#if defined(CONFIG_SOC_IMX25)
73 if (cpu_is_mx25()) { 79 if (cpu_is_mx25()) {
74 v = readl(MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + 80 v = readl(MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
75 USBCTRL_OTGBASE_OFFSET)); 81 USBCTRL_OTGBASE_OFFSET));
76 82
77 switch (port) { 83 switch (port) {
@@ -108,14 +114,14 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
108 return -EINVAL; 114 return -EINVAL;
109 } 115 }
110 116
111 writel(v, MX25_IO_ADDRESS(MX25_OTG_BASE_ADDR + 117 writel(v, MX25_IO_ADDRESS(MX25_USB_BASE_ADDR +
112 USBCTRL_OTGBASE_OFFSET)); 118 USBCTRL_OTGBASE_OFFSET));
113 return 0; 119 return 0;
114 } 120 }
115#endif /* CONFIG_ARCH_MX25 */ 121#endif /* if defined(CONFIG_SOC_IMX25) */
116#if defined(CONFIG_ARCH_MX3) 122#if defined(CONFIG_ARCH_MX3)
117 if (cpu_is_mx31()) { 123 if (cpu_is_mx31()) {
118 v = readl(MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + 124 v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
119 USBCTRL_OTGBASE_OFFSET)); 125 USBCTRL_OTGBASE_OFFSET));
120 126
121 switch (port) { 127 switch (port) {
@@ -153,13 +159,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
153 return -EINVAL; 159 return -EINVAL;
154 } 160 }
155 161
156 writel(v, MX31_IO_ADDRESS(MX31_OTG_BASE_ADDR + 162 writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR +
157 USBCTRL_OTGBASE_OFFSET)); 163 USBCTRL_OTGBASE_OFFSET));
158 return 0; 164 return 0;
159 } 165 }
160 166
161 if (cpu_is_mx35()) { 167 if (cpu_is_mx35()) {
162 v = readl(MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + 168 v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
163 USBCTRL_OTGBASE_OFFSET)); 169 USBCTRL_OTGBASE_OFFSET));
164 170
165 switch (port) { 171 switch (port) {
@@ -196,7 +202,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
196 return -EINVAL; 202 return -EINVAL;
197 } 203 }
198 204
199 writel(v, MX35_IO_ADDRESS(MX35_OTG_BASE_ADDR + 205 writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR +
200 USBCTRL_OTGBASE_OFFSET)); 206 USBCTRL_OTGBASE_OFFSET));
201 return 0; 207 return 0;
202 } 208 }
@@ -206,7 +212,7 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
206 /* On i.MX27 we can use the i.MX31 USBCTRL bits, they 212 /* On i.MX27 we can use the i.MX31 USBCTRL bits, they
207 * are identical 213 * are identical
208 */ 214 */
209 v = readl(MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + 215 v = readl(MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
210 USBCTRL_OTGBASE_OFFSET)); 216 USBCTRL_OTGBASE_OFFSET));
211 switch (port) { 217 switch (port) {
212 case 0: /* OTG port */ 218 case 0: /* OTG port */
@@ -241,12 +247,12 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
241 default: 247 default:
242 return -EINVAL; 248 return -EINVAL;
243 } 249 }
244 writel(v, MX27_IO_ADDRESS(MX27_OTG_BASE_ADDR + 250 writel(v, MX27_IO_ADDRESS(MX27_USB_BASE_ADDR +
245 USBCTRL_OTGBASE_OFFSET)); 251 USBCTRL_OTGBASE_OFFSET));
246 return 0; 252 return 0;
247 } 253 }
248#endif /* CONFIG_MACH_MX27 */ 254#endif /* CONFIG_MACH_MX27 */
249#ifdef CONFIG_ARCH_MX51 255#ifdef CONFIG_SOC_IMX51
250 if (cpu_is_mx51()) { 256 if (cpu_is_mx51()) {
251 void __iomem *usb_base; 257 void __iomem *usb_base;
252 void __iomem *usbotg_base; 258 void __iomem *usbotg_base;
@@ -254,6 +260,10 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
254 int ret = 0; 260 int ret = 0;
255 261
256 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); 262 usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K);
263 if (!usb_base) {
264 printk(KERN_ERR "%s(): ioremap failed\n", __func__);
265 return -ENOMEM;
266 }
257 267
258 switch (port) { 268 switch (port) {
259 case 0: /* OTG port */ 269 case 0: /* OTG port */
@@ -262,6 +272,9 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
262 case 1: /* Host 1 port */ 272 case 1: /* Host 1 port */
263 usbotg_base = usb_base + MXC_H1_OFFSET; 273 usbotg_base = usb_base + MXC_H1_OFFSET;
264 break; 274 break;
275 case 2: /* Host 2 port */
276 usbotg_base = usb_base + MXC_H2_OFFSET;
277 break;
265 default: 278 default:
266 printk(KERN_ERR"%s no such port %d\n", __func__, port); 279 printk(KERN_ERR"%s no such port %d\n", __func__, port);
267 ret = -ENOENT; 280 ret = -ENOENT;
@@ -274,10 +287,13 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
274 if (flags & MXC_EHCI_INTERNAL_PHY) { 287 if (flags & MXC_EHCI_INTERNAL_PHY) {
275 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 288 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
276 289
277 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 290 if (flags & MXC_EHCI_POWER_PINS_ENABLED) {
278 v |= (MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is not used */ 291 /* OC/USBPWR is not used */
279 else 292 v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
280 v &= ~(MXC_OTG_PHYCTRL_OC_DIS_BIT | MXC_OTG_UCTRL_OPM_BIT); /* OC/USBPWR is used */ 293 } else {
294 /* OC/USBPWR is used */
295 v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
296 }
281 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); 297 __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
282 298
283 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 299 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
@@ -285,16 +301,23 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
285 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */ 301 v |= MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup enable */
286 else 302 else
287 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */ 303 v &= ~MXC_OTG_UCTRL_OWIE_BIT;/* OTG wakeup disable */
304 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
305 v |= MXC_OTG_UCTRL_OPM_BIT;
306 else
307 v &= ~MXC_OTG_UCTRL_OPM_BIT;
288 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET); 308 __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
289 } 309 }
290 break; 310 break;
291 case 1: /* Host 1 */ 311 case 1: /* Host 1 */
292 /*Host ULPI */ 312 /*Host ULPI */
293 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); 313 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
294 if (flags & MXC_EHCI_WAKEUP_ENABLED) 314 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
295 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ 315 /* HOST1 wakeup/ULPI intr enable */
296 else 316 v |= (MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
297 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);/* HOST1 wakeup/ULPI intr disable */ 317 } else {
318 /* HOST1 wakeup/ULPI intr disable */
319 v &= ~(MXC_H1_UCTRL_H1WIE_BIT | MXC_H1_UCTRL_H1UIE_BIT);
320 }
298 321
299 if (flags & MXC_EHCI_POWER_PINS_ENABLED) 322 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
300 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/ 323 v &= ~MXC_H1_UCTRL_H1PM_BIT; /* HOST1 power mask used*/
@@ -315,6 +338,22 @@ int mxc_initialize_usb_hw(int port, unsigned int flags)
315 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK; 338 v &= MXC_UCMD_ITC_NO_THRESHOLD_MASK;
316 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET); 339 __raw_writel(v, usbotg_base + MXC_USBCMD_OFFSET);
317 break; 340 break;
341 case 2: /* Host 2 ULPI */
342 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
343 if (flags & MXC_EHCI_WAKEUP_ENABLED) {
344 /* HOST1 wakeup/ULPI intr enable */
345 v |= (MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
346 } else {
347 /* HOST1 wakeup/ULPI intr disable */
348 v &= ~(MXC_H2_UCTRL_H2WIE_BIT | MXC_H2_UCTRL_H2UIE_BIT);
349 }
350
351 if (flags & MXC_EHCI_POWER_PINS_ENABLED)
352 v &= ~MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
353 else
354 v |= MXC_H2_UCTRL_H2PM_BIT; /* HOST2 power mask used*/
355 __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
356 break;
318 } 357 }
319 358
320error: 359error:
diff --git a/arch/arm/plat-mxc/gpio.c b/arch/arm/plat-mxc/gpio.c
index 9c3e36232b5b..bc2c7bc6f10a 100644
--- a/arch/arm/plat-mxc/gpio.c
+++ b/arch/arm/plat-mxc/gpio.c
@@ -175,7 +175,7 @@ static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
175static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc) 175static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
176{ 176{
177 u32 irq_stat; 177 u32 irq_stat;
178 struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); 178 struct mxc_gpio_port *port = get_irq_data(irq);
179 179
180 irq_stat = __raw_readl(port->base + GPIO_ISR) & 180 irq_stat = __raw_readl(port->base + GPIO_ISR) &
181 __raw_readl(port->base + GPIO_IMR); 181 __raw_readl(port->base + GPIO_IMR);
@@ -188,7 +188,7 @@ static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
188{ 188{
189 int i; 189 int i;
190 u32 irq_msk, irq_stat; 190 u32 irq_msk, irq_stat;
191 struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq); 191 struct mxc_gpio_port *port = get_irq_data(irq);
192 192
193 /* walk through all interrupt status registers */ 193 /* walk through all interrupt status registers */
194 for (i = 0; i < gpio_table_size; i++) { 194 for (i = 0; i < gpio_table_size; i++) {
@@ -349,3 +349,113 @@ int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
349 349
350 return 0; 350 return 0;
351} 351}
352
353#define DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, _irq_high) \
354 { \
355 .chip.label = "gpio-" #_id, \
356 .irq = _irq, \
357 .irq_high = _irq_high, \
358 .base = soc ## _IO_ADDRESS( \
359 soc ## _GPIO ## _hwid ## _BASE_ADDR), \
360 .virtual_irq_start = MXC_GPIO_IRQ_START + (_id) * 32, \
361 }
362
363#define DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, _irq) \
364 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(soc, _id, _hwid, _irq, 0)
365#define DEFINE_IMX_GPIO_PORT(soc, _id, _hwid) \
366 DEFINE_IMX_GPIO_PORT_IRQ(soc, _id, _hwid, 0)
367
368#define DEFINE_REGISTER_FUNCTION(prefix) \
369int __init prefix ## _register_gpios(void) \
370{ \
371 return mxc_gpio_init(prefix ## _gpio_ports, \
372 ARRAY_SIZE(prefix ## _gpio_ports)); \
373}
374
375#if defined(CONFIG_SOC_IMX1)
376static struct mxc_gpio_port imx1_gpio_ports[] = {
377 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 0, 1, MX1_GPIO_INT_PORTA),
378 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 1, 2, MX1_GPIO_INT_PORTB),
379 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 2, 3, MX1_GPIO_INT_PORTC),
380 DEFINE_IMX_GPIO_PORT_IRQ(MX1, 3, 4, MX1_GPIO_INT_PORTD),
381};
382
383DEFINE_REGISTER_FUNCTION(imx1)
384
385#endif /* if defined(CONFIG_SOC_IMX1) */
386
387#if defined(CONFIG_SOC_IMX21)
388static struct mxc_gpio_port imx21_gpio_ports[] = {
389 DEFINE_IMX_GPIO_PORT_IRQ(MX21, 0, 1, MX21_INT_GPIO),
390 DEFINE_IMX_GPIO_PORT(MX21, 1, 2),
391 DEFINE_IMX_GPIO_PORT(MX21, 2, 3),
392 DEFINE_IMX_GPIO_PORT(MX21, 3, 4),
393 DEFINE_IMX_GPIO_PORT(MX21, 4, 5),
394 DEFINE_IMX_GPIO_PORT(MX21, 5, 6),
395};
396
397DEFINE_REGISTER_FUNCTION(imx21)
398
399#endif /* if defined(CONFIG_SOC_IMX21) */
400
401#if defined(CONFIG_SOC_IMX25)
402static struct mxc_gpio_port imx25_gpio_ports[] = {
403 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 0, 1, MX25_INT_GPIO1),
404 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 1, 2, MX25_INT_GPIO2),
405 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 2, 3, MX25_INT_GPIO3),
406 DEFINE_IMX_GPIO_PORT_IRQ(MX25, 3, 4, MX25_INT_GPIO4),
407};
408
409DEFINE_REGISTER_FUNCTION(imx25)
410
411#endif /* if defined(CONFIG_SOC_IMX25) */
412
413#if defined(CONFIG_SOC_IMX27)
414static struct mxc_gpio_port imx27_gpio_ports[] = {
415 DEFINE_IMX_GPIO_PORT_IRQ(MX27, 0, 1, MX27_INT_GPIO),
416 DEFINE_IMX_GPIO_PORT(MX27, 1, 2),
417 DEFINE_IMX_GPIO_PORT(MX27, 2, 3),
418 DEFINE_IMX_GPIO_PORT(MX27, 3, 4),
419 DEFINE_IMX_GPIO_PORT(MX27, 4, 5),
420 DEFINE_IMX_GPIO_PORT(MX27, 5, 6),
421};
422
423DEFINE_REGISTER_FUNCTION(imx27)
424
425#endif /* if defined(CONFIG_SOC_IMX27) */
426
427#if defined(CONFIG_SOC_IMX31)
428static struct mxc_gpio_port imx31_gpio_ports[] = {
429 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
430 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
431 DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
432};
433
434DEFINE_REGISTER_FUNCTION(imx31)
435
436#endif /* if defined(CONFIG_SOC_IMX31) */
437
438#if defined(CONFIG_SOC_IMX35)
439static struct mxc_gpio_port imx35_gpio_ports[] = {
440 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
441 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
442 DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
443};
444
445DEFINE_REGISTER_FUNCTION(imx35)
446
447#endif /* if defined(CONFIG_SOC_IMX35) */
448
449#if defined(CONFIG_SOC_IMX50)
450static struct mxc_gpio_port imx50_gpio_ports[] = {
451 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 0, 1, MX50_INT_GPIO1_LOW, MX50_INT_GPIO1_HIGH),
452 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 1, 2, MX50_INT_GPIO2_LOW, MX50_INT_GPIO2_HIGH),
453 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 2, 3, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
454 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 3, 4, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
455 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 4, 5, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
456 DEFINE_IMX_GPIO_PORT_IRQ_HIGH(MX50, 5, 6, MX50_INT_GPIO3_LOW, MX50_INT_GPIO3_HIGH),
457};
458
459DEFINE_REGISTER_FUNCTION(imx50)
460
461#endif /* if defined(CONFIG_SOC_IMX50) */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index 7a1e1f89ff09..aea2cd3b6d15 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -20,7 +20,9 @@ extern void mx25_map_io(void);
20extern void mx27_map_io(void); 20extern void mx27_map_io(void);
21extern void mx31_map_io(void); 21extern void mx31_map_io(void);
22extern void mx35_map_io(void); 22extern void mx35_map_io(void);
23extern void mx50_map_io(void);
23extern void mx51_map_io(void); 24extern void mx51_map_io(void);
25extern void mx53_map_io(void);
24extern void mxc91231_map_io(void); 26extern void mxc91231_map_io(void);
25extern void mxc_init_irq(void __iomem *); 27extern void mxc_init_irq(void __iomem *);
26extern void tzic_init_irq(void __iomem *); 28extern void tzic_init_irq(void __iomem *);
@@ -30,7 +32,9 @@ extern void mx25_init_irq(void);
30extern void mx27_init_irq(void); 32extern void mx27_init_irq(void);
31extern void mx31_init_irq(void); 33extern void mx31_init_irq(void);
32extern void mx35_init_irq(void); 34extern void mx35_init_irq(void);
35extern void mx50_init_irq(void);
33extern void mx51_init_irq(void); 36extern void mx51_init_irq(void);
37extern void mx53_init_irq(void);
34extern void mxc91231_init_irq(void); 38extern void mxc91231_init_irq(void);
35extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq); 39extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
36extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int); 40extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
@@ -42,6 +46,8 @@ extern int mx31_clocks_init(unsigned long fref);
42extern int mx35_clocks_init(void); 46extern int mx35_clocks_init(void);
43extern int mx51_clocks_init(unsigned long ckil, unsigned long osc, 47extern int mx51_clocks_init(unsigned long ckil, unsigned long osc,
44 unsigned long ckih1, unsigned long ckih2); 48 unsigned long ckih1, unsigned long ckih2);
49extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
50 unsigned long ckih1, unsigned long ckih2);
45extern int mxc91231_clocks_init(unsigned long fref); 51extern int mxc91231_clocks_init(unsigned long fref);
46extern int mxc_register_gpios(void); 52extern int mxc_register_gpios(void);
47extern int mxc_register_device(struct platform_device *pdev, void *data); 53extern int mxc_register_device(struct platform_device *pdev, void *data);
@@ -50,5 +56,6 @@ extern void mxc_arch_reset_init(void __iomem *);
50extern void mxc91231_power_off(void); 56extern void mxc91231_power_off(void);
51extern void mxc91231_arch_reset(int, const char *); 57extern void mxc91231_arch_reset(int, const char *);
52extern void mxc91231_prepare_idle(void); 58extern void mxc91231_prepare_idle(void);
53 59extern void mx51_efikamx_reset(void);
60extern int mx53_revision(void);
54#endif 61#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index d56213fb901b..3b3a37c25c56 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -10,58 +10,49 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 * 11 *
12 */ 12 */
13#define IMX_NEEDS_DEPRECATED_SYMBOLS 13#include <mach/hardware.h>
14 14
15#ifdef CONFIG_ARCH_MX1 15#ifdef CONFIG_ARCH_MX1
16#include <mach/mx1.h> 16#define UART_PADDR MX1_UART1_BASE_ADDR
17#define UART_PADDR UART1_BASE_ADDR
18#define UART_VADDR IO_ADDRESS(UART1_BASE_ADDR)
19#endif 17#endif
20 18
21#ifdef CONFIG_ARCH_MX25 19#ifdef CONFIG_ARCH_MX25
22#ifdef UART_PADDR 20#ifdef UART_PADDR
23#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 21#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
24#endif 22#endif
25#include <mach/mx25.h>
26#define UART_PADDR MX25_UART1_BASE_ADDR 23#define UART_PADDR MX25_UART1_BASE_ADDR
27#define UART_VADDR MX25_AIPS1_IO_ADDRESS(MX25_UART1_BASE_ADDR)
28#endif 24#endif
29 25
30#ifdef CONFIG_ARCH_MX2 26#ifdef CONFIG_ARCH_MX2
31#ifdef UART_PADDR 27#ifdef UART_PADDR
32#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 28#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
33#endif 29#endif
34#include <mach/mx2x.h> 30#define UART_PADDR MX2x_UART1_BASE_ADDR
35#define UART_PADDR UART1_BASE_ADDR
36#define UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
37#endif 31#endif
38 32
39#ifdef CONFIG_ARCH_MX3 33#ifdef CONFIG_ARCH_MX3
40#ifdef UART_PADDR 34#ifdef UART_PADDR
41#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 35#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
42#endif 36#endif
43#include <mach/mx3x.h> 37#define UART_PADDR MX3x_UART1_BASE_ADDR
44#define UART_PADDR UART1_BASE_ADDR
45#define UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
46#endif 38#endif
47 39
48#ifdef CONFIG_ARCH_MX5 40#ifdef CONFIG_ARCH_MX5
49#ifdef UART_PADDR 41#ifdef UART_PADDR
50#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 42#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
51#endif 43#endif
52#include <mach/mx51.h>
53#define UART_PADDR MX51_UART1_BASE_ADDR 44#define UART_PADDR MX51_UART1_BASE_ADDR
54#define UART_VADDR MX51_AIPS1_IO_ADDRESS(MX51_UART1_BASE_ADDR)
55#endif 45#endif
56 46
57#ifdef CONFIG_ARCH_MXC91231 47#ifdef CONFIG_ARCH_MXC91231
58#ifdef UART_PADDR 48#ifdef UART_PADDR
59#error "CONFIG_DEBUG_LL is incompatible with multiple archs" 49#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
60#endif 50#endif
61#include <mach/mxc91231.h>
62#define UART_PADDR MXC91231_UART2_BASE_ADDR 51#define UART_PADDR MXC91231_UART2_BASE_ADDR
63#define UART_VADDR MXC91231_IO_ADDRESS(MXC91231_UART2_BASE_ADDR)
64#endif 52#endif
53
54#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
55
65 .macro addruart, rp, rv 56 .macro addruart, rp, rv
66 ldr \rp, =UART_PADDR @ physical 57 ldr \rp, =UART_PADDR @ physical
67 ldr \rv, =UART_VADDR @ virtual 58 ldr \rv, =UART_VADDR @ virtual
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 8c6896fd1e5f..8658c9caa650 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -10,9 +10,19 @@
10#include <linux/platform_device.h> 10#include <linux/platform_device.h>
11#include <linux/init.h> 11#include <linux/init.h>
12 12
13struct platform_device *imx_add_platform_device(const char *name, int id, 13struct platform_device *imx_add_platform_device_dmamask(
14 const char *name, int id,
14 const struct resource *res, unsigned int num_resources, 15 const struct resource *res, unsigned int num_resources,
15 const void *data, size_t size_data); 16 const void *data, size_t size_data, u64 dmamask);
17
18static inline struct platform_device *imx_add_platform_device(
19 const char *name, int id,
20 const struct resource *res, unsigned int num_resources,
21 const void *data, size_t size_data)
22{
23 return imx_add_platform_device_dmamask(
24 name, id, res, num_resources, data, size_data, 0);
25}
16 26
17#include <linux/fec.h> 27#include <linux/fec.h>
18struct imx_fec_data { 28struct imx_fec_data {
@@ -24,15 +34,63 @@ struct platform_device *__init imx_add_fec(
24 const struct fec_platform_data *pdata); 34 const struct fec_platform_data *pdata);
25 35
26#include <linux/can/platform/flexcan.h> 36#include <linux/can/platform/flexcan.h>
27struct platform_device *__init imx_add_flexcan(int id, 37struct imx_flexcan_data {
28 resource_size_t iobase, resource_size_t iosize, 38 int id;
29 resource_size_t irq, 39 resource_size_t iobase;
40 resource_size_t iosize;
41 resource_size_t irq;
42};
43struct platform_device *__init imx_add_flexcan(
44 const struct imx_flexcan_data *data,
30 const struct flexcan_platform_data *pdata); 45 const struct flexcan_platform_data *pdata);
31 46
47#include <linux/fsl_devices.h>
48struct imx_fsl_usb2_udc_data {
49 resource_size_t iobase;
50 resource_size_t irq;
51};
52struct platform_device *__init imx_add_fsl_usb2_udc(
53 const struct imx_fsl_usb2_udc_data *data,
54 const struct fsl_usb2_platform_data *pdata);
55
32#include <linux/gpio_keys.h> 56#include <linux/gpio_keys.h>
33struct platform_device *__init imx_add_gpio_keys( 57struct platform_device *__init imx_add_gpio_keys(
34 const struct gpio_keys_platform_data *pdata); 58 const struct gpio_keys_platform_data *pdata);
35 59
60#include <mach/mx21-usbhost.h>
61struct imx_imx21_hcd_data {
62 resource_size_t iobase;
63 resource_size_t irq;
64};
65struct platform_device *__init imx_add_imx21_hcd(
66 const struct imx_imx21_hcd_data *data,
67 const struct mx21_usbh_platform_data *pdata);
68
69struct imx_imx2_wdt_data {
70 int id;
71 resource_size_t iobase;
72 resource_size_t iosize;
73};
74struct platform_device *__init imx_add_imx2_wdt(
75 const struct imx_imx2_wdt_data *data);
76
77struct imx_imxdi_rtc_data {
78 resource_size_t iobase;
79 resource_size_t irq;
80};
81struct platform_device *__init imx_add_imxdi_rtc(
82 const struct imx_imxdi_rtc_data *data);
83
84#include <mach/imxfb.h>
85struct imx_imx_fb_data {
86 resource_size_t iobase;
87 resource_size_t iosize;
88 resource_size_t irq;
89};
90struct platform_device *__init imx_add_imx_fb(
91 const struct imx_imx_fb_data *data,
92 const struct imx_fb_platform_data *pdata);
93
36#include <mach/i2c.h> 94#include <mach/i2c.h>
37struct imx_imx_i2c_data { 95struct imx_imx_i2c_data {
38 int id; 96 int id;
@@ -44,6 +102,16 @@ struct platform_device *__init imx_add_imx_i2c(
44 const struct imx_imx_i2c_data *data, 102 const struct imx_imx_i2c_data *data,
45 const struct imxi2c_platform_data *pdata); 103 const struct imxi2c_platform_data *pdata);
46 104
105#include <linux/input/matrix_keypad.h>
106struct imx_imx_keypad_data {
107 resource_size_t iobase;
108 resource_size_t iosize;
109 resource_size_t irq;
110};
111struct platform_device *__init imx_add_imx_keypad(
112 const struct imx_imx_keypad_data *data,
113 const struct matrix_keymap_data *pdata);
114
47#include <mach/ssi.h> 115#include <mach/ssi.h>
48struct imx_imx_ssi_data { 116struct imx_imx_ssi_data {
49 int id; 117 int id;
@@ -82,6 +150,67 @@ struct platform_device *__init imx_add_imx_uart_1irq(
82 const struct imx_imx_uart_1irq_data *data, 150 const struct imx_imx_uart_1irq_data *data,
83 const struct imxuart_platform_data *pdata); 151 const struct imxuart_platform_data *pdata);
84 152
153#include <mach/usb.h>
154struct imx_imx_udc_data {
155 resource_size_t iobase;
156 resource_size_t iosize;
157 resource_size_t irq0;
158 resource_size_t irq1;
159 resource_size_t irq2;
160 resource_size_t irq3;
161 resource_size_t irq4;
162 resource_size_t irq5;
163 resource_size_t irq6;
164};
165struct platform_device *__init imx_add_imx_udc(
166 const struct imx_imx_udc_data *data,
167 const struct imxusb_platform_data *pdata);
168
169#include <mach/mx1_camera.h>
170struct imx_mx1_camera_data {
171 resource_size_t iobase;
172 resource_size_t iosize;
173 resource_size_t irq;
174};
175struct platform_device *__init imx_add_mx1_camera(
176 const struct imx_mx1_camera_data *data,
177 const struct mx1_camera_pdata *pdata);
178
179#include <mach/mx2_cam.h>
180struct imx_mx2_camera_data {
181 resource_size_t iobasecsi;
182 resource_size_t iosizecsi;
183 resource_size_t irqcsi;
184 resource_size_t iobaseemmaprp;
185 resource_size_t iosizeemmaprp;
186 resource_size_t irqemmaprp;
187};
188struct platform_device *__init imx_add_mx2_camera(
189 const struct imx_mx2_camera_data *data,
190 const struct mx2_camera_platform_data *pdata);
191
192#include <mach/mxc_ehci.h>
193struct imx_mxc_ehci_data {
194 int id;
195 resource_size_t iobase;
196 resource_size_t irq;
197};
198struct platform_device *__init imx_add_mxc_ehci(
199 const struct imx_mxc_ehci_data *data,
200 const struct mxc_usbh_platform_data *pdata);
201
202#include <mach/mmc.h>
203struct imx_mxc_mmc_data {
204 int id;
205 resource_size_t iobase;
206 resource_size_t iosize;
207 resource_size_t irq;
208 resource_size_t dmareq;
209};
210struct platform_device *__init imx_add_mxc_mmc(
211 const struct imx_mxc_mmc_data *data,
212 const struct imxmmc_platform_data *pdata);
213
85#include <mach/mxc_nand.h> 214#include <mach/mxc_nand.h>
86struct imx_mxc_nand_data { 215struct imx_mxc_nand_data {
87 /* 216 /*
@@ -99,24 +228,39 @@ struct platform_device *__init imx_add_mxc_nand(
99 const struct imx_mxc_nand_data *data, 228 const struct imx_mxc_nand_data *data,
100 const struct mxc_nand_platform_data *pdata); 229 const struct mxc_nand_platform_data *pdata);
101 230
102#include <mach/spi.h> 231struct imx_mxc_pwm_data {
103struct imx_spi_imx_data {
104 const char *devid;
105 int id; 232 int id;
106 resource_size_t iobase; 233 resource_size_t iobase;
107 resource_size_t iosize; 234 resource_size_t iosize;
108 int irq; 235 resource_size_t irq;
109}; 236};
110struct platform_device *__init imx_add_spi_imx( 237struct platform_device *__init imx_add_mxc_pwm(
111 const struct imx_spi_imx_data *data, 238 const struct imx_mxc_pwm_data *data);
112 const struct spi_imx_master *pdata); 239
240struct imx_mxc_w1_data {
241 resource_size_t iobase;
242};
243struct platform_device *__init imx_add_mxc_w1(
244 const struct imx_mxc_w1_data *data);
113 245
114#include <mach/esdhc.h> 246#include <mach/esdhc.h>
115struct imx_esdhc_imx_data { 247struct imx_sdhci_esdhc_imx_data {
116 int id; 248 int id;
117 resource_size_t iobase; 249 resource_size_t iobase;
118 resource_size_t irq; 250 resource_size_t irq;
119}; 251};
120struct platform_device *__init imx_add_esdhc( 252struct platform_device *__init imx_add_sdhci_esdhc_imx(
121 const struct imx_esdhc_imx_data *data, 253 const struct imx_sdhci_esdhc_imx_data *data,
122 const struct esdhc_platform_data *pdata); 254 const struct esdhc_platform_data *pdata);
255
256#include <mach/spi.h>
257struct imx_spi_imx_data {
258 const char *devid;
259 int id;
260 resource_size_t iobase;
261 resource_size_t iosize;
262 int irq;
263};
264struct platform_device *__init imx_add_spi_imx(
265 const struct imx_spi_imx_data *data,
266 const struct spi_imx_master *pdata);
diff --git a/arch/arm/plat-mxc/include/mach/entry-macro.S b/arch/arm/plat-mxc/include/mach/entry-macro.S
index aeb08697726b..bd9bb9799141 100644
--- a/arch/arm/plat-mxc/include/mach/entry-macro.S
+++ b/arch/arm/plat-mxc/include/mach/entry-macro.S
@@ -54,15 +54,15 @@
54#elif defined CONFIG_MXC_TZIC 54#elif defined CONFIG_MXC_TZIC
55 @ Load offset & priority of the highest priority 55 @ Load offset & priority of the highest priority
56 @ interrupt pending. 56 @ interrupt pending.
57 @ 0x080 is INTSEC0 register
57 @ 0xD80 is HIPND0 register 58 @ 0xD80 is HIPND0 register
58 mov \irqnr, #0 59 mov \irqnr, #0
59 mov \irqstat, #0x0D80 601000: add \irqstat, \base, \irqnr, lsr #3
601000: 61 ldr \tmp, [\irqstat, #0xd80]
61 ldr \tmp, [\irqstat, \base] 62 ldr \irqstat, [\irqstat, #0x080]
62 cmp \tmp, #0 63 ands \tmp, \tmp, \irqstat
63 bne 1001f 64 bne 1001f
64 addeq \irqnr, \irqnr, #32 65 add \irqnr, \irqnr, #32
65 addeq \irqstat, \irqstat, #4
66 cmp \irqnr, #128 66 cmp \irqnr, #128
67 blo 1000b 67 blo 1000b
68 b 2001f 68 b 2001f
diff --git a/arch/arm/plat-mxc/include/mach/gpio.h b/arch/arm/plat-mxc/include/mach/gpio.h
index af33b74f569e..0044e2f1bea8 100644
--- a/arch/arm/plat-mxc/include/mach/gpio.h
+++ b/arch/arm/plat-mxc/include/mach/gpio.h
@@ -23,6 +23,11 @@
23#include <mach/hardware.h> 23#include <mach/hardware.h>
24#include <asm-generic/gpio.h> 24#include <asm-generic/gpio.h>
25 25
26
27/* There's a off-by-one betweem the gpio bank number and the gpiochip */
28/* range e.g. GPIO_1_5 is gpio 5 under linux */
29#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
30
26/* use gpiolib dispatchers */ 31/* use gpiolib dispatchers */
27#define gpio_get_value __gpio_get_value 32#define gpio_get_value __gpio_get_value
28#define gpio_set_value __gpio_set_value 33#define gpio_set_value __gpio_set_value
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index ebadf4ac43fc..26bb1bab4aeb 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -22,13 +22,92 @@
22 22
23#include <asm/sizes.h> 23#include <asm/sizes.h>
24 24
25#define IMX_IO_ADDRESS(addr, module) \ 25#ifdef __ASSEMBLER__
26 ((void __force __iomem *) \ 26#define IOMEM(addr) (addr)
27 (((unsigned long)((addr) - (module ## _BASE_ADDR)) < module ## _SIZE) ?\ 27#else
28 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)) 28#define IOMEM(addr) ((void __force __iomem *)(addr))
29#endif
30
31#define IMX_IO_P2V_MODULE(addr, module) \
32 (((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
33 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
34
35/*
36 * This is rather complicated for humans and ugly to verify, but for a machine
37 * it's OK. Still more as it is usually only applied to constants. The upsides
38 * on using this approach are:
39 *
40 * - same mapping on all i.MX machines
41 * - works for assembler, too
42 * - no need to nurture #defines for virtual addresses
43 *
44 * The downside it, it's hard to verify (but I have a script for that).
45 *
46 * Obviously this needs to be injective for each SoC. In general it maps the
47 * whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
48 * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
49 *
50 * It applies the following mappings for the different SoCs:
51 *
52 * mx1:
53 * IO 0x00200000+0x100000 -> 0xf4000000+0x100000
54 * mx21:
55 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
56 * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
57 * X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
58 * mx25:
59 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
60 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
61 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
62 * mx27:
63 * AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
64 * SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
65 * X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
66 * mx31:
67 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
68 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
69 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
70 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
71 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
72 * mx35:
73 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
74 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
75 * AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
76 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
77 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
78 * mx50:
79 * TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
80 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
81 * AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
82 * AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
83 * mx51:
84 * IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
85 * DEBUG 0x60000000+0x100000 -> 0xf5000000+0x100000
86 * SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
87 * AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
88 * AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
89 * mxc91231:
90 * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000
91 * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
92 * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000
93 * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000
94 * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
95 * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
96 * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000
97 * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
98 */
99#define IMX_IO_P2V(x) ( \
100 0xf4000000 + \
101 (((x) & 0x50000000) >> 6) + \
102 (((x) & 0x0b000000) >> 4) + \
103 (((x) & 0x000fffff)))
104
105#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
29 106
30#ifdef CONFIG_ARCH_MX5 107#ifdef CONFIG_ARCH_MX5
108#include <mach/mx50.h>
31#include <mach/mx51.h> 109#include <mach/mx51.h>
110#include <mach/mx53.h>
32#endif 111#endif
33 112
34#ifdef CONFIG_ARCH_MX3 113#ifdef CONFIG_ARCH_MX3
@@ -61,4 +140,11 @@
61 140
62#include <mach/mxc.h> 141#include <mach/mxc.h>
63 142
143#define imx_map_entry(soc, name, _type) { \
144 .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
145 .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
146 .length = soc ## _ ## name ## _SIZE, \
147 .type = _type, \
148}
149
64#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */ 150#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/imxfb.h b/arch/arm/plat-mxc/include/mach/imxfb.h
index 5263506b7ddf..9de8f062ad5d 100644
--- a/arch/arm/plat-mxc/include/mach/imxfb.h
+++ b/arch/arm/plat-mxc/include/mach/imxfb.h
@@ -1,6 +1,8 @@
1/* 1/*
2 * This structure describes the machine which we are running on. 2 * This structure describes the machine which we are running on.
3 */ 3 */
4#ifndef __MACH_IMXFB_H__
5#define __MACH_IMXFB_H__
4 6
5#include <linux/fb.h> 7#include <linux/fb.h>
6 8
@@ -79,3 +81,4 @@ struct imx_fb_platform_data {
79}; 81};
80 82
81void set_imx_fb_info(struct imx_fb_platform_data *); 83void set_imx_fb_info(struct imx_fb_platform_data *);
84#endif /* ifndef __MACH_IMXFB_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx50.h b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
new file mode 100644
index 000000000000..058a922ca147
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx50.h
@@ -0,0 +1,977 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_IOMUX_MX50_H__
20#define __MACH_IOMUX_MX50_H__
21
22#include <mach/iomux-v3.h>
23
24#define MX50_ELCDIF_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
25
26#define MX50_SD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
27 PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_HIGH)
28
29#define MX50_UART_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE)
30
31#define MX50_I2C_PAD_CTRL (PAD_CTL_ODE | PAD_CTL_DSE_HIGH | \
32 PAD_CTL_PUS_100K_UP | PAD_CTL_HYS)
33
34#define MX50_USB_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP)
36
37#define MX50_FEC_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
38 PAD_CTL_PUS_22K_UP | PAD_CTL_ODE | \
39 PAD_CTL_DSE_HIGH)
40
41#define MX50_OWIRE_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
42 PAD_CTL_PUS_100K_UP | PAD_CTL_ODE | \
43 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
44
45#define MX50_KEYPAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \
46 PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_HIGH)
47
48#define MX50_CSPI_SS_PAD (PAD_CTL_PKE | PAD_CTL_PUE | \
49 PAD_CTL_PUS_22K_UP | PAD_CTL_DSE_HIGH)
50
51#define MX50_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x2CC, 0x20, 0, 0x0, 0, NO_PAD_CTRL)
52#define MX50_PAD_KEY_COL0__GPIO_4_0 IOMUX_PAD(0x2CC, 0x20, 1, 0x0, 0, NO_PAD_CTRL)
53#define MX50_PAD_KEY_COL0__NANDF_CLE IOMUX_PAD(0x2CC, 0x20, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
54
55#define MX50_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x2D0, 0x24, 0, 0x0, 0, MX50_KEYPAD_CTRL)
56#define MX50_PAD_KEY_ROW0__GPIO_4_1 IOMUX_PAD(0x2D0, 0x24, 1, 0x0, 0, NO_PAD_CTRL)
57#define MX50_PAD_KEY_ROW0__NANDF_ALE IOMUX_PAD(0x2D0, 0x24, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
58
59#define MX50_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x2D4, 0x28, 0, 0x0, 0, NO_PAD_CTRL)
60#define MX50_PAD_KEY_COL1__GPIO_4_2 IOMUX_PAD(0x2D4, 0x28, 1, 0x0, 0, NO_PAD_CTRL)
61#define MX50_PAD_KEY_COL1__NANDF_CE0 IOMUX_PAD(0x2D4, 0x28, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
62
63#define MX50_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x2D8, 0x2C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
64#define MX50_PAD_KEY_ROW1__GPIO_4_3 IOMUX_PAD(0x2D8, 0x2C, 1, 0x0, 0, NO_PAD_CTRL)
65#define MX50_PAD_KEY_ROW1__NANDF_CE1 IOMUX_PAD(0x2D8, 0x2C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
66
67#define MX50_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x2DC, 0x30, 0, 0x0, 0, MX50_KEYPAD_CTRL)
68#define MX50_PAD_KEY_COL2__GPIO_4_4 IOMUX_PAD(0x2DC, 0x30, 1, 0x0, 0, NO_PAD_CTRL)
69#define MX50_PAD_KEY_COL2__NANDF_CE2 IOMUX_PAD(0x2DC, 0x30, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
70
71#define MX50_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x2E0, 0x34, 0, 0x0, 0, MX50_KEYPAD_CTRL)
72#define MX50_PAD_KEY_ROW2__GPIO_4_5 IOMUX_PAD(0x2E0, 0x34, 1, 0x0, 0, NO_PAD_CTRL)
73#define MX50_PAD_KEY_ROW2__NANDF_CE3 IOMUX_PAD(0x2E0, 0x34, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
74
75#define MX50_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x2E4, 0x38, 0, 0x0, 0, NO_PAD_CTRL)
76#define MX50_PAD_KEY_COL3__GPIO_4_6 IOMUX_PAD(0x2E4, 0x38, 1, 0x0, 0, NO_PAD_CTRL)
77#define MX50_PAD_KEY_COL3__NANDF_READY IOMUX_PAD(0x2E4, 0x38, 2, 0x7b4, 0, PAD_CTL_PKE | \
78 PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
79#define MX50_PAD_KEY_COL3__SDMA_EXT0 IOMUX_PAD(0x2E4, 0x38, 6, 0x7b8, 0, NO_PAD_CTRL)
80
81#define MX50_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x2E8, 0x3C, 0, 0x0, 0, MX50_KEYPAD_CTRL)
82#define MX50_PAD_KEY_ROW3__GPIO_4_7 IOMUX_PAD(0x2E8, 0x3C, 1, 0x0, 0, NO_PAD_CTRL)
83#define MX50_PAD_KEY_ROW3__NANDF_DQS IOMUX_PAD(0x2E8, 0x3C, 2, 0x7b0, 0, PAD_CTL_DSE_HIGH)
84#define MX50_PAD_KEY_ROW3__SDMA_EXT1 IOMUX_PAD(0x2E8, 0x3C, 6, 0x7bc, 0, NO_PAD_CTRL)
85
86#define MX50_PAD_I2C1_SCL__I2C1_SCL IOMUX_PAD(0x2EC, 0x40, IOMUX_CONFIG_SION, 0x0, 0, \
87 MX50_I2C_PAD_CTRL)
88#define MX50_PAD_I2C1_SCL__GPIO_6_18 IOMUX_PAD(0x2EC, 0x40, 1, 0x0, 0, NO_PAD_CTRL)
89#define MX50_PAD_I2C1_SCL__UART2_TXD IOMUX_PAD(0x2EC, 0x40, 2, 0x7cc, 0, MX50_UART_PAD_CTRL)
90
91#define MX50_PAD_I2C1_SDA__I2C1_SDA IOMUX_PAD(0x2F0, 0x44, IOMUX_CONFIG_SION, 0x0, 0, \
92 MX50_I2C_PAD_CTRL)
93#define MX50_PAD_I2C1_SDA__GPIO_6_19 IOMUX_PAD(0x2F0, 0x44, 1, 0x0, 0, NO_PAD_CTRL)
94#define MX50_PAD_I2C1_SDA__UART2_RXD IOMUX_PAD(0x2F0, 0x44, 2, 0x7cc, 1, MX50_UART_PAD_CTRL)
95
96#define MX50_PAD_I2C2_SCL__I2C2_SCL IOMUX_PAD(0x2F4, 0x48, IOMUX_CONFIG_SION, 0x0, 0, \
97 MX50_I2C_PAD_CTRL)
98#define MX50_PAD_I2C2_SCL__GPIO_6_20 IOMUX_PAD(0x2F4, 0x48, 1, 0x0, 0, NO_PAD_CTRL)
99#define MX50_PAD_I2C2_SCL__UART2_CTS IOMUX_PAD(0x2F4, 0x48, 2, 0x7c8, 0, MX50_UART_PAD_CTRL)
100#define MX50_PAD_I2C2_SCL__DCDC_OK IOMUX_PAD(0x2F4, 0x48, 7, 0x0, 0, NO_PAD_CTRL)
101
102#define MX50_PAD_I2C2_SDA__I2C2_SDA IOMUX_PAD(0x2F8, 0x4C, IOMUX_CONFIG_SION, 0x0, 0, \
103 MX50_I2C_PAD_CTRL)
104#define MX50_PAD_I2C2_SDA__GPIO_6_21 IOMUX_PAD(0x2F8, 0x4C, 1, 0x0, 0, NO_PAD_CTRL)
105#define MX50_PAD_I2C2_SDA__UART2_RTS IOMUX_PAD(0x2F8, 0x4C, 2, 0x7c8, 1, MX50_UART_PAD_CTRL)
106#define MX50_PAD_I2C2_SDA__PWRSTABLE IOMUX_PAD(0x2F8, 0x4C, 7, 0x0, 0, NO_PAD_CTRL)
107
108#define MX50_PAD_I2C3_SCL__I2C3_SCL IOMUX_PAD(0x2FC, 0x50, IOMUX_CONFIG_SION, 0x0, 0, \
109 MX50_I2C_PAD_CTRL)
110#define MX50_PAD_I2C3_SCL__GPIO_6_22 IOMUX_PAD(0x2FC, 0x50, 1, 0x0, 0, NO_PAD_CTRL)
111#define MX50_PAD_I2C3_SCL__FEC_MDC IOMUX_PAD(0x2FC, 0x50, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
112#define MX50_PAD_I2C3_SCL__PMIC_RDY IOMUX_PAD(0x2FC, 0x50, 3, 0x0, 0, NO_PAD_CTRL)
113#define MX50_PAD_I2C3_SCL__GPT_CAPIN1 IOMUX_PAD(0x2FC, 0x50, 5, 0x0, 0, NO_PAD_CTRL)
114#define MX50_PAD_I2C3_SCL__USBOTG_OC IOMUX_PAD(0x2FC, 0x50, 7, 0x7E8, 0, MX50_USB_PAD_CTRL)
115
116#define MX50_PAD_I2C3_SDA__I2C3_SDA IOMUX_PAD(0x300, 0x54, IOMUX_CONFIG_SION, 0x0, 0, \
117 MX50_I2C_PAD_CTRL)
118#define MX50_PAD_I2C3_SDA__GPIO_6_23 IOMUX_PAD(0x300, 0x54, 1, 0x0, 0, NO_PAD_CTRL)
119#define MX50_PAD_I2C3_SDA__FEC_MDIO IOMUX_PAD(0x300, 0x54, 2, 0x774, 0, MX50_FEC_PAD_CTRL)
120#define MX50_PAD_I2C3_SDA__PWRFAIL_INT IOMUX_PAD(0x300, 0x54, 3, 0x0, 0, NO_PAD_CTRL)
121#define MX50_PAD_I2C3_SDA__ALARM_DEB IOMUX_PAD(0x300, 0x54, 4, 0x0, 0, NO_PAD_CTRL)
122#define MX50_PAD_I2C3_SDA__GPT_CAPIN1 IOMUX_PAD(0x300, 0x54, 5, 0x0, 0, NO_PAD_CTRL)
123#define MX50_PAD_I2C3_SDA__USBOTG_PWR IOMUX_PAD(0x300, 0x54, 7, 0x0, 0, \
124 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
125
126#define MX50_PAD_PWM1__PWM1_PWMO IOMUX_PAD(0x304, 0x58, 0, 0x0, 0, NO_PAD_CTRL)
127#define MX50_PAD_PWM1__GPIO_6_24 IOMUX_PAD(0x304, 0x58, 1, 0x0, 0, NO_PAD_CTRL)
128#define MX50_PAD_PWM1__USBOTG_OC IOMUX_PAD(0x304, 0x58, 2, 0x7E8, 1, MX50_USB_PAD_CTRL)
129#define MX50_PAD_PWM1__GPT_CMPOUT1 IOMUX_PAD(0x304, 0x58, 5, 0x0, 0, NO_PAD_CTRL)
130
131#define MX50_PAD_PWM2__PWM2_PWMO IOMUX_PAD(0x308, 0x5C, 0, 0x0, 0, NO_PAD_CTRL)
132#define MX50_PAD_PWM2__GPIO_6_25 IOMUX_PAD(0x308, 0x5C, 1, 0x0, 0, NO_PAD_CTRL)
133#define MX50_PAD_PWM2__USBOTG_PWR IOMUX_PAD(0x308, 0x5C, 2, 0x0, 0, \
134 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
135#define MX50_PAD_PWM2__DCDC_PWM IOMUX_PAD(0x308, 0x5C, 4, 0x0, 0, NO_PAD_CTRL)
136#define MX50_PAD_PWM2__GPT_CMPOUT2 IOMUX_PAD(0x308, 0x5C, 5, 0x0, 0, NO_PAD_CTRL)
137#define MX50_PAD_PWM2__ANY_PU_RST IOMUX_PAD(0x308, 0x5C, 7, 0x0, 0, NO_PAD_CTRL)
138
139#define MX50_PAD_OWIRE__OWIRE IOMUX_PAD(0x30C, 0x60, 0, 0x0, 0, MX50_OWIRE_PAD_CTRL)
140#define MX50_PAD_OWIRE__GPIO_6_26 IOMUX_PAD(0x30C, 0x60, 1, 0x0, 0, NO_PAD_CTRL)
141#define MX50_PAD_OWIRE__USBH1_OC IOMUX_PAD(0x30C, 0x60, 2, 0x0, 0, MX50_USB_PAD_CTRL)
142#define MX50_PAD_OWIRE__SSI_EXT1_CLK IOMUX_PAD(0x30C, 0x60, 3, 0x0, 0, NO_PAD_CTRL)
143#define MX50_PAD_OWIRE__EPDC_PWRIRQ IOMUX_PAD(0x30C, 0x60, 4, 0x0, 0, NO_PAD_CTRL)
144#define MX50_PAD_OWIRE__GPT_CMPOUT3 IOMUX_PAD(0x30C, 0x60, 5, 0x0, 0, NO_PAD_CTRL)
145
146#define MX50_PAD_EPITO__EPITO IOMUX_PAD(0x310, 0x64, 0, 0x0, 0, NO_PAD_CTRL)
147#define MX50_PAD_EPITO__GPIO_6_27 IOMUX_PAD(0x310, 0x64, 1, 0x0, 0, NO_PAD_CTRL)
148#define MX50_PAD_EPITO__USBH1_PWR IOMUX_PAD(0x310, 0x64, 2, 0x0, 0, \
149 PAD_CTL_PKE | PAD_CTL_DSE_HIGH)
150#define MX50_PAD_EPITO__SSI_EXT2_CLK IOMUX_PAD(0x310, 0x64, 3, 0x0, 0, NO_PAD_CTRL)
151#define MX50_PAD_EPITO__TOG_EN IOMUX_PAD(0x310, 0x64, 4, 0x0, 0, NO_PAD_CTRL)
152#define MX50_PAD_EPITO__GPT_CLKIN IOMUX_PAD(0x310, 0x64, 5, 0x0, 0, NO_PAD_CTRL)
153
154#define MX50_PAD_WDOG__WDOG IOMUX_PAD(0x314, 0x68, 0, 0x0, 0, NO_PAD_CTRL)
155#define MX50_PAD_WDOG__GPIO_6_28 IOMUX_PAD(0x314, 0x68, 1, 0x0, 0, NO_PAD_CTRL)
156#define MX50_PAD_WDOG__WDOG_RST IOMUX_PAD(0x314, 0x68, 2, 0x0, 0, NO_PAD_CTRL)
157#define MX50_PAD_WDOG__XTAL32K IOMUX_PAD(0x314, 0x68, 6, 0x0, 0, NO_PAD_CTRL)
158
159#define MX50_PAD_SSI_TXFS__SSI_TXFS IOMUX_PAD(0x318, 0x6C, 0, 0x0, 0, NO_PAD_CTRL)
160#define MX50_PAD_SSI_TXFS__GPIO_6_0 IOMUX_PAD(0x318, 0x6C, 1, 0x0, 0, NO_PAD_CTRL)
161
162#define MX50_PAD_SSI_TXC__SSI_TXC IOMUX_PAD(0x31C, 0x70, 0, 0x0, 0, NO_PAD_CTRL)
163#define MX50_PAD_SSI_TXC__GPIO_6_1 IOMUX_PAD(0x31C, 0x70, 1, 0x0, 0, NO_PAD_CTRL)
164
165#define MX50_PAD_SSI_TXD__SSI_TXD IOMUX_PAD(0x320, 0x74, 0, 0x0, 0, NO_PAD_CTRL)
166#define MX50_PAD_SSI_TXD__GPIO_6_2 IOMUX_PAD(0x320, 0x74, 1, 0x0, 0, NO_PAD_CTRL)
167#define MX50_PAD_SSI_TXD__CSPI_RDY IOMUX_PAD(0x320, 0x74, 4, 0x6e8, 0, NO_PAD_CTRL)
168
169#define MX50_PAD_SSI_RXD__SSI_RXD IOMUX_PAD(0x324, 0x78, 0, 0x0, 0, NO_PAD_CTRL)
170#define MX50_PAD_SSI_RXD__GPIO_6_3 IOMUX_PAD(0x324, 0x78, 1, 0x0, 0, NO_PAD_CTRL)
171#define MX50_PAD_SSI_RXD__CSPI_SS3 IOMUX_PAD(0x324, 0x78, 4, 0x6f4, 0, MX50_CSPI_SS_PAD)
172
173#define MX50_PAD_SSI_RXFS__AUD3_RXFS IOMUX_PAD(0x328, 0x7C, 0, 0x0, 0, NO_PAD_CTRL)
174#define MX50_PAD_SSI_RXFS__GPIO_6_4 IOMUX_PAD(0x328, 0x7C, 1, 0x0, 0, NO_PAD_CTRL)
175#define MX50_PAD_SSI_RXFS__UART5_TXD IOMUX_PAD(0x328, 0x7C, 2, 0x7e4, 0, MX50_UART_PAD_CTRL)
176#define MX50_PAD_SSI_RXFS__WEIM_D6 IOMUX_PAD(0x328, 0x7C, 3, 0x804, 0, NO_PAD_CTRL)
177#define MX50_PAD_SSI_RXFS__CSPI_SS2 IOMUX_PAD(0x328, 0x7C, 4, 0x6f0, 0, MX50_CSPI_SS_PAD)
178#define MX50_PAD_SSI_RXFS__FEC_COL IOMUX_PAD(0x328, 0x7C, 5, 0x770, 0, PAD_CTL_DSE_HIGH)
179#define MX50_PAD_SSI_RXFS__FEC_MDC IOMUX_PAD(0x328, 0x7C, 6, 0x0, 0, PAD_CTL_DSE_HIGH)
180
181#define MX50_PAD_SSI_RXC__AUD3_RXC IOMUX_PAD(0x32C, 0x80, 0, 0x0, 0, NO_PAD_CTRL)
182#define MX50_PAD_SSI_RXC__GPIO_6_5 IOMUX_PAD(0x32C, 0x80, 1, 0x0, 0, NO_PAD_CTRL)
183#define MX50_PAD_SSI_RXC__UART5_RXD IOMUX_PAD(0x32C, 0x80, 2, 0x7e4, 1, MX50_UART_PAD_CTRL)
184#define MX50_PAD_SSI_RXC__WEIM_D7 IOMUX_PAD(0x32C, 0x80, 3, 0x808, 0, NO_PAD_CTRL)
185#define MX50_PAD_SSI_RXC__CSPI_SS1 IOMUX_PAD(0x32C, 0x80, 4, 0x6ec, 0, MX50_CSPI_SS_PAD)
186#define MX50_PAD_SSI_RXC__FEC_RX_CLK IOMUX_PAD(0x32C, 0x80, 5, 0x780, 0, NO_PAD_CTRL)
187#define MX50_PAD_SSI_RXC__FEC_MDIO IOMUX_PAD(0x32C, 0x80, 6, 0x774, 1, MX50_FEC_PAD_CTRL)
188
189#define MX50_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x330, 0x84, 0, 0x7c4, 0, MX50_UART_PAD_CTRL)
190#define MX50_PAD_UART1_TXD__GPIO_6_6 IOMUX_PAD(0x330, 0x84, 1, 0x0, 0, NO_PAD_CTRL)
191
192#define MX50_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x334, 0x88, 0, 0x7c4, 1, MX50_UART_PAD_CTRL)
193#define MX50_PAD_UART1_RXD__GPIO_6_7 IOMUX_PAD(0x334, 0x88, 1, 0x0, 0, NO_PAD_CTRL)
194
195#define MX50_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x338, 0x8C, 0, 0x7c0, 0, MX50_UART_PAD_CTRL)
196#define MX50_PAD_UART1_CTS__GPIO_6_8 IOMUX_PAD(0x338, 0x8C, 1, 0x0, 0, NO_PAD_CTRL)
197#define MX50_PAD_UART1_CTS__UART5_TXD IOMUX_PAD(0x338, 0x8C, 2, 0x7e4, 2, MX50_UART_PAD_CTRL)
198#define MX50_PAD_UART1_CTS__SD4_D4 IOMUX_PAD(0x338, 0x8C, 4, 0x760, 0, MX50_SD_PAD_CTRL)
199#define MX50_PAD_UART1_CTS__SD4_CMD IOMUX_PAD(0x338, 0x8C, 5, 0x74c, 0, MX50_SD_PAD_CTRL)
200
201#define MX50_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x33C, 0x90, 0, 0x7c0, 1, MX50_UART_PAD_CTRL)
202#define MX50_PAD_UART1_RTS__GPIO_6_9 IOMUX_PAD(0x33C, 0x90, 1, 0x0, 0, NO_PAD_CTRL)
203#define MX50_PAD_UART1_RTS__UART5_RXD IOMUX_PAD(0x33C, 0x90, 2, 0x7e4, 3, MX50_UART_PAD_CTRL)
204#define MX50_PAD_UART1_RTS__SD4_D5 IOMUX_PAD(0x33C, 0x90, 4, 0x0, 1, MX50_SD_PAD_CTRL)
205#define MX50_PAD_UART1_RTS__SD4_CLK IOMUX_PAD(0x33C, 0x90, 5, 0x0, 1, MX50_SD_PAD_CTRL)
206
207#define MX50_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x340, 0x94, 0, 0x7cc, 2, MX50_UART_PAD_CTRL)
208#define MX50_PAD_UART2_TXD__GPIO_6_10 IOMUX_PAD(0x340, 0x94, 1, 0x0, 0, NO_PAD_CTRL)
209#define MX50_PAD_UART2_TXD__SD4_D6 IOMUX_PAD(0x340, 0x94, 4, 0x768, 0, MX50_SD_PAD_CTRL)
210#define MX50_PAD_UART2_TXD__SD4_D4 IOMUX_PAD(0x340, 0x94, 5, 0x760, 1, MX50_SD_PAD_CTRL)
211
212#define MX50_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x344, 0x98, 0, 0x7cc, 3, MX50_UART_PAD_CTRL)
213#define MX50_PAD_UART2_RXD__GPIO_6_11 IOMUX_PAD(0x344, 0x98, 1, 0x0, 0, NO_PAD_CTRL)
214#define MX50_PAD_UART2_RXD__SD4_D7 IOMUX_PAD(0x344, 0x98, 4, 0x76c, 0, MX50_SD_PAD_CTRL)
215#define MX50_PAD_UART2_RXD__SD4_D5 IOMUX_PAD(0x344, 0x98, 5, 0x764, 1, MX50_SD_PAD_CTRL)
216
217#define MX50_PAD_UART2_CTS__UART2_CTS IOMUX_PAD(0x348, 0x9C, 0, 0x7c8, 2, MX50_UART_PAD_CTRL)
218#define MX50_PAD_UART2_CTS__GPIO_6_12 IOMUX_PAD(0x348, 0x9C, 1, 0x0, 0, NO_PAD_CTRL)
219#define MX50_PAD_UART2_CTS__SD4_CMD IOMUX_PAD(0x348, 0x9C, 4, 0x74c, 1, MX50_SD_PAD_CTRL)
220#define MX50_PAD_UART2_CTS__SD4_D6 IOMUX_PAD(0x348, 0x9C, 5, 0x768, 1, MX50_SD_PAD_CTRL)
221
222#define MX50_PAD_UART2_RTS__UART2_RTS IOMUX_PAD(0x34C, 0xA0, 0, 0x7c8, 3, MX50_UART_PAD_CTRL)
223#define MX50_PAD_UART2_RTS__GPIO_6_13 IOMUX_PAD(0x34C, 0xA0, 1, 0x0, 0, NO_PAD_CTRL)
224#define MX50_PAD_UART2_RTS__SD4_CLK IOMUX_PAD(0x34C, 0xA0, 4, 0x748, 1, MX50_SD_PAD_CTRL)
225#define MX50_PAD_UART2_RTS__SD4_D7 IOMUX_PAD(0x34C, 0xA0, 5, 0x76c, 1, MX50_SD_PAD_CTRL)
226
227#define MX50_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x350, 0xA4, 0, 0x7d4, 0, MX50_UART_PAD_CTRL)
228#define MX50_PAD_UART3_TXD__GPIO_6_14 IOMUX_PAD(0x350, 0xA4, 1, 0x0, 0, NO_PAD_CTRL)
229#define MX50_PAD_UART3_TXD__SD1_D4 IOMUX_PAD(0x350, 0xA4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
230#define MX50_PAD_UART3_TXD__SD4_D0 IOMUX_PAD(0x350, 0xA4, 4, 0x750, 0, MX50_SD_PAD_CTRL)
231#define MX50_PAD_UART3_TXD__SD2_WP IOMUX_PAD(0x350, 0xA4, 5, 0x744, 0, MX50_SD_PAD_CTRL)
232#define MX50_PAD_UART3_TXD__WEIM_D12 IOMUX_PAD(0x350, 0xA4, 6, 0x81c, 0, NO_PAD_CTRL)
233
234#define MX50_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x354, 0xA8, 0, 0x7d4, 1, MX50_UART_PAD_CTRL)
235#define MX50_PAD_UART3_RXD__GPIO_6_15 IOMUX_PAD(0x354, 0xA8, 1, 0x0, 0, NO_PAD_CTRL)
236#define MX50_PAD_UART3_RXD__SD1_D5 IOMUX_PAD(0x354, 0xA8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
237#define MX50_PAD_UART3_RXD__SD4_D1 IOMUX_PAD(0x354, 0xA8, 4, 0x754, 0, MX50_SD_PAD_CTRL)
238#define MX50_PAD_UART3_RXD__SD2_CD IOMUX_PAD(0x354, 0xA8, 5, 0x740, 0, MX50_SD_PAD_CTRL)
239#define MX50_PAD_UART3_RXD__WEIM_D13 IOMUX_PAD(0x354, 0xA8, 6, 0x820, 0, NO_PAD_CTRL)
240
241#define MX50_PAD_UART4_TXD__UART4_TXD IOMUX_PAD(0x358, 0xAC, 0, 0x7dc, 0, MX50_UART_PAD_CTRL)
242#define MX50_PAD_UART4_TXD__GPIO_6_16 IOMUX_PAD(0x358, 0xAC, 1, 0x0, 0, NO_PAD_CTRL)
243#define MX50_PAD_UART4_TXD__UART3_CTS IOMUX_PAD(0x358, 0xAC, 2, 0x7d0, 0, MX50_UART_PAD_CTRL)
244#define MX50_PAD_UART4_TXD__SD1_D6 IOMUX_PAD(0x358, 0xAC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
245#define MX50_PAD_UART4_TXD__SD4_D2 IOMUX_PAD(0x358, 0xAC, 4, 0x758, 0, MX50_SD_PAD_CTRL)
246#define MX50_PAD_UART4_TXD__SD2_LCTL IOMUX_PAD(0x358, 0xAC, 5, 0x0, 0, MX50_SD_PAD_CTRL)
247#define MX50_PAD_UART4_TXD__WEIM_D14 IOMUX_PAD(0x358, 0xAC, 6, 0x824, 0, NO_PAD_CTRL)
248
249#define MX50_PAD_UART4_RXD__UART4_RXD IOMUX_PAD(0x35C, 0xB0, 0, 0x7dc, 1, MX50_UART_PAD_CTRL)
250#define MX50_PAD_UART4_RXD__GPIO_6_17 IOMUX_PAD(0x35C, 0xB0, 1, 0x0, 0, NO_PAD_CTRL)
251#define MX50_PAD_UART4_RXD__UART3_RTS IOMUX_PAD(0x35C, 0xB0, 2, 0x7d0, 1, MX50_UART_PAD_CTRL)
252#define MX50_PAD_UART4_RXD__SD1_D7 IOMUX_PAD(0x35C, 0xB0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
253#define MX50_PAD_UART4_RXD__SD4_D3 IOMUX_PAD(0x35C, 0xB0, 4, 0x75c, 0, MX50_SD_PAD_CTRL)
254#define MX50_PAD_UART4_RXD__SD1_LCTL IOMUX_PAD(0x35C, 0xB0, 5, 0x0, 0, MX50_SD_PAD_CTRL)
255#define MX50_PAD_UART4_RXD__WEIM_D15 IOMUX_PAD(0x35C, 0xB0, 6, 0x828, 0, NO_PAD_CTRL)
256
257#define MX50_PAD_CSPI_SCLK__CSPI_SCLK IOMUX_PAD(0x360, 0xB4, 0, 0x0, 0, NO_PAD_CTRL)
258#define MX50_PAD_CSPI_SCLK__GPIO_4_8 IOMUX_PAD(0x360, 0xB4, 1, 0x0, 0, NO_PAD_CTRL)
259
260#define MX50_PAD_CSPI_MOSI__CSPI_MOSI IOMUX_PAD(0x364, 0xB8, 0, 0x0, 0, NO_PAD_CTRL)
261#define MX50_PAD_CSPI_MOSI__GPIO_4_9 IOMUX_PAD(0x364, 0xB8, 1, 0x0, 0, NO_PAD_CTRL)
262
263#define MX50_PAD_CSPI_MISO__CSPI_MISO IOMUX_PAD(0x368, 0xBC, 0, 0x0, 0, NO_PAD_CTRL)
264#define MX50_PAD_CSPI_MISO__GPIO_4_10 IOMUX_PAD(0x368, 0xBC, 1, 0x0, 0, NO_PAD_CTRL)
265
266#define MX50_PAD_CSPI_SS0__CSPI_SS0 IOMUX_PAD(0x36C, 0xC0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
267#define MX50_PAD_CSPI_SS0__GPIO_4_11 IOMUX_PAD(0x36C, 0xC0, 1, 0x0, 0, NO_PAD_CTRL)
268
269#define MX50_PAD_ECSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x370, 0xC4, 0, 0x0, 0, NO_PAD_CTRL)
270#define MX50_PAD_ECSPI1_SCLK__GPIO_4_12 IOMUX_PAD(0x370, 0xC4, 1, 0x0, 0, NO_PAD_CTRL)
271#define MX50_PAD_ECSPI1_SCLK__CSPI_RDY IOMUX_PAD(0x370, 0xC4, 2, 0x6e8, 1, NO_PAD_CTRL)
272#define MX50_PAD_ECSPI1_SCLK__ECSPI2_RDY IOMUX_PAD(0x370, 0xC4, 3, 0x0, 0, NO_PAD_CTRL)
273#define MX50_PAD_ECSPI1_SCLK__UART3_RTS IOMUX_PAD(0x370, 0xC4, 4, 0x7d0, 2, MX50_UART_PAD_CTRL)
274#define MX50_PAD_ECSPI1_SCLK__EPDC_SDCE6 IOMUX_PAD(0x370, 0xC4, 5, 0x0, 0, NO_PAD_CTRL)
275#define MX50_PAD_ECSPI1_SCLK__WEIM_D8 IOMUX_PAD(0x370, 0xC4, 7, 0x80c, 0, NO_PAD_CTRL)
276
277#define MX50_PAD_ECSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x374, 0xC8, 0, 0x0, 0, NO_PAD_CTRL)
278#define MX50_PAD_ECSPI1_MOSI__GPIO_4_13 IOMUX_PAD(0x374, 0xC8, 1, 0x0, 0, NO_PAD_CTRL)
279#define MX50_PAD_ECSPI1_MOSI__CSPI_SS1 IOMUX_PAD(0x374, 0xC8, 2, 0x6ec, 1, MX50_CSPI_SS_PAD)
280#define MX50_PAD_ECSPI1_MOSI__ECSPI2_SS1 IOMUX_PAD(0x374, 0xC8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
281#define MX50_PAD_ECSPI1_MOSI__UART3_CTS IOMUX_PAD(0x374, 0xC8, 4, 0x7d0, 3, MX50_UART_PAD_CTRL)
282#define MX50_PAD_ECSPI1_MOSI__EPDC_SDCE7 IOMUX_PAD(0x374, 0xC8, 5, 0x0, 0, NO_PAD_CTRL)
283#define MX50_PAD_ECSPI1_MOSI__WEIM_D9 IOMUX_PAD(0x374, 0xC8, 7, 0x810, 0, NO_PAD_CTRL)
284
285#define MX50_PAD_ECSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x378, 0xCC, 0, 0x0, 0, NO_PAD_CTRL)
286#define MX50_PAD_ECSPI1_MISO__GPIO_4_14 IOMUX_PAD(0x378, 0xCC, 1, 0x0, 0, NO_PAD_CTRL)
287#define MX50_PAD_ECSPI1_MISO__CSPI_SS2 IOMUX_PAD(0x378, 0xCC, 2, 0x6f0, 1, MX50_CSPI_SS_PAD)
288#define MX50_PAD_ECSPI1_MISO__ECSPI2_SS2 IOMUX_PAD(0x378, 0xCC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
289#define MX50_PAD_ECSPI1_MISO__UART4_RTS IOMUX_PAD(0x378, 0xCC, 4, 0x7d8, 0, MX50_UART_PAD_CTRL)
290#define MX50_PAD_ECSPI1_MISO__EPDC_SDCE8 IOMUX_PAD(0x378, 0xCC, 5, 0x0, 0, NO_PAD_CTRL)
291#define MX50_PAD_ECSPI1_MISO__WEIM_D10 IOMUX_PAD(0x378, 0xCC, 7, 0x814, 0, NO_PAD_CTRL)
292
293#define MX50_PAD_ECSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x37C, 0xD0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
294#define MX50_PAD_ECSPI1_SS0__GPIO_4_15 IOMUX_PAD(0x37C, 0xD0, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
295#define MX50_PAD_ECSPI1_SS0__CSPI_SS3 IOMUX_PAD(0x37C, 0xD0, 2, 0x6f4, 1, MX50_CSPI_SS_PAD)
296#define MX50_PAD_ECSPI1_SS0__ECSPI2_SS3 IOMUX_PAD(0x37C, 0xD0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
297#define MX50_PAD_ECSPI1_SS0__UART4_CTS IOMUX_PAD(0x37C, 0xD0, 4, 0x7d8, 1, MX50_UART_PAD_CTRL)
298#define MX50_PAD_ECSPI1_SS0__EPDC_SDCE9 IOMUX_PAD(0x37C, 0xD0, 5, 0x0, 0, NO_PAD_CTRL)
299#define MX50_PAD_ECSPI1_SS0__WEIM_D11 IOMUX_PAD(0x37C, 0xD0, 7, 0x818, 0, NO_PAD_CTRL)
300
301#define MX50_PAD_ECSPI2_SCLK__ECSPI2_SCLK IOMUX_PAD(0x380, 0xD4, 0, 0x0, 0, NO_PAD_CTRL)
302#define MX50_PAD_ECSPI2_SCLK__GPIO_4_16 IOMUX_PAD(0x380, 0xD4, 1, 0x0, 0, NO_PAD_CTRL)
303#define MX50_PAD_ECSPI2_SCLK__ELCDIF_WR IOMUX_PAD(0x380, 0xD4, 2, 0x0, 0, NO_PAD_CTRL)
304#define MX50_PAD_ECSPI2_SCLK__ECSPI1_RDY IOMUX_PAD(0x380, 0xD4, 3, 0x0, 0, NO_PAD_CTRL)
305#define MX50_PAD_ECSPI2_SCLK__UART5_RTS IOMUX_PAD(0x380, 0xD4, 4, 0x7e0, 0, MX50_UART_PAD_CTRL)
306#define MX50_PAD_ECSPI2_SCLK__ELCDIF_DOTCLK IOMUX_PAD(0x380, 0xD4, 5, 0x0, 0, NO_PAD_CTRL)
307#define MX50_PAD_ECSPI2_SCLK__NANDF_CEN4 IOMUX_PAD(0x380, 0xD4, 6, 0x0, 0, NO_PAD_CTRL)
308#define MX50_PAD_ECSPI2_SCLK__WEIM_D8 IOMUX_PAD(0x380, 0xD4, 7, 0x80c, 1, NO_PAD_CTRL)
309
310#define MX50_PAD_ECSPI2_MOSI__ECSPI2_MOSI IOMUX_PAD(0x384, 0xD8, 0, 0x0, 0, NO_PAD_CTRL)
311#define MX50_PAD_ECSPI2_MOSI__GPIO_4_17 IOMUX_PAD(0x384, 0xD8, 1, 0x0, 0, NO_PAD_CTRL)
312#define MX50_PAD_ECSPI2_MOSI__ELCDIF_RD IOMUX_PAD(0x384, 0xD8, 2, 0x0, 0, NO_PAD_CTRL)
313#define MX50_PAD_ECSPI2_MOSI__ECSPI1_SS1 IOMUX_PAD(0x384, 0xD8, 3, 0x0, 0, MX50_CSPI_SS_PAD)
314#define MX50_PAD_ECSPI2_MOSI__UART5_CTS IOMUX_PAD(0x384, 0xD8, 4, 0x7e0, 1, MX50_UART_PAD_CTRL)
315#define MX50_PAD_ECSPI2_MOSI__ELCDIF_EN IOMUX_PAD(0x384, 0xD8, 5, 0x0, 0, NO_PAD_CTRL)
316#define MX50_PAD_ECSPI2_MOSI__NANDF_CEN5 IOMUX_PAD(0x384, 0xD8, 6, 0x0, 0, NO_PAD_CTRL)
317#define MX50_PAD_ECSPI2_MOSI__WEIM_D9 IOMUX_PAD(0x384, 0xD8, 7, 0x810, 1, NO_PAD_CTRL)
318
319#define MX50_PAD_ECSPI2_MISO__ECSPI2_MISO IOMUX_PAD(0x388, 0xDC, 0, 0x73c, 0, NO_PAD_CTRL)
320#define MX50_PAD_ECSPI2_MISO__GPIO_4_18 IOMUX_PAD(0x388, 0xDC, 1, 0x0, 0, PAD_CTL_PUS_100K_UP)
321#define MX50_PAD_ECSPI2_MISO__ELCDIF_RS IOMUX_PAD(0x388, 0xDC, 2, 0x0, 0, NO_PAD_CTRL)
322#define MX50_PAD_ECSPI2_MISO__ECSPI1_SS2 IOMUX_PAD(0x388, 0xDC, 3, 0x0, 0, MX50_CSPI_SS_PAD)
323#define MX50_PAD_ECSPI2_MISO__UART5_TXD IOMUX_PAD(0x388, 0xDC, 4, 0x7e4, 4, MX50_UART_PAD_CTRL)
324#define MX50_PAD_ECSPI2_MISO__ELCDIF_VSYNC IOMUX_PAD(0x388, 0xDC, 5, 0x0, 0, NO_PAD_CTRL)
325#define MX50_PAD_ECSPI2_MISO__NANDF_CEN6 IOMUX_PAD(0x388, 0xDC, 6, 0x0, 0, NO_PAD_CTRL)
326#define MX50_PAD_ECSPI2_MISO__WEIM_D10 IOMUX_PAD(0x388, 0xDC, 7, 0x814, 1, NO_PAD_CTRL)
327
328#define MX50_PAD_ECSPI2_SS0__ECSPI2_SS0 IOMUX_PAD(0x38C, 0xE0, 0, 0x0, 0, MX50_CSPI_SS_PAD)
329#define MX50_PAD_ECSPI2_SS0__GPIO_4_19 IOMUX_PAD(0x38C, 0xE0, 1, 0x0, 0, NO_PAD_CTRL)
330#define MX50_PAD_ECSPI2_SS0__ELCDIF_CS IOMUX_PAD(0x38C, 0xE0, 2, 0x0, 0, NO_PAD_CTRL)
331#define MX50_PAD_ECSPI2_SS0__ECSPI1_SS3 IOMUX_PAD(0x38C, 0xE0, 3, 0x0, 0, MX50_CSPI_SS_PAD)
332#define MX50_PAD_ECSPI2_SS0__UART5_RXD IOMUX_PAD(0x38C, 0xE0, 4, 0x7e4, 5, MX50_UART_PAD_CTRL)
333#define MX50_PAD_ECSPI2_SS0__ELCDIF_HSYNC IOMUX_PAD(0x38C, 0xE0, 5, 0x6f8, 0, NO_PAD_CTRL)
334#define MX50_PAD_ECSPI2_SS0__NANDF_CEN7 IOMUX_PAD(0x38C, 0xE0, 6, 0x0, 0, NO_PAD_CTRL)
335#define MX50_PAD_ECSPI2_SS0__WEIM_D11 IOMUX_PAD(0x38C, 0xE0, 7, 0x818, 1, NO_PAD_CTRL)
336
337#define MX50_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x390, 0xE4, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
338#define MX50_PAD_SD1_CLK__GPIO_5_0 IOMUX_PAD(0x390, 0xE4, 1, 0x0, 0, NO_PAD_CTRL)
339#define MX50_PAD_SD1_CLK__CLKO IOMUX_PAD(0x390, 0xE4, 7, 0x0, 0, NO_PAD_CTRL)
340
341#define MX50_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x394, 0xE8, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
342#define MX50_PAD_SD1_CMD__GPIO_5_1 IOMUX_PAD(0x394, 0xE8, 1, 0x0, 0, NO_PAD_CTRL)
343#define MX50_PAD_SD1_CMD__CLKO2 IOMUX_PAD(0x394, 0xE8, 7, 0x0, 0, NO_PAD_CTRL)
344
345#define MX50_PAD_SD1_D0__SD1_D0 IOMUX_PAD(0x398, 0xEC, 0, 0x0, 0, MX50_SD_PAD_CTRL)
346#define MX50_PAD_SD1_D0__GPIO_5_2 IOMUX_PAD(0x398, 0xEC, 1, 0x0, 0, NO_PAD_CTRL)
347#define MX50_PAD_SD1_D0__PLL1_BYP IOMUX_PAD(0x398, 0xEC, 7, 0x6dc, 0, NO_PAD_CTRL)
348
349#define MX50_PAD_SD1_D1__SD1_D1 IOMUX_PAD(0x39C, 0xF0, 0, 0x0, 0, MX50_SD_PAD_CTRL)
350#define MX50_PAD_SD1_D1__GPIO_5_3 IOMUX_PAD(0x39C, 0xF0, 1, 0x0, 0, NO_PAD_CTRL)
351#define MX50_PAD_SD1_D1__PLL2_BYP IOMUX_PAD(0x39C, 0xF0, 7, 0x6e0, 0, NO_PAD_CTRL)
352
353#define MX50_PAD_SD1_D2__SD1_D2 IOMUX_PAD(0x3A0, 0xF4, 0, 0x0, 0, MX50_SD_PAD_CTRL)
354#define MX50_PAD_SD1_D2__GPIO_5_4 IOMUX_PAD(0x3A0, 0xF4, 1, 0x0, 0, NO_PAD_CTRL)
355#define MX50_PAD_SD1_D2__PLL3_BYP IOMUX_PAD(0x3A0, 0xF4, 7, 0x6e4, 0, NO_PAD_CTRL)
356
357#define MX50_PAD_SD1_D3__SD1_D3 IOMUX_PAD(0x3A4, 0xF8, 0, 0x0, 0, MX50_SD_PAD_CTRL)
358#define MX50_PAD_SD1_D3__GPIO_5_5 IOMUX_PAD(0x3A4, 0xF8, 1, 0x0, 0, NO_PAD_CTRL)
359
360#define MX50_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x3A8, 0xFC, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
361#define MX50_PAD_SD2_CLK__GPIO_5_6 IOMUX_PAD(0x3A8, 0xFC, 1, 0x0, 0, NO_PAD_CTRL)
362#define MX50_PAD_SD2_CLK__MSHC_SCLK IOMUX_PAD(0x3A8, 0xFC, 2, 0x0, 0, MX50_SD_PAD_CTRL)
363
364#define MX50_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x3AC, 0x100, IOMUX_CONFIG_SION, 0x0, 0, MX50_SD_PAD_CTRL)
365#define MX50_PAD_SD2_CMD__GPIO_5_7 IOMUX_PAD(0x3AC, 0x100, 1, 0x0, 0, NO_PAD_CTRL)
366#define MX50_PAD_SD2_CMD__MSHC_BS IOMUX_PAD(0x3AC, 0x100, 2, 0x0, 0, MX50_SD_PAD_CTRL)
367
368#define MX50_PAD_SD2_D0__SD2_D0 IOMUX_PAD(0x3B0, 0x104, 0, 0x0, 0, MX50_SD_PAD_CTRL)
369#define MX50_PAD_SD2_D0__GPIO_5_8 IOMUX_PAD(0x3B0, 0x104, 1, 0x0, 0, NO_PAD_CTRL)
370#define MX50_PAD_SD2_D0__MSHC_D0 IOMUX_PAD(0x3B0, 0x104, 2, 0x0, 0, MX50_SD_PAD_CTRL)
371#define MX50_PAD_SD2_D0__KEY_COL4 IOMUX_PAD(0x3B0, 0x104, 3, 0x790, 0, NO_PAD_CTRL)
372
373#define MX50_PAD_SD2_D1__SD2_D1 IOMUX_PAD(0x3B4, 0x108, 0, 0x0, 0, MX50_SD_PAD_CTRL)
374#define MX50_PAD_SD2_D1__GPIO_5_9 IOMUX_PAD(0x3B4, 0x108, 1, 0x0, 0, NO_PAD_CTRL)
375#define MX50_PAD_SD2_D1__MSHC_D1 IOMUX_PAD(0x3B4, 0x108, 2, 0x0, 0, MX50_SD_PAD_CTRL)
376#define MX50_PAD_SD2_D1__KEY_ROW4 IOMUX_PAD(0x3B4, 0x108, 3, 0x7a0, 0, NO_PAD_CTRL)
377
378#define MX50_PAD_SD2_D2__SD2_D2 IOMUX_PAD(0x3B8, 0x10C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
379#define MX50_PAD_SD2_D2__GPIO_5_10 IOMUX_PAD(0x3B8, 0x10C, 1, 0x0, 0, NO_PAD_CTRL)
380#define MX50_PAD_SD2_D2__MSHC_D2 IOMUX_PAD(0x3B8, 0x10C, 2, 0x0, 0, MX50_SD_PAD_CTRL)
381#define MX50_PAD_SD2_D2__KEY_COL5 IOMUX_PAD(0x3B8, 0x10C, 3, 0x794, 0, NO_PAD_CTRL)
382
383#define MX50_PAD_SD2_D3__SD2_D3 IOMUX_PAD(0x3BC, 0x110, 0, 0x0, 0, MX50_SD_PAD_CTRL)
384#define MX50_PAD_SD2_D3__GPIO_5_11 IOMUX_PAD(0x3BC, 0x110, 1, 0x0, 0, NO_PAD_CTRL)
385#define MX50_PAD_SD2_D3__MSHC_D3 IOMUX_PAD(0x3BC, 0x110, 2, 0x0, 0, MX50_SD_PAD_CTRL)
386#define MX50_PAD_SD2_D3__KEY_ROW5 IOMUX_PAD(0x3BC, 0x110, 3, 0x7a4, 0, NO_PAD_CTRL)
387
388#define MX50_PAD_SD2_D4__SD2_D4 IOMUX_PAD(0x3C0, 0x114, 0, 0x0, 0, MX50_SD_PAD_CTRL)
389#define MX50_PAD_SD2_D4__GPIO_5_12 IOMUX_PAD(0x3C0, 0x114, 1, 0x0, 0, NO_PAD_CTRL)
390#define MX50_PAD_SD2_D4__AUD4_RXFS IOMUX_PAD(0x3C0, 0x114, 2, 0x6d0, 0, NO_PAD_CTRL)
391#define MX50_PAD_SD2_D4__KEY_COL6 IOMUX_PAD(0x3C0, 0x114, 3, 0x798, 0, NO_PAD_CTRL)
392#define MX50_PAD_SD2_D4__WEIM_D0 IOMUX_PAD(0x3C0, 0x114, 4, 0x7ec, 0, NO_PAD_CTRL)
393#define MX50_PAD_SD2_D4__CCM_OUT0 IOMUX_PAD(0x3C0, 0x114, 7, 0x0, 0, NO_PAD_CTRL)
394
395#define MX50_PAD_SD2_D5__SD2_D5 IOMUX_PAD(0x3C4, 0x118, 0, 0x0, 0, MX50_SD_PAD_CTRL)
396#define MX50_PAD_SD2_D5__GPIO_5_13 IOMUX_PAD(0x3C4, 0x118, 1, 0x0, 0, NO_PAD_CTRL)
397#define MX50_PAD_SD2_D5__AUD4_RXC IOMUX_PAD(0x3C4, 0x118, 2, 0x6cc, 0, NO_PAD_CTRL)
398#define MX50_PAD_SD2_D5__KEY_ROW6 IOMUX_PAD(0x3C4, 0x118, 3, 0x7a8, 0, NO_PAD_CTRL)
399#define MX50_PAD_SD2_D5__WEIM_D1 IOMUX_PAD(0x3C4, 0x118, 4, 0x7f0, 0, NO_PAD_CTRL)
400#define MX50_PAD_SD2_D5__CCM_OUT1 IOMUX_PAD(0x3C4, 0x118, 7, 0x0, 0, NO_PAD_CTRL)
401
402#define MX50_PAD_SD2_D6__SD2_D6 IOMUX_PAD(0x3C8, 0x11C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
403#define MX50_PAD_SD2_D6__GPIO_5_14 IOMUX_PAD(0x3C8, 0x11C, 1, 0x0, 0, NO_PAD_CTRL)
404#define MX50_PAD_SD2_D6__AUD4_RXD IOMUX_PAD(0x3C8, 0x11C, 2, 0x6c4, 0, NO_PAD_CTRL)
405#define MX50_PAD_SD2_D6__KEY_COL7 IOMUX_PAD(0x3C8, 0x11C, 3, 0x79c, 0, NO_PAD_CTRL)
406#define MX50_PAD_SD2_D6__WEIM_D2 IOMUX_PAD(0x3C8, 0x11C, 4, 0x7f4, 0, NO_PAD_CTRL)
407#define MX50_PAD_SD2_D6__CCM_OUT2 IOMUX_PAD(0x3C8, 0x11C, 7, 0x0, 0, NO_PAD_CTRL)
408
409#define MX50_PAD_SD2_D7__SD2_D7 IOMUX_PAD(0x3CC, 0x120, 0, 0x0, 0, MX50_SD_PAD_CTRL)
410#define MX50_PAD_SD2_D7__GPIO_5_15 IOMUX_PAD(0x3CC, 0x120, 1, 0x0, 0, NO_PAD_CTRL)
411#define MX50_PAD_SD2_D7__AUD4_TXFS IOMUX_PAD(0x3CC, 0x120, 2, 0x6d8, 0, NO_PAD_CTRL)
412#define MX50_PAD_SD2_D7__KEY_ROW7 IOMUX_PAD(0x3CC, 0x120, 3, 0x7ac, 0, NO_PAD_CTRL)
413#define MX50_PAD_SD2_D7__WEIM_D3 IOMUX_PAD(0x3CC, 0x120, 4, 0x7f8, 0, NO_PAD_CTRL)
414#define MX50_PAD_SD2_D7__CCM_STOP IOMUX_PAD(0x3CC, 0x120, 7, 0x0, 0, NO_PAD_CTRL)
415
416#define MX50_PAD_SD2_WP__SD2_WP IOMUX_PAD(0x3D0, 0x124, 0, 0x744, 1, MX50_SD_PAD_CTRL)
417#define MX50_PAD_SD2_WP__GPIO_5_16 IOMUX_PAD(0x3D0, 0x124, 1, 0x0, 0, NO_PAD_CTRL)
418#define MX50_PAD_SD2_WP__AUD4_TXD IOMUX_PAD(0x3D0, 0x124, 2, 0x6c8, 0, NO_PAD_CTRL)
419#define MX50_PAD_SD2_WP__WEIM_D4 IOMUX_PAD(0x3D0, 0x124, 4, 0x7fc, 0, NO_PAD_CTRL)
420#define MX50_PAD_SD2_WP__CCM_WAIT IOMUX_PAD(0x3D0, 0x124, 7, 0x0, 0, NO_PAD_CTRL)
421
422#define MX50_PAD_SD2_CD__SD2_CD IOMUX_PAD(0x3D4, 0x128, 0, 0x740, 1, MX50_SD_PAD_CTRL)
423#define MX50_PAD_SD2_CD__GPIO_5_17 IOMUX_PAD(0x3D4, 0x128, 1, 0x0, 0, NO_PAD_CTRL)
424#define MX50_PAD_SD2_CD__AUD4_TXC IOMUX_PAD(0x3D4, 0x128, 2, 0x6d4, 0, NO_PAD_CTRL)
425#define MX50_PAD_SD2_CD__WEIM_D5 IOMUX_PAD(0x3D4, 0x128, 4, 0x800, 0, NO_PAD_CTRL)
426#define MX50_PAD_SD2_CD__CCM_REF_EN IOMUX_PAD(0x3D4, 0x128, 7, 0x0, 0, NO_PAD_CTRL)
427
428#define MX50_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x3D8, 0, 0, 0x0, 0, NO_PAD_CTRL)
429
430#define MX50_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x3DC, 0, 0, 0x0, 0, NO_PAD_CTRL)
431
432#define MX50_PAD_PMIC_PORT_B__PMIC_PORT_B IOMUX_PAD(0x3E0, 0, 0, 0x0, 0, NO_PAD_CTRL)
433
434#define MX50_PAD_PMIC_BOOT_MODE1__PMIC_BOOT_MODE1 IOMUX_PAD(0x3E4, 0, 0, 0x0, 0, NO_PAD_CTRL)
435
436#define MX50_PAD_PMIC_RESET_IN_B__PMIC_RESET_IN_B IOMUX_PAD(0x3E8, 0, 0, 0x0, 0, NO_PAD_CTRL)
437
438#define MX50_PAD_PMIC_BOOT_MODE0__PMIC_BOOT_MODE0 IOMUX_PAD(0x3EC, 0, 0, 0x0, 0, NO_PAD_CTRL)
439
440#define MX50_PAD_PMIC_TEST_MODE__PMIC_TEST_MODE IOMUX_PAD(0x3F0, 0, 0, 0x0, 0, NO_PAD_CTRL)
441
442#define MX50_PAD_PMIC_JTAG_TMS__PMIC_JTAG_TMS IOMUX_PAD(0x3F4, 0, 0, 0x0, 0, NO_PAD_CTRL)
443
444#define MX50_PAD_PMIC_JTAG_MOD__PMIC_JTAG_MOD IOMUX_PAD(0x3F8, 0, 0, 0x0, 0, NO_PAD_CTRL)
445
446#define MX50_PAD_PMIC_JTAG_TRSTB__PMIC_JTAG_TRSTB IOMUX_PAD(0x3FC, 0, 0, 0x0, 0, NO_PAD_CTRL)
447
448#define MX50_PAD_PMIC_JTAG_TDI__PMIC_JTAG_TDI IOMUX_PAD(0x400, 0, 0, 0x0, 0, NO_PAD_CTRL)
449
450#define MX50_PAD_PMIC_JTAG_TCK__PMIC_JTAG_TCK IOMUX_PAD(0x404, 0, 0, 0x0, 0, NO_PAD_CTRL)
451
452#define MX50_PAD_PMIC_JTAG_TDO__PMIC_JTAG_TDO IOMUX_PAD(0x408, 0, 0, 0x0, 0, NO_PAD_CTRL)
453
454#define MX50_PAD_DISP_D0__DISP_D0 IOMUX_PAD(0x40C, 0x12C, 0, 0x6fc, 0, MX50_ELCDIF_PAD_CTRL)
455#define MX50_PAD_DISP_D0__GPIO_2_0 IOMUX_PAD(0x40C, 0x12C, 1, 0x0, 0, NO_PAD_CTRL)
456#define MX50_PAD_DISP_D0__FEC_TXCLK IOMUX_PAD(0x40C, 0x12C, 2, 0x78c, 0, PAD_CTL_HYS | PAD_CTL_PKE)
457
458#define MX50_PAD_DISP_D1__DISP_D1 IOMUX_PAD(0x410, 0x130, 0, 0x700, 0, MX50_ELCDIF_PAD_CTRL)
459#define MX50_PAD_DISP_D1__GPIO_2_1 IOMUX_PAD(0x410, 0x130, 1, 0x0, 0, NO_PAD_CTRL)
460#define MX50_PAD_DISP_D1__FEC_RX_ER IOMUX_PAD(0x410, 0x130, 2, 0x788, 0, PAD_CTL_HYS | PAD_CTL_PKE)
461#define MX50_PAD_DISP_D1__WEIM_A17 IOMUX_PAD(0x410, 0x130, 3, 0x0, 0, NO_PAD_CTRL)
462
463#define MX50_PAD_DISP_D2__DISP_D2 IOMUX_PAD(0x414, 0x134, 0, 0x704, 0, MX50_ELCDIF_PAD_CTRL)
464#define MX50_PAD_DISP_D2__GPIO_2_2 IOMUX_PAD(0x414, 0x134, 1, 0x0, 0, NO_PAD_CTRL)
465#define MX50_PAD_DISP_D2__FEC_RX_DV IOMUX_PAD(0x414, 0x134, 2, 0x784, 0, PAD_CTL_HYS | PAD_CTL_PKE)
466#define MX50_PAD_DISP_D2__WEIM_A18 IOMUX_PAD(0x414, 0x134, 3, 0x0, 0, NO_PAD_CTRL)
467
468#define MX50_PAD_DISP_D3__DISP_D3 IOMUX_PAD(0x418, 0x138, 0, 0x708, 0, MX50_ELCDIF_PAD_CTRL)
469#define MX50_PAD_DISP_D3__GPIO_2_3 IOMUX_PAD(0x418, 0x138, 1, 0x0, 0, NO_PAD_CTRL)
470#define MX50_PAD_DISP_D3__FEC_RXD1 IOMUX_PAD(0x418, 0x138, 2, 0x77C, 0, PAD_CTL_HYS | PAD_CTL_PKE)
471#define MX50_PAD_DISP_D3__WEIM_A19 IOMUX_PAD(0x418, 0x138, 3, 0x0, 0, NO_PAD_CTRL)
472#define MX50_PAD_DISP_D3__FEC_COL IOMUX_PAD(0x418, 0x138, 4, 0x770, 1, NO_PAD_CTRL)
473
474#define MX50_PAD_DISP_D4__DISP_D4 IOMUX_PAD(0x41C, 0x13C, 0, 0x70c, 0, MX50_ELCDIF_PAD_CTRL)
475#define MX50_PAD_DISP_D4__GPIO_2_4 IOMUX_PAD(0x41C, 0x13C, 1, 0x0, 0, NO_PAD_CTRL)
476#define MX50_PAD_DISP_D4__FEC_RXD0 IOMUX_PAD(0x41C, 0x13C, 2, 0x778, 0, PAD_CTL_HYS | PAD_CTL_PKE)
477#define MX50_PAD_DISP_D4__WEIM_A20 IOMUX_PAD(0x41C, 0x13C, 3, 0x0, 0, NO_PAD_CTRL)
478
479#define MX50_PAD_DISP_D5__DISP_D5 IOMUX_PAD(0x420, 0x140, 0, 0x710, 0, MX50_ELCDIF_PAD_CTRL)
480#define MX50_PAD_DISP_D5__GPIO_2_5 IOMUX_PAD(0x420, 0x140, 1, 0x0, 0, NO_PAD_CTRL)
481#define MX50_PAD_DISP_D5__FEC_TX_EN IOMUX_PAD(0x420, 0x140, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
482#define MX50_PAD_DISP_D5__WEIM_A21 IOMUX_PAD(0x420, 0x140, 3, 0x0, 0, NO_PAD_CTRL)
483
484#define MX50_PAD_DISP_D6__DISP_D6 IOMUX_PAD(0x424, 0x144, 0, 0x714, 0, MX50_ELCDIF_PAD_CTRL)
485#define MX50_PAD_DISP_D6__GPIO_2_6 IOMUX_PAD(0x424, 0x144, 1, 0x0, 0, NO_PAD_CTRL)
486#define MX50_PAD_DISP_D6__FEC_TXD1 IOMUX_PAD(0x424, 0x144, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
487#define MX50_PAD_DISP_D6__WEIM_A22 IOMUX_PAD(0x424, 0x144, 3, 0x0, 0, NO_PAD_CTRL)
488#define MX50_PAD_DISP_D6__FEC_RX_CLK IOMUX_PAD(0x424, 0x144, 4, 0x780, 1, NO_PAD_CTRL)
489
490#define MX50_PAD_DISP_D7__DISP_D7 IOMUX_PAD(0x428, 0x148, 0, 0x718, 0, MX50_ELCDIF_PAD_CTRL)
491#define MX50_PAD_DISP_D7__GPIO_2_7 IOMUX_PAD(0x428, 0x148, 1, 0x0, 0, NO_PAD_CTRL)
492#define MX50_PAD_DISP_D7__FEC_TXD0 IOMUX_PAD(0x428, 0x148, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
493#define MX50_PAD_DISP_D7__WEIM_A23 IOMUX_PAD(0x428, 0x148, 3, 0x0, 0, NO_PAD_CTRL)
494
495
496#define MX50_PAD_DISP_WR__ELCDIF_WR IOMUX_PAD(0x42C, 0x14C, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
497#define MX50_PAD_DISP_WR__GPIO_2_16 IOMUX_PAD(0x42C, 0x14C, 1, 0x0, 0, NO_PAD_CTRL)
498#define MX50_PAD_DISP_WR__ELCDIF_PIXCLK IOMUX_PAD(0x42C, 0x14C, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
499#define MX50_PAD_DISP_WR__WEIM_A24 IOMUX_PAD(0x42C, 0x14C, 3, 0x0, 0, NO_PAD_CTRL)
500
501#define MX50_PAD_DISP_RD__ELCDIF_RD IOMUX_PAD(0x430, 0x150, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
502#define MX50_PAD_DISP_RD__GPIO_2_19 IOMUX_PAD(0x430, 0x150, 1, 0x0, 0, NO_PAD_CTRL)
503#define MX50_PAD_DISP_RD__ELCDIF_EN IOMUX_PAD(0x430, 0x150, 2, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
504#define MX50_PAD_DISP_RD__WEIM_A25 IOMUX_PAD(0x430, 0x150, 3, 0x0, 0, NO_PAD_CTRL)
505
506#define MX50_PAD_DISP_RS__ELCDIF_RS IOMUX_PAD(0x434, 0x154, 0, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
507#define MX50_PAD_DISP_RS__GPIO_2_17 IOMUX_PAD(0x434, 0x154, 1, 0x0, 0, NO_PAD_CTRL)
508#define MX50_PAD_DISP_RS__ELCDIF_VSYNC IOMUX_PAD(0x434, 0x154, 2, 0x73c, 1, MX50_ELCDIF_PAD_CTRL)
509#define MX50_PAD_DISP_RS__WEIM_A26 IOMUX_PAD(0x434, 0x154, 3, 0x0, 0, NO_PAD_CTRL)
510
511#define MX50_PAD_DISP_CS__ELCDIF_CS IOMUX_PAD(0x438, 0x158, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
512#define MX50_PAD_DISP_CS__GPIO_2_21 IOMUX_PAD(0x438, 0x158, 1, 0x0, 0, NO_PAD_CTRL)
513#define MX50_PAD_DISP_CS__ELCDIF_HSYNC IOMUX_PAD(0x438, 0x158, 2, 0x6f8, 1, MX50_ELCDIF_PAD_CTRL)
514#define MX50_PAD_DISP_CS__WEIM_A27 IOMUX_PAD(0x438, 0x158, 3, 0x0, 0, NO_PAD_CTRL)
515#define MX50_PAD_DISP_CS__WEIM_CS3 IOMUX_PAD(0x438, 0x158, 4, 0x0, 0, NO_PAD_CTRL)
516
517#define MX50_PAD_DISP_BUSY__ELCDIF_HSYNC IOMUX_PAD(0x43C, 0x15C, 0, 0x6f8, 2, MX50_ELCDIF_PAD_CTRL)
518#define MX50_PAD_DISP_BUSY__GPIO_2_18 IOMUX_PAD(0x43C, 0x15C, 1, 0x0, 0, NO_PAD_CTRL)
519#define MX50_PAD_DISP_BUSY__WEIM_CS3 IOMUX_PAD(0x43C, 0x15C, 3, 0x0, 0, NO_PAD_CTRL)
520
521#define MX50_PAD_DISP_RESET__ELCDIF_RST IOMUX_PAD(0x440, 0x160, 0, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
522#define MX50_PAD_DISP_RESET__GPIO_2_20 IOMUX_PAD(0x440, 0x160, 1, 0x0, 0, NO_PAD_CTRL)
523#define MX50_PAD_DISP_RESET__WEIM_CS3 IOMUX_PAD(0x440, 0x160, 4, 0x0, 0, NO_PAD_CTRL)
524
525#define MX50_PAD_SD3_CMD__SD3_CMD IOMUX_PAD(0x444, 0x164, 0, 0x0, 0, MX50_SD_PAD_CTRL)
526#define MX50_PAD_SD3_CMD__GPIO_5_18 IOMUX_PAD(0x444, 0x164, 1, 0x0, 0, NO_PAD_CTRL)
527#define MX50_PIN_SD3_CMD__NANDF_WRN IOMUX_PAD(0x444, 0x164, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
528#define MX50_PAD_SD3_CMD__SSP_CMD IOMUX_PAD(0x444, 0x164, 3, 0x0, 0, NO_PAD_CTRL)
529
530#define MX50_PAD_SD3_CLK__SD3_CLK IOMUX_PAD(0x448, 0x168, 0, 0x0, 0, MX50_SD_PAD_CTRL)
531#define MX50_PAD_SD3_CLK__GPIO_5_19 IOMUX_PAD(0x448, 0x168, 1, 0x0, 0, NO_PAD_CTRL)
532#define MX50_PIN_SD3_CLK__NANDF_RDN IOMUX_PAD(0x448, 0x168, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
533#define MX50_PAD_SD3_CLK__SSP_CLK IOMUX_PAD(0x448, 0x168, 3, 0x0, 0, NO_PAD_CTRL)
534
535#define MX50_PAD_SD3_D0__SD3_D0 IOMUX_PAD(0x44C, 0x16C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
536#define MX50_PAD_SD3_D0__GPIO_5_20 IOMUX_PAD(0x44C, 0x16C, 1, 0x0, 0, NO_PAD_CTRL)
537#define MX50_PIN_SD3_D0__NANDF_D4 IOMUX_PAD(0x44C, 0x16C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
538#define MX50_PAD_SD3_D0__SSP_D0 IOMUX_PAD(0x44C, 0x16C, 3, 0x0, 0, NO_PAD_CTRL)
539#define MX50_PAD_SD3_D0__PLL1_BYP IOMUX_PAD(0x44C, 0x16C, 7, 0x6dc, 1, NO_PAD_CTRL)
540
541#define MX50_PAD_SD3_D1__SD3_D1 IOMUX_PAD(0x450, 0x170, 0, 0x0, 0, MX50_SD_PAD_CTRL)
542#define MX50_PAD_SD3_D1__GPIO_5_21 IOMUX_PAD(0x450, 0x170, 1, 0x0, 0, NO_PAD_CTRL)
543#define MX50_PIN_SD3_D1__NANDF_D5 IOMUX_PAD(0x450, 0x170, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
544#define MX50_PAD_SD3_D1__PLL2_BYP IOMUX_PAD(0x450, 0x170, 7, 0x6e0, 1, NO_PAD_CTRL)
545
546#define MX50_PAD_SD3_D2__SD3_D2 IOMUX_PAD(0x454, 0x174, 0, 0x0, 0, MX50_SD_PAD_CTRL)
547#define MX50_PAD_SD3_D2__GPIO_5_22 IOMUX_PAD(0x454, 0x174, 1, 0x0, 0, NO_PAD_CTRL)
548#define MX50_PIN_SD3_D2__NANDF_D6 IOMUX_PAD(0x454, 0x174, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
549#define MX50_PAD_SD3_D2__SSP_D2 IOMUX_PAD(0x454, 0x174, 3, 0x0, 0, NO_PAD_CTRL)
550#define MX50_PAD_SD3_D2__PLL3_BYP IOMUX_PAD(0x454, 0x174, 7, 0x6e4, 1, NO_PAD_CTRL)
551
552#define MX50_PAD_SD3_D3__SD3_D3 IOMUX_PAD(0x458, 0x178, 0, 0x0, 0, MX50_SD_PAD_CTRL)
553#define MX50_PAD_SD3_D3__GPIO_5_23 IOMUX_PAD(0x458, 0x178, 1, 0x0, 0, NO_PAD_CTRL)
554#define MX50_PIN_SD3_D3__NANDF_D7 IOMUX_PAD(0x458, 0x178, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
555#define MX50_PAD_SD3_D3__SSP_D3 IOMUX_PAD(0x458, 0x178, 3, 0x0, 0, NO_PAD_CTRL)
556
557#define MX50_PAD_SD3_D4__SD3_D4 IOMUX_PAD(0x45C, 0x17C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
558#define MX50_PAD_SD3_D4__GPIO_5_24 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
559#define MX50_PIN_SD3_D4__NANDF_D0 IOMUX_PAD(0x45C, 0x17C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
560#define MX50_PAD_SD3_D4__SSP_D4 IOMUX_PAD(0x45C, 0x17C, 1, 0x0, 0, NO_PAD_CTRL)
561
562#define MX50_PAD_SD3_D5__SD3_D5 IOMUX_PAD(0x460, 0x180, 0, 0x0, 0, MX50_SD_PAD_CTRL)
563#define MX50_PAD_SD3_D5__GPIO_5_25 IOMUX_PAD(0x460, 0x180, 1, 0x0, 0, NO_PAD_CTRL)
564#define MX50_PIN_SD3_D5__NANDF_D1 IOMUX_PAD(0x460, 0x180, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
565#define MX50_PAD_SD3_D5__SSP_D5 IOMUX_PAD(0x460, 0x180, 3, 0x0, 0, NO_PAD_CTRL)
566
567#define MX50_PAD_SD3_D6__SD3_D6 IOMUX_PAD(0x464, 0x184, 0, 0x0, 0, MX50_SD_PAD_CTRL)
568#define MX50_PAD_SD3_D6__GPIO_5_26 IOMUX_PAD(0x464, 0x184, 1, 0x0, 0, NO_PAD_CTRL)
569#define MX50_PIN_SD3_D6__NANDF_D2 IOMUX_PAD(0x464, 0x184, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
570#define MX50_PAD_SD3_D6__SSP_D6 IOMUX_PAD(0x464, 0x184, 3, 0x0, 0, NO_PAD_CTRL)
571
572#define MX50_PAD_SD3_D7__SD3_D7 IOMUX_PAD(0x468, 0x188, 0, 0x0, 0, MX50_SD_PAD_CTRL)
573#define MX50_PAD_SD3_D7__GPIO_5_27 IOMUX_PAD(0x468, 0x188, 1, 0x0, 0, NO_PAD_CTRL)
574#define MX50_PIN_SD3_D7__NANDF_D3 IOMUX_PAD(0x468, 0x188, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
575#define MX50_PAD_SD3_D7__SSP_D7 IOMUX_PAD(0x468, 0x188, 3, 0x0, 0, NO_PAD_CTRL)
576
577#define MX50_PAD_SD3_WP__SD3_WP IOMUX_PAD(0x46C, 0x18C, 0, 0x0, 0, MX50_SD_PAD_CTRL)
578#define MX50_PAD_SD3_WP__GPIO_5_28 IOMUX_PAD(0x46C, 0x18C, 1, 0x0, 0, NO_PAD_CTRL)
579#define MX50_PIN_SD3_WP__NANDF_RESETN IOMUX_PAD(0x46C, 0x18C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
580#define MX50_PAD_SD3_WP__SSP_CD IOMUX_PAD(0x46C, 0x18C, 3, 0x0, 0, NO_PAD_CTRL)
581#define MX50_PAD_SD3_WP__SD4_LCTL IOMUX_PAD(0x46C, 0x18C, 4, 0x0, 0, MX50_SD_PAD_CTRL)
582#define MX50_PAD_SD3_WP__WEIM_CS3 IOMUX_PAD(0x46C, 0x18C, 5, 0x0, 0, NO_PAD_CTRL)
583
584#define MX50_PAD_DISP_D8__DISP_D8 IOMUX_PAD(0x470, 0x190, 0, 0x71c, 0, MX50_ELCDIF_PAD_CTRL)
585#define MX50_PAD_DISP_D8__GPIO_2_8 IOMUX_PAD(0x470, 0x190, 1, 0x0, 0, NO_PAD_CTRL)
586#define MX50_PAD_DISP_D8__NANDF_CLE IOMUX_PAD(0x470, 0x190, 2, 0x0, 0, NO_PAD_CTRL)
587#define MX50_PAD_DISP_D8__SD1_LCTL IOMUX_PAD(0x470, 0x190, 3, 0x0, 0, MX50_SD_PAD_CTRL)
588#define MX50_PAD_DISP_D8__SD4_CMD IOMUX_PAD(0x470, 0x190, 4, 0x74c, 2, MX50_SD_PAD_CTRL)
589#define MX50_PAD_DISP_D8__KEY_COL4 IOMUX_PAD(0x470, 0x190, 5, 0x790, 1, NO_PAD_CTRL)
590#define MX50_PAD_DISP_D8__FEC_TX_CLK IOMUX_PAD(0x470, 0x190, 6, 0x78c, 1, NO_PAD_CTRL)
591
592#define MX50_PAD_DISP_D9__DISP_D9 IOMUX_PAD(0x474, 0x194, 0, 0x720, 0, MX50_ELCDIF_PAD_CTRL)
593#define MX50_PAD_DISP_D9__GPIO_2_9 IOMUX_PAD(0x474, 0x194, 1, 0x0, 0, NO_PAD_CTRL)
594#define MX50_PAD_DISP_D9__NANDF_ALE IOMUX_PAD(0x474, 0x194, 2, 0x0, 0, NO_PAD_CTRL)
595#define MX50_PAD_DISP_D9__SD2_LCTL IOMUX_PAD(0x474, 0x194, 3, 0x0, 0, MX50_SD_PAD_CTRL)
596#define MX50_PAD_DISP_D9__SD4_CLK IOMUX_PAD(0x474, 0x194, 4, 0x748, 2, MX50_SD_PAD_CTRL)
597#define MX50_PAD_DISP_D9__KEY_ROW4 IOMUX_PAD(0x474, 0x194, 5, 0x7a0, 1, NO_PAD_CTRL)
598#define MX50_PAD_DISP_D9__FEC_RX_ER IOMUX_PAD(0x474, 0x194, 6, 0x788, 1, NO_PAD_CTRL)
599
600#define MX50_PAD_DISP_D10__DISP_D10 IOMUX_PAD(0x478, 0x198, 0, 0x724, 0, MX50_ELCDIF_PAD_CTRL)
601#define MX50_PAD_DISP_D10__GPIO_2_10 IOMUX_PAD(0x478, 0x198, 1, 0x0, 0, NO_PAD_CTRL)
602#define MX50_PAD_DISP_D10__NANDF_CEN0 IOMUX_PAD(0x478, 0x198, 2, 0x0, 0, NO_PAD_CTRL)
603#define MX50_PAD_DISP_D10__SD3_LCTL IOMUX_PAD(0x478, 0x198, 3, 0x0, 0, MX50_SD_PAD_CTRL)
604#define MX50_PAD_DISP_D10__SD4_D0 IOMUX_PAD(0x478, 0x198, 4, 0x750, 1, MX50_SD_PAD_CTRL)
605#define MX50_PAD_DISP_D10__KEY_COL5 IOMUX_PAD(0x478, 0x198, 5, 0x794, 1, NO_PAD_CTRL)
606#define MX50_PAD_DISP_D10__FEC_RX_DV IOMUX_PAD(0x478, 0x198, 6, 0x784, 1, NO_PAD_CTRL)
607
608#define MX50_PAD_DISP_D11__DISP_D11 IOMUX_PAD(0x47C, 0x19C, 0, 0x728, 0, MX50_ELCDIF_PAD_CTRL)
609#define MX50_PAD_DISP_D11__GPIO_2_11 IOMUX_PAD(0x47C, 0x19C, 1, 0x0, 0, NO_PAD_CTRL)
610#define MX50_PAD_DISP_D11__NANDF_CEN1 IOMUX_PAD(0x47C, 0x19C, 2, 0x0, 0, NO_PAD_CTRL)
611#define MX50_PAD_DISP_D11__SD4_D1 IOMUX_PAD(0x47C, 0x19C, 4, 0x754, 1, MX50_SD_PAD_CTRL)
612#define MX50_PAD_DISP_D11__KEY_ROW5 IOMUX_PAD(0x47C, 0x19C, 5, 0x7a4, 1, NO_PAD_CTRL)
613#define MX50_PAD_DISP_D11__FEC_RDAT1 IOMUX_PAD(0x47C, 0x19C, 6, 0x77c, 1, NO_PAD_CTRL)
614
615#define MX50_PAD_DISP_D12__DISP_D12 IOMUX_PAD(0x480, 0x1A0, 0, 0x72c, 0, MX50_ELCDIF_PAD_CTRL)
616#define MX50_PAD_DISP_D12__GPIO_2_12 IOMUX_PAD(0x480, 0x1A0, 1, 0x0, 0, NO_PAD_CTRL)
617#define MX50_PAD_DISP_D12__NANDF_CEN2 IOMUX_PAD(0x480, 0x1A0, 2, 0x0, 0, NO_PAD_CTRL)
618#define MX50_PAD_DISP_D12__SD1_CD IOMUX_PAD(0x480, 0x1A0, 3, 0x0, 0, MX50_SD_PAD_CTRL)
619#define MX50_PAD_DISP_D12__SD4_D2 IOMUX_PAD(0x480, 0x1A0, 4, 0x758, 1, MX50_SD_PAD_CTRL)
620#define MX50_PAD_DISP_D12__KEY_COL6 IOMUX_PAD(0x480, 0x1A0, 5, 0x798, 1, NO_PAD_CTRL)
621#define MX50_PAD_DISP_D12__FEC_RDAT0 IOMUX_PAD(0x480, 0x1A0, 6, 0x778, 1, NO_PAD_CTRL)
622
623#define MX50_PAD_DISP_D13__DISP_D13 IOMUX_PAD(0x484, 0x1A4, 0, 0x730, 0, MX50_ELCDIF_PAD_CTRL)
624#define MX50_PAD_DISP_D13__GPIO_2_13 IOMUX_PAD(0x484, 0x1A4, 1, 0x0, 0, NO_PAD_CTRL)
625#define MX50_PAD_DISP_D13__NANDF_CEN3 IOMUX_PAD(0x484, 0x1A4, 2, 0x0, 0, NO_PAD_CTRL)
626#define MX50_PAD_DISP_D13__SD3_CD IOMUX_PAD(0x484, 0x1A4, 3, 0x0, 0, MX50_SD_PAD_CTRL)
627#define MX50_PAD_DISP_D13__SD4_D3 IOMUX_PAD(0x484, 0x1A4, 4, 0x75c, 1, MX50_SD_PAD_CTRL)
628#define MX50_PAD_DISP_D13__KEY_ROW6 IOMUX_PAD(0x484, 0x1A4, 5, 0x7a8, 1, NO_PAD_CTRL)
629#define MX50_PAD_DISP_D13__FEC_TX_EN IOMUX_PAD(0x484, 0x1A4, 6, 0x0, 0, NO_PAD_CTRL)
630
631#define MX50_PAD_DISP_D14__DISP_D14 IOMUX_PAD(0x488, 0x1A8, 0, 0x734, 0, MX50_ELCDIF_PAD_CTRL)
632#define MX50_PAD_DISP_D14__GPIO_2_14 IOMUX_PAD(0x488, 0x1A8, 1, 0x0, 0, NO_PAD_CTRL)
633#define MX50_PAD_DISP_D14__NANDF_RDY0 IOMUX_PAD(0x488, 0x1A8, 2, 0x7b4, 1, NO_PAD_CTRL)
634#define MX50_PAD_DISP_D14__SD1_WP IOMUX_PAD(0x488, 0x1A8, 3, 0x0, 0, MX50_SD_PAD_CTRL)
635#define MX50_PAD_DISP_D14__SD4_WP IOMUX_PAD(0x488, 0x1A8, 4, 0x0, 0, MX50_SD_PAD_CTRL)
636#define MX50_PAD_DISP_D14__KEY_COL7 IOMUX_PAD(0x488, 0x1A8, 5, 0x79c, 1, NO_PAD_CTRL)
637#define MX50_PAD_DISP_D14__FEC_TDAT1 IOMUX_PAD(0x488, 0x1A8, 6, 0x0, 0, NO_PAD_CTRL)
638
639#define MX50_PAD_DISP_D15__DISP_D15 IOMUX_PAD(0x48C, 0x1AC, 0, 0x738, 0, MX50_ELCDIF_PAD_CTRL)
640#define MX50_PAD_DISP_D15__GPIO_2_15 IOMUX_PAD(0x48C, 0x1AC, 1, 0x0, 0, NO_PAD_CTRL)
641#define MX50_PAD_DISP_D15__NANDF_DQS IOMUX_PAD(0x48C, 0x1AC, 2, 0x7b0, 1, NO_PAD_CTRL)
642#define MX50_PAD_DISP_D15__SD3_RST IOMUX_PAD(0x48C, 0x1AC, 3, 0x0, 0, MX50_SD_PAD_CTRL)
643#define MX50_PAD_DISP_D15__SD4_CD IOMUX_PAD(0x48C, 0x1AC, 4, 0x0, 0, MX50_SD_PAD_CTRL)
644#define MX50_PAD_DISP_D15__KEY_ROW7 IOMUX_PAD(0x48C, 0x1AC, 5, 0x7ac, 1, NO_PAD_CTRL)
645#define MX50_PAD_DISP_D15__FEC_TDAT0 IOMUX_PAD(0x48C, 0x1AC, 6, 0x0, 0, NO_PAD_CTRL)
646
647#define MX50_PAD_EPDC_D0__EPDC_D0 IOMUX_PAD(0x54C, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL)
648#define MX50_PAD_EPDC_D0__GPIO_3_0 IOMUX_PAD(0x54C, 0x1B0, 1, 0x0, 0, NO_PAD_CTRL)
649#define MX50_PAD_EPDC_D0__WEIM_D0 IOMUX_PAD(0x54C, 0x1B0, 2, 0x7ec, 1, NO_PAD_CTRL)
650#define MX50_PAD_EPDC_D0__ELCDIF_RS IOMUX_PAD(0x54C, 0x1B0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
651#define MX50_PAD_EPDC_D0__ELCDIF_PIXCLK IOMUX_PAD(0x54C, 0x1B0, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
652
653#define MX50_PAD_EPDC_D1__EPDC_D1 IOMUX_PAD(0x550, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL)
654#define MX50_PAD_EPDC_D1__GPIO_3_1 IOMUX_PAD(0x550, 0x1B4, 1, 0x0, 0, NO_PAD_CTRL)
655#define MX50_PAD_EPDC_D1__WEIM_D1 IOMUX_PAD(0x550, 0x1B4, 2, 0x7f0, 1, NO_PAD_CTRL)
656#define MX50_PAD_EPDC_D1__ELCDIF_CS IOMUX_PAD(0x550, 0x1B4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
657#define MX50_PAD_EPDC_D1__ELCDIF_EN IOMUX_PAD(0x550, 0x1B4, 4, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
658
659#define MX50_PAD_EPDC_D2__EPDC_D2 IOMUX_PAD(0x554, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL)
660#define MX50_PAD_EPDC_D2__GPIO_3_2 IOMUX_PAD(0x554, 0x1B8, 1, 0x0, 0, NO_PAD_CTRL)
661#define MX50_PAD_EPDC_D2__WEIM_D2 IOMUX_PAD(0x554, 0x1B8, 2, 0x7f4, 1, NO_PAD_CTRL)
662#define MX50_PAD_EPDC_D2__ELCDIF_WR IOMUX_PAD(0x554, 0x1B8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
663#define MX50_PAD_EPDC_D2__ELCDIF_VSYNC IOMUX_PAD(0x554, 0x1B8, 4, 0x73c, 2, MX50_ELCDIF_PAD_CTRL)
664
665#define MX50_PAD_EPDC_D3__EPDC_D3 IOMUX_PAD(0x558, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL)
666#define MX50_PAD_EPDC_D3__GPIO_3_3 IOMUX_PAD(0x558, 0x1BC, 1, 0x0, 0, NO_PAD_CTRL)
667#define MX50_PAD_EPDC_D3__WEIM_D3 IOMUX_PAD(0x558, 0x1BC, 2, 0x7f8, 1, NO_PAD_CTRL)
668#define MX50_PAD_EPDC_D3__ELCDIF_RD IOMUX_PAD(0x558, 0x1BC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
669#define MX50_PAD_EPDC_D3__ELCDIF_HSYNC IOMUX_PAD(0x558, 0x1BC, 4, 0x6f8, 3, MX50_ELCDIF_PAD_CTRL)
670
671#define MX50_PAD_EPDC_D4__EPDC_D4 IOMUX_PAD(0x55C, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL)
672#define MX50_PAD_EPDC_D4__GPIO_3_4 IOMUX_PAD(0x55C, 0x1C0, 1, 0x0, 0, NO_PAD_CTRL)
673#define MX50_PAD_EPDC_D4__WEIM_D4 IOMUX_PAD(0x55C, 0x1C0, 2, 0x7fc, 1, NO_PAD_CTRL)
674
675#define MX50_PAD_EPDC_D5__EPDC_D5 IOMUX_PAD(0x560, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL)
676#define MX50_PAD_EPDC_D5__GPIO_3_5 IOMUX_PAD(0x560, 0x1C4, 1, 0x0, 0, NO_PAD_CTRL)
677#define MX50_PAD_EPDC_D5__WEIM_D5 IOMUX_PAD(0x560, 0x1C4, 2, 0x800, 1, NO_PAD_CTRL)
678
679#define MX50_PAD_EPDC_D6__EPDC_D6 IOMUX_PAD(0x564, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL)
680#define MX50_PAD_EPDC_D6__GPIO_3_6 IOMUX_PAD(0x564, 0x1C8, 1, 0x0, 0, NO_PAD_CTRL)
681#define MX50_PAD_EPDC_D6__WEIM_D6 IOMUX_PAD(0x564, 0x1C8, 2, 0x804, 1, NO_PAD_CTRL)
682
683#define MX50_PAD_EPDC_D7__EPDC_D7 IOMUX_PAD(0x568, 0x1CC, 0, 0x0, 0, NO_PAD_CTRL)
684#define MX50_PAD_EPDC_D7__GPIO_3_7 IOMUX_PAD(0x568, 0x1CC, 1, 0x0, 0, NO_PAD_CTRL)
685#define MX50_PAD_EPDC_D7__WEIM_D7 IOMUX_PAD(0x568, 0x1CC, 2, 0x808, 1, NO_PAD_CTRL)
686
687#define MX50_PAD_EPDC_D8__EPDC_D8 IOMUX_PAD(0x56C, 0x1D0, 0, 0x0, 0, NO_PAD_CTRL)
688#define MX50_PAD_EPDC_D8__GPIO_3_8 IOMUX_PAD(0x56C, 0x1D0, 1, 0x0, 0, NO_PAD_CTRL)
689#define MX50_PAD_EPDC_D8__WEIM_D8 IOMUX_PAD(0x56C, 0x1D0, 2, 0x80c, 2, NO_PAD_CTRL)
690#define MX50_PAD_EPDC_D8__ELCDIF_D24 IOMUX_PAD(0x56C, 0x1D0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
691
692#define MX50_PAD_EPDC_D9__EPDC_D9 IOMUX_PAD(0x570, 0x1D4, 0, 0x0, 0, NO_PAD_CTRL)
693#define MX50_PAD_EPDC_D9__GPIO_3_9 IOMUX_PAD(0x570, 0x1D4, 1, 0x0, 0, NO_PAD_CTRL)
694#define MX50_PAD_EPDC_D9__WEIM_D9 IOMUX_PAD(0x570, 0x1D4, 2, 0x0, 0, NO_PAD_CTRL)
695#define MX50_PAD_EPDC_D9__ELCDIF_D25 IOMUX_PAD(0x570, 0x1D4, 3, 0x810, 2, MX50_ELCDIF_PAD_CTRL)
696
697#define MX50_PAD_EPDC_D10__EPDC_D10 IOMUX_PAD(0x574, 0x1D8, 0, 0x0, 0, NO_PAD_CTRL)
698#define MX50_PAD_EPDC_D10__GPIO_3_10 IOMUX_PAD(0x574, 0x1D8, 1, 0x0, 0, NO_PAD_CTRL)
699#define MX50_PAD_EPDC_D10__WEIM_D10 IOMUX_PAD(0x574, 0x1D8, 2, 0x814, 2, NO_PAD_CTRL)
700#define MX50_PAD_EPDC_D10__ELCDIF_D26 IOMUX_PAD(0x574, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL)
701
702#define MX50_PAD_EPDC_D11__EPDC_D11 IOMUX_PAD(0x578, 0x1DC, 0, 0x0, 0, NO_PAD_CTRL)
703#define MX50_PAD_EPDC_D11__GPIO_3_11 IOMUX_PAD(0x578, 0x1DC, 1, 0x0, 0, NO_PAD_CTRL)
704#define MX50_PAD_EPDC_D11__WEIM_D11 IOMUX_PAD(0x578, 0x1DC, 2, 0x818, 2, NO_PAD_CTRL)
705#define MX50_PAD_EPDC_D11__ELCDIF_D27 IOMUX_PAD(0x578, 0x1DC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
706
707#define MX50_PAD_EPDC_D12__EPDC_D12 IOMUX_PAD(0x57C, 0x1E0, 0, 0x0, 0, NO_PAD_CTRL)
708#define MX50_PAD_EPDC_D12__GPIO_3_12 IOMUX_PAD(0x57C, 0x1E0, 1, 0x0, 0, NO_PAD_CTRL)
709#define MX50_PAD_EPDC_D12__WEIM_D12 IOMUX_PAD(0x57C, 0x1E0, 2, 0x81c, 1, NO_PAD_CTRL)
710#define MX50_PAD_EPDC_D12__ELCDIF_D28 IOMUX_PAD(0x57C, 0x1E0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
711
712#define MX50_PAD_EPDC_D13__EPDC_D13 IOMUX_PAD(0x580, 0x1E4, 0, 0x0, 0, NO_PAD_CTRL)
713#define MX50_PAD_EPDC_D13__GPIO_3_13 IOMUX_PAD(0x580, 0x1E4, 1, 0x0, 0, NO_PAD_CTRL)
714#define MX50_PAD_EPDC_D13__WEIM_D13 IOMUX_PAD(0x580, 0x1E4, 2, 0x820, 1, NO_PAD_CTRL)
715#define MX50_PAD_EPDC_D13__ELCDIF_D29 IOMUX_PAD(0x580, 0x1E4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
716
717#define MX50_PAD_EPDC_D14__EPDC_D14 IOMUX_PAD(0x584, 0x1E8, 0, 0x0, 0, NO_PAD_CTRL)
718#define MX50_PAD_EPDC_D14__GPIO_3_14 IOMUX_PAD(0x584, 0x1E8, 1, 0x0, 0, NO_PAD_CTRL)
719#define MX50_PAD_EPDC_D14__WEIM_D14 IOMUX_PAD(0x584, 0x1E8, 2, 0x824, 1, NO_PAD_CTRL)
720#define MX50_PAD_EPDC_D14__ELCDIF_D30 IOMUX_PAD(0x584, 0x1E8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
721#define MX50_PAD_EPDC_D14__AUD6_TXD IOMUX_PAD(0x584, 0x1E8, 4, 0x0, 0, NO_PAD_CTRL)
722
723#define MX50_PAD_EPDC_D15__EPDC_D15 IOMUX_PAD(0x588, 0x1EC, 0, 0x0, 0, NO_PAD_CTRL)
724#define MX50_PAD_EPDC_D15__GPIO_3_15 IOMUX_PAD(0x588, 0x1EC, 1, 0x0, 0, NO_PAD_CTRL)
725#define MX50_PAD_EPDC_D15__WEIM_D15 IOMUX_PAD(0x588, 0x1EC, 2, 0x828, 1, NO_PAD_CTRL)
726#define MX50_PAD_EPDC_D15__ELCDIF_D31 IOMUX_PAD(0x588, 0x1EC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
727#define MX50_PAD_EPDC_D15__AUD6_TXC IOMUX_PAD(0x588, 0x1EC, 4, 0x0, 0, NO_PAD_CTRL)
728
729#define MX50_PAD_EPDC_GDCLK__EPDC_GDCLK IOMUX_PAD(0x58C, 0x1F0, 0, 0x0, 0, NO_PAD_CTRL)
730#define MX50_PAD_EPDC_GDCLK__GPIO_3_16 IOMUX_PAD(0x58C, 0x1F0, 1, 0x0, 0, NO_PAD_CTRL)
731#define MX50_PAD_EPDC_GDCLK__WEIM_D16 IOMUX_PAD(0x58C, 0x1F0, 2, 0x0, 0, NO_PAD_CTRL)
732#define MX50_PAD_EPDC_GDCLK__ELCDIF_D16 IOMUX_PAD(0x58C, 0x1F0, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
733#define MX50_PAD_EPDC_GDCLK__AUD6_TXFS IOMUX_PAD(0x58C, 0x1F0, 4, 0x0, 0, NO_PAD_CTRL)
734
735#define MX50_PAD_EPDC_GDSP__EPDC_GDSP IOMUX_PAD(0x590, 0x1F4, 0, 0x0, 0, NO_PAD_CTRL)
736#define MX50_PAD_EPDC_GDSP__GPIO_3_17 IOMUX_PAD(0x590, 0x1F4, 1, 0x0, 0, NO_PAD_CTRL)
737#define MX50_PAD_EPDC_GDSP__WEIM_D17 IOMUX_PAD(0x590, 0x1F4, 2, 0x0, 0, NO_PAD_CTRL)
738#define MX50_PAD_EPDC_GDSP__ELCDIF_D17 IOMUX_PAD(0x590, 0x1F4, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
739#define MX50_PAD_EPDC_GDSP__AUD6_RXD IOMUX_PAD(0x590, 0x1F4, 4, 0x0, 0, NO_PAD_CTRL)
740
741#define MX50_PAD_EPDC_GDOE__EPDC_GDOE IOMUX_PAD(0x594, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL)
742#define MX50_PAD_EPDC_GDOE__GPIO_3_18 IOMUX_PAD(0x594, 0x1F8, 1, 0x0, 0, NO_PAD_CTRL)
743#define MX50_PAD_EPDC_GDOE__WEIM_D18 IOMUX_PAD(0x594, 0x1F8, 2, 0x0, 0, NO_PAD_CTRL)
744#define MX50_PAD_EPDC_GDOE__ELCDIF_D18 IOMUX_PAD(0x594, 0x1F8, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
745#define MX50_PAD_EPDC_GDOE__AUD6_RXC IOMUX_PAD(0x594, 0x1F8, 4, 0x0, 0, NO_PAD_CTRL)
746
747#define MX50_PAD_EPDC_GDRL__EPDC_GDRL IOMUX_PAD(0x598, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL)
748#define MX50_PAD_EPDC_GDRL__GPIO_3_19 IOMUX_PAD(0x598, 0x1FC, 1, 0x0, 0, NO_PAD_CTRL)
749#define MX50_PAD_EPDC_GDRL__WEIM_D19 IOMUX_PAD(0x598, 0x1FC, 2, 0x0, 0, NO_PAD_CTRL)
750#define MX50_PAD_EPDC_GDRL__ELCDIF_D19 IOMUX_PAD(0x598, 0x1FC, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
751#define MX50_PAD_EPDC_GDRL__AUD6_RXFS IOMUX_PAD(0x598, 0x1FC, 4, 0x0, 0, NO_PAD_CTRL)
752
753#define MX50_PAD_EPDC_SDCLK__EPDC_SDCLK IOMUX_PAD(0x59C, 0x200, 0, 0x0, 0, NO_PAD_CTRL)
754#define MX50_PAD_EPDC_SDCLK__GPIO_3_20 IOMUX_PAD(0x59C, 0x200, 1, 0x0, 0, NO_PAD_CTRL)
755#define MX50_PAD_EPDC_SDCLK__WEIM_D20 IOMUX_PAD(0x59C, 0x200, 2, 0x0, 0, NO_PAD_CTRL)
756#define MX50_PAD_EPDC_SDCLK__ELCDIF_D20 IOMUX_PAD(0x59C, 0x200, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
757#define MX50_PAD_EPDC_SDCLK__AUD5_TXD IOMUX_PAD(0x59C, 0x200, 4, 0x0, 0, NO_PAD_CTRL)
758
759#define MX50_PAD_EPDC_SDOEZ__EPDC_SDOEZ IOMUX_PAD(0x5A0, 0x204, 0, 0x0, 0, NO_PAD_CTRL)
760#define MX50_PAD_EPDC_SDOEZ__GPIO_3_21 IOMUX_PAD(0x5A0, 0x204, 1, 0x0, 0, NO_PAD_CTRL)
761#define MX50_PAD_EPDC_SDOEZ__WEIM_D21 IOMUX_PAD(0x5A0, 0x204, 2, 0x0, 0, NO_PAD_CTRL)
762#define MX50_PAD_EPDC_SDOEZ__ELCDIF_D21 IOMUX_PAD(0x5A0, 0x204, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
763#define MX50_PAD_EPDC_SDOEZ__AUD5_TXC IOMUX_PAD(0x5A0, 0x204, 4, 0x0, 0, NO_PAD_CTRL)
764
765#define MX50_PAD_EPDC_SDOED__EPDC_SDOED IOMUX_PAD(0x5A4, 0x208, 0, 0x0, 0, NO_PAD_CTRL)
766#define MX50_PAD_EPDC_SDOED__GPIO_3_22 IOMUX_PAD(0x5A4, 0x208, 1, 0x0, 0, NO_PAD_CTRL)
767#define MX50_PAD_EPDC_SDOED__WEIM_D22 IOMUX_PAD(0x5A4, 0x208, 2, 0x0, 0, NO_PAD_CTRL)
768#define MX50_PAD_EPDC_SDOED__ELCDIF_D22 IOMUX_PAD(0x5A4, 0x208, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
769#define MX50_PAD_EPDC_SDOED__AUD5_TXFS IOMUX_PAD(0x5A4, 0x208, 4, 0x0, 0, NO_PAD_CTRL)
770
771#define MX50_PAD_EPDC_SDOE__EPDC_SDOE IOMUX_PAD(0x5A8, 0x20C, 0, 0x0, 0, NO_PAD_CTRL)
772#define MX50_PAD_EPDC_SDOE__GPIO_3_23 IOMUX_PAD(0x5A8, 0x20C, 1, 0x0, 0, NO_PAD_CTRL)
773#define MX50_PAD_EPDC_SDOE__WEIM_D23 IOMUX_PAD(0x5A8, 0x20C, 2, 0x0, 0, NO_PAD_CTRL)
774#define MX50_PAD_EPDC_SDOE__ELCDIF_D23 IOMUX_PAD(0x5A8, 0x20C, 3, 0x0, 0, MX50_ELCDIF_PAD_CTRL)
775#define MX50_PAD_EPDC_SDOE__AUD5_RXD IOMUX_PAD(0x5A8, 0x20C, 4, 0x0, 0, NO_PAD_CTRL)
776
777#define MX50_PAD_EPDC_SDLE__EPDC_SDLE IOMUX_PAD(0x5AC, 0x210, 0, 0x0, 0, NO_PAD_CTRL)
778#define MX50_PAD_EPDC_SDLE__GPIO_3_24 IOMUX_PAD(0x5AC, 0x210, 1, 0x0, 0, NO_PAD_CTRL)
779#define MX50_PAD_EPDC_SDLE__WEIM_D24 IOMUX_PAD(0x5AC, 0x210, 2, 0x0, 0, NO_PAD_CTRL)
780#define MX50_PAD_EPDC_SDLE__ELCDIF_D8 IOMUX_PAD(0x5AC, 0x210, 3, 0x71c, 1, MX50_ELCDIF_PAD_CTRL)
781#define MX50_PAD_EPDC_SDLE__AUD5_RXC IOMUX_PAD(0x5AC, 0x210, 4, 0x0, 0, NO_PAD_CTRL)
782
783#define MX50_PAD_EPDC_SDCLKN__EPDC_SDCLKN IOMUX_PAD(0x5B0, 0x214, 0, 0x0, 0, NO_PAD_CTRL)
784#define MX50_PAD_EPDC_SDCLKN__GPIO_3_25 IOMUX_PAD(0x5B0, 0x214, 1, 0x0, 0, NO_PAD_CTRL)
785#define MX50_PAD_EPDC_SDCLKN__WEIM_D25 IOMUX_PAD(0x5B0, 0x214, 2, 0x0, 0, NO_PAD_CTRL)
786#define MX50_PAD_EPDC_SDCLKN__ELCDIF_D9 IOMUX_PAD(0x5B0, 0x214, 3, 0x720, 1, MX50_ELCDIF_PAD_CTRL)
787#define MX50_PAD_EPDC_SDCLKN__AUD5_RXFS IOMUX_PAD(0x5B0, 0x214, 4, 0x0, 0, NO_PAD_CTRL)
788
789#define MX50_PAD_EPDC_SDSHR__EPDC_SDSHR IOMUX_PAD(0x5B4, 0x218, 0, 0x0, 0, NO_PAD_CTRL)
790#define MX50_PAD_EPDC_SDSHR__GPIO_3_26 IOMUX_PAD(0x5B4, 0x218, 1, 0x0, 0, NO_PAD_CTRL)
791#define MX50_PAD_EPDC_SDSHR__WEIM_D26 IOMUX_PAD(0x5B4, 0x218, 2, 0x0, 0, NO_PAD_CTRL)
792#define MX50_PAD_EPDC_SDSHR__ELCDIF_D10 IOMUX_PAD(0x5B4, 0x218, 3, 0x724, 1, MX50_ELCDIF_PAD_CTRL)
793#define MX50_PAD_EPDC_SDSHR__AUD4_TXD IOMUX_PAD(0x5B4, 0x218, 4, 0x6c8, 1, NO_PAD_CTRL)
794
795#define MX50_PAD_EPDC_PWRCOM__EPDC_PWRCOM IOMUX_PAD(0x5B8, 0x21C, 0, 0x0, 0, NO_PAD_CTRL)
796#define MX50_PAD_EPDC_PWRCOM__GPIO_3_27 IOMUX_PAD(0x5B8, 0x21C, 1, 0x0, 0, NO_PAD_CTRL)
797#define MX50_PAD_EPDC_PWRCOM__WEIM_D27 IOMUX_PAD(0x5B8, 0x21C, 2, 0x0, 0, NO_PAD_CTRL)
798#define MX50_PAD_EPDC_PWRCOM__ELCDIF_D11 IOMUX_PAD(0x5B8, 0x21C, 3, 0x728, 1, MX50_ELCDIF_PAD_CTRL)
799#define MX50_PAD_EPDC_PWRCOM__AUD4_TXC IOMUX_PAD(0x5B8, 0x21C, 4, 0x6d4, 1, NO_PAD_CTRL)
800
801#define MX50_PAD_EPDC_PWRSTAT__EPDC_PWRSTAT IOMUX_PAD(0x5BC, 0x220, 0, 0x0, 0, NO_PAD_CTRL)
802#define MX50_PAD_EPDC_PWRSTAT__GPIO_3_28 IOMUX_PAD(0x5BC, 0x220, 1, 0x0, 0, NO_PAD_CTRL)
803#define MX50_PAD_EPDC_PWRSTAT__WEIM_D28 IOMUX_PAD(0x5BC, 0x220, 2, 0x0, 0, NO_PAD_CTRL)
804#define MX50_PAD_EPDC_PWRSTAT__ELCDIF_D12 IOMUX_PAD(0x5BC, 0x220, 3, 0x72c, 1, MX50_ELCDIF_PAD_CTRL)
805#define MX50_PAD_EPDC_PWRSTAT__AUD4_TXFS IOMUX_PAD(0x5BC, 0x220, 4, 0x6d8, 1, NO_PAD_CTRL)
806
807#define MX50_PAD_EPDC_PWRCTRL0__EPDC_PWRCTRL0 IOMUX_PAD(0x5C0, 0x224, 0, 0x0, 0, NO_PAD_CTRL)
808#define MX50_PAD_EPDC_PWRCTRL0__GPIO_3_29 IOMUX_PAD(0x5C0, 0x224, 1, 0x0, 0, NO_PAD_CTRL)
809#define MX50_PAD_EPDC_PWRCTRL0__WEIM_D29 IOMUX_PAD(0x5C0, 0x224, 2, 0x0, 0, NO_PAD_CTRL)
810#define MX50_PAD_EPDC_PWRCTRL0__ELCDIF_D13 IOMUX_PAD(0x5C0, 0x224, 3, 0x730, 1, MX50_ELCDIF_PAD_CTRL)
811#define MX50_PAD_EPDC_PWRCTRL0__AUD4_RXD IOMUX_PAD(0x5C0, 0x224, 4, 0x6c4, 1, NO_PAD_CTRL)
812
813#define MX50_PAD_EPDC_PWRCTRL1__EPDC_PWRCTRL1 IOMUX_PAD(0x5C4, 0x228, 0, 0x0, 0, NO_PAD_CTRL)
814#define MX50_PAD_EPDC_PWRCTRL1__GPIO_3_30 IOMUX_PAD(0x5C4, 0x228, 1, 0x0, 0, NO_PAD_CTRL)
815#define MX50_PAD_EPDC_PWRCTRL1__WEIM_D30 IOMUX_PAD(0x5C4, 0x228, 2, 0x0, 0, NO_PAD_CTRL)
816#define MX50_PAD_EPDC_PWRCTRL1__ELCDIF_D14 IOMUX_PAD(0x5C4, 0x228, 3, 0x734, 1, MX50_ELCDIF_PAD_CTRL)
817#define MX50_PAD_EPDC_PWRCTRL1__AUD4_RXC IOMUX_PAD(0x5C4, 0x228, 4, 0x6cc, 1, NO_PAD_CTRL)
818
819#define MX50_PAD_EPDC_PWRCTRL2__EPDC_PWRCTRL2 IOMUX_PAD(0x5C8, 0x22C, 0, 0x0, 0, NO_PAD_CTRL)
820#define MX50_PAD_EPDC_PWRCTRL2__GPIO_3_31 IOMUX_PAD(0x5C8, 0x22C, 1, 0x0, 0, NO_PAD_CTRL)
821#define MX50_PAD_EPDC_PWRCTRL2__WEIM_D31 IOMUX_PAD(0x5C8, 0x22C, 2, 0x0, 0, NO_PAD_CTRL)
822#define MX50_PAD_EPDC_PWRCTRL2__ELCDIF_D15 IOMUX_PAD(0x5C8, 0x22C, 3, 0x738, 1, MX50_ELCDIF_PAD_CTRL)
823#define MX50_PAD_EPDC_PWRCTRL2__AUD4_RXFS IOMUX_PAD(0x5C8, 0x22C, 4, 0x6d0, 1, NO_PAD_CTRL)
824#define MX50_PAD_EPDC_PWRCTRL2__SDMA_EXT0 IOMUX_PAD(0x5C8, 0x22C, 6, 0x7b8, 1, NO_PAD_CTRL)
825
826#define MX50_PAD_EPDC_PWRCTRL3__PWRCTRL3 IOMUX_PAD(0x5CC, 0x230, 0, 0x0, 0, NO_PAD_CTRL)
827#define MX50_PAD_EPDC_PWRCTRL3__GPIO_4_20 IOMUX_PAD(0x5CC, 0x230, 1, 0x0, 0, NO_PAD_CTRL)
828#define MX50_PAD_EPDC_PWRCTRL3__WEIM_EB2 IOMUX_PAD(0x5CC, 0x230, 2, 0x0, 0, NO_PAD_CTRL)
829#define MX50_PAD_EPDC_PWRCTRL3__SDMA_EXT1 IOMUX_PAD(0x5CC, 0x230, 6, 0x7bc, 1, NO_PAD_CTRL)
830
831#define MX50_PAD_EPDC_VCOM0__EPDC_VCOM0 IOMUX_PAD(0x5D0, 0x234, 0, 0x0, 0, NO_PAD_CTRL)
832#define MX50_PAD_EPDC_VCOM0__GPIO_4_21 IOMUX_PAD(0x5D0, 0x234, 1, 0x0, 0, NO_PAD_CTRL)
833#define MX50_PAD_EPDC_VCOM0__WEIM_EB3 IOMUX_PAD(0x5D0, 0x234, 2, 0x0, 0, NO_PAD_CTRL)
834
835#define MX50_PAD_EPDC_VCOM1__EPDC_VCOM1 IOMUX_PAD(0x5D4, 0x238, 0, 0x0, 0, NO_PAD_CTRL)
836#define MX50_PAD_EPDC_VCOM1__GPIO_4_22 IOMUX_PAD(0x5D4, 0x238, 1, 0x0, 0, NO_PAD_CTRL)
837#define MX50_PAD_EPDC_VCOM1__WEIM_CS3 IOMUX_PAD(0x5D4, 0x238, 2, 0x0, 0, NO_PAD_CTRL)
838
839#define MX50_PAD_EPDC_BDR0__EPDC_BDR0 IOMUX_PAD(0x5D8, 0x23C, 0, 0x0, 0, NO_PAD_CTRL)
840#define MX50_PAD_EPDC_BDR0__GPIO_4_23 IOMUX_PAD(0x5D8, 0x23C, 1, 0x0, 0, NO_PAD_CTRL)
841#define MX50_PAD_EPDC_BDR0__ELCDIF_D7 IOMUX_PAD(0x5D8, 0x23C, 3, 0x718, 1, MX50_ELCDIF_PAD_CTRL)
842
843#define MX50_PAD_EPDC_BDR1__EPDC_BDR1 IOMUX_PAD(0x5DC, 0x240, 0, 0x0, 0, NO_PAD_CTRL)
844#define MX50_PAD_EPDC_BDR1__GPIO_4_24 IOMUX_PAD(0x5DC, 0x240, 1, 0x0, 0, NO_PAD_CTRL)
845#define MX50_PAD_EPDC_BDR1__ELCDIF_D6 IOMUX_PAD(0x5DC, 0x240, 3, 0x714, 1, MX50_ELCDIF_PAD_CTRL)
846
847#define MX50_PAD_EPDC_SDCE0__EPDC_SDCE0 IOMUX_PAD(0x5E0, 0x244, 0, 0x0, 0, NO_PAD_CTRL)
848#define MX50_PAD_EPDC_SDCE0__GPIO_4_25 IOMUX_PAD(0x5E0, 0x244, 1, 0x0, 0, NO_PAD_CTRL)
849#define MX50_PAD_EPDC_SDCE0__ELCDIF_D5 IOMUX_PAD(0x5E0, 0x244, 3, 0x710, 1, MX50_ELCDIF_PAD_CTRL)
850
851#define MX50_PAD_EPDC_SDCE1__EPDC_SDCE1 IOMUX_PAD(0x5E4, 0x248, 0, 0x0, 0, NO_PAD_CTRL)
852#define MX50_PAD_EPDC_SDCE1__GPIO_4_26 IOMUX_PAD(0x5E4, 0x248, 1, 0x0, 0, NO_PAD_CTRL)
853#define MX50_PAD_EPDC_SDCE1__ELCDIF_D4 IOMUX_PAD(0x5E4, 0x248, 2, 0x70c, 1, MX50_ELCDIF_PAD_CTRL)
854
855#define MX50_PAD_EPDC_SDCE2__EPDC_SDCE2 IOMUX_PAD(0x5E8, 0x24C, 0, 0x0, 0, NO_PAD_CTRL)
856#define MX50_PAD_EPDC_SDCE2__GPIO_4_27 IOMUX_PAD(0x5E8, 0x24C, 1, 0x0, 0, NO_PAD_CTRL)
857#define MX50_PAD_EPDC_SDCE2__ELCDIF_DAT3 IOMUX_PAD(0x5E8, 0x24C, 3, 0x708, 1, MX50_ELCDIF_PAD_CTRL)
858
859#define MX50_PAD_EPDC_SDCE3__EPDC_SDCE3 IOMUX_PAD(0x5EC, 0x250, 0, 0x0, 0, NO_PAD_CTRL)
860#define MX50_PAD_EPDC_SDCE3__GPIO_4_28 IOMUX_PAD(0x5EC, 0x250, 1, 0x0, 0, NO_PAD_CTRL)
861#define MX50_PAD_EPDC_SDCE3__ELCDIF_D2 IOMUX_PAD(0x5EC, 0x250, 3, 0x704, 1, MX50_ELCDIF_PAD_CTRL)
862
863#define MX50_PAD_EPDC_SDCE4__EPDC_SDCE4 IOMUX_PAD(0x5F0, 0x254, 0, 0x0, 0, NO_PAD_CTRL)
864#define MX50_PAD_EPDC_SDCE4__GPIO_4_29 IOMUX_PAD(0x5F0, 0x254, 1, 0x0, 0, NO_PAD_CTRL)
865#define MX50_PAD_EPDC_SDCE4__ELCDIF_D1 IOMUX_PAD(0x5F0, 0x254, 3, 0x700, 1, MX50_ELCDIF_PAD_CTRL)
866
867#define MX50_PAD_EPDC_SDCE5__EPDC_SDCE5 IOMUX_PAD(0x5F4, 0x258, 0, 0x0, 0, NO_PAD_CTRL)
868#define MX50_PAD_EPDC_SDCE5__GPIO_4_30 IOMUX_PAD(0x5F4, 0x258, 1, 0x0, 0, NO_PAD_CTRL)
869#define MX50_PAD_EPDC_SDCE5__ELCDIF_D0 IOMUX_PAD(0x5F4, 0x258, 3, 0x6fc, 1, MX50_ELCDIF_PAD_CTRL)
870
871#define MX50_PAD_EIM_DA0__WEIM_A0 IOMUX_PAD(0x5F8, 0x25C, 0, 0x0, 0, NO_PAD_CTRL)
872#define MX50_PAD_EIM_DA0__GPIO_1_0 IOMUX_PAD(0x5F8, 0x25C, 1, 0x0, 0, NO_PAD_CTRL)
873#define MX50_PAD_EIM_DA0__KEY_COL4 IOMUX_PAD(0x5f8, 0x25C, 3, 0x790, 2, NO_PAD_CTRL)
874
875#define MX50_PAD_EIM_DA1__WEIM_A1 IOMUX_PAD(0x5FC, 0x260, 0, 0x0, 0, NO_PAD_CTRL)
876#define MX50_PAD_EIM_DA1__GPIO_1_1 IOMUX_PAD(0x5FC, 0x260, 1, 0x0, 0, NO_PAD_CTRL)
877#define MX50_PAD_EIM_DA1__KEY_ROW4 IOMUX_PAD(0x5fc, 0x260, 3, 0x7a0, 2, MX50_KEYPAD_CTRL)
878
879#define MX50_PAD_EIM_DA2__WEIM_A2 IOMUX_PAD(0x600, 0x264, 0, 0x0, 0, NO_PAD_CTRL)
880#define MX50_PAD_EIM_DA2__GPIO_1_2 IOMUX_PAD(0x600, 0x264, 1, 0x0, 0, NO_PAD_CTRL)
881#define MX50_PAD_EIM_DA2__KEY_COL5 IOMUX_PAD(0x600, 0x264, 3, 0x794, 2, NO_PAD_CTRL)
882
883#define MX50_PAD_EIM_DA3__WEIM_A3 IOMUX_PAD(0x604, 0x268, 0, 0x0, 0, NO_PAD_CTRL)
884#define MX50_PAD_EIM_DA3__GPIO_1_3 IOMUX_PAD(0x604, 0x268, 1, 0x0, 0, NO_PAD_CTRL)
885#define MX50_PAD_EIM_DA3__KEY_ROW5 IOMUX_PAD(0x604, 0x268, 3, 0x7a4, 2, MX50_KEYPAD_CTRL)
886
887#define MX50_PAD_EIM_DA4__WEIM_A4 IOMUX_PAD(0x608, 0x26C, 0, 0x0, 0, NO_PAD_CTRL)
888#define MX50_PAD_EIM_DA4__GPIO_1_4 IOMUX_PAD(0x608, 0x26C, 1, 0x0, 0, NO_PAD_CTRL)
889#define MX50_PAD_EIM_DA4__KEY_COL6 IOMUX_PAD(0x608, 0x26C, 3, 0x798, 2, NO_PAD_CTRL)
890
891#define MX50_PAD_EIM_DA5__WEIM_A5 IOMUX_PAD(0x60C, 0x270, 0, 0x0, 0, NO_PAD_CTRL)
892#define MX50_PAD_EIM_DA5__GPIO_1_5 IOMUX_PAD(0x60C, 0x270, 1, 0x0, 0, NO_PAD_CTRL)
893#define MX50_PAD_EIM_DA5__KEY_ROW6 IOMUX_PAD(0x60C, 0x270, 3, 0x7a8, 2, MX50_KEYPAD_CTRL)
894
895#define MX50_PAD_EIM_DA6__WEIM_A6 IOMUX_PAD(0x610, 0x274, 0, 0x0, 0, NO_PAD_CTRL)
896#define MX50_PAD_EIM_DA6__GPIO_1_6 IOMUX_PAD(0x610, 0x274, 1, 0x0, 0, NO_PAD_CTRL)
897#define MX50_PAD_EIM_DA6__KEY_COL7 IOMUX_PAD(0x610, 0x274, 3, 0x79c, 2, NO_PAD_CTRL)
898
899#define MX50_PAD_EIM_DA7__WEIM_A7 IOMUX_PAD(0x614, 0x278, 0, 0x0, 0, NO_PAD_CTRL)
900#define MX50_PAD_EIM_DA7__GPIO_1_7 IOMUX_PAD(0x614, 0x278, 1, 0x0, 0, NO_PAD_CTRL)
901#define MX50_PAD_EIM_DA7__KEY_ROW7 IOMUX_PAD(0x614, 0x278, 3, 0x7ac, 2, MX50_KEYPAD_CTRL)
902
903#define MX50_PAD_EIM_DA8__WEIM_A8 IOMUX_PAD(0x618, 0x27C, 0, 0x0, 0, NO_PAD_CTRL)
904#define MX50_PAD_EIM_DA8__GPIO_1_8 IOMUX_PAD(0x618, 0x27C, 1, 0x0, 0, NO_PAD_CTRL)
905#define MX50_PIN_EIM_DA8__NANDF_CLE IOMUX_PAD(0x618, 0x27C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
906
907#define MX50_PAD_EIM_DA9__WEIM_A9 IOMUX_PAD(0x61C, 0x280, 0, 0x0, 0, NO_PAD_CTRL)
908#define MX50_PAD_EIM_DA9__GPIO_1_9 IOMUX_PAD(0x61C, 0x280, 1, 0x0, 0, NO_PAD_CTRL)
909#define MX50_PIN_EIM_DA9__NANDF_ALE IOMUX_PAD(0x61C, 0x280, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
910
911#define MX50_PAD_EIM_DA10__WEIM_A10 IOMUX_PAD(0x620, 0x284, 0, 0x0, 0, NO_PAD_CTRL)
912#define MX50_PAD_EIM_DA10__GPIO_1_10 IOMUX_PAD(0x620, 0x284, 1, 0x0, 0, NO_PAD_CTRL)
913#define MX50_PIN_EIM_DA10__NANDF_CE0 IOMUX_PAD(0x620, 0x284, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
914
915#define MX50_PAD_EIM_DA11__WEIM_A11 IOMUX_PAD(0x624, 0x288, 0, 0x0, 0, NO_PAD_CTRL)
916#define MX50_PAD_EIM_DA11__GPIO_1_11 IOMUX_PAD(0x624, 0x288, 1, 0x0, 0, NO_PAD_CTRL)
917#define MX50_PIN_EIM_DA11__NANDF_CE1 IOMUX_PAD(0x624, 0x288, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
918
919#define MX50_PAD_EIM_DA12__WEIM_A12 IOMUX_PAD(0x628, 0x28C, 0, 0x0, 0, NO_PAD_CTRL)
920#define MX50_PAD_EIM_DA12__GPIO_1_12 IOMUX_PAD(0x628, 0x28C, 1, 0x0, 0, NO_PAD_CTRL)
921#define MX50_PIN_EIM_DA12__NANDF_CE2 IOMUX_PAD(0x628, 0x28C, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
922#define MX50_PAD_EIM_DA12__EPDC_SDCE6 IOMUX_PAD(0x628, 0x28C, 3, 0x0, 0, NO_PAD_CTRL)
923
924#define MX50_PAD_EIM_DA13__WEIM_A13 IOMUX_PAD(0x62C, 0x290, 0, 0x0, 0, NO_PAD_CTRL)
925#define MX50_PAD_EIM_DA13__GPIO_1_13 IOMUX_PAD(0x62C, 0x290, 1, 0x0, 0, NO_PAD_CTRL)
926#define MX50_PIN_EIM_DA13__NANDF_CE3 IOMUX_PAD(0x62C, 0x290, 2, 0x0, 0, PAD_CTL_DSE_HIGH)
927#define MX50_PIN_EIM_DA13__EPDC_SDCE7 IOMUX_PAD(0x62C, 0x290, 3, 0x0, 0, NO_PAD_CTRL)
928
929#define MX50_PAD_EIM_DA14__WEIM_A14 IOMUX_PAD(0x630, 0x294, 0, 0x0, 0, NO_PAD_CTRL)
930#define MX50_PAD_EIM_DA14__GPIO_1_14 IOMUX_PAD(0x630, 0x294, 1, 0x0, 0, NO_PAD_CTRL)
931#define MX50_PAD_EIM_DA14__NANDF_READY IOMUX_PAD(0x630, 0x294, 2, 0x7B4, 2, PAD_CTL_PKE | \
932 PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
933#define MX50_PAD_EIM_DA14__EPDC_SDCE8 IOMUX_PAD(0x630, 0x294, 3, 0x0, 0, NO_PAD_CTRL)
934
935#define MX50_PAD_EIM_DA15__WEIM_A15 IOMUX_PAD(0x634, 0x298, 0, 0x0, 0, NO_PAD_CTRL)
936#define MX50_PAD_EIM_DA15__GPIO_1_15 IOMUX_PAD(0x634, 0x298, 1, 0x0, 0, NO_PAD_CTRL)
937#define MX50_PIN_EIM_DA15__NANDF_DQS IOMUX_PAD(0x634, 0x298, 2, 0x7B0, 2, PAD_CTL_DSE_HIGH)
938#define MX50_PAD_EIM_DA15__EPDC_SDCE9 IOMUX_PAD(0x634, 0x298, 3, 0x0, 0, NO_PAD_CTRL)
939
940#define MX50_PAD_EIM_CS2__WEIM_CS2 IOMUX_PAD(0x638, 0x29C, 0, 0x0, 0, NO_PAD_CTRL)
941#define MX50_PAD_EIM_CS2__GPIO_1_16 IOMUX_PAD(0x638, 0x29C, 1, 0x0, 0, NO_PAD_CTRL)
942#define MX50_PAD_EIM_CS2__WEIM_A27 IOMUX_PAD(0x638, 0x29C, 2, 0x0, 0, NO_PAD_CTRL)
943
944#define MX50_PAD_EIM_CS1__WEIM_CS1 IOMUX_PAD(0x63C, 0x2A0, 0, 0x0, 0, NO_PAD_CTRL)
945#define MX50_PAD_EIM_CS1__GPIO_1_17 IOMUX_PAD(0x63C, 0x2A0, 1, 0x0, 0, NO_PAD_CTRL)
946
947#define MX50_PAD_EIM_CS0__WEIM_CS0 IOMUX_PAD(0x640, 0x2A4, 0, 0x0, 0, NO_PAD_CTRL)
948#define MX50_PAD_EIM_CS0__GPIO_1_18 IOMUX_PAD(0x640, 0x2A4, 1, 0x0, 0, NO_PAD_CTRL)
949
950#define MX50_PAD_EIM_EB0__WEIM_EB0 IOMUX_PAD(0x644, 0x2A8, 0, 0x0, 0, NO_PAD_CTRL)
951#define MX50_PAD_EIM_EB0__GPIO_1_19 IOMUX_PAD(0x644, 0x2A8, 1, 0x0, 0, NO_PAD_CTRL)
952
953#define MX50_PAD_EIM_EB1__WEIM_EB1 IOMUX_PAD(0x648, 0x2AC, 0, 0x0, 0, NO_PAD_CTRL)
954#define MX50_PAD_EIM_EB1__GPIO_1_20 IOMUX_PAD(0x648, 0x2AC, 1, 0x0, 0, NO_PAD_CTRL)
955
956#define MX50_PAD_EIM_WAIT__WEIM_WAIT IOMUX_PAD(0x64C, 0x2B0, 0, 0x0, 0, NO_PAD_CTRL)
957#define MX50_PAD_EIM_WAIT__GPIO_1_21 IOMUX_PAD(0x64C, 0x2B0, 1, 0x0, 0, NO_PAD_CTRL)
958
959#define MX50_PAD_EIM_BCLK__WEIM_BCLK IOMUX_PAD(0x650, 0x2B4, 0, 0x0, 0, NO_PAD_CTRL)
960#define MX50_PAD_EIM_BCLK__GPIO_1_22 IOMUX_PAD(0x650, 0x2B4, 1, 0x0, 0, NO_PAD_CTRL)
961
962#define MX50_PAD_EIM_RDY__WEIM_RDY IOMUX_PAD(0x654, 0x2B8, 0, 0x0, 0, NO_PAD_CTRL)
963#define MX50_PAD_EIM_RDY__GPIO_1_23 IOMUX_PAD(0x654, 0x2B8, 1, 0x0, 0, NO_PAD_CTRL)
964
965#define MX50_PAD_EIM_OE__WEIM_OE IOMUX_PAD(0x658, 0x2BC, 0, 0x0, 0, NO_PAD_CTRL)
966#define MX50_PAD_EIM_OE__GPIO_1_24 IOMUX_PAD(0x658, 0x2BC, 1, 0x0, 0, NO_PAD_CTRL)
967
968#define MX50_PAD_EIM_RW__WEIM_RW IOMUX_PAD(0x65C, 0x2C0, 0, 0x0, 0, NO_PAD_CTRL)
969#define MX50_PAD_EIM_RW__GPIO_1_25 IOMUX_PAD(0x65C, 0x2C0, 1, 0x0, 0, NO_PAD_CTRL)
970
971#define MX50_PAD_EIM_LBA__WEIM_LBA IOMUX_PAD(0x660, 0x2C4, 0, 0x0, 0, NO_PAD_CTRL)
972#define MX50_PAD_EIM_LBA__GPIO_1_26 IOMUX_PAD(0x660, 0x2C4, 1, 0x0, 0, NO_PAD_CTRL)
973
974#define MX50_PAD_EIM_CRE__WEIM_CRE IOMUX_PAD(0x664, 0x2C8, 0, 0x0, 0, NO_PAD_CTRL)
975#define MX50_PAD_EIM_CRE__GPIO_1_27 IOMUX_PAD(0x664, 0x2C8, 1, 0x0, 0, NO_PAD_CTRL)
976
977#endif /* __MACH_IOMUX_MX50_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index d7a41e9a2605..b6767f90ef14 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -15,373 +15,1553 @@
15 15
16#include <mach/iomux-v3.h> 16#include <mach/iomux-v3.h>
17 17
18/*
19 * various IOMUX alternate output functions (1-7)
20 */
21typedef enum iomux_config {
22 IOMUX_CONFIG_ALT0,
23 IOMUX_CONFIG_ALT1,
24 IOMUX_CONFIG_ALT2,
25 IOMUX_CONFIG_ALT3,
26 IOMUX_CONFIG_ALT4,
27 IOMUX_CONFIG_ALT5,
28 IOMUX_CONFIG_ALT6,
29 IOMUX_CONFIG_ALT7,
30 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
31 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
32} iomux_pin_cfg_t;
33
34/* Pad control groupings */ 18/* Pad control groupings */
35#define MX51_UART1_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_PUE | \ 19#define MX51_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
36 PAD_CTL_DSE_HIGH) 20 PAD_CTL_HYS | PAD_CTL_SRE_FAST)
37#define MX51_UART2_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_DSE_HIGH | \
38 PAD_CTL_SRE_FAST)
39#define MX51_UART3_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
40 PAD_CTL_SRE_FAST)
41#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \ 21#define MX51_I2C_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
42 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | PAD_CTL_HYS) 22 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
43#define MX51_USBH1_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 23 PAD_CTL_HYS)
44 PAD_CTL_PUS_100K_UP | PAD_CTL_PUE | \ 24#define MX51_ESDHC_PAD_CTRL (PAD_CTL_SRE_FAST | PAD_CTL_ODE | \
45 PAD_CTL_PKE | PAD_CTL_HYS) 25 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
46#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \ 26 PAD_CTL_HYS)
47 PAD_CTL_SRE_FAST) 27#define MX51_USBH1_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
48#define MX51_GPIO_PAD_CTRL_2 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 28 PAD_CTL_DSE_HIGH | PAD_CTL_PUS_100K_UP | \
49 PAD_CTL_PUS_100K_UP) 29 PAD_CTL_HYS | PAD_CTL_PUE)
50#define MX51_ECSPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \ 30#define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \
51 PAD_CTL_SRE_FAST) 31 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST)
52#define MX51_SDHCI_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PUS_47K_UP | \ 32#define MX51_SDHCI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
53 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_SRE_FAST | \ 33 PAD_CTL_PUS_47K_UP | PAD_CTL_PUE | \
54 PAD_CTL_DVS) 34 PAD_CTL_SRE_FAST | PAD_CTL_DVS)
35#define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
55 36
56#define MX51_PAD_CTRL_1 (PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \ 37#define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS)
57 PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS) 38#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP)
58#define MX51_PAD_CTRL_2 (PAD_CTL_HYS | PAD_CTL_PKE) 39#define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
59#define MX51_PAD_CTRL_3 (PAD_CTL_PKE | PAD_CTL_PUS_100K_UP) 40#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
60#define MX51_PAD_CTRL_4 (PAD_CTL_DVS | PAD_CTL_HYS | PAD_CTL_PKE)
61#define MX51_PAD_CTRL_5 (PAD_CTL_DVS | PAD_CTL_DSE_HIGH)
62 41
63/* 42/*
64 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode> 43 * The naming convention for the pad modes is MX51_PAD_<padname>__<padmode>
65 * If <padname> or <padmode> refers to a GPIO, it is named GPIO_<unit>_<num> 44 * If <padname> or <padmode> refers to a GPIO, it is named GPIO<unit>_<num>
66 * See also iomux-v3.h 45 * See also iomux-v3.h
67 */ 46 */
68 47
69/* PAD MUX ALT INPSE PATH PADCTRL */ 48/* Raw pin modes without pad control */
70#define MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x7a8, 0x01c, 0, 0x0, 0, NO_PAD_CTRL) 49/* PAD MUX ALT INPSE PATH PADCTRL */
71#define MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x7a8, 0x020, 0, 0x0, 0, NO_PAD_CTRL) 50#define _MX51_PAD_EIM_D16__AUD4_RXFS IOMUX_PAD(0x3f0, 0x5c, 5, 0x0000, 0, 0)
72#define MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x7a8, 0x024, 0, 0x0, 0, NO_PAD_CTRL) 51#define _MX51_PAD_EIM_D16__AUD5_TXD IOMUX_PAD(0x3f0, 0x5c, 7, 0x08d8, 0, 0)
73#define MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x7a8, 0x028, 0, 0x0, 0, NO_PAD_CTRL) 52#define _MX51_PAD_EIM_D16__EIM_D16 IOMUX_PAD(0x3f0, 0x5c, 0, 0x0000, 0, 0)
74#define MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x7ac, 0x02c, 0, 0x0, 0, NO_PAD_CTRL) 53#define _MX51_PAD_EIM_D16__GPIO2_0 IOMUX_PAD(0x3f0, 0x5c, 1, 0x0000, 0, 0)
75#define MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x7ac, 0x030, 0, 0x0, 0, NO_PAD_CTRL) 54#define _MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x5c, 0x14, 0x09b4, 0, 0)
76#define MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x7ac, 0x034, 0, 0x0, 0, NO_PAD_CTRL) 55#define _MX51_PAD_EIM_D16__UART2_CTS IOMUX_PAD(0x3f0, 0x5c, 3, 0x0000, 0, 0)
77#define MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x7ac, 0x038, 0, 0x0, 0, NO_PAD_CTRL) 56#define _MX51_PAD_EIM_D16__USBH2_DATA0 IOMUX_PAD(0x3f0, 0x5c, 2, 0x0000, 0, 0)
78#define MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x7b0, 0x03c, 0, 0x0, 0, NO_PAD_CTRL) 57#define _MX51_PAD_EIM_D17__AUD5_RXD IOMUX_PAD(0x3f4, 0x60, 7, 0x08d4, 0, 0)
79#define MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x7b0, 0x040, 0, 0x0, 0, NO_PAD_CTRL) 58#define _MX51_PAD_EIM_D17__EIM_D17 IOMUX_PAD(0x3f4, 0x60, 0, 0x0000, 0, 0)
80#define MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x7b0, 0x044, 0, 0x0, 0, NO_PAD_CTRL) 59#define _MX51_PAD_EIM_D17__GPIO2_1 IOMUX_PAD(0x3f4, 0x60, 1, 0x0000, 0, 0)
81#define MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x7b0, 0x048, 0, 0x0, 0, NO_PAD_CTRL) 60#define _MX51_PAD_EIM_D17__UART2_RXD IOMUX_PAD(0x3f4, 0x60, 3, 0x09ec, 0, 0)
82#define MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x7bc, 0x04c, 0, 0x0, 0, NO_PAD_CTRL) 61#define _MX51_PAD_EIM_D17__UART3_CTS IOMUX_PAD(0x3f4, 0x60, 4, 0x0000, 0, 0)
83#define MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x7bc, 0x050, 0, 0x0, 0, NO_PAD_CTRL) 62#define _MX51_PAD_EIM_D17__USBH2_DATA1 IOMUX_PAD(0x3f4, 0x60, 2, 0x0000, 0, 0)
84#define MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x7bc, 0x054, 0, 0x0, 0, NO_PAD_CTRL) 63#define _MX51_PAD_EIM_D18__AUD5_TXC IOMUX_PAD(0x3f8, 0x64, 7, 0x08e4, 0, 0)
85#define MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x7bc, 0x058, 0, 0x0, 0, NO_PAD_CTRL) 64#define _MX51_PAD_EIM_D18__EIM_D18 IOMUX_PAD(0x3f8, 0x64, 0, 0x0000, 0, 0)
86#define MX51_PAD_EIM_D16__GPIO_2_0 IOMUX_PAD(0x3f0, 0x05c, 1, 0x0, 0, NO_PAD_CTRL) 65#define _MX51_PAD_EIM_D18__GPIO2_2 IOMUX_PAD(0x3f8, 0x64, 1, 0x0000, 0, 0)
87#define MX51_PAD_EIM_D16__I2C1_SDA IOMUX_PAD(0x3f0, 0x05c, (4 | IOMUX_CONFIG_SION), \ 66#define _MX51_PAD_EIM_D18__UART2_TXD IOMUX_PAD(0x3f8, 0x64, 3, 0x0000, 0, 0)
88 0x09b4, 0, MX51_I2C_PAD_CTRL) 67#define _MX51_PAD_EIM_D18__UART3_RTS IOMUX_PAD(0x3f8, 0x64, 4, 0x09f0, 1, 0)
89#define MX51_PAD_EIM_D17__GPIO_2_1 IOMUX_PAD(0x3f4, 0x060, 1, 0x0, 0, NO_PAD_CTRL) 68#define _MX51_PAD_EIM_D18__USBH2_DATA2 IOMUX_PAD(0x3f8, 0x64, 2, 0x0000, 0, 0)
90#define MX51_PAD_EIM_D18__GPIO_2_2 IOMUX_PAD(0x3f8, 0x064, 1, 0x0, 0, NO_PAD_CTRL) 69#define _MX51_PAD_EIM_D19__AUD4_RXC IOMUX_PAD(0x3fc, 0x68, 5, 0x0000, 0, 0)
91#define MX51_PAD_EIM_D19__GPIO_2_3 IOMUX_PAD(0x3fc, 0x068, 1, 0x0, 0, NO_PAD_CTRL) 70#define _MX51_PAD_EIM_D19__AUD5_TXFS IOMUX_PAD(0x3fc, 0x68, 7, 0x08e8, 0, 0)
92#define MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x068, (4 | IOMUX_CONFIG_SION), \ 71#define _MX51_PAD_EIM_D19__EIM_D19 IOMUX_PAD(0x3fc, 0x68, 0, 0x0000, 0, 0)
93 0x09b0, 0, MX51_I2C_PAD_CTRL) 72#define _MX51_PAD_EIM_D19__GPIO2_3 IOMUX_PAD(0x3fc, 0x68, 1, 0x0000, 0, 0)
94#define MX51_PAD_EIM_D20__GPIO_2_4 IOMUX_PAD(0x400, 0x06c, 1, 0x0, 0, NO_PAD_CTRL) 73#define _MX51_PAD_EIM_D19__I2C1_SCL IOMUX_PAD(0x3fc, 0x68, 0x14, 0x09b0, 0, 0)
95#define MX51_PAD_EIM_D21__GPIO_2_5 IOMUX_PAD(0x404, 0x070, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 74#define _MX51_PAD_EIM_D19__UART2_RTS IOMUX_PAD(0x3fc, 0x68, 3, 0x09e8, 1, 0)
96#define MX51_PAD_EIM_D22__GPIO_2_6 IOMUX_PAD(0x408, 0x074, 1, 0x0, 0, NO_PAD_CTRL) 75#define _MX51_PAD_EIM_D19__USBH2_DATA3 IOMUX_PAD(0x3fc, 0x68, 2, 0x0000, 0, 0)
97#define MX51_PAD_EIM_D23__GPIO_2_7 IOMUX_PAD(0x40c, 0x078, 1, 0x0, 0, NO_PAD_CTRL) 76#define _MX51_PAD_EIM_D20__AUD4_TXD IOMUX_PAD(0x400, 0x6c, 5, 0x08c8, 0, 0)
98#define MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x07c, 3, 0x0, 0, MX51_UART3_PAD_CTRL) 77#define _MX51_PAD_EIM_D20__EIM_D20 IOMUX_PAD(0x400, 0x6c, 0, 0x0000, 0, 0)
99#define MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x080, 3, 0x9f4, 0, MX51_UART3_PAD_CTRL) 78#define _MX51_PAD_EIM_D20__GPIO2_4 IOMUX_PAD(0x400, 0x6c, 1, 0x0000, 0, 0)
100#define MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x080, 4, 0x0, 0, MX51_UART2_PAD_CTRL) 79#define _MX51_PAD_EIM_D20__SRTC_ALARM_DEB IOMUX_PAD(0x400, 0x6c, 4, 0x0000, 0, 0)
101#define MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x084, 3, 0x0, 0, MX51_UART3_PAD_CTRL) 80#define _MX51_PAD_EIM_D20__USBH2_DATA4 IOMUX_PAD(0x400, 0x6c, 2, 0x0000, 0, 0)
102#define MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x084, 4, 0x9e8, 3, MX51_UART2_PAD_CTRL) 81#define _MX51_PAD_EIM_D21__AUD4_RXD IOMUX_PAD(0x404, 0x70, 5, 0x08c4, 0, 0)
103#define MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x088, 3, 0x9f0, 3, MX51_UART3_PAD_CTRL) 82#define _MX51_PAD_EIM_D21__EIM_D21 IOMUX_PAD(0x404, 0x70, 0, 0x0000, 0, 0)
104#define MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x08c, 0, 0x0, 0, NO_PAD_CTRL) 83#define _MX51_PAD_EIM_D21__GPIO2_5 IOMUX_PAD(0x404, 0x70, 1, 0x0000, 0, 0)
105#define MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x090, 0, 0x0, 0, NO_PAD_CTRL) 84#define _MX51_PAD_EIM_D21__SRTC_ALARM_DEB IOMUX_PAD(0x404, 0x70, 3, 0x0000, 0, 0)
106#define MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x094, 0, 0x0, 0, NO_PAD_CTRL) 85#define _MX51_PAD_EIM_D21__USBH2_DATA5 IOMUX_PAD(0x404, 0x70, 2, 0x0000, 0, 0)
107#define MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x09c, 0, 0x0, 0, NO_PAD_CTRL) 86#define _MX51_PAD_EIM_D22__AUD4_TXC IOMUX_PAD(0x408, 0x74, 5, 0x08cc, 0, 0)
108#define MX51_PAD_EIM_A16__GPIO_2_10 IOMUX_PAD(0x430, 0x09c, 1, 0x0, 0, NO_PAD_CTRL) 87#define _MX51_PAD_EIM_D22__EIM_D22 IOMUX_PAD(0x408, 0x74, 0, 0x0000, 0, 0)
109#define MX51_PAD_EIM_A17__GPIO_2_11 IOMUX_PAD(0x434, 0x0a0, 1, 0x0, 0, NO_PAD_CTRL) 88#define _MX51_PAD_EIM_D22__GPIO2_6 IOMUX_PAD(0x408, 0x74, 1, 0x0000, 0, 0)
110#define MX51_PAD_EIM_A18__GPIO_2_12 IOMUX_PAD(0x438, 0x0a4, 1, 0x0, 0, NO_PAD_CTRL) 89#define _MX51_PAD_EIM_D22__USBH2_DATA6 IOMUX_PAD(0x408, 0x74, 2, 0x0000, 0, 0)
111#define MX51_PAD_EIM_A19__GPIO_2_13 IOMUX_PAD(0x43c, 0x0a8, 1, 0x0, 0, NO_PAD_CTRL) 90#define _MX51_PAD_EIM_D23__AUD4_TXFS IOMUX_PAD(0x40c, 0x78, 5, 0x08d0, 0, 0)
112#define MX51_PAD_EIM_A20__GPIO_2_14 IOMUX_PAD(0x440, 0x0ac, 1, 0x0, 0, NO_PAD_CTRL) 91#define _MX51_PAD_EIM_D23__EIM_D23 IOMUX_PAD(0x40c, 0x78, 0, 0x0000, 0, 0)
113#define MX51_PAD_EIM_A21__GPIO_2_15 IOMUX_PAD(0x444, 0x0b0, 1, 0x0, 0, NO_PAD_CTRL) 92#define _MX51_PAD_EIM_D23__GPIO2_7 IOMUX_PAD(0x40c, 0x78, 1, 0x0000, 0, 0)
114#define MX51_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x448, 0x0b4, 1, 0x0, 0, NO_PAD_CTRL) 93#define _MX51_PAD_EIM_D23__SPDIF_OUT1 IOMUX_PAD(0x40c, 0x78, 4, 0x0000, 0, 0)
115#define MX51_PAD_EIM_A23__GPIO_2_17 IOMUX_PAD(0x44c, 0x0b8, 1, 0x0, 0, NO_PAD_CTRL) 94#define _MX51_PAD_EIM_D23__USBH2_DATA7 IOMUX_PAD(0x40c, 0x78, 2, 0x0000, 0, 0)
116#define MX51_PAD_EIM_A24__GPIO_2_18 IOMUX_PAD(0x450, 0x0bc, 1, 0x0, 0, NO_PAD_CTRL) 95#define _MX51_PAD_EIM_D24__AUD6_RXFS IOMUX_PAD(0x410, 0x7c, 5, 0x08f8, 0, 0)
117#define MX51_PAD_EIM_A25__GPIO_2_19 IOMUX_PAD(0x454, 0x0c0, 1, 0x0, 0, NO_PAD_CTRL) 96#define _MX51_PAD_EIM_D24__EIM_D24 IOMUX_PAD(0x410, 0x7c, 0, 0x0000, 0, 0)
118#define MX51_PAD_EIM_A26__GPIO_2_20 IOMUX_PAD(0x458, 0x0c4, 1, 0x0, 0, NO_PAD_CTRL) 97#define _MX51_PAD_EIM_D24__GPIO2_8 IOMUX_PAD(0x410, 0x7c, 1, 0x0000, 0, 0)
119#define MX51_PAD_EIM_A27__GPIO_2_21 IOMUX_PAD(0x45c, 0x0c8, 1, 0x0, 0, NO_PAD_CTRL) 98#define _MX51_PAD_EIM_D24__I2C2_SDA IOMUX_PAD(0x410, 0x7c, 0x14, 0x09bc, 0, 0)
120#define MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0x0cc, 0, 0x0, 0, NO_PAD_CTRL) 99#define _MX51_PAD_EIM_D24__UART3_CTS IOMUX_PAD(0x410, 0x7c, 3, 0x0000, 0, 0)
121#define MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0x0d0, 0, 0x0, 0, NO_PAD_CTRL) 100#define _MX51_PAD_EIM_D24__USBOTG_DATA0 IOMUX_PAD(0x410, 0x7c, 2, 0x0000, 0, 0)
122#define MX51_PAD_EIM_EB2__GPIO_2_22 IOMUX_PAD(0x468, 0x0d4, 1, 0x0, 0, NO_PAD_CTRL) 101#define _MX51_PAD_EIM_D25__EIM_D25 IOMUX_PAD(0x414, 0x80, 0, 0x0000, 0, 0)
123#define MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0x0d4, 3, 0x0, 0, MX51_PAD_CTRL_1 | PAD_CTL_PUS_22K_UP) 102#define _MX51_PAD_EIM_D25__KEY_COL6 IOMUX_PAD(0x414, 0x80, 1, 0x09c8, 0, 0)
124#define MX51_PAD_EIM_EB3__GPIO_2_23 IOMUX_PAD(0x46c, 0x0d8, 1, 0x0, 0, NO_PAD_CTRL) 103#define _MX51_PAD_EIM_D25__UART2_CTS IOMUX_PAD(0x414, 0x80, 4, 0x0000, 0, 0)
125#define MX51_PAD_EIM_EB3__FEC_RDAT1 IOMUX_PAD(0x46c, 0x0d8, 3, 0x0, 0, MX51_PAD_CTRL_2) 104#define _MX51_PAD_EIM_D25__UART3_RXD IOMUX_PAD(0x414, 0x80, 3, 0x09f4, 0, 0)
126#define MX51_PAD_EIM_OE__GPIO_2_24 IOMUX_PAD(0x470, 0x0dc, 1, 0x0, 0, NO_PAD_CTRL) 105#define _MX51_PAD_EIM_D25__USBOTG_DATA1 IOMUX_PAD(0x414, 0x80, 2, 0x0000, 0, 0)
127#define MX51_PAD_EIM_CS0__GPIO_2_25 IOMUX_PAD(0x474, 0x0e0, 1, 0x0, 0, NO_PAD_CTRL) 106#define _MX51_PAD_EIM_D26__EIM_D26 IOMUX_PAD(0x418, 0x84, 0, 0x0000, 0, 0)
128#define MX51_PAD_EIM_CS1__GPIO_2_26 IOMUX_PAD(0x478, 0x0e4, 1, 0x0, 0, NO_PAD_CTRL) 107#define _MX51_PAD_EIM_D26__KEY_COL7 IOMUX_PAD(0x418, 0x84, 1, 0x09cc, 0, 0)
129#define MX51_PAD_EIM_CS2__GPIO_2_27 IOMUX_PAD(0x47c, 0x0e8, 1, 0x0, 0, NO_PAD_CTRL) 108#define _MX51_PAD_EIM_D26__UART2_RTS IOMUX_PAD(0x418, 0x84, 4, 0x09e8, 3, 0)
130#define MX51_PAD_EIM_CS2__FEC_RDAT2 IOMUX_PAD(0x47c, 0x0e8, 3, 0x0, 0, MX51_PAD_CTRL_2) 109#define _MX51_PAD_EIM_D26__UART3_TXD IOMUX_PAD(0x418, 0x84, 3, 0x0000, 0, 0)
131#define MX51_PAD_EIM_CS3__GPIO_2_28 IOMUX_PAD(0x480, 0x0ec, 1, 0x0, 0, NO_PAD_CTRL) 110#define _MX51_PAD_EIM_D26__USBOTG_DATA2 IOMUX_PAD(0x418, 0x84, 2, 0x0000, 0, 0)
132#define MX51_PAD_EIM_CS3__FEC_RDAT3 IOMUX_PAD(0x480, 0x0ec, 3, 0x0, 0, MX51_PAD_CTRL_2) 111#define _MX51_PAD_EIM_D27__AUD6_RXC IOMUX_PAD(0x41c, 0x88, 5, 0x08f4, 0, 0)
133#define MX51_PAD_EIM_CS4__GPIO_2_29 IOMUX_PAD(0x484, 0x0f0, 1, 0x0, 0, NO_PAD_CTRL) 112#define _MX51_PAD_EIM_D27__EIM_D27 IOMUX_PAD(0x41c, 0x88, 0, 0x0000, 0, 0)
134#define MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0x0f0, 3, 0x0, 0, MX51_PAD_CTRL_2) 113#define _MX51_PAD_EIM_D27__GPIO2_9 IOMUX_PAD(0x41c, 0x88, 1, 0x0000, 0, 0)
135#define MX51_PAD_EIM_CS5__GPIO_2_30 IOMUX_PAD(0x488, 0x0f4, 1, 0x0, 0, NO_PAD_CTRL) 114#define _MX51_PAD_EIM_D27__I2C2_SCL IOMUX_PAD(0x41c, 0x88, 0x14, 0x09b8, 0, 0)
136#define MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0x0f4, 3, 0x0, 0, MX51_PAD_CTRL_2) 115#define _MX51_PAD_EIM_D27__UART3_RTS IOMUX_PAD(0x41c, 0x88, 3, 0x09f0, 3, 0)
137#define MX51_PAD_EIM_DTACK__GPIO_2_31 IOMUX_PAD(0x48c, 0x0f8, 1, 0x0, 0, NO_PAD_CTRL) 116#define _MX51_PAD_EIM_D27__USBOTG_DATA3 IOMUX_PAD(0x41c, 0x88, 2, 0x0000, 0, 0)
138#define MX51_PAD_EIM_LBA__GPIO_3_1 IOMUX_PAD(0x494, 0x0FC, 1, 0x0, 0, NO_PAD_CTRL) 117#define _MX51_PAD_EIM_D28__AUD6_TXD IOMUX_PAD(0x420, 0x8c, 5, 0x08f0, 0, 0)
139#define MX51_PAD_EIM_CRE__GPIO_3_2 IOMUX_PAD(0x4A0, 0x100, 1, 0x0, 0, NO_PAD_CTRL) 118#define _MX51_PAD_EIM_D28__EIM_D28 IOMUX_PAD(0x420, 0x8c, 0, 0x0000, 0, 0)
140#define MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4D0, 0x104, 0, 0x0, 0, NO_PAD_CTRL) 119#define _MX51_PAD_EIM_D28__KEY_ROW4 IOMUX_PAD(0x420, 0x8c, 1, 0x09d0, 0, 0)
141#define MX51_PAD_NANDF_WE_B__GPIO_3_3 IOMUX_PAD(0x4E4, 0x108, 3, 0x0, 0, NO_PAD_CTRL) 120#define _MX51_PAD_EIM_D28__USBOTG_DATA4 IOMUX_PAD(0x420, 0x8c, 2, 0x0000, 0, 0)
142#define MX51_PAD_NANDF_RE_B__GPIO_3_4 IOMUX_PAD(0x4E8, 0x10C, 3, 0x0, 0, NO_PAD_CTRL) 121#define _MX51_PAD_EIM_D29__AUD6_RXD IOMUX_PAD(0x424, 0x90, 5, 0x08ec, 0, 0)
143#define MX51_PAD_NANDF_ALE__GPIO_3_5 IOMUX_PAD(0x4EC, 0x110, 3, 0x0, 0, NO_PAD_CTRL) 122#define _MX51_PAD_EIM_D29__EIM_D29 IOMUX_PAD(0x424, 0x90, 0, 0x0000, 0, 0)
144#define MX51_PAD_NANDF_CLE__GPIO_3_6 IOMUX_PAD(0x4F0, 0x114, 3, 0x0, 0, NO_PAD_CTRL) 123#define _MX51_PAD_EIM_D29__KEY_ROW5 IOMUX_PAD(0x424, 0x90, 1, 0x09d4, 0, 0)
145#define MX51_PAD_NANDF_WP_B__GPIO_3_7 IOMUX_PAD(0x4F4, 0x118, 3, 0x0, 0, NO_PAD_CTRL) 124#define _MX51_PAD_EIM_D29__USBOTG_DATA5 IOMUX_PAD(0x424, 0x90, 2, 0x0000, 0, 0)
146#define MX51_PAD_NANDF_RB0__GPIO_3_8 IOMUX_PAD(0x4F8, 0x11C, 3, 0x0, 0, NO_PAD_CTRL) 125#define _MX51_PAD_EIM_D30__AUD6_TXC IOMUX_PAD(0x428, 0x94, 5, 0x08fc, 0, 0)
147#define MX51_PAD_NANDF_RB1__GPIO_3_9 IOMUX_PAD(0x4FC, 0x120, 3, 0x0, 0, NO_PAD_CTRL) 126#define _MX51_PAD_EIM_D30__EIM_D30 IOMUX_PAD(0x428, 0x94, 0, 0x0000, 0, 0)
148#define MX51_PAD_NANDF_RB2__GPIO_3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0, 0, NO_PAD_CTRL) 127#define _MX51_PAD_EIM_D30__KEY_ROW6 IOMUX_PAD(0x428, 0x94, 1, 0x09d8, 0, 0)
149#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) 128#define _MX51_PAD_EIM_D30__USBOTG_DATA6 IOMUX_PAD(0x428, 0x94, 2, 0x0000, 0, 0)
150#define MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x0, 0, MX51_PAD_CTRL_2) 129#define _MX51_PAD_EIM_D31__AUD6_TXFS IOMUX_PAD(0x42c, 0x98, 5, 0x0900, 0, 0)
151#define MX51_PAD_NANDF_RB3__GPIO_3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0, 0, NO_PAD_CTRL) 130#define _MX51_PAD_EIM_D31__EIM_D31 IOMUX_PAD(0x42c, 0x98, 0, 0x0000, 0, 0)
152#define MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) 131#define _MX51_PAD_EIM_D31__KEY_ROW7 IOMUX_PAD(0x42c, 0x98, 1, 0x09dc, 0, 0)
153#define MX51_PAD_NANDF_RB3__FEC_RXCLK IOMUX_PAD(0x504, 0x128, 1, 0x0, 0, MX51_PAD_CTRL_2) 132#define _MX51_PAD_EIM_D31__USBOTG_DATA7 IOMUX_PAD(0x42c, 0x98, 2, 0x0000, 0, 0)
154#define MX51_PAD_NANDF_RB6__FEC_RDAT0 IOMUX_PAD(0x5DC, 0x134, 1, 0x0, 0, MX51_PAD_CTRL_4) 133#define _MX51_PAD_EIM_A16__EIM_A16 IOMUX_PAD(0x430, 0x9c, 0, 0x0000, 0, 0)
155#define MX51_PAD_NANDF_RB7__FEC_TDAT0 IOMUX_PAD(0x5E0, 0x138, 1, 0x0, 0, MX51_PAD_CTRL_5) 134#define _MX51_PAD_EIM_A16__GPIO2_10 IOMUX_PAD(0x430, 0x9c, 1, 0x0000, 0, 0)
156#define MX51_PAD_GPIO_NAND__GPIO_3_12 IOMUX_PAD(0x514, 0x12C, 3, 0x0, 0, NO_PAD_CTRL) 135#define _MX51_PAD_EIM_A16__OSC_FREQ_SEL0 IOMUX_PAD(0x430, 0x9c, 7, 0x0000, 0, 0)
157#define MX51_PAD_NANDF_CS0__GPIO_3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0, 0, NO_PAD_CTRL) 136#define _MX51_PAD_EIM_A17__EIM_A17 IOMUX_PAD(0x434, 0xa0, 0, 0x0000, 0, 0)
158#define MX51_PAD_NANDF_CS1__GPIO_3_17 IOMUX_PAD(0x51C, 0x134, 3, 0x0, 0, NO_PAD_CTRL) 137#define _MX51_PAD_EIM_A17__GPIO2_11 IOMUX_PAD(0x434, 0xa0, 1, 0x0000, 0, 0)
159#define MX51_PAD_NANDF_CS2__GPIO_3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0, 0, NO_PAD_CTRL) 138#define _MX51_PAD_EIM_A17__OSC_FREQ_SEL1 IOMUX_PAD(0x434, 0xa0, 7, 0x0000, 0, 0)
160#define MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0, 0, MX51_PAD_CTRL_5) 139#define _MX51_PAD_EIM_A18__BOOT_LPB0 IOMUX_PAD(0x438, 0xa4, 7, 0x0000, 0, 0)
161#define MX51_PAD_NANDF_CS3__GPIO_3_19 IOMUX_PAD(0x524, 0x13C, 3, 0x0, 0, NO_PAD_CTRL) 140#define _MX51_PAD_EIM_A18__EIM_A18 IOMUX_PAD(0x438, 0xa4, 0, 0x0000, 0, 0)
162#define MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13C, 2, 0x0, 0, MX51_PAD_CTRL_5) 141#define _MX51_PAD_EIM_A18__GPIO2_12 IOMUX_PAD(0x438, 0xa4, 1, 0x0000, 0, 0)
163#define MX51_PAD_NANDF_CS4__GPIO_3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0, 0, NO_PAD_CTRL) 142#define _MX51_PAD_EIM_A19__BOOT_LPB1 IOMUX_PAD(0x43c, 0xa8, 7, 0x0000, 0, 0)
164#define MX51_PAD_NANDF_CS4__FEC_TDAT1 IOMUX_PAD(0x528, 0x140, 2, 0x0, 0, MX51_PAD_CTRL_5) 143#define _MX51_PAD_EIM_A19__EIM_A19 IOMUX_PAD(0x43c, 0xa8, 0, 0x0000, 0, 0)
165#define MX51_PAD_NANDF_CS5__GPIO_3_21 IOMUX_PAD(0x52C, 0x144, 3, 0x0, 0, NO_PAD_CTRL) 144#define _MX51_PAD_EIM_A19__GPIO2_13 IOMUX_PAD(0x43c, 0xa8, 1, 0x0000, 0, 0)
166#define MX51_PAD_NANDF_CS5__FEC_TDAT2 IOMUX_PAD(0x52C, 0x144, 2, 0x0, 0, MX51_PAD_CTRL_5) 145#define _MX51_PAD_EIM_A20__BOOT_UART_SRC0 IOMUX_PAD(0x440, 0xac, 7, 0x0000, 0, 0)
167#define MX51_PAD_NANDF_CS6__GPIO_3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0, 0, NO_PAD_CTRL) 146#define _MX51_PAD_EIM_A20__EIM_A20 IOMUX_PAD(0x440, 0xac, 0, 0x0000, 0, 0)
168#define MX51_PAD_NANDF_CS6__FEC_TDAT3 IOMUX_PAD(0x530, 0x148, 2, 0x0, 0, MX51_PAD_CTRL_5) 147#define _MX51_PAD_EIM_A20__GPIO2_14 IOMUX_PAD(0x440, 0xac, 1, 0x0000, 0, 0)
169#define MX51_PAD_NANDF_CS7__GPIO_3_23 IOMUX_PAD(0x534, 0x14C, 3, 0x0, 0, NO_PAD_CTRL) 148#define _MX51_PAD_EIM_A21__BOOT_UART_SRC1 IOMUX_PAD(0x444, 0xb0, 7, 0x0000, 0, 0)
170#define MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14C, 1, 0x0, 0, MX51_PAD_CTRL_5) 149#define _MX51_PAD_EIM_A21__EIM_A21 IOMUX_PAD(0x444, 0xb0, 0, 0x0000, 0, 0)
171#define MX51_PAD_NANDF_RDY_INT__GPIO_3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0, 0, NO_PAD_CTRL) 150#define _MX51_PAD_EIM_A21__GPIO2_15 IOMUX_PAD(0x444, 0xb0, 1, 0x0000, 0, 0)
172#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0, 0, MX51_PAD_CTRL_4) 151#define _MX51_PAD_EIM_A22__EIM_A22 IOMUX_PAD(0x448, 0xb4, 0, 0x0000, 0, 0)
173#define MX51_PAD_NANDF_D15__GPIO_3_25 IOMUX_PAD(0x53C, 0x154, 3, 0x0, 0, NO_PAD_CTRL) 152#define _MX51_PAD_EIM_A22__GPIO2_16 IOMUX_PAD(0x448, 0xb4, 1, 0x0000, 0, 0)
174#define MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53C, 0x154, 2, 0x0, 0, MX51_ECSPI_PAD_CTRL) 153#define _MX51_PAD_EIM_A23__BOOT_HPN_EN IOMUX_PAD(0x44c, 0xb8, 7, 0x0000, 0, 0)
175#define MX51_PAD_NANDF_D14__GPIO_3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0, 0, NO_PAD_CTRL) 154#define _MX51_PAD_EIM_A23__EIM_A23 IOMUX_PAD(0x44c, 0xb8, 0, 0x0000, 0, 0)
176#define MX51_PAD_NANDF_D13__GPIO_3_27 IOMUX_PAD(0x544, 0x15C, 3, 0x0, 0, NO_PAD_CTRL) 155#define _MX51_PAD_EIM_A23__GPIO2_17 IOMUX_PAD(0x44c, 0xb8, 1, 0x0000, 0, 0)
177#define MX51_PAD_NANDF_D12__GPIO_3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0, 0, NO_PAD_CTRL) 156#define _MX51_PAD_EIM_A24__EIM_A24 IOMUX_PAD(0x450, 0xbc, 0, 0x0000, 0, 0)
178#define MX51_PAD_NANDF_D11__GPIO_3_29 IOMUX_PAD(0x54C, 0x164, 3, 0x0, 0, NO_PAD_CTRL) 157#define _MX51_PAD_EIM_A24__GPIO2_18 IOMUX_PAD(0x450, 0xbc, 1, 0x0000, 0, 0)
179#define MX51_PAD_NANDF_D10__GPIO_3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0, 0, NO_PAD_CTRL) 158#define _MX51_PAD_EIM_A24__USBH2_CLK IOMUX_PAD(0x450, 0xbc, 2, 0x0000, 0, 0)
180#define MX51_PAD_NANDF_D9__GPIO_3_31 IOMUX_PAD(0x554, 0x16C, 3, 0x0, 0, NO_PAD_CTRL) 159#define _MX51_PAD_EIM_A25__DISP1_PIN4 IOMUX_PAD(0x454, 0xc0, 6, 0x0000, 0, 0)
181#define MX51_PAD_NANDF_D8__GPIO_4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0, 0, NO_PAD_CTRL) 160#define _MX51_PAD_EIM_A25__EIM_A25 IOMUX_PAD(0x454, 0xc0, 0, 0x0000, 0, 0)
182#define MX51_PAD_NANDF_D7__GPIO_4_1 IOMUX_PAD(0x55C, 0x174, 3, 0x0, 0, NO_PAD_CTRL) 161#define _MX51_PAD_EIM_A25__GPIO2_19 IOMUX_PAD(0x454, 0xc0, 1, 0x0000, 0, 0)
183#define MX51_PAD_NANDF_D6__GPIO_4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0, 0, NO_PAD_CTRL) 162#define _MX51_PAD_EIM_A25__USBH2_DIR IOMUX_PAD(0x454, 0xc0, 2, 0x0000, 0, 0)
184#define MX51_PAD_NANDF_D5__GPIO_4_3 IOMUX_PAD(0x564, 0x17C, 3, 0x0, 0, NO_PAD_CTRL) 163#define _MX51_PAD_EIM_A26__CSI1_DATA_EN IOMUX_PAD(0x458, 0xc4, 5, 0x09a0, 0, 0)
185#define MX51_PAD_NANDF_D4__GPIO_4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0, 0, NO_PAD_CTRL) 164#define _MX51_PAD_EIM_A26__DISP2_EXT_CLK IOMUX_PAD(0x458, 0xc4, 6, 0x0908, 0, 0)
186#define MX51_PAD_NANDF_D3__GPIO_4_5 IOMUX_PAD(0x56C, 0x184, 3, 0x0, 0, NO_PAD_CTRL) 165#define _MX51_PAD_EIM_A26__EIM_A26 IOMUX_PAD(0x458, 0xc4, 0, 0x0000, 0, 0)
187#define MX51_PAD_NANDF_D2__GPIO_4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0, 0, NO_PAD_CTRL) 166#define _MX51_PAD_EIM_A26__GPIO2_20 IOMUX_PAD(0x458, 0xc4, 1, 0x0000, 0, 0)
188#define MX51_PAD_NANDF_D1__GPIO_4_7 IOMUX_PAD(0x574, 0x18C, 3, 0x0, 0, NO_PAD_CTRL) 167#define _MX51_PAD_EIM_A26__USBH2_STP IOMUX_PAD(0x458, 0xc4, 2, 0x0000, 0, 0)
189#define MX51_PAD_NANDF_D0__GPIO_4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0, 0, NO_PAD_CTRL) 168#define _MX51_PAD_EIM_A27__CSI2_DATA_EN IOMUX_PAD(0x45c, 0xc8, 5, 0x099c, 0, 0)
190#define MX51_PAD_CSI1_D8__GPIO_3_12 IOMUX_PAD(0x57C, 0x194, 3, 0x0, 0, NO_PAD_CTRL) 169#define _MX51_PAD_EIM_A27__DISP1_PIN1 IOMUX_PAD(0x45c, 0xc8, 6, 0x09a4, 0, 0)
191#define MX51_PAD_CSI1_D9__GPIO_3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0, 0, NO_PAD_CTRL) 170#define _MX51_PAD_EIM_A27__EIM_A27 IOMUX_PAD(0x45c, 0xc8, 0, 0x0000, 0, 0)
192#define MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19C, 0, 0x0, 0, NO_PAD_CTRL) 171#define _MX51_PAD_EIM_A27__GPIO2_21 IOMUX_PAD(0x45c, 0xc8, 1, 0x0000, 0, 0)
193#define MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1A0, 0, 0x0, 0, NO_PAD_CTRL) 172#define _MX51_PAD_EIM_A27__USBH2_NXT IOMUX_PAD(0x45c, 0xc8, 2, 0x0000, 0, 0)
194#define MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58C, 0x1A4, 0, 0x0, 0, NO_PAD_CTRL) 173#define _MX51_PAD_EIM_EB0__EIM_EB0 IOMUX_PAD(0x460, 0xcc, 0, 0x0000, 0, 0)
195#define MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1A8, 0, 0x0, 0, NO_PAD_CTRL) 174#define _MX51_PAD_EIM_EB1__EIM_EB1 IOMUX_PAD(0x464, 0xd0, 0, 0x0000, 0, 0)
196#define MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1AC, 0, 0x0, 0, NO_PAD_CTRL) 175#define _MX51_PAD_EIM_EB2__AUD5_RXFS IOMUX_PAD(0x468, 0xd4, 6, 0x08e0, 0, 0)
197#define MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1B0, 0, 0x0, 0, NO_PAD_CTRL) 176#define _MX51_PAD_EIM_EB2__CSI1_D2 IOMUX_PAD(0x468, 0xd4, 5, 0x0000, 0, 0)
198#define MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59C, 0x1B4, 0, 0x0, 0, NO_PAD_CTRL) 177#define _MX51_PAD_EIM_EB2__EIM_EB2 IOMUX_PAD(0x468, 0xd4, 0, 0x0000, 0, 0)
199#define MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5A0, 0x1B8, 0, 0x0, 0, NO_PAD_CTRL) 178#define _MX51_PAD_EIM_EB2__FEC_MDIO IOMUX_PAD(0x468, 0xd4, 3, 0x0954, 0, 0)
200#define MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5A4, 0x1BC, 0, 0x0, 0, NO_PAD_CTRL) 179#define _MX51_PAD_EIM_EB2__GPIO2_22 IOMUX_PAD(0x468, 0xd4, 1, 0x0000, 0, 0)
201#define MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5A8, 0x1C0, 0, 0x0, 0, NO_PAD_CTRL) 180#define _MX51_PAD_EIM_EB2__GPT_CMPOUT1 IOMUX_PAD(0x468, 0xd4, 7, 0x0000, 0, 0)
202#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5AC, 0x1C4, 0, 0x0, 0, NO_PAD_CTRL) 181#define _MX51_PAD_EIM_EB3__AUD5_RXC IOMUX_PAD(0x46c, 0xd8, 6, 0x08dc, 0, 0)
203#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5B0, 0x1C8, 0, 0x0, 0, NO_PAD_CTRL) 182#define _MX51_PAD_EIM_EB3__CSI1_D3 IOMUX_PAD(0x46c, 0xd8, 5, 0x0000, 0, 0)
204#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5B4, 0x000, 0, 0x0, 0, NO_PAD_CTRL) 183#define _MX51_PAD_EIM_EB3__EIM_EB3 IOMUX_PAD(0x46c, 0xd8, 0, 0x0000, 0, 0)
205#define MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5B8, 0x000, 0, 0x0, 0, NO_PAD_CTRL) 184#define _MX51_PAD_EIM_EB3__FEC_RDATA1 IOMUX_PAD(0x46c, 0xd8, 3, 0x095c, 0, 0)
206#define MX51_PAD_CSI1_PKE0__CSI1_PKE0 IOMUX_PAD(0x860, 0x000, 0, 0x0, 0, NO_PAD_CTRL) 185#define _MX51_PAD_EIM_EB3__GPIO2_23 IOMUX_PAD(0x46c, 0xd8, 1, 0x0000, 0, 0)
207#define MX51_PAD_CSI2_D12__GPIO_4_9 IOMUX_PAD(0x5BC, 0x1CC, 3, 0x0, 0, NO_PAD_CTRL) 186#define _MX51_PAD_EIM_EB3__GPT_CMPOUT2 IOMUX_PAD(0x46c, 0xd8, 7, 0x0000, 0, 0)
208#define MX51_PAD_CSI2_D13__GPIO_4_10 IOMUX_PAD(0x5C0, 0x1D0, 3, 0x0, 0, NO_PAD_CTRL) 187#define _MX51_PAD_EIM_OE__EIM_OE IOMUX_PAD(0x470, 0xdc, 0, 0x0000, 0, 0)
209#define MX51_PAD_CSI2_D14__GPIO_4_11 IOMUX_PAD(0x5C4, 0x1D4, 3, 0x0, 0, NO_PAD_CTRL) 188#define _MX51_PAD_EIM_OE__GPIO2_24 IOMUX_PAD(0x470, 0xdc, 1, 0x0000, 0, 0)
210#define MX51_PAD_CSI2_D15__GPIO_4_12 IOMUX_PAD(0x5C8, 0x1D8, 3, 0x0, 0, NO_PAD_CTRL) 189#define _MX51_PAD_EIM_CS0__EIM_CS0 IOMUX_PAD(0x474, 0xe0, 0, 0x0000, 0, 0)
211#define MX51_PAD_CSI2_D16__GPIO_4_11 IOMUX_PAD(0x5CC, 0x1DC, 3, 0x0, 0, NO_PAD_CTRL) 190#define _MX51_PAD_EIM_CS0__GPIO2_25 IOMUX_PAD(0x474, 0xe0, 1, 0x0000, 0, 0)
212#define MX51_PAD_CSI2_D17__GPIO_4_12 IOMUX_PAD(0x5D0, 0x1E0, 3, 0x0, 0, NO_PAD_CTRL) 191#define _MX51_PAD_EIM_CS1__EIM_CS1 IOMUX_PAD(0x478, 0xe4, 0, 0x0000, 0, 0)
213#define MX51_PAD_CSI2_D18__GPIO_4_11 IOMUX_PAD(0x5D4, 0x1E4, 3, 0x0, 0, NO_PAD_CTRL) 192#define _MX51_PAD_EIM_CS1__GPIO2_26 IOMUX_PAD(0x478, 0xe4, 1, 0x0000, 0, 0)
214#define MX51_PAD_CSI2_D19__GPIO_4_12 IOMUX_PAD(0x5D8, 0x1E8, 3, 0x0, 0, NO_PAD_CTRL) 193#define _MX51_PAD_EIM_CS2__AUD5_TXD IOMUX_PAD(0x47c, 0xe8, 6, 0x08d8, 1, 0)
215#define MX51_PAD_CSI2_VSYNC__GPIO_4_13 IOMUX_PAD(0x5DC, 0x1EC, 3, 0x0, 0, NO_PAD_CTRL) 194#define _MX51_PAD_EIM_CS2__CSI1_D4 IOMUX_PAD(0x47c, 0xe8, 5, 0x0000, 0, 0)
216#define MX51_PAD_CSI2_HSYNC__GPIO_4_14 IOMUX_PAD(0x5E0, 0x1F0, 3, 0x0, 0, NO_PAD_CTRL) 195#define _MX51_PAD_EIM_CS2__EIM_CS2 IOMUX_PAD(0x47c, 0xe8, 0, 0x0000, 0, 0)
217#define MX51_PAD_CSI2_PIXCLK__GPIO_4_15 IOMUX_PAD(0x5E4, 0x1F4, 3, 0x0, 0, NO_PAD_CTRL) 196#define _MX51_PAD_EIM_CS2__FEC_RDATA2 IOMUX_PAD(0x47c, 0xe8, 3, 0x0960, 0, 0)
218#define MX51_PAD_I2C1_CLK__GPIO_4_16 IOMUX_PAD(0x5E8, 0x1F8, 3, 0x0, 0, NO_PAD_CTRL) 197#define _MX51_PAD_EIM_CS2__GPIO2_27 IOMUX_PAD(0x47c, 0xe8, 1, 0x0000, 0, 0)
219#define MX51_PAD_I2C1_CLK__HSI2C_CLK IOMUX_PAD(0x5E8, 0x1F8, 0, 0x0, 0, NO_PAD_CTRL) 198#define _MX51_PAD_EIM_CS2__USBOTG_STP IOMUX_PAD(0x47c, 0xe8, 2, 0x0000, 0, 0)
220#define MX51_PAD_I2C1_DAT__GPIO_4_17 IOMUX_PAD(0x5EC, 0x1FC, 3, 0x0, 0, NO_PAD_CTRL) 199#define _MX51_PAD_EIM_CS3__AUD5_RXD IOMUX_PAD(0x480, 0xec, 6, 0x08d4, 1, 0)
221#define MX51_PAD_I2C1_DAT__HSI2C_DAT IOMUX_PAD(0x5EC, 0x1FC, 0, 0x0, 0, NO_PAD_CTRL) 200#define _MX51_PAD_EIM_CS3__CSI1_D5 IOMUX_PAD(0x480, 0xec, 5, 0x0000, 0, 0)
222#define MX51_PAD_AUD3_BB_TXD__AUD3_BB_TXD IOMUX_PAD(0x5F0, 0x200, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) 201#define _MX51_PAD_EIM_CS3__EIM_CS3 IOMUX_PAD(0x480, 0xec, 0, 0x0000, 0, 0)
223#define MX51_PAD_AUD3_BB_TXD__GPIO_4_18 IOMUX_PAD(0x5F0, 0x200, 3, 0x0, 0, NO_PAD_CTRL) 202#define _MX51_PAD_EIM_CS3__FEC_RDATA3 IOMUX_PAD(0x480, 0xec, 3, 0x0964, 0, 0)
224#define MX51_PAD_AUD3_BB_RXD__AUD3_BB_RXD IOMUX_PAD(0x5F4, 0x204, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) 203#define _MX51_PAD_EIM_CS3__GPIO2_28 IOMUX_PAD(0x480, 0xec, 1, 0x0000, 0, 0)
225#define MX51_PAD_AUD3_BB_RXD__GPIO_4_19 IOMUX_PAD(0x5F4, 0x204, 3, 0x0, 0, NO_PAD_CTRL) 204#define _MX51_PAD_EIM_CS3__USBOTG_NXT IOMUX_PAD(0x480, 0xec, 2, 0x0000, 0, 0)
226#define MX51_PAD_AUD3_BB_CK__AUD3_BB_CK IOMUX_PAD(0x5F8, 0x208, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) 205#define _MX51_PAD_EIM_CS4__AUD5_TXC IOMUX_PAD(0x484, 0xf0, 6, 0x08e4, 1, 0)
227#define MX51_PAD_AUD3_BB_CK__GPIO_4_20 IOMUX_PAD(0x5F8, 0x208, 3, 0x0, 0, NO_PAD_CTRL) 206#define _MX51_PAD_EIM_CS4__CSI1_D6 IOMUX_PAD(0x484, 0xf0, 5, 0x0000, 0, 0)
228#define MX51_PAD_AUD3_BB_FS__AUD3_BB_FS IOMUX_PAD(0x5FC, 0x20C, IOMUX_CONFIG_SION, 0x0, 0, NO_PAD_CTRL) 207#define _MX51_PAD_EIM_CS4__EIM_CS4 IOMUX_PAD(0x484, 0xf0, 0, 0x0000, 0, 0)
229#define MX51_PAD_AUD3_BB_FS__GPIO_4_21 IOMUX_PAD(0x5FC, 0x20C, 3, 0x0, 0, NO_PAD_CTRL) 208#define _MX51_PAD_EIM_CS4__FEC_RX_ER IOMUX_PAD(0x484, 0xf0, 3, 0x0970, 0, 0)
230#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 209#define _MX51_PAD_EIM_CS4__GPIO2_29 IOMUX_PAD(0x484, 0xf0, 1, 0x0000, 0, 0)
231#define MX51_PAD_CSPI1_MOSI__GPIO_4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0, 0, NO_PAD_CTRL) 210#define _MX51_PAD_EIM_CS4__USBOTG_CLK IOMUX_PAD(0x484, 0xf0, 2, 0x0000, 0, 0)
232#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 211#define _MX51_PAD_EIM_CS5__AUD5_TXFS IOMUX_PAD(0x488, 0xf4, 6, 0x08e8, 1, 0)
233#define MX51_PAD_CSPI1_MISO__GPIO_4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0, 0, NO_PAD_CTRL) 212#define _MX51_PAD_EIM_CS5__CSI1_D7 IOMUX_PAD(0x488, 0xf4, 5, 0x0000, 0, 0)
234#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 213#define _MX51_PAD_EIM_CS5__DISP1_EXT_CLK IOMUX_PAD(0x488, 0xf4, 4, 0x0904, 0, 0)
235#define MX51_PAD_CSPI1_SS0__GPIO_4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0, 0, NO_PAD_CTRL) 214#define _MX51_PAD_EIM_CS5__EIM_CS5 IOMUX_PAD(0x488, 0xf4, 0, 0x0000, 0, 0)
236#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60C, 0x21C, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 215#define _MX51_PAD_EIM_CS5__FEC_CRS IOMUX_PAD(0x488, 0xf4, 3, 0x0950, 0, 0)
237#define MX51_PAD_CSPI1_SS1__GPIO_4_25 IOMUX_PAD(0x60C, 0x21C, 3, 0x0, 0, NO_PAD_CTRL) 216#define _MX51_PAD_EIM_CS5__GPIO2_30 IOMUX_PAD(0x488, 0xf4, 1, 0x0000, 0, 0)
238#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 217#define _MX51_PAD_EIM_CS5__USBOTG_DIR IOMUX_PAD(0x488, 0xf4, 2, 0x0000, 0, 0)
239#define MX51_PAD_CSPI1_RDY__GPIO_4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0, 0, NO_PAD_CTRL) 218#define _MX51_PAD_EIM_DTACK__EIM_DTACK IOMUX_PAD(0x48c, 0xf8, 0, 0x0000, 0, 0)
240#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0, 0, MX51_ECSPI_PAD_CTRL) 219#define _MX51_PAD_EIM_DTACK__GPIO2_31 IOMUX_PAD(0x48c, 0xf8, 1, 0x0000, 0, 0)
241#define MX51_PAD_CSPI1_SCLK__GPIO_4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0, 0, NO_PAD_CTRL) 220#define _MX51_PAD_EIM_LBA__EIM_LBA IOMUX_PAD(0x494, 0xfc, 0, 0x0000, 0, 0)
242#define MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x9e4, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 221#define _MX51_PAD_EIM_LBA__GPIO3_1 IOMUX_PAD(0x494, 0xfc, 1, 0x0978, 0, 0)
243#define MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61C, 0x22C, 0, 0x0, 0, MX51_UART1_PAD_CTRL | PAD_CTL_SRE_FAST) 222#define _MX51_PAD_EIM_CRE__EIM_CRE IOMUX_PAD(0x4a0, 0x100, 0, 0x0000, 0, 0)
244#define MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART1_PAD_CTRL) 223#define _MX51_PAD_EIM_CRE__GPIO3_2 IOMUX_PAD(0x4a0, 0x100, 1, 0x097c, 0, 0)
245#define MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0, 0, MX51_UART1_PAD_CTRL) 224#define _MX51_PAD_DRAM_CS1__DRAM_CS1 IOMUX_PAD(0x4d0, 0x104, 0, 0x0000, 0, 0)
246#define MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x9ec, 2, MX51_UART2_PAD_CTRL) 225#define _MX51_PAD_NANDF_WE_B__GPIO3_3 IOMUX_PAD(0x4e4, 0x108, 3, 0x0980, 0, 0)
247#define MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62C, 0x23C, 0, 0x0, 0, MX51_UART2_PAD_CTRL) 226#define _MX51_PAD_NANDF_WE_B__NANDF_WE_B IOMUX_PAD(0x4e4, 0x108, 0, 0x0000, 0, 0)
248#define MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x9f4, 4, MX51_UART3_PAD_CTRL) 227#define _MX51_PAD_NANDF_WE_B__PATA_DIOW IOMUX_PAD(0x4e4, 0x108, 1, 0x0000, 0, 0)
249#define MX51_PAD_UART3_RXD__GPIO_1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0, 0, NO_PAD_CTRL) 228#define _MX51_PAD_NANDF_WE_B__SD3_DATA0 IOMUX_PAD(0x4e4, 0x108, 2, 0x093c, 0, 0)
250#define MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0, 0, MX51_UART3_PAD_CTRL) 229#define _MX51_PAD_NANDF_RE_B__GPIO3_4 IOMUX_PAD(0x4e8, 0x10c, 3, 0x0984, 0, 0)
251#define MX51_PAD_UART3_TXD__GPIO_1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0, 0, NO_PAD_CTRL) 230#define _MX51_PAD_NANDF_RE_B__NANDF_RE_B IOMUX_PAD(0x4e8, 0x10c, 0, 0x0000, 0, 0)
252#define MX51_PAD_OWIRE_LINE__GPIO_1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0, 0, NO_PAD_CTRL) 231#define _MX51_PAD_NANDF_RE_B__PATA_DIOR IOMUX_PAD(0x4e8, 0x10c, 1, 0x0000, 0, 0)
253#define MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63C, 0x24C, 0, 0x0, 0, NO_PAD_CTRL) 232#define _MX51_PAD_NANDF_RE_B__SD3_DATA1 IOMUX_PAD(0x4e8, 0x10c, 2, 0x0940, 0, 0)
254#define MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0, 0, NO_PAD_CTRL) 233#define _MX51_PAD_NANDF_ALE__GPIO3_5 IOMUX_PAD(0x4ec, 0x110, 3, 0x0988, 0, 0)
255#define MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0, 0, NO_PAD_CTRL) 234#define _MX51_PAD_NANDF_ALE__NANDF_ALE IOMUX_PAD(0x4ec, 0x110, 0, 0x0000, 0, 0)
256#define MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0, 0, NO_PAD_CTRL) 235#define _MX51_PAD_NANDF_ALE__PATA_BUFFER_EN IOMUX_PAD(0x4ec, 0x110, 1, 0x0000, 0, 0)
257#define MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64C, 0x25C, 0, 0x0, 0, NO_PAD_CTRL) 236#define _MX51_PAD_NANDF_CLE__GPIO3_6 IOMUX_PAD(0x4f0, 0x114, 3, 0x098c, 0, 0)
258#define MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0, 0, NO_PAD_CTRL) 237#define _MX51_PAD_NANDF_CLE__NANDF_CLE IOMUX_PAD(0x4f0, 0x114, 0, 0x0000, 0, 0)
259#define MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0, 0, NO_PAD_CTRL) 238#define _MX51_PAD_NANDF_CLE__PATA_RESET_B IOMUX_PAD(0x4f0, 0x114, 1, 0x0000, 0, 0)
260#define MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0, 0, NO_PAD_CTRL) 239#define _MX51_PAD_NANDF_WP_B__GPIO3_7 IOMUX_PAD(0x4f4, 0x118, 3, 0x0990, 0, 0)
261#define MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65C, 0x26C, 0, 0x0, 0, NO_PAD_CTRL) 240#define _MX51_PAD_NANDF_WP_B__NANDF_WP_B IOMUX_PAD(0x4f4, 0x118, 0, 0x0000, 0, 0)
262#define MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65C, 0x26C, 2, 0x9f0, 4, MX51_UART3_PAD_CTRL) 241#define _MX51_PAD_NANDF_WP_B__PATA_DMACK IOMUX_PAD(0x4f4, 0x118, 1, 0x0000, 0, 0)
263#define MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65C, 0x26C, (3 | IOMUX_CONFIG_SION), \ 242#define _MX51_PAD_NANDF_WP_B__SD3_DATA2 IOMUX_PAD(0x4f4, 0x118, 2, 0x0944, 0, 0)
264 0x09b8, 1, MX51_I2C_PAD_CTRL) 243#define _MX51_PAD_NANDF_RB0__ECSPI2_SS1 IOMUX_PAD(0x4f8, 0x11c, 5, 0x0930, 0, 0)
265#define MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0, 0, NO_PAD_CTRL) 244#define _MX51_PAD_NANDF_RB0__GPIO3_8 IOMUX_PAD(0x4f8, 0x11c, 3, 0x0994, 0, 0)
266#define MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0, 0, MX51_UART3_PAD_CTRL) 245#define _MX51_PAD_NANDF_RB0__NANDF_RB0 IOMUX_PAD(0x4f8, 0x11c, 0, 0x0000, 0, 0)
267#define MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, (3 | IOMUX_CONFIG_SION), \ 246#define _MX51_PAD_NANDF_RB0__PATA_DMARQ IOMUX_PAD(0x4f8, 0x11c, 1, 0x0000, 0, 0)
268 0x09bc, 1, MX51_I2C_PAD_CTRL) 247#define _MX51_PAD_NANDF_RB0__SD3_DATA3 IOMUX_PAD(0x4f8, 0x11c, 2, 0x0948, 0, 0)
269#define MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 248#define _MX51_PAD_NANDF_RB1__CSPI_MOSI IOMUX_PAD(0x4fc, 0x120, 6, 0x091c, 0, 0)
270#define MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67C, 0x27C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 249#define _MX51_PAD_NANDF_RB1__ECSPI2_RDY IOMUX_PAD(0x4fc, 0x120, 2, 0x0000, 0, 0)
271#define MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 250#define _MX51_PAD_NANDF_RB1__GPIO3_9 IOMUX_PAD(0x4fc, 0x120, 3, 0x0000, 0, 0)
272#define MX51_PAD_USBH1_STP__GPIO_1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0, 0, MX51_USBH1_PAD_CTRL) 251#define _MX51_PAD_NANDF_RB1__NANDF_RB1 IOMUX_PAD(0x4fc, 0x120, 0, 0x0000, 0, 0)
273#define MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 252#define _MX51_PAD_NANDF_RB1__PATA_IORDY IOMUX_PAD(0x4fc, 0x120, 1, 0x0000, 0, 0)
274#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 253#define _MX51_PAD_NANDF_RB1__SD4_CMD IOMUX_PAD(0x4fc, 0x120, 5, 0x0000, 0, 0)
275#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68C, 0x28C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 254#define _MX51_PAD_NANDF_RB2__DISP2_WAIT IOMUX_PAD(0x500, 0x124, 5, 0x09a8, 0, 0)
276#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 255#define _MX51_PAD_NANDF_RB2__ECSPI2_SCLK IOMUX_PAD(0x500, 0x124, 2, 0x0000, 0, 0)
277#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 256#define _MX51_PAD_NANDF_RB2__FEC_COL IOMUX_PAD(0x500, 0x124, 1, 0x094c, 0, 0)
278#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 257#define _MX51_PAD_NANDF_RB2__GPIO3_10 IOMUX_PAD(0x500, 0x124, 3, 0x0000, 0, 0)
279#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69C, 0x29C, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 258#define _MX51_PAD_NANDF_RB2__NANDF_RB2 IOMUX_PAD(0x500, 0x124, 0, 0x0000, 0, 0)
280#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6A0, 0x2A0, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 259#define _MX51_PAD_NANDF_RB2__USBH3_H3_DP IOMUX_PAD(0x500, 0x124, 7, 0x0000, 0, 0)
281#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6A4, 0x2A4, 0, 0x0, 0, MX51_USBH1_PAD_CTRL) 260#define _MX51_PAD_NANDF_RB2__USBH3_NXT IOMUX_PAD(0x500, 0x124, 6, 0x0a20, 0, 0)
282#define MX51_PAD_DI1_PIN11__GPIO_3_0 IOMUX_PAD(0x6A8, 0x2A8, 4, 0x0, 0, NO_PAD_CTRL) 261#define _MX51_PAD_NANDF_RB3__DISP1_WAIT IOMUX_PAD(0x504, 0x128, 5, 0x0000, 0, 0)
283#define MX51_PAD_DI1_PIN12__GPIO_3_1 IOMUX_PAD(0x6AC, 0x2AC, 4, 0x978, 1, NO_PAD_CTRL) 262#define _MX51_PAD_NANDF_RB3__ECSPI2_MISO IOMUX_PAD(0x504, 0x128, 2, 0x0000, 0, 0)
284#define MX51_PAD_DI1_PIN13__GPIO_3_2 IOMUX_PAD(0x6B0, 0x2B0, 4, 0x97c, 1, NO_PAD_CTRL) 263#define _MX51_PAD_NANDF_RB3__FEC_RX_CLK IOMUX_PAD(0x504, 0x128, 1, 0x0968, 0, 0)
285#define MX51_PAD_DI1_D0_CS__GPIO_3_3 IOMUX_PAD(0x6B4, 0x2B4, 4, 0x980, 1, NO_PAD_CTRL) 264#define _MX51_PAD_NANDF_RB3__GPIO3_11 IOMUX_PAD(0x504, 0x128, 3, 0x0000, 0, 0)
286#define MX51_PAD_DI1_D1_CS__GPIO_3_4 IOMUX_PAD(0x6B8, 0x2B8, 4, 0x984, 1, NO_PAD_CTRL) 265#define _MX51_PAD_NANDF_RB3__NANDF_RB3 IOMUX_PAD(0x504, 0x128, 0, 0x0000, 0, 0)
287#define MX51_PAD_DISPB2_SER_DIN__GPIO_3_5 IOMUX_PAD(0x6BC, 0x2BC, 4, 0x988, 1, NO_PAD_CTRL) 266#define _MX51_PAD_NANDF_RB3__USBH3_CLK IOMUX_PAD(0x504, 0x128, 6, 0x09f8, 0, 0)
288#define MX51_PAD_DISPB2_SER_DIO__GPIO_3_6 IOMUX_PAD(0x6C0, 0x2C0, 4, 0x98c, 1, NO_PAD_CTRL) 267#define _MX51_PAD_NANDF_RB3__USBH3_H3_DM IOMUX_PAD(0x504, 0x128, 7, 0x0000, 0, 0)
289#define MX51_PAD_DISPB2_SER_CLK__GPIO_3_7 IOMUX_PAD(0x6C4, 0x2C4, 4, 0x990, 1, NO_PAD_CTRL) 268#define _MX51_PAD_GPIO_NAND__GPIO_NAND IOMUX_PAD(0x514, 0x12c, 0, 0x0998, 0, 0)
290#define MX51_PAD_DISPB2_SER_RS__GPIO_3_8 IOMUX_PAD(0x6C8, 0x2C8, 4, 0x994, 1, NO_PAD_CTRL) 269#define _MX51_PAD_GPIO_NAND__PATA_INTRQ IOMUX_PAD(0x514, 0x12c, 1, 0x0000, 0, 0)
291#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6CC, 0x2CC, 0, 0x0, 0, NO_PAD_CTRL) 270#define _MX51_PAD_NANDF_CS0__GPIO3_16 IOMUX_PAD(0x518, 0x130, 3, 0x0000, 0, 0)
292#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6D0, 0x2D0, 0, 0x0, 0, NO_PAD_CTRL) 271#define _MX51_PAD_NANDF_CS0__NANDF_CS0 IOMUX_PAD(0x518, 0x130, 0, 0x0000, 0, 0)
293#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6D4, 0x2D4, 0, 0x0, 0, NO_PAD_CTRL) 272#define _MX51_PAD_NANDF_CS1__GPIO3_17 IOMUX_PAD(0x51c, 0x134, 3, 0x0000, 0, 0)
294#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6D8, 0x2D8, 0, 0x0, 0, NO_PAD_CTRL) 273#define _MX51_PAD_NANDF_CS1__NANDF_CS1 IOMUX_PAD(0x51c, 0x134, 0, 0x0000, 0, 0)
295#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6DC, 0x2DC, 0, 0x0, 0, NO_PAD_CTRL) 274#define _MX51_PAD_NANDF_CS2__CSPI_SCLK IOMUX_PAD(0x520, 0x138, 6, 0x0914, 0, 0)
296#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6E0, 0x2E0, 0, 0x0, 0, NO_PAD_CTRL) 275#define _MX51_PAD_NANDF_CS2__FEC_TX_ER IOMUX_PAD(0x520, 0x138, 2, 0x0000, 0, 0)
297#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6E4, 0x2E4, 0, 0x0, 0, NO_PAD_CTRL) 276#define _MX51_PAD_NANDF_CS2__GPIO3_18 IOMUX_PAD(0x520, 0x138, 3, 0x0000, 0, 0)
298#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6E8, 0x2E8, 0, 0x0, 0, NO_PAD_CTRL) 277#define _MX51_PAD_NANDF_CS2__NANDF_CS2 IOMUX_PAD(0x520, 0x138, 0, 0x0000, 0, 0)
299#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6EC, 0x2EC, 0, 0x0, 0, NO_PAD_CTRL) 278#define _MX51_PAD_NANDF_CS2__PATA_CS_0 IOMUX_PAD(0x520, 0x138, 1, 0x0000, 0, 0)
300#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6F0, 0x2F0, 0, 0x0, 0, NO_PAD_CTRL) 279#define _MX51_PAD_NANDF_CS2__SD4_CLK IOMUX_PAD(0x520, 0x138, 5, 0x0000, 0, 0)
301#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6F4, 0x2F4, 0, 0x0, 0, NO_PAD_CTRL) 280#define _MX51_PAD_NANDF_CS2__USBH3_H1_DP IOMUX_PAD(0x520, 0x138, 7, 0x0000, 0, 0)
302#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6F8, 0x2F8, 0, 0x0, 0, NO_PAD_CTRL) 281#define _MX51_PAD_NANDF_CS3__FEC_MDC IOMUX_PAD(0x524, 0x13c, 2, 0x0000, 0, 0)
303#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6FC, 0x2FC, 0, 0x0, 0, NO_PAD_CTRL) 282#define _MX51_PAD_NANDF_CS3__GPIO3_19 IOMUX_PAD(0x524, 0x13c, 3, 0x0000, 0, 0)
304#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0, 0, NO_PAD_CTRL) 283#define _MX51_PAD_NANDF_CS3__NANDF_CS3 IOMUX_PAD(0x524, 0x13c, 0, 0x0000, 0, 0)
305#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0, 0, NO_PAD_CTRL) 284#define _MX51_PAD_NANDF_CS3__PATA_CS_1 IOMUX_PAD(0x524, 0x13c, 1, 0x0000, 0, 0)
306#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0, 0, NO_PAD_CTRL) 285#define _MX51_PAD_NANDF_CS3__SD4_DAT0 IOMUX_PAD(0x524, 0x13c, 5, 0x0000, 0, 0)
307#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70C, 0x30C, 0, 0x0, 0, NO_PAD_CTRL) 286#define _MX51_PAD_NANDF_CS3__USBH3_H1_DM IOMUX_PAD(0x524, 0x13c, 7, 0x0000, 0, 0)
308#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0, 0, NO_PAD_CTRL) 287#define _MX51_PAD_NANDF_CS4__FEC_TDATA1 IOMUX_PAD(0x528, 0x140, 2, 0x0000, 0, 0)
309#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0, 0, NO_PAD_CTRL) 288#define _MX51_PAD_NANDF_CS4__GPIO3_20 IOMUX_PAD(0x528, 0x140, 3, 0x0000, 0, 0)
310#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0, 0, NO_PAD_CTRL) 289#define _MX51_PAD_NANDF_CS4__NANDF_CS4 IOMUX_PAD(0x528, 0x140, 0, 0x0000, 0, 0)
311#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71C, 0x31C, 0, 0x0, 0, NO_PAD_CTRL) 290#define _MX51_PAD_NANDF_CS4__PATA_DA_0 IOMUX_PAD(0x528, 0x140, 1, 0x0000, 0, 0)
312#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0, 0, NO_PAD_CTRL) 291#define _MX51_PAD_NANDF_CS4__SD4_DAT1 IOMUX_PAD(0x528, 0x140, 5, 0x0000, 0, 0)
313#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0, 0, NO_PAD_CTRL) 292#define _MX51_PAD_NANDF_CS4__USBH3_STP IOMUX_PAD(0x528, 0x140, 7, 0x0a24, 0, 0)
314#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0, 0, NO_PAD_CTRL) 293#define _MX51_PAD_NANDF_CS5__FEC_TDATA2 IOMUX_PAD(0x52c, 0x144, 2, 0x0000, 0, 0)
315#define MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72C, 0x32C, 0, 0x0, 0, NO_PAD_CTRL) 294#define _MX51_PAD_NANDF_CS5__GPIO3_21 IOMUX_PAD(0x52c, 0x144, 3, 0x0000, 0, 0)
316#define MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0, 0, NO_PAD_CTRL) 295#define _MX51_PAD_NANDF_CS5__NANDF_CS5 IOMUX_PAD(0x52c, 0x144, 0, 0x0000, 0, 0)
317#define MX51_PAD_DI_GP1__DI_GP1 IOMUX_PAD(0x73C, 0x334, 0, 0x0, 0, NO_PAD_CTRL) 296#define _MX51_PAD_NANDF_CS5__PATA_DA_1 IOMUX_PAD(0x52c, 0x144, 1, 0x0000, 0, 0)
318#define MX51_PAD_DI_GP2__DI_GP2 IOMUX_PAD(0x740, 0x338, 0, 0x0, 0, NO_PAD_CTRL) 297#define _MX51_PAD_NANDF_CS5__SD4_DAT2 IOMUX_PAD(0x52c, 0x144, 5, 0x0000, 0, 0)
319#define MX51_PAD_DI_GP3__DI_GP3 IOMUX_PAD(0x744, 0x33C, 0, 0x0, 0, NO_PAD_CTRL) 298#define _MX51_PAD_NANDF_CS5__USBH3_DIR IOMUX_PAD(0x52c, 0x144, 7, 0x0a1c, 0, 0)
320#define MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0, 0, NO_PAD_CTRL) 299#define _MX51_PAD_NANDF_CS6__CSPI_SS3 IOMUX_PAD(0x530, 0x148, 7, 0x0928, 0, 0)
321#define MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74C, 0x344, 0, 0x0, 0, NO_PAD_CTRL) 300#define _MX51_PAD_NANDF_CS6__FEC_TDATA3 IOMUX_PAD(0x530, 0x148, 2, 0x0000, 0, 0)
322#define MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0, 0, NO_PAD_CTRL) 301#define _MX51_PAD_NANDF_CS6__GPIO3_22 IOMUX_PAD(0x530, 0x148, 3, 0x0000, 0, 0)
323#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34C, 0, 0x0, 0, NO_PAD_CTRL) 302#define _MX51_PAD_NANDF_CS6__NANDF_CS6 IOMUX_PAD(0x530, 0x148, 0, 0x0000, 0, 0)
324#define MX51_PAD_DI_GP4__DI_GP4 IOMUX_PAD(0x758, 0x350, 0, 0x0, 0, NO_PAD_CTRL) 303#define _MX51_PAD_NANDF_CS6__PATA_DA_2 IOMUX_PAD(0x530, 0x148, 1, 0x0000, 0, 0)
325#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75C, 0x354, 0, 0x0, 0, NO_PAD_CTRL) 304#define _MX51_PAD_NANDF_CS6__SD4_DAT3 IOMUX_PAD(0x530, 0x148, 5, 0x0000, 0, 0)
326#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0, 0, NO_PAD_CTRL) 305#define _MX51_PAD_NANDF_CS7__FEC_TX_EN IOMUX_PAD(0x534, 0x14c, 1, 0x0000, 0, 0)
327#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35C, 0, 0x0, 0, NO_PAD_CTRL) 306#define _MX51_PAD_NANDF_CS7__GPIO3_23 IOMUX_PAD(0x534, 0x14c, 3, 0x0000, 0, 0)
328#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0, 0, NO_PAD_CTRL) 307#define _MX51_PAD_NANDF_CS7__NANDF_CS7 IOMUX_PAD(0x534, 0x14c, 0, 0x0000, 0, 0)
329#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76C, 0x364, 0, 0x0, 0, NO_PAD_CTRL) 308#define _MX51_PAD_NANDF_CS7__SD3_CLK IOMUX_PAD(0x534, 0x14c, 5, 0x0000, 0, 0)
330#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0, 0, NO_PAD_CTRL) 309#define _MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 IOMUX_PAD(0x538, 0x150, 2, 0x0000, 0, 0)
331#define MX51_PAD_DISP2_DAT6__GPIO_1_19 IOMUX_PAD(0x774, 0x36C, 5, 0x0, 0, NO_PAD_CTRL) 310#define _MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK IOMUX_PAD(0x538, 0x150, 1, 0x0974, 0, 0)
332#define MX51_PAD_DISP2_DAT7__GPIO_1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0, 0, NO_PAD_CTRL) 311#define _MX51_PAD_NANDF_RDY_INT__GPIO3_24 IOMUX_PAD(0x538, 0x150, 3, 0x0000, 0, 0)
333#define MX51_PAD_DISP2_DAT8__GPIO_1_30 IOMUX_PAD(0x77C, 0x374, 5, 0x0, 0, NO_PAD_CTRL) 312#define _MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT IOMUX_PAD(0x538, 0x150, 0, 0x0938, 0, 0)
334#define MX51_PAD_DISP2_DAT9__GPIO_1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0, 0, NO_PAD_CTRL) 313#define _MX51_PAD_NANDF_RDY_INT__SD3_CMD IOMUX_PAD(0x538, 0x150, 5, 0x0000, 0, 0)
335#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37C, 0, 0x0, 0, NO_PAD_CTRL) 314#define _MX51_PAD_NANDF_D15__ECSPI2_MOSI IOMUX_PAD(0x53c, 0x154, 2, 0x0000, 0, 0)
336#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0, 0, NO_PAD_CTRL) 315#define _MX51_PAD_NANDF_D15__GPIO3_25 IOMUX_PAD(0x53c, 0x154, 3, 0x0000, 0, 0)
337#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78C, 0x384, 0, 0x0, 0, NO_PAD_CTRL) 316#define _MX51_PAD_NANDF_D15__NANDF_D15 IOMUX_PAD(0x53c, 0x154, 0, 0x0000, 0, 0)
338#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0, 0, NO_PAD_CTRL) 317#define _MX51_PAD_NANDF_D15__PATA_DATA15 IOMUX_PAD(0x53c, 0x154, 1, 0x0000, 0, 0)
339#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38C, 0, 0x0, 0, NO_PAD_CTRL) 318#define _MX51_PAD_NANDF_D15__SD3_DAT7 IOMUX_PAD(0x53c, 0x154, 5, 0x0000, 0, 0)
340#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0, 0, NO_PAD_CTRL) 319#define _MX51_PAD_NANDF_D14__ECSPI2_SS3 IOMUX_PAD(0x540, 0x158, 2, 0x0934, 0, 0)
341#define MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79C, 0x394, IOMUX_CONFIG_SION, 0x0, 0, \ 320#define _MX51_PAD_NANDF_D14__GPIO3_26 IOMUX_PAD(0x540, 0x158, 3, 0x0000, 0, 0)
342 MX51_SDHCI_PAD_CTRL) 321#define _MX51_PAD_NANDF_D14__NANDF_D14 IOMUX_PAD(0x540, 0x158, 0, 0x0000, 0, 0)
343#define MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79C, 0x394, 1, 0x8e0, 1, NO_PAD_CTRL) 322#define _MX51_PAD_NANDF_D14__PATA_DATA14 IOMUX_PAD(0x540, 0x158, 1, 0x0000, 0, 0)
344#define MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7A0, 0x398, IOMUX_CONFIG_SION, 0x0, 0, \ 323#define _MX51_PAD_NANDF_D14__SD3_DAT6 IOMUX_PAD(0x540, 0x158, 5, 0x0000, 0, 0)
345 MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) 324#define _MX51_PAD_NANDF_D13__ECSPI2_SS2 IOMUX_PAD(0x544, 0x15c, 2, 0x0000, 0, 0)
346#define MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7A0, 0x398, 1, 0x8dc, 1, NO_PAD_CTRL) 325#define _MX51_PAD_NANDF_D13__GPIO3_27 IOMUX_PAD(0x544, 0x15c, 3, 0x0000, 0, 0)
347#define MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7A4, 0x39C, IOMUX_CONFIG_SION, 0x0, 0, \ 326#define _MX51_PAD_NANDF_D13__NANDF_D13 IOMUX_PAD(0x544, 0x15c, 0, 0x0000, 0, 0)
348 MX51_SDHCI_PAD_CTRL) 327#define _MX51_PAD_NANDF_D13__PATA_DATA13 IOMUX_PAD(0x544, 0x15c, 1, 0x0000, 0, 0)
349#define MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7A4, 0x39C, 1, 0x8d8, 2, NO_PAD_CTRL) 328#define _MX51_PAD_NANDF_D13__SD3_DAT5 IOMUX_PAD(0x544, 0x15c, 5, 0x0000, 0, 0)
350#define MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7A8, 0x3A0, IOMUX_CONFIG_SION, 0x0, 0, \ 329#define _MX51_PAD_NANDF_D12__ECSPI2_SS1 IOMUX_PAD(0x548, 0x160, 2, 0x0930, 1, 0)
351 MX51_SDHCI_PAD_CTRL) 330#define _MX51_PAD_NANDF_D12__GPIO3_28 IOMUX_PAD(0x548, 0x160, 3, 0x0000, 0, 0)
352#define MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7A8, 0x3A0, 1, 0x8d4, 2, NO_PAD_CTRL) 331#define _MX51_PAD_NANDF_D12__NANDF_D12 IOMUX_PAD(0x548, 0x160, 0, 0x0000, 0, 0)
353#define MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7AC, 0x3A4, IOMUX_CONFIG_SION, 0x0, 0, \ 332#define _MX51_PAD_NANDF_D12__PATA_DATA12 IOMUX_PAD(0x548, 0x160, 1, 0x0000, 0, 0)
354 MX51_SDHCI_PAD_CTRL) 333#define _MX51_PAD_NANDF_D12__SD3_DAT4 IOMUX_PAD(0x548, 0x160, 5, 0x0000, 0, 0)
355#define MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7AC, 0x3A4, 1, 0x8e4, 2, NO_PAD_CTRL) 334#define _MX51_PAD_NANDF_D11__FEC_RX_DV IOMUX_PAD(0x54c, 0x164, 2, 0x096c, 0, 0)
356#define MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7B0, 0x3A8, IOMUX_CONFIG_SION, 0x0, 0, \ 335#define _MX51_PAD_NANDF_D11__GPIO3_29 IOMUX_PAD(0x54c, 0x164, 3, 0x0000, 0, 0)
357 MX51_SDHCI_PAD_CTRL) 336#define _MX51_PAD_NANDF_D11__NANDF_D11 IOMUX_PAD(0x54c, 0x164, 0, 0x0000, 0, 0)
358#define MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7B0, 0x3A8, 1, 0x8e8, 2, NO_PAD_CTRL) 337#define _MX51_PAD_NANDF_D11__PATA_DATA11 IOMUX_PAD(0x54c, 0x164, 1, 0x0000, 0, 0)
359#define MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7BC, 0x3B4, IOMUX_CONFIG_SION, 0x0, 1, \ 338#define _MX51_PAD_NANDF_D11__SD3_DATA3 IOMUX_PAD(0x54c, 0x164, 5, 0x0948, 1, 0)
360 MX51_SDHCI_PAD_CTRL) 339#define _MX51_PAD_NANDF_D10__GPIO3_30 IOMUX_PAD(0x550, 0x168, 3, 0x0000, 0, 0)
361#define MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7C0, 0x3B8, IOMUX_CONFIG_SION, 0x0, 0, \ 340#define _MX51_PAD_NANDF_D10__NANDF_D10 IOMUX_PAD(0x550, 0x168, 0, 0x0000, 0, 0)
362 MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS) 341#define _MX51_PAD_NANDF_D10__PATA_DATA10 IOMUX_PAD(0x550, 0x168, 1, 0x0000, 0, 0)
363#define MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7C4, 0x3BC, IOMUX_CONFIG_SION, 0x0, 0, \ 342#define _MX51_PAD_NANDF_D10__SD3_DATA2 IOMUX_PAD(0x550, 0x168, 5, 0x0944, 1, 0)
364 MX51_SDHCI_PAD_CTRL) 343#define _MX51_PAD_NANDF_D9__FEC_RDATA0 IOMUX_PAD(0x554, 0x16c, 0x12, 0x0958, 0, 0)
365#define MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7C8, 0x3C0, IOMUX_CONFIG_SION, 0x0, 0, \ 344#define _MX51_PAD_NANDF_D9__GPIO3_31 IOMUX_PAD(0x554, 0x16c, 3, 0x0000, 0, 0)
366 MX51_SDHCI_PAD_CTRL) 345#define _MX51_PAD_NANDF_D9__NANDF_D9 IOMUX_PAD(0x554, 0x16c, 0, 0x0000, 0, 0)
367#define MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7CC, 0x3C4, IOMUX_CONFIG_SION, 0x0, 0, \ 346#define _MX51_PAD_NANDF_D9__PATA_DATA9 IOMUX_PAD(0x554, 0x16c, 1, 0x0000, 0, 0)
368 MX51_SDHCI_PAD_CTRL) 347#define _MX51_PAD_NANDF_D9__SD3_DATA1 IOMUX_PAD(0x554, 0x16c, 5, 0x0940, 1, 0)
369#define MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7D0, 0x3C8, IOMUX_CONFIG_SION, 0x0, 0, \ 348#define _MX51_PAD_NANDF_D8__FEC_TDATA0 IOMUX_PAD(0x558, 0x170, 2, 0x0000, 0, 0)
370 MX51_SDHCI_PAD_CTRL) 349#define _MX51_PAD_NANDF_D8__GPIO4_0 IOMUX_PAD(0x558, 0x170, 3, 0x0000, 0, 0)
371#define MX51_PAD_GPIO_1_0__GPIO_1_0 IOMUX_PAD(0x7B4, 0x3AC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 350#define _MX51_PAD_NANDF_D8__NANDF_D8 IOMUX_PAD(0x558, 0x170, 0, 0x0000, 0, 0)
372#define MX51_PAD_GPIO_1_1__GPIO_1_1 IOMUX_PAD(0x7B8, 0x3B0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 351#define _MX51_PAD_NANDF_D8__PATA_DATA8 IOMUX_PAD(0x558, 0x170, 1, 0x0000, 0, 0)
373#define MX51_PAD_GPIO_1_2__GPIO_1_2 IOMUX_PAD(0x7D4, 0x3CC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 352#define _MX51_PAD_NANDF_D8__SD3_DATA0 IOMUX_PAD(0x558, 0x170, 5, 0x093c, 1, 0)
374#define MX51_PAD_GPIO_1_2__I2C2_SCL IOMUX_PAD(0x7D4, 0x3CC, (2 | IOMUX_CONFIG_SION), \ 353#define _MX51_PAD_NANDF_D7__GPIO4_1 IOMUX_PAD(0x55c, 0x174, 3, 0x0000, 0, 0)
375 0x9b8, 3, MX51_I2C_PAD_CTRL) 354#define _MX51_PAD_NANDF_D7__NANDF_D7 IOMUX_PAD(0x55c, 0x174, 0, 0x0000, 0, 0)
376#define MX51_PAD_GPIO_1_3__GPIO_1_3 IOMUX_PAD(0x7D8, 0x3D0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 355#define _MX51_PAD_NANDF_D7__PATA_DATA7 IOMUX_PAD(0x55c, 0x174, 1, 0x0000, 0, 0)
377#define MX51_PAD_GPIO_1_3__I2C2_SDA IOMUX_PAD(0x7D8, 0x3D0, (2 | IOMUX_CONFIG_SION), \ 356#define _MX51_PAD_NANDF_D7__USBH3_DATA0 IOMUX_PAD(0x55c, 0x174, 5, 0x09fc, 0, 0)
378 0x9bc, 3, MX51_I2C_PAD_CTRL) 357#define _MX51_PAD_NANDF_D6__GPIO4_2 IOMUX_PAD(0x560, 0x178, 3, 0x0000, 0, 0)
379#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7FC, 0x3D4, 0, 0x0, 0, NO_PAD_CTRL) 358#define _MX51_PAD_NANDF_D6__NANDF_D6 IOMUX_PAD(0x560, 0x178, 0, 0x0000, 0, 0)
380#define MX51_PAD_GPIO_1_4__GPIO_1_4 IOMUX_PAD(0x804, 0x3D8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 359#define _MX51_PAD_NANDF_D6__PATA_DATA6 IOMUX_PAD(0x560, 0x178, 1, 0x0000, 0, 0)
381#define MX51_PAD_GPIO_1_5__GPIO_1_5 IOMUX_PAD(0x808, 0x3DC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 360#define _MX51_PAD_NANDF_D6__SD4_LCTL IOMUX_PAD(0x560, 0x178, 2, 0x0000, 0, 0)
382#define MX51_PAD_GPIO_1_6__GPIO_1_6 IOMUX_PAD(0x80C, 0x3E0, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 361#define _MX51_PAD_NANDF_D6__USBH3_DATA1 IOMUX_PAD(0x560, 0x178, 5, 0x0a00, 0, 0)
383#define MX51_PAD_GPIO_1_7__GPIO_1_7 IOMUX_PAD(0x810, 0x3E4, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 362#define _MX51_PAD_NANDF_D5__GPIO4_3 IOMUX_PAD(0x564, 0x17c, 3, 0x0000, 0, 0)
384#define MX51_PAD_GPIO_1_8__GPIO_1_8 IOMUX_PAD(0x814, 0x3E8, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 363#define _MX51_PAD_NANDF_D5__NANDF_D5 IOMUX_PAD(0x564, 0x17c, 0, 0x0000, 0, 0)
385#define MX51_PAD_GPIO_1_9__GPIO_1_9 IOMUX_PAD(0x818, 0x3EC, 1, 0x0, 0, MX51_GPIO_PAD_CTRL) 364#define _MX51_PAD_NANDF_D5__PATA_DATA5 IOMUX_PAD(0x564, 0x17c, 1, 0x0000, 0, 0)
365#define _MX51_PAD_NANDF_D5__SD4_WP IOMUX_PAD(0x564, 0x17c, 2, 0x0000, 0, 0)
366#define _MX51_PAD_NANDF_D5__USBH3_DATA2 IOMUX_PAD(0x564, 0x17c, 5, 0x0a04, 0, 0)
367#define _MX51_PAD_NANDF_D4__GPIO4_4 IOMUX_PAD(0x568, 0x180, 3, 0x0000, 0, 0)
368#define _MX51_PAD_NANDF_D4__NANDF_D4 IOMUX_PAD(0x568, 0x180, 0, 0x0000, 0, 0)
369#define _MX51_PAD_NANDF_D4__PATA_DATA4 IOMUX_PAD(0x568, 0x180, 1, 0x0000, 0, 0)
370#define _MX51_PAD_NANDF_D4__SD4_CD IOMUX_PAD(0x568, 0x180, 2, 0x0000, 0, 0)
371#define _MX51_PAD_NANDF_D4__USBH3_DATA3 IOMUX_PAD(0x568, 0x180, 5, 0x0a08, 0, 0)
372#define _MX51_PAD_NANDF_D3__GPIO4_5 IOMUX_PAD(0x56c, 0x184, 3, 0x0000, 0, 0)
373#define _MX51_PAD_NANDF_D3__NANDF_D3 IOMUX_PAD(0x56c, 0x184, 0, 0x0000, 0, 0)
374#define _MX51_PAD_NANDF_D3__PATA_DATA3 IOMUX_PAD(0x56c, 0x184, 1, 0x0000, 0, 0)
375#define _MX51_PAD_NANDF_D3__SD4_DAT4 IOMUX_PAD(0x56c, 0x184, 2, 0x0000, 0, 0)
376#define _MX51_PAD_NANDF_D3__USBH3_DATA4 IOMUX_PAD(0x56c, 0x184, 5, 0x0a0c, 0, 0)
377#define _MX51_PAD_NANDF_D2__GPIO4_6 IOMUX_PAD(0x570, 0x188, 3, 0x0000, 0, 0)
378#define _MX51_PAD_NANDF_D2__NANDF_D2 IOMUX_PAD(0x570, 0x188, 0, 0x0000, 0, 0)
379#define _MX51_PAD_NANDF_D2__PATA_DATA2 IOMUX_PAD(0x570, 0x188, 1, 0x0000, 0, 0)
380#define _MX51_PAD_NANDF_D2__SD4_DAT5 IOMUX_PAD(0x570, 0x188, 2, 0x0000, 0, 0)
381#define _MX51_PAD_NANDF_D2__USBH3_DATA5 IOMUX_PAD(0x570, 0x188, 5, 0x0a10, 0, 0)
382#define _MX51_PAD_NANDF_D1__GPIO4_7 IOMUX_PAD(0x574, 0x18c, 3, 0x0000, 0, 0)
383#define _MX51_PAD_NANDF_D1__NANDF_D1 IOMUX_PAD(0x574, 0x18c, 0, 0x0000, 0, 0)
384#define _MX51_PAD_NANDF_D1__PATA_DATA1 IOMUX_PAD(0x574, 0x18c, 1, 0x0000, 0, 0)
385#define _MX51_PAD_NANDF_D1__SD4_DAT6 IOMUX_PAD(0x574, 0x18c, 2, 0x0000, 0, 0)
386#define _MX51_PAD_NANDF_D1__USBH3_DATA6 IOMUX_PAD(0x574, 0x18c, 5, 0x0a14, 0, 0)
387#define _MX51_PAD_NANDF_D0__GPIO4_8 IOMUX_PAD(0x578, 0x190, 3, 0x0000, 0, 0)
388#define _MX51_PAD_NANDF_D0__NANDF_D0 IOMUX_PAD(0x578, 0x190, 0, 0x0000, 0, 0)
389#define _MX51_PAD_NANDF_D0__PATA_DATA0 IOMUX_PAD(0x578, 0x190, 1, 0x0000, 0, 0)
390#define _MX51_PAD_NANDF_D0__SD4_DAT7 IOMUX_PAD(0x578, 0x190, 2, 0x0000, 0, 0)
391#define _MX51_PAD_NANDF_D0__USBH3_DATA7 IOMUX_PAD(0x578, 0x190, 5, 0x0a18, 0, 0)
392#define _MX51_PAD_CSI1_D8__CSI1_D8 IOMUX_PAD(0x57c, 0x194, 0, 0x0000, 0, 0)
393#define _MX51_PAD_CSI1_D8__GPIO3_12 IOMUX_PAD(0x57c, 0x194, 3, 0x0998, 1, 0)
394#define _MX51_PAD_CSI1_D9__CSI1_D9 IOMUX_PAD(0x580, 0x198, 0, 0x0000, 0, 0)
395#define _MX51_PAD_CSI1_D9__GPIO3_13 IOMUX_PAD(0x580, 0x198, 3, 0x0000, 0, 0)
396#define _MX51_PAD_CSI1_D10__CSI1_D10 IOMUX_PAD(0x584, 0x19c, 0, 0x0000, 0, 0)
397#define _MX51_PAD_CSI1_D11__CSI1_D11 IOMUX_PAD(0x588, 0x1a0, 0, 0x0000, 0, 0)
398#define _MX51_PAD_CSI1_D12__CSI1_D12 IOMUX_PAD(0x58c, 0x1a4, 0, 0x0000, 0, 0)
399#define _MX51_PAD_CSI1_D13__CSI1_D13 IOMUX_PAD(0x590, 0x1a8, 0, 0x0000, 0, 0)
400#define _MX51_PAD_CSI1_D14__CSI1_D14 IOMUX_PAD(0x594, 0x1ac, 0, 0x0000, 0, 0)
401#define _MX51_PAD_CSI1_D15__CSI1_D15 IOMUX_PAD(0x598, 0x1b0, 0, 0x0000, 0, 0)
402#define _MX51_PAD_CSI1_D16__CSI1_D16 IOMUX_PAD(0x59c, 0x1b4, 0, 0x0000, 0, 0)
403#define _MX51_PAD_CSI1_D17__CSI1_D17 IOMUX_PAD(0x5a0, 0x1b8, 0, 0x0000, 0, 0)
404#define _MX51_PAD_CSI1_D18__CSI1_D18 IOMUX_PAD(0x5a4, 0x1bc, 0, 0x0000, 0, 0)
405#define _MX51_PAD_CSI1_D19__CSI1_D19 IOMUX_PAD(0x5a8, 0x1c0, 0, 0x0000, 0, 0)
406#define _MX51_PAD_CSI1_VSYNC__CSI1_VSYNC IOMUX_PAD(0x5ac, 0x1c4, 0, 0x0000, 0, 0)
407#define _MX51_PAD_CSI1_VSYNC__GPIO3_14 IOMUX_PAD(0x5ac, 0x1c4, 3, 0x0000, 0, 0)
408#define _MX51_PAD_CSI1_HSYNC__CSI1_HSYNC IOMUX_PAD(0x5b0, 0x1c8, 0, 0x0000, 0, 0)
409#define _MX51_PAD_CSI1_HSYNC__GPIO3_15 IOMUX_PAD(0x5b0, 0x1c8, 3, 0x0000, 0, 0)
410#define _MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK IOMUX_PAD(0x5b4, 0x000, 0, 0x0000, 0, 0)
411#define _MX51_PAD_CSI1_MCLK__CSI1_MCLK IOMUX_PAD(0x5b8, 0x000, 0, 0x0000, 0, 0)
412#define _MX51_PAD_CSI2_D12__CSI2_D12 IOMUX_PAD(0x5bc, 0x1cc, 0, 0x0000, 0, 0)
413#define _MX51_PAD_CSI2_D12__GPIO4_9 IOMUX_PAD(0x5bc, 0x1cc, 3, 0x0000, 0, 0)
414#define _MX51_PAD_CSI2_D13__CSI2_D13 IOMUX_PAD(0x5c0, 0x1d0, 0, 0x0000, 0, 0)
415#define _MX51_PAD_CSI2_D13__GPIO4_10 IOMUX_PAD(0x5c0, 0x1d0, 3, 0x0000, 0, 0)
416#define _MX51_PAD_CSI2_D14__CSI2_D14 IOMUX_PAD(0x5c4, 0x1d4, 0, 0x0000, 0, 0)
417#define _MX51_PAD_CSI2_D15__CSI2_D15 IOMUX_PAD(0x5c8, 0x1d8, 0, 0x0000, 0, 0)
418#define _MX51_PAD_CSI2_D16__CSI2_D16 IOMUX_PAD(0x5cc, 0x1dc, 0, 0x0000, 0, 0)
419#define _MX51_PAD_CSI2_D17__CSI2_D17 IOMUX_PAD(0x5d0, 0x1e0, 0, 0x0000, 0, 0)
420#define _MX51_PAD_CSI2_D18__CSI2_D18 IOMUX_PAD(0x5d4, 0x1e4, 0, 0x0000, 0, 0)
421#define _MX51_PAD_CSI2_D18__GPIO4_11 IOMUX_PAD(0x5d4, 0x1e4, 3, 0x0000, 0, 0)
422#define _MX51_PAD_CSI2_D19__CSI2_D19 IOMUX_PAD(0x5d8, 0x1e8, 0, 0x0000, 0, 0)
423#define _MX51_PAD_CSI2_D19__GPIO4_12 IOMUX_PAD(0x5d8, 0x1e8, 3, 0x0000, 0, 0)
424#define _MX51_PAD_CSI2_VSYNC__CSI2_VSYNC IOMUX_PAD(0x5dc, 0x1ec, 0, 0x0000, 0, 0)
425#define _MX51_PAD_CSI2_VSYNC__GPIO4_13 IOMUX_PAD(0x5dc, 0x1ec, 3, 0x0000, 0, 0)
426#define _MX51_PAD_CSI2_HSYNC__CSI2_HSYNC IOMUX_PAD(0x5e0, 0x1f0, 0, 0x0000, 0, 0)
427#define _MX51_PAD_CSI2_HSYNC__GPIO4_14 IOMUX_PAD(0x5e0, 0x1f0, 3, 0x0000, 0, 0)
428#define _MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK IOMUX_PAD(0x5e4, 0x1f4, 0, 0x0000, 0, 0)
429#define _MX51_PAD_CSI2_PIXCLK__GPIO4_15 IOMUX_PAD(0x5e4, 0x1f4, 3, 0x0000, 0, 0)
430#define _MX51_PAD_I2C1_CLK__GPIO4_16 IOMUX_PAD(0x5e8, 0x1f8, 3, 0x0000, 0, 0)
431#define _MX51_PAD_I2C1_CLK__I2C1_CLK IOMUX_PAD(0x5e8, 0x1f8, 0x10, 0x0000, 0, 0)
432#define _MX51_PAD_I2C1_DAT__GPIO4_17 IOMUX_PAD(0x5ec, 0x1fc, 3, 0x0000, 0, 0)
433#define _MX51_PAD_I2C1_DAT__I2C1_DAT IOMUX_PAD(0x5ec, 0x1fc, 0x10, 0x0000, 0, 0)
434#define _MX51_PAD_AUD3_BB_TXD__AUD3_TXD IOMUX_PAD(0x5f0, 0x200, 0, 0x0000, 0, 0)
435#define _MX51_PAD_AUD3_BB_TXD__GPIO4_18 IOMUX_PAD(0x5f0, 0x200, 3, 0x0000, 0, 0)
436#define _MX51_PAD_AUD3_BB_RXD__AUD3_RXD IOMUX_PAD(0x5f4, 0x204, 0, 0x0000, 0, 0)
437#define _MX51_PAD_AUD3_BB_RXD__GPIO4_19 IOMUX_PAD(0x5f4, 0x204, 3, 0x0000, 0, 0)
438#define _MX51_PAD_AUD3_BB_RXD__UART3_RXD IOMUX_PAD(0x5f4, 0x204, 1, 0x09f4, 2, 0)
439#define _MX51_PAD_AUD3_BB_CK__AUD3_TXC IOMUX_PAD(0x5f8, 0x208, 0, 0x0000, 0, 0)
440#define _MX51_PAD_AUD3_BB_CK__GPIO4_20 IOMUX_PAD(0x5f8, 0x208, 3, 0x0000, 0, 0)
441#define _MX51_PAD_AUD3_BB_FS__AUD3_TXFS IOMUX_PAD(0x5fc, 0x20c, 0, 0x0000, 0, 0)
442#define _MX51_PAD_AUD3_BB_FS__GPIO4_21 IOMUX_PAD(0x5fc, 0x20c, 3, 0x0000, 0, 0)
443#define _MX51_PAD_AUD3_BB_FS__UART3_TXD IOMUX_PAD(0x5fc, 0x20c, 1, 0x0000, 0, 0)
444#define _MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI IOMUX_PAD(0x600, 0x210, 0, 0x0000, 0, 0)
445#define _MX51_PAD_CSPI1_MOSI__GPIO4_22 IOMUX_PAD(0x600, 0x210, 3, 0x0000, 0, 0)
446#define _MX51_PAD_CSPI1_MOSI__I2C1_SDA IOMUX_PAD(0x600, 0x210, 0x11, 0x09b4, 1, 0)
447#define _MX51_PAD_CSPI1_MISO__AUD4_RXD IOMUX_PAD(0x604, 0x214, 1, 0x08c4, 1, 0)
448#define _MX51_PAD_CSPI1_MISO__ECSPI1_MISO IOMUX_PAD(0x604, 0x214, 0, 0x0000, 0, 0)
449#define _MX51_PAD_CSPI1_MISO__GPIO4_23 IOMUX_PAD(0x604, 0x214, 3, 0x0000, 0, 0)
450#define _MX51_PAD_CSPI1_SS0__AUD4_TXC IOMUX_PAD(0x608, 0x218, 1, 0x08cc, 1, 0)
451#define _MX51_PAD_CSPI1_SS0__ECSPI1_SS0 IOMUX_PAD(0x608, 0x218, 0, 0x0000, 0, 0)
452#define _MX51_PAD_CSPI1_SS0__GPIO4_24 IOMUX_PAD(0x608, 0x218, 3, 0x0000, 0, 0)
453#define _MX51_PAD_CSPI1_SS1__AUD4_TXD IOMUX_PAD(0x60c, 0x21c, 1, 0x08c8, 1, 0)
454#define _MX51_PAD_CSPI1_SS1__ECSPI1_SS1 IOMUX_PAD(0x60c, 0x21c, 0, 0x0000, 0, 0)
455#define _MX51_PAD_CSPI1_SS1__GPIO4_25 IOMUX_PAD(0x60c, 0x21c, 3, 0x0000, 0, 0)
456#define _MX51_PAD_CSPI1_RDY__AUD4_TXFS IOMUX_PAD(0x610, 0x220, 1, 0x08d0, 1, 0)
457#define _MX51_PAD_CSPI1_RDY__ECSPI1_RDY IOMUX_PAD(0x610, 0x220, 0, 0x0000, 0, 0)
458#define _MX51_PAD_CSPI1_RDY__GPIO4_26 IOMUX_PAD(0x610, 0x220, 3, 0x0000, 0, 0)
459#define _MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK IOMUX_PAD(0x614, 0x224, 0, 0x0000, 0, 0)
460#define _MX51_PAD_CSPI1_SCLK__GPIO4_27 IOMUX_PAD(0x614, 0x224, 3, 0x0000, 0, 0)
461#define _MX51_PAD_CSPI1_SCLK__I2C1_SCL IOMUX_PAD(0x614, 0x224, 0x11, 0x09b0, 1, 0)
462#define _MX51_PAD_UART1_RXD__GPIO4_28 IOMUX_PAD(0x618, 0x228, 3, 0x0000, 0, 0)
463#define _MX51_PAD_UART1_RXD__UART1_RXD IOMUX_PAD(0x618, 0x228, 0, 0x09e4, 0, 0)
464#define _MX51_PAD_UART1_TXD__GPIO4_29 IOMUX_PAD(0x61c, 0x22c, 3, 0x0000, 0, 0)
465#define _MX51_PAD_UART1_TXD__PWM2_PWMO IOMUX_PAD(0x61c, 0x22c, 1, 0x0000, 0, 0)
466#define _MX51_PAD_UART1_TXD__UART1_TXD IOMUX_PAD(0x61c, 0x22c, 0, 0x0000, 0, 0)
467#define _MX51_PAD_UART1_RTS__GPIO4_30 IOMUX_PAD(0x620, 0x230, 3, 0x0000, 0, 0)
468#define _MX51_PAD_UART1_RTS__UART1_RTS IOMUX_PAD(0x620, 0x230, 0, 0x09e0, 0, 0)
469#define _MX51_PAD_UART1_CTS__GPIO4_31 IOMUX_PAD(0x624, 0x234, 3, 0x0000, 0, 0)
470#define _MX51_PAD_UART1_CTS__UART1_CTS IOMUX_PAD(0x624, 0x234, 0, 0x0000, 0, 0)
471#define _MX51_PAD_UART2_RXD__FIRI_TXD IOMUX_PAD(0x628, 0x238, 1, 0x0000, 0, 0)
472#define _MX51_PAD_UART2_RXD__GPIO1_20 IOMUX_PAD(0x628, 0x238, 3, 0x0000, 0, 0)
473#define _MX51_PAD_UART2_RXD__UART2_RXD IOMUX_PAD(0x628, 0x238, 0, 0x09ec, 2, 0)
474#define _MX51_PAD_UART2_TXD__FIRI_RXD IOMUX_PAD(0x62c, 0x23c, 1, 0x0000, 0, 0)
475#define _MX51_PAD_UART2_TXD__GPIO1_21 IOMUX_PAD(0x62c, 0x23c, 3, 0x0000, 0, 0)
476#define _MX51_PAD_UART2_TXD__UART2_TXD IOMUX_PAD(0x62c, 0x23c, 0, 0x09ec, 3, 0)
477#define _MX51_PAD_UART3_RXD__CSI1_D0 IOMUX_PAD(0x630, 0x240, 2, 0x0000, 0, 0)
478#define _MX51_PAD_UART3_RXD__GPIO1_22 IOMUX_PAD(0x630, 0x240, 3, 0x0000, 0, 0)
479#define _MX51_PAD_UART3_RXD__UART1_DTR IOMUX_PAD(0x630, 0x240, 0, 0x0000, 0, 0)
480#define _MX51_PAD_UART3_RXD__UART3_RXD IOMUX_PAD(0x630, 0x240, 1, 0x09f4, 4, 0)
481#define _MX51_PAD_UART3_TXD__CSI1_D1 IOMUX_PAD(0x634, 0x244, 2, 0x0000, 0, 0)
482#define _MX51_PAD_UART3_TXD__GPIO1_23 IOMUX_PAD(0x634, 0x244, 3, 0x0000, 0, 0)
483#define _MX51_PAD_UART3_TXD__UART1_DSR IOMUX_PAD(0x634, 0x244, 0, 0x0000, 0, 0)
484#define _MX51_PAD_UART3_TXD__UART3_TXD IOMUX_PAD(0x634, 0x244, 1, 0x0000, 0, 0)
485#define _MX51_PAD_OWIRE_LINE__GPIO1_24 IOMUX_PAD(0x638, 0x248, 3, 0x0000, 0, 0)
486#define _MX51_PAD_OWIRE_LINE__OWIRE_LINE IOMUX_PAD(0x638, 0x248, 0, 0x0000, 0, 0)
487#define _MX51_PAD_OWIRE_LINE__SPDIF_OUT IOMUX_PAD(0x638, 0x248, 6, 0x0000, 0, 0)
488#define _MX51_PAD_KEY_ROW0__KEY_ROW0 IOMUX_PAD(0x63c, 0x24c, 0, 0x0000, 0, 0)
489#define _MX51_PAD_KEY_ROW1__KEY_ROW1 IOMUX_PAD(0x640, 0x250, 0, 0x0000, 0, 0)
490#define _MX51_PAD_KEY_ROW2__KEY_ROW2 IOMUX_PAD(0x644, 0x254, 0, 0x0000, 0, 0)
491#define _MX51_PAD_KEY_ROW3__KEY_ROW3 IOMUX_PAD(0x648, 0x258, 0, 0x0000, 0, 0)
492#define _MX51_PAD_KEY_COL0__KEY_COL0 IOMUX_PAD(0x64c, 0x25c, 0, 0x0000, 0, 0)
493#define _MX51_PAD_KEY_COL0__PLL1_BYP IOMUX_PAD(0x64c, 0x25c, 7, 0x090c, 0, 0)
494#define _MX51_PAD_KEY_COL1__KEY_COL1 IOMUX_PAD(0x650, 0x260, 0, 0x0000, 0, 0)
495#define _MX51_PAD_KEY_COL1__PLL2_BYP IOMUX_PAD(0x650, 0x260, 7, 0x0910, 0, 0)
496#define _MX51_PAD_KEY_COL2__KEY_COL2 IOMUX_PAD(0x654, 0x264, 0, 0x0000, 0, 0)
497#define _MX51_PAD_KEY_COL2__PLL3_BYP IOMUX_PAD(0x654, 0x264, 7, 0x0000, 0, 0)
498#define _MX51_PAD_KEY_COL3__KEY_COL3 IOMUX_PAD(0x658, 0x268, 0, 0x0000, 0, 0)
499#define _MX51_PAD_KEY_COL4__I2C2_SCL IOMUX_PAD(0x65c, 0x26c, 0x13, 0x09b8, 1, 0)
500#define _MX51_PAD_KEY_COL4__KEY_COL4 IOMUX_PAD(0x65c, 0x26c, 0, 0x0000, 0, 0)
501#define _MX51_PAD_KEY_COL4__SPDIF_OUT1 IOMUX_PAD(0x65c, 0x26c, 6, 0x0000, 0, 0)
502#define _MX51_PAD_KEY_COL4__UART1_RI IOMUX_PAD(0x65c, 0x26c, 1, 0x0000, 0, 0)
503#define _MX51_PAD_KEY_COL4__UART3_RTS IOMUX_PAD(0x65c, 0x26c, 2, 0x09f0, 4, 0)
504#define _MX51_PAD_KEY_COL5__I2C2_SDA IOMUX_PAD(0x660, 0x270, 0x13, 0x09bc, 1, 0)
505#define _MX51_PAD_KEY_COL5__KEY_COL5 IOMUX_PAD(0x660, 0x270, 0, 0x0000, 0, 0)
506#define _MX51_PAD_KEY_COL5__UART1_DCD IOMUX_PAD(0x660, 0x270, 1, 0x0000, 0, 0)
507#define _MX51_PAD_KEY_COL5__UART3_CTS IOMUX_PAD(0x660, 0x270, 2, 0x0000, 0, 0)
508#define _MX51_PAD_USBH1_CLK__CSPI_SCLK IOMUX_PAD(0x678, 0x278, 1, 0x0914, 1, 0)
509#define _MX51_PAD_USBH1_CLK__GPIO1_25 IOMUX_PAD(0x678, 0x278, 2, 0x0000, 0, 0)
510#define _MX51_PAD_USBH1_CLK__I2C2_SCL IOMUX_PAD(0x678, 0x278, 0x15, 0x09b8, 2, 0)
511#define _MX51_PAD_USBH1_CLK__USBH1_CLK IOMUX_PAD(0x678, 0x278, 0, 0x0000, 0, 0)
512#define _MX51_PAD_USBH1_DIR__CSPI_MOSI IOMUX_PAD(0x67c, 0x27c, 1, 0x091c, 1, 0)
513#define _MX51_PAD_USBH1_DIR__GPIO1_26 IOMUX_PAD(0x67c, 0x27c, 2, 0x0000, 0, 0)
514#define _MX51_PAD_USBH1_DIR__I2C2_SDA IOMUX_PAD(0x67c, 0x27c, 0x15, 0x09bc, 2, 0)
515#define _MX51_PAD_USBH1_DIR__USBH1_DIR IOMUX_PAD(0x67c, 0x27c, 0, 0x0000, 0, 0)
516#define _MX51_PAD_USBH1_STP__CSPI_RDY IOMUX_PAD(0x680, 0x280, 1, 0x0000, 0, 0)
517#define _MX51_PAD_USBH1_STP__GPIO1_27 IOMUX_PAD(0x680, 0x280, 2, 0x0000, 0, 0)
518#define _MX51_PAD_USBH1_STP__UART3_RXD IOMUX_PAD(0x680, 0x280, 5, 0x09f4, 6, 0)
519#define _MX51_PAD_USBH1_STP__USBH1_STP IOMUX_PAD(0x680, 0x280, 0, 0x0000, 0, 0)
520#define _MX51_PAD_USBH1_NXT__CSPI_MISO IOMUX_PAD(0x684, 0x284, 1, 0x0918, 0, 0)
521#define _MX51_PAD_USBH1_NXT__GPIO1_28 IOMUX_PAD(0x684, 0x284, 2, 0x0000, 0, 0)
522#define _MX51_PAD_USBH1_NXT__UART3_TXD IOMUX_PAD(0x684, 0x284, 5, 0x0000, 0, 0)
523#define _MX51_PAD_USBH1_NXT__USBH1_NXT IOMUX_PAD(0x684, 0x284, 0, 0x0000, 0, 0)
524#define _MX51_PAD_USBH1_DATA0__GPIO1_11 IOMUX_PAD(0x688, 0x288, 2, 0x0000, 0, 0)
525#define _MX51_PAD_USBH1_DATA0__UART2_CTS IOMUX_PAD(0x688, 0x288, 1, 0x0000, 0, 0)
526#define _MX51_PAD_USBH1_DATA0__USBH1_DATA0 IOMUX_PAD(0x688, 0x288, 0, 0x0000, 0, 0)
527#define _MX51_PAD_USBH1_DATA1__GPIO1_12 IOMUX_PAD(0x68c, 0x28c, 2, 0x0000, 0, 0)
528#define _MX51_PAD_USBH1_DATA1__UART2_RXD IOMUX_PAD(0x68c, 0x28c, 1, 0x09ec, 4, 0)
529#define _MX51_PAD_USBH1_DATA1__USBH1_DATA1 IOMUX_PAD(0x68c, 0x28c, 0, 0x0000, 0, 0)
530#define _MX51_PAD_USBH1_DATA2__GPIO1_13 IOMUX_PAD(0x690, 0x290, 2, 0x0000, 0, 0)
531#define _MX51_PAD_USBH1_DATA2__UART2_TXD IOMUX_PAD(0x690, 0x290, 1, 0x09ec, 5, 0)
532#define _MX51_PAD_USBH1_DATA2__USBH1_DATA2 IOMUX_PAD(0x690, 0x290, 0, 0x0000, 0, 0)
533#define _MX51_PAD_USBH1_DATA3__GPIO1_14 IOMUX_PAD(0x694, 0x294, 2, 0x0000, 0, 0)
534#define _MX51_PAD_USBH1_DATA3__UART2_RTS IOMUX_PAD(0x694, 0x294, 1, 0x09e8, 5, 0)
535#define _MX51_PAD_USBH1_DATA3__USBH1_DATA3 IOMUX_PAD(0x694, 0x294, 0, 0x0000, 0, 0)
536#define _MX51_PAD_USBH1_DATA4__CSPI_SS0 IOMUX_PAD(0x698, 0x298, 1, 0x0000, 0, 0)
537#define _MX51_PAD_USBH1_DATA4__GPIO1_15 IOMUX_PAD(0x698, 0x298, 2, 0x0000, 0, 0)
538#define _MX51_PAD_USBH1_DATA4__USBH1_DATA4 IOMUX_PAD(0x698, 0x298, 0, 0x0000, 0, 0)
539#define _MX51_PAD_USBH1_DATA5__CSPI_SS1 IOMUX_PAD(0x69c, 0x29c, 1, 0x0920, 0, 0)
540#define _MX51_PAD_USBH1_DATA5__GPIO1_16 IOMUX_PAD(0x69c, 0x29c, 2, 0x0000, 0, 0)
541#define _MX51_PAD_USBH1_DATA5__USBH1_DATA5 IOMUX_PAD(0x69c, 0x29c, 0, 0x0000, 0, 0)
542#define _MX51_PAD_USBH1_DATA6__CSPI_SS3 IOMUX_PAD(0x6a0, 0x2a0, 1, 0x0928, 1, 0)
543#define _MX51_PAD_USBH1_DATA6__GPIO1_17 IOMUX_PAD(0x6a0, 0x2a0, 2, 0x0000, 0, 0)
544#define _MX51_PAD_USBH1_DATA6__USBH1_DATA6 IOMUX_PAD(0x6a0, 0x2a0, 0, 0x0000, 0, 0)
545#define _MX51_PAD_USBH1_DATA7__ECSPI1_SS3 IOMUX_PAD(0x6a4, 0x2a4, 1, 0x0000, 0, 0)
546#define _MX51_PAD_USBH1_DATA7__ECSPI2_SS3 IOMUX_PAD(0x6a4, 0x2a4, 5, 0x0934, 1, 0)
547#define _MX51_PAD_USBH1_DATA7__GPIO1_18 IOMUX_PAD(0x6a4, 0x2a4, 2, 0x0000, 0, 0)
548#define _MX51_PAD_USBH1_DATA7__USBH1_DATA7 IOMUX_PAD(0x6a4, 0x2a4, 0, 0x0000, 0, 0)
549#define _MX51_PAD_DI1_PIN11__DI1_PIN11 IOMUX_PAD(0x6a8, 0x2a8, 0, 0x0000, 0, 0)
550#define _MX51_PAD_DI1_PIN11__ECSPI1_SS2 IOMUX_PAD(0x6a8, 0x2a8, 7, 0x0000, 0, 0)
551#define _MX51_PAD_DI1_PIN11__GPIO3_0 IOMUX_PAD(0x6a8, 0x2a8, 4, 0x0000, 0, 0)
552#define _MX51_PAD_DI1_PIN12__DI1_PIN12 IOMUX_PAD(0x6ac, 0x2ac, 0, 0x0000, 0, 0)
553#define _MX51_PAD_DI1_PIN12__GPIO3_1 IOMUX_PAD(0x6ac, 0x2ac, 4, 0x0978, 1, 0)
554#define _MX51_PAD_DI1_PIN13__DI1_PIN13 IOMUX_PAD(0x6b0, 0x2b0, 0, 0x0000, 0, 0)
555#define _MX51_PAD_DI1_PIN13__GPIO3_2 IOMUX_PAD(0x6b0, 0x2b0, 4, 0x097c, 1, 0)
556#define _MX51_PAD_DI1_D0_CS__DI1_D0_CS IOMUX_PAD(0x6b4, 0x2b4, 0, 0x0000, 0, 0)
557#define _MX51_PAD_DI1_D0_CS__GPIO3_3 IOMUX_PAD(0x6b4, 0x2b4, 4, 0x0980, 1, 0)
558#define _MX51_PAD_DI1_D1_CS__DI1_D1_CS IOMUX_PAD(0x6b8, 0x2b8, 0, 0x0000, 0, 0)
559#define _MX51_PAD_DI1_D1_CS__DISP1_PIN14 IOMUX_PAD(0x6b8, 0x2b8, 2, 0x0000, 0, 0)
560#define _MX51_PAD_DI1_D1_CS__DISP1_PIN5 IOMUX_PAD(0x6b8, 0x2b8, 3, 0x0000, 0, 0)
561#define _MX51_PAD_DI1_D1_CS__GPIO3_4 IOMUX_PAD(0x6b8, 0x2b8, 4, 0x0984, 1, 0)
562#define _MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 IOMUX_PAD(0x6bc, 0x2bc, 2, 0x09a4, 1, 0)
563#define _MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN IOMUX_PAD(0x6bc, 0x2bc, 0, 0x09c4, 0, 0)
564#define _MX51_PAD_DISPB2_SER_DIN__GPIO3_5 IOMUX_PAD(0x6bc, 0x2bc, 4, 0x0988, 1, 0)
565#define _MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 IOMUX_PAD(0x6c0, 0x2c0, 3, 0x0000, 0, 0)
566#define _MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO IOMUX_PAD(0x6c0, 0x2c0, 0, 0x09c4, 1, 0)
567#define _MX51_PAD_DISPB2_SER_DIO__GPIO3_6 IOMUX_PAD(0x6c0, 0x2c0, 4, 0x098c, 1, 0)
568#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 IOMUX_PAD(0x6c4, 0x2c4, 2, 0x0000, 0, 0)
569#define _MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 IOMUX_PAD(0x6c4, 0x2c4, 3, 0x0000, 0, 0)
570#define _MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK IOMUX_PAD(0x6c4, 0x2c4, 0, 0x0000, 0, 0)
571#define _MX51_PAD_DISPB2_SER_CLK__GPIO3_7 IOMUX_PAD(0x6c4, 0x2c4, 4, 0x0990, 1, 0)
572#define _MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0)
573#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 IOMUX_PAD(0x6c8, 0x2c8, 2, 0x0000, 0, 0)
574#define _MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 IOMUX_PAD(0x6c8, 0x2c8, 3, 0x0000, 0, 0)
575#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0)
576#define _MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS IOMUX_PAD(0x6c8, 0x2c8, 0, 0x0000, 0, 0)
577#define _MX51_PAD_DISPB2_SER_RS__GPIO3_8 IOMUX_PAD(0x6c8, 0x2c8, 4, 0x0994, 1, 0)
578#define _MX51_PAD_DISP1_DAT0__DISP1_DAT0 IOMUX_PAD(0x6cc, 0x2cc, 0, 0x0000, 0, 0)
579#define _MX51_PAD_DISP1_DAT1__DISP1_DAT1 IOMUX_PAD(0x6d0, 0x2d0, 0, 0x0000, 0, 0)
580#define _MX51_PAD_DISP1_DAT2__DISP1_DAT2 IOMUX_PAD(0x6d4, 0x2d4, 0, 0x0000, 0, 0)
581#define _MX51_PAD_DISP1_DAT3__DISP1_DAT3 IOMUX_PAD(0x6d8, 0x2d8, 0, 0x0000, 0, 0)
582#define _MX51_PAD_DISP1_DAT4__DISP1_DAT4 IOMUX_PAD(0x6dc, 0x2dc, 0, 0x0000, 0, 0)
583#define _MX51_PAD_DISP1_DAT5__DISP1_DAT5 IOMUX_PAD(0x6e0, 0x2e0, 0, 0x0000, 0, 0)
584#define _MX51_PAD_DISP1_DAT6__BOOT_USB_SRC IOMUX_PAD(0x6e4, 0x2e4, 7, 0x0000, 0, 0)
585#define _MX51_PAD_DISP1_DAT6__DISP1_DAT6 IOMUX_PAD(0x6e4, 0x2e4, 0, 0x0000, 0, 0)
586#define _MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG IOMUX_PAD(0x6e8, 0x2e8, 7, 0x0000, 0, 0)
587#define _MX51_PAD_DISP1_DAT7__DISP1_DAT7 IOMUX_PAD(0x6e8, 0x2e8, 0, 0x0000, 0, 0)
588#define _MX51_PAD_DISP1_DAT8__BOOT_SRC0 IOMUX_PAD(0x6ec, 0x2ec, 7, 0x0000, 0, 0)
589#define _MX51_PAD_DISP1_DAT8__DISP1_DAT8 IOMUX_PAD(0x6ec, 0x2ec, 0, 0x0000, 0, 0)
590#define _MX51_PAD_DISP1_DAT9__BOOT_SRC1 IOMUX_PAD(0x6f0, 0x2f0, 7, 0x0000, 0, 0)
591#define _MX51_PAD_DISP1_DAT9__DISP1_DAT9 IOMUX_PAD(0x6f0, 0x2f0, 0, 0x0000, 0, 0)
592#define _MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE IOMUX_PAD(0x6f4, 0x2f4, 7, 0x0000, 0, 0)
593#define _MX51_PAD_DISP1_DAT10__DISP1_DAT10 IOMUX_PAD(0x6f4, 0x2f4, 0, 0x0000, 0, 0)
594#define _MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 IOMUX_PAD(0x6f8, 0x2f8, 7, 0x0000, 0, 0)
595#define _MX51_PAD_DISP1_DAT11__DISP1_DAT11 IOMUX_PAD(0x6f8, 0x2f8, 0, 0x0000, 0, 0)
596#define _MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL IOMUX_PAD(0x6fc, 0x2fc, 7, 0x0000, 0, 0)
597#define _MX51_PAD_DISP1_DAT12__DISP1_DAT12 IOMUX_PAD(0x6fc, 0x2fc, 0, 0x0000, 0, 0)
598#define _MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 IOMUX_PAD(0x700, 0x300, 7, 0x0000, 0, 0)
599#define _MX51_PAD_DISP1_DAT13__DISP1_DAT13 IOMUX_PAD(0x700, 0x300, 0, 0x0000, 0, 0)
600#define _MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 IOMUX_PAD(0x704, 0x304, 7, 0x0000, 0, 0)
601#define _MX51_PAD_DISP1_DAT14__DISP1_DAT14 IOMUX_PAD(0x704, 0x304, 0, 0x0000, 0, 0)
602#define _MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH IOMUX_PAD(0x708, 0x308, 7, 0x0000, 0, 0)
603#define _MX51_PAD_DISP1_DAT15__DISP1_DAT15 IOMUX_PAD(0x708, 0x308, 0, 0x0000, 0, 0)
604#define _MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 IOMUX_PAD(0x70c, 0x30c, 7, 0x0000, 0, 0)
605#define _MX51_PAD_DISP1_DAT16__DISP1_DAT16 IOMUX_PAD(0x70c, 0x30c, 0, 0x0000, 0, 0)
606#define _MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 IOMUX_PAD(0x710, 0x310, 7, 0x0000, 0, 0)
607#define _MX51_PAD_DISP1_DAT17__DISP1_DAT17 IOMUX_PAD(0x710, 0x310, 0, 0x0000, 0, 0)
608#define _MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 IOMUX_PAD(0x714, 0x314, 7, 0x0000, 0, 0)
609#define _MX51_PAD_DISP1_DAT18__DISP1_DAT18 IOMUX_PAD(0x714, 0x314, 0, 0x0000, 0, 0)
610#define _MX51_PAD_DISP1_DAT18__DISP2_PIN11 IOMUX_PAD(0x714, 0x314, 5, 0x0000, 0, 0)
611#define _MX51_PAD_DISP1_DAT18__DISP2_PIN5 IOMUX_PAD(0x714, 0x314, 4, 0x0000, 0, 0)
612#define _MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 IOMUX_PAD(0x718, 0x318, 7, 0x0000, 0, 0)
613#define _MX51_PAD_DISP1_DAT19__DISP1_DAT19 IOMUX_PAD(0x718, 0x318, 0, 0x0000, 0, 0)
614#define _MX51_PAD_DISP1_DAT19__DISP2_PIN12 IOMUX_PAD(0x718, 0x318, 5, 0x0000, 0, 0)
615#define _MX51_PAD_DISP1_DAT19__DISP2_PIN6 IOMUX_PAD(0x718, 0x318, 4, 0x0000, 0, 0)
616#define _MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 IOMUX_PAD(0x71c, 0x31c, 7, 0x0000, 0, 0)
617#define _MX51_PAD_DISP1_DAT20__DISP1_DAT20 IOMUX_PAD(0x71c, 0x31c, 0, 0x0000, 0, 0)
618#define _MX51_PAD_DISP1_DAT20__DISP2_PIN13 IOMUX_PAD(0x71c, 0x31c, 5, 0x0000, 0, 0)
619#define _MX51_PAD_DISP1_DAT20__DISP2_PIN7 IOMUX_PAD(0x71c, 0x31c, 4, 0x0000, 0, 0)
620#define _MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 IOMUX_PAD(0x720, 0x320, 7, 0x0000, 0, 0)
621#define _MX51_PAD_DISP1_DAT21__DISP1_DAT21 IOMUX_PAD(0x720, 0x320, 0, 0x0000, 0, 0)
622#define _MX51_PAD_DISP1_DAT21__DISP2_PIN14 IOMUX_PAD(0x720, 0x320, 5, 0x0000, 0, 0)
623#define _MX51_PAD_DISP1_DAT21__DISP2_PIN8 IOMUX_PAD(0x720, 0x320, 4, 0x0000, 0, 0)
624#define _MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 IOMUX_PAD(0x724, 0x324, 7, 0x0000, 0, 0)
625#define _MX51_PAD_DISP1_DAT22__DISP1_DAT22 IOMUX_PAD(0x724, 0x324, 0, 0x0000, 0, 0)
626#define _MX51_PAD_DISP1_DAT22__DISP2_D0_CS IOMUX_PAD(0x724, 0x324, 6, 0x0000, 0, 0)
627#define _MX51_PAD_DISP1_DAT22__DISP2_DAT16 IOMUX_PAD(0x724, 0x324, 5, 0x0000, 0, 0)
628#define _MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 IOMUX_PAD(0x728, 0x328, 7, 0x0000, 0, 0)
629#define _MX51_PAD_DISP1_DAT23__DISP1_DAT23 IOMUX_PAD(0x728, 0x328, 0, 0x0000, 0, 0)
630#define _MX51_PAD_DISP1_DAT23__DISP2_D1_CS IOMUX_PAD(0x728, 0x328, 6, 0x0000, 0, 0)
631#define _MX51_PAD_DISP1_DAT23__DISP2_DAT17 IOMUX_PAD(0x728, 0x328, 5, 0x0000, 0, 0)
632#define _MX51_PAD_DISP1_DAT23__DISP2_SER_CS IOMUX_PAD(0x728, 0x328, 4, 0x0000, 0, 0)
633#define _MX51_PAD_DI1_PIN3__DI1_PIN3 IOMUX_PAD(0x72c, 0x32c, 0, 0x0000, 0, 0)
634#define _MX51_PAD_DI1_PIN2__DI1_PIN2 IOMUX_PAD(0x734, 0x330, 0, 0x0000, 0, 0)
635#define _MX51_PAD_DI_GP2__DISP1_SER_CLK IOMUX_PAD(0x740, 0x338, 0, 0x0000, 0, 0)
636#define _MX51_PAD_DI_GP2__DISP2_WAIT IOMUX_PAD(0x740, 0x338, 2, 0x09a8, 1, 0)
637#define _MX51_PAD_DI_GP3__CSI1_DATA_EN IOMUX_PAD(0x744, 0x33c, 3, 0x09a0, 1, 0)
638#define _MX51_PAD_DI_GP3__DISP1_SER_DIO IOMUX_PAD(0x744, 0x33c, 0, 0x09c0, 0, 0)
639#define _MX51_PAD_DI_GP3__FEC_TX_ER IOMUX_PAD(0x744, 0x33c, 2, 0x0000, 0, 0)
640#define _MX51_PAD_DI2_PIN4__CSI2_DATA_EN IOMUX_PAD(0x748, 0x340, 3, 0x099c, 1, 0)
641#define _MX51_PAD_DI2_PIN4__DI2_PIN4 IOMUX_PAD(0x748, 0x340, 0, 0x0000, 0, 0)
642#define _MX51_PAD_DI2_PIN4__FEC_CRS IOMUX_PAD(0x748, 0x340, 2, 0x0950, 1, 0)
643#define _MX51_PAD_DI2_PIN2__DI2_PIN2 IOMUX_PAD(0x74c, 0x344, 0, 0x0000, 0, 0)
644#define _MX51_PAD_DI2_PIN2__FEC_MDC IOMUX_PAD(0x74c, 0x344, 2, 0x0000, 0, 0)
645#define _MX51_PAD_DI2_PIN3__DI2_PIN3 IOMUX_PAD(0x750, 0x348, 0, 0x0000, 0, 0)
646#define _MX51_PAD_DI2_PIN3__FEC_MDIO IOMUX_PAD(0x750, 0x348, 2, 0x0954, 1, 0)
647#define _MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK IOMUX_PAD(0x754, 0x34c, 0, 0x0000, 0, 0)
648#define _MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 IOMUX_PAD(0x754, 0x34c, 2, 0x095c, 1, 0)
649#define _MX51_PAD_DI_GP4__DI2_PIN15 IOMUX_PAD(0x758, 0x350, 4, 0x0000, 0, 0)
650#define _MX51_PAD_DI_GP4__DISP1_SER_DIN IOMUX_PAD(0x758, 0x350, 0, 0x09c0, 1, 0)
651#define _MX51_PAD_DI_GP4__DISP2_PIN1 IOMUX_PAD(0x758, 0x350, 3, 0x0000, 0, 0)
652#define _MX51_PAD_DI_GP4__FEC_RDATA2 IOMUX_PAD(0x758, 0x350, 2, 0x0960, 1, 0)
653#define _MX51_PAD_DISP2_DAT0__DISP2_DAT0 IOMUX_PAD(0x75c, 0x354, 0, 0x0000, 0, 0)
654#define _MX51_PAD_DISP2_DAT0__FEC_RDATA3 IOMUX_PAD(0x75c, 0x354, 2, 0x0964, 1, 0)
655#define _MX51_PAD_DISP2_DAT0__KEY_COL6 IOMUX_PAD(0x75c, 0x354, 4, 0x09c8, 1, 0)
656#define _MX51_PAD_DISP2_DAT0__UART3_RXD IOMUX_PAD(0x75c, 0x354, 5, 0x09f4, 8, 0)
657#define _MX51_PAD_DISP2_DAT0__USBH3_CLK IOMUX_PAD(0x75c, 0x354, 3, 0x09f8, 1, 0)
658#define _MX51_PAD_DISP2_DAT1__DISP2_DAT1 IOMUX_PAD(0x760, 0x358, 0, 0x0000, 0, 0)
659#define _MX51_PAD_DISP2_DAT1__FEC_RX_ER IOMUX_PAD(0x760, 0x358, 2, 0x0970, 1, 0)
660#define _MX51_PAD_DISP2_DAT1__KEY_COL7 IOMUX_PAD(0x760, 0x358, 4, 0x09cc, 1, 0)
661#define _MX51_PAD_DISP2_DAT1__UART3_TXD IOMUX_PAD(0x760, 0x358, 5, 0x0000, 0, 0)
662#define _MX51_PAD_DISP2_DAT1__USBH3_DIR IOMUX_PAD(0x760, 0x358, 3, 0x0a1c, 1, 0)
663#define _MX51_PAD_DISP2_DAT2__DISP2_DAT2 IOMUX_PAD(0x764, 0x35c, 0, 0x0000, 0, 0)
664#define _MX51_PAD_DISP2_DAT3__DISP2_DAT3 IOMUX_PAD(0x768, 0x360, 0, 0x0000, 0, 0)
665#define _MX51_PAD_DISP2_DAT4__DISP2_DAT4 IOMUX_PAD(0x76c, 0x364, 0, 0x0000, 0, 0)
666#define _MX51_PAD_DISP2_DAT5__DISP2_DAT5 IOMUX_PAD(0x770, 0x368, 0, 0x0000, 0, 0)
667#define _MX51_PAD_DISP2_DAT6__DISP2_DAT6 IOMUX_PAD(0x774, 0x36c, 0, 0x0000, 0, 0)
668#define _MX51_PAD_DISP2_DAT6__FEC_TDATA1 IOMUX_PAD(0x774, 0x36c, 2, 0x0000, 0, 0)
669#define _MX51_PAD_DISP2_DAT6__GPIO1_19 IOMUX_PAD(0x774, 0x36c, 5, 0x0000, 0, 0)
670#define _MX51_PAD_DISP2_DAT6__KEY_ROW4 IOMUX_PAD(0x774, 0x36c, 4, 0x09d0, 1, 0)
671#define _MX51_PAD_DISP2_DAT6__USBH3_STP IOMUX_PAD(0x774, 0x36c, 3, 0x0a24, 1, 0)
672#define _MX51_PAD_DISP2_DAT7__DISP2_DAT7 IOMUX_PAD(0x778, 0x370, 0, 0x0000, 0, 0)
673#define _MX51_PAD_DISP2_DAT7__FEC_TDATA2 IOMUX_PAD(0x778, 0x370, 2, 0x0000, 0, 0)
674#define _MX51_PAD_DISP2_DAT7__GPIO1_29 IOMUX_PAD(0x778, 0x370, 5, 0x0000, 0, 0)
675#define _MX51_PAD_DISP2_DAT7__KEY_ROW5 IOMUX_PAD(0x778, 0x370, 4, 0x09d4, 1, 0)
676#define _MX51_PAD_DISP2_DAT7__USBH3_NXT IOMUX_PAD(0x778, 0x370, 3, 0x0a20, 1, 0)
677#define _MX51_PAD_DISP2_DAT8__DISP2_DAT8 IOMUX_PAD(0x77c, 0x374, 0, 0x0000, 0, 0)
678#define _MX51_PAD_DISP2_DAT8__FEC_TDATA3 IOMUX_PAD(0x77c, 0x374, 2, 0x0000, 0, 0)
679#define _MX51_PAD_DISP2_DAT8__GPIO1_30 IOMUX_PAD(0x77c, 0x374, 5, 0x0000, 0, 0)
680#define _MX51_PAD_DISP2_DAT8__KEY_ROW6 IOMUX_PAD(0x77c, 0x374, 4, 0x09d8, 1, 0)
681#define _MX51_PAD_DISP2_DAT8__USBH3_DATA0 IOMUX_PAD(0x77c, 0x374, 3, 0x09fc, 1, 0)
682#define _MX51_PAD_DISP2_DAT9__AUD6_RXC IOMUX_PAD(0x780, 0x378, 4, 0x08f4, 1, 0)
683#define _MX51_PAD_DISP2_DAT9__DISP2_DAT9 IOMUX_PAD(0x780, 0x378, 0, 0x0000, 0, 0)
684#define _MX51_PAD_DISP2_DAT9__FEC_TX_EN IOMUX_PAD(0x780, 0x378, 2, 0x0000, 0, 0)
685#define _MX51_PAD_DISP2_DAT9__GPIO1_31 IOMUX_PAD(0x780, 0x378, 5, 0x0000, 0, 0)
686#define _MX51_PAD_DISP2_DAT9__USBH3_DATA1 IOMUX_PAD(0x780, 0x378, 3, 0x0a00, 1, 0)
687#define _MX51_PAD_DISP2_DAT10__DISP2_DAT10 IOMUX_PAD(0x784, 0x37c, 0, 0x0000, 0, 0)
688#define _MX51_PAD_DISP2_DAT10__DISP2_SER_CS IOMUX_PAD(0x784, 0x37c, 5, 0x0000, 0, 0)
689#define _MX51_PAD_DISP2_DAT10__FEC_COL IOMUX_PAD(0x784, 0x37c, 2, 0x094c, 1, 0)
690#define _MX51_PAD_DISP2_DAT10__KEY_ROW7 IOMUX_PAD(0x784, 0x37c, 4, 0x09dc, 1, 0)
691#define _MX51_PAD_DISP2_DAT10__USBH3_DATA2 IOMUX_PAD(0x784, 0x37c, 3, 0x0a04, 1, 0)
692#define _MX51_PAD_DISP2_DAT11__AUD6_TXD IOMUX_PAD(0x788, 0x380, 4, 0x08f0, 1, 0)
693#define _MX51_PAD_DISP2_DAT11__DISP2_DAT11 IOMUX_PAD(0x788, 0x380, 0, 0x0000, 0, 0)
694#define _MX51_PAD_DISP2_DAT11__FEC_RX_CLK IOMUX_PAD(0x788, 0x380, 2, 0x0968, 1, 0)
695#define _MX51_PAD_DISP2_DAT11__GPIO1_10 IOMUX_PAD(0x788, 0x380, 7, 0x0000, 0, 0)
696#define _MX51_PAD_DISP2_DAT11__USBH3_DATA3 IOMUX_PAD(0x788, 0x380, 3, 0x0a08, 1, 0)
697#define _MX51_PAD_DISP2_DAT12__AUD6_RXD IOMUX_PAD(0x78c, 0x384, 4, 0x08ec, 1, 0)
698#define _MX51_PAD_DISP2_DAT12__DISP2_DAT12 IOMUX_PAD(0x78c, 0x384, 0, 0x0000, 0, 0)
699#define _MX51_PAD_DISP2_DAT12__FEC_RX_DV IOMUX_PAD(0x78c, 0x384, 2, 0x096c, 1, 0)
700#define _MX51_PAD_DISP2_DAT12__USBH3_DATA4 IOMUX_PAD(0x78c, 0x384, 3, 0x0a0c, 1, 0)
701#define _MX51_PAD_DISP2_DAT13__AUD6_TXC IOMUX_PAD(0x790, 0x388, 4, 0x08fc, 1, 0)
702#define _MX51_PAD_DISP2_DAT13__DISP2_DAT13 IOMUX_PAD(0x790, 0x388, 0, 0x0000, 0, 0)
703#define _MX51_PAD_DISP2_DAT13__FEC_TX_CLK IOMUX_PAD(0x790, 0x388, 2, 0x0974, 1, 0)
704#define _MX51_PAD_DISP2_DAT13__USBH3_DATA5 IOMUX_PAD(0x790, 0x388, 3, 0x0a10, 1, 0)
705#define _MX51_PAD_DISP2_DAT14__AUD6_TXFS IOMUX_PAD(0x794, 0x38c, 4, 0x0900, 1, 0)
706#define _MX51_PAD_DISP2_DAT14__DISP2_DAT14 IOMUX_PAD(0x794, 0x38c, 0, 0x0000, 0, 0)
707#define _MX51_PAD_DISP2_DAT14__FEC_RDATA0 IOMUX_PAD(0x794, 0x38c, 2, 0x0958, 1, 0)
708#define _MX51_PAD_DISP2_DAT14__USBH3_DATA6 IOMUX_PAD(0x794, 0x38c, 3, 0x0a14, 1, 0)
709#define _MX51_PAD_DISP2_DAT15__AUD6_RXFS IOMUX_PAD(0x798, 0x390, 4, 0x08f8, 1, 0)
710#define _MX51_PAD_DISP2_DAT15__DISP1_SER_CS IOMUX_PAD(0x798, 0x390, 5, 0x0000, 0, 0)
711#define _MX51_PAD_DISP2_DAT15__DISP2_DAT15 IOMUX_PAD(0x798, 0x390, 0, 0x0000, 0, 0)
712#define _MX51_PAD_DISP2_DAT15__FEC_TDATA0 IOMUX_PAD(0x798, 0x390, 2, 0x0000, 0, 0)
713#define _MX51_PAD_DISP2_DAT15__USBH3_DATA7 IOMUX_PAD(0x798, 0x390, 3, 0x0a18, 1, 0)
714#define _MX51_PAD_SD1_CMD__AUD5_RXFS IOMUX_PAD(0x79c, 0x394, 1, 0x08e0, 1, 0)
715#define _MX51_PAD_SD1_CMD__CSPI_MOSI IOMUX_PAD(0x79c, 0x394, 2, 0x091c, 2, 0)
716#define _MX51_PAD_SD1_CMD__SD1_CMD IOMUX_PAD(0x79c, 0x394, 0x10, 0x0000, 0, 0)
717#define _MX51_PAD_SD1_CLK__AUD5_RXC IOMUX_PAD(0x7a0, 0x398, 1, 0x08dc, 1, 0)
718#define _MX51_PAD_SD1_CLK__CSPI_SCLK IOMUX_PAD(0x7a0, 0x398, 2, 0x0914, 2, 0)
719#define _MX51_PAD_SD1_CLK__SD1_CLK IOMUX_PAD(0x7a0, 0x398, 0x10, 0x0000, 0, 0)
720#define _MX51_PAD_SD1_DATA0__AUD5_TXD IOMUX_PAD(0x7a4, 0x39c, 1, 0x08d8, 2, 0)
721#define _MX51_PAD_SD1_DATA0__CSPI_MISO IOMUX_PAD(0x7a4, 0x39c, 2, 0x0918, 1, 0)
722#define _MX51_PAD_SD1_DATA0__SD1_DATA0 IOMUX_PAD(0x7a4, 0x39c, 0x10, 0x0000, 0, 0)
723#define _MX51_PAD_EIM_DA0__EIM_DA0 IOMUX_PAD(0x000, 0x01c, 0, 0x0000, 0, 0)
724#define _MX51_PAD_EIM_DA1__EIM_DA1 IOMUX_PAD(0x000, 0x020, 0, 0x0000, 0, 0)
725#define _MX51_PAD_EIM_DA2__EIM_DA2 IOMUX_PAD(0x000, 0x024, 0, 0x0000, 0, 0)
726#define _MX51_PAD_EIM_DA3__EIM_DA3 IOMUX_PAD(0x000, 0x028, 0, 0x0000, 0, 0)
727#define _MX51_PAD_SD1_DATA1__AUD5_RXD IOMUX_PAD(0x7a8, 0x3a0, 1, 0x08d4, 2, 0)
728#define _MX51_PAD_SD1_DATA1__SD1_DATA1 IOMUX_PAD(0x7a8, 0x3a0, 0x10, 0x0000, 0, 0)
729#define _MX51_PAD_EIM_DA4__EIM_DA4 IOMUX_PAD(0x000, 0x02c, 0, 0x0000, 0, 0)
730#define _MX51_PAD_EIM_DA5__EIM_DA5 IOMUX_PAD(0x000, 0x030, 0, 0x0000, 0, 0)
731#define _MX51_PAD_EIM_DA6__EIM_DA6 IOMUX_PAD(0x000, 0x034, 0, 0x0000, 0, 0)
732#define _MX51_PAD_EIM_DA7__EIM_DA7 IOMUX_PAD(0x000, 0x038, 0, 0x0000, 0, 0)
733#define _MX51_PAD_SD1_DATA2__AUD5_TXC IOMUX_PAD(0x7ac, 0x3a4, 1, 0x08e4, 2, 0)
734#define _MX51_PAD_SD1_DATA2__SD1_DATA2 IOMUX_PAD(0x7ac, 0x3a4, 0x10, 0x0000, 0, 0)
735#define _MX51_PAD_EIM_DA10__EIM_DA10 IOMUX_PAD(0x000, 0x044, 0, 0x0000, 0, 0)
736#define _MX51_PAD_EIM_DA11__EIM_DA11 IOMUX_PAD(0x000, 0x048, 0, 0x0000, 0, 0)
737#define _MX51_PAD_EIM_DA8__EIM_DA8 IOMUX_PAD(0x000, 0x03c, 0, 0x0000, 0, 0)
738#define _MX51_PAD_EIM_DA9__EIM_DA9 IOMUX_PAD(0x000, 0x040, 0, 0x0000, 0, 0)
739#define _MX51_PAD_SD1_DATA3__AUD5_TXFS IOMUX_PAD(0x7b0, 0x3a8, 1, 0x08e8, 2, 0)
740#define _MX51_PAD_SD1_DATA3__CSPI_SS1 IOMUX_PAD(0x7b0, 0x3a8, 2, 0x0920, 1, 0)
741#define _MX51_PAD_SD1_DATA3__SD1_DATA3 IOMUX_PAD(0x7b0, 0x3a8, 0x10, 0x0000, 0, 0)
742#define _MX51_PAD_GPIO1_0__CSPI_SS2 IOMUX_PAD(0x7b4, 0x3ac, 2, 0x0924, 0, 0)
743#define _MX51_PAD_GPIO1_0__GPIO1_0 IOMUX_PAD(0x7b4, 0x3ac, 1, 0x0000, 0, 0)
744#define _MX51_PAD_GPIO1_0__SD1_CD IOMUX_PAD(0x7b4, 0x3ac, 0, 0x0000, 0, 0)
745#define _MX51_PAD_GPIO1_1__CSPI_MISO IOMUX_PAD(0x7b8, 0x3b0, 2, 0x0918, 2, 0)
746#define _MX51_PAD_GPIO1_1__GPIO1_1 IOMUX_PAD(0x7b8, 0x3b0, 1, 0x0000, 0, 0)
747#define _MX51_PAD_GPIO1_1__SD1_WP IOMUX_PAD(0x7b8, 0x3b0, 0, 0x0000, 0, 0)
748#define _MX51_PAD_EIM_DA12__EIM_DA12 IOMUX_PAD(0x000, 0x04c, 0, 0x0000, 0, 0)
749#define _MX51_PAD_EIM_DA13__EIM_DA13 IOMUX_PAD(0x000, 0x050, 0, 0x0000, 0, 0)
750#define _MX51_PAD_EIM_DA14__EIM_DA14 IOMUX_PAD(0x000, 0x054, 0, 0x0000, 0, 0)
751#define _MX51_PAD_EIM_DA15__EIM_DA15 IOMUX_PAD(0x000, 0x058, 0, 0x0000, 0, 0)
752#define _MX51_PAD_SD2_CMD__CSPI_MOSI IOMUX_PAD(0x000, 0x3b4, 2, 0x091c, 3, 0)
753#define _MX51_PAD_SD2_CMD__I2C1_SCL IOMUX_PAD(0x7bc, 0x3b4, 0x11, 0x09b0, 2, 0)
754#define _MX51_PAD_SD2_CMD__SD2_CMD IOMUX_PAD(0x7bc, 0x3b4, 0x10, 0x0000, 0, 0)
755#define _MX51_PAD_SD2_CLK__CSPI_SCLK IOMUX_PAD(0x7c0, 0x3b8, 2, 0x0914, 3, 0)
756#define _MX51_PAD_SD2_CLK__I2C1_SDA IOMUX_PAD(0x7c0, 0x3b8, 0x11, 0x09b4, 2, 0)
757#define _MX51_PAD_SD2_CLK__SD2_CLK IOMUX_PAD(0x7c0, 0x3b8, 0x10, 0x0000, 0, 0)
758#define _MX51_PAD_SD2_DATA0__CSPI_MISO IOMUX_PAD(0x7c4, 0x3bc, 2, 0x0918, 3, 0)
759#define _MX51_PAD_SD2_DATA0__SD1_DAT4 IOMUX_PAD(0x7c4, 0x3bc, 1, 0x0000, 0, 0)
760#define _MX51_PAD_SD2_DATA0__SD2_DATA0 IOMUX_PAD(0x7c4, 0x3bc, 0x10, 0x0000, 0, 0)
761#define _MX51_PAD_SD2_DATA1__SD1_DAT5 IOMUX_PAD(0x7c8, 0x3c0, 1, 0x0000, 0, 0)
762#define _MX51_PAD_SD2_DATA1__SD2_DATA1 IOMUX_PAD(0x7c8, 0x3c0, 0x10, 0x0000, 0, 0)
763#define _MX51_PAD_SD2_DATA1__USBH3_H2_DP IOMUX_PAD(0x7c8, 0x3c0, 2, 0x0000, 0, 0)
764#define _MX51_PAD_SD2_DATA2__SD1_DAT6 IOMUX_PAD(0x7cc, 0x3c4, 1, 0x0000, 0, 0)
765#define _MX51_PAD_SD2_DATA2__SD2_DATA2 IOMUX_PAD(0x7cc, 0x3c4, 0x10, 0x0000, 0, 0)
766#define _MX51_PAD_SD2_DATA2__USBH3_H2_DM IOMUX_PAD(0x7cc, 0x3c4, 2, 0x0000, 0, 0)
767#define _MX51_PAD_SD2_DATA3__CSPI_SS2 IOMUX_PAD(0x7d0, 0x3c8, 2, 0x0924, 1, 0)
768#define _MX51_PAD_SD2_DATA3__SD1_DAT7 IOMUX_PAD(0x7d0, 0x3c8, 1, 0x0000, 0, 0)
769#define _MX51_PAD_SD2_DATA3__SD2_DATA3 IOMUX_PAD(0x7d0, 0x3c8, 0x10, 0x0000, 0, 0)
770#define _MX51_PAD_GPIO1_2__CCM_OUT_2 IOMUX_PAD(0x7d4, 0x3cc, 5, 0x0000, 0, 0)
771#define _MX51_PAD_GPIO1_2__GPIO1_2 IOMUX_PAD(0x7d4, 0x3cc, 0, 0x0000, 0, 0)
772#define _MX51_PAD_GPIO1_2__I2C2_SCL IOMUX_PAD(0x7d4, 0x3cc, 0x12, 0x09b8, 3, 0)
773#define _MX51_PAD_GPIO1_2__PLL1_BYP IOMUX_PAD(0x7d4, 0x3cc, 7, 0x090c, 1, 0)
774#define _MX51_PAD_GPIO1_2__PWM1_PWMO IOMUX_PAD(0x7d4, 0x3cc, 1, 0x0000, 0, 0)
775#define _MX51_PAD_GPIO1_3__GPIO1_3 IOMUX_PAD(0x7d8, 0x3d0, 0, 0x0000, 0, 0)
776#define _MX51_PAD_GPIO1_3__I2C2_SDA IOMUX_PAD(0x7d8, 0x3d0, 0x12, 0x09bc, 3, 0)
777#define _MX51_PAD_GPIO1_3__PLL2_BYP IOMUX_PAD(0x7d8, 0x3d0, 7, 0x0910, 1, 0)
778#define _MX51_PAD_GPIO1_3__PWM2_PWMO IOMUX_PAD(0x7d8, 0x3d0, 1, 0x0000, 0, 0)
779#define _MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ IOMUX_PAD(0x7fc, 0x3d4, 0, 0x0000, 0, 0)
780#define _MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B IOMUX_PAD(0x7fc, 0x3d4, 1, 0x0000, 0, 0)
781#define _MX51_PAD_GPIO1_4__DISP2_EXT_CLK IOMUX_PAD(0x804, 0x3d8, 4, 0x0908, 1, 0)
782#define _MX51_PAD_GPIO1_4__EIM_RDY IOMUX_PAD(0x804, 0x3d8, 3, 0x0938, 1, 0)
783#define _MX51_PAD_GPIO1_4__GPIO1_4 IOMUX_PAD(0x804, 0x3d8, 0, 0x0000, 0, 0)
784#define _MX51_PAD_GPIO1_4__WDOG1_WDOG_B IOMUX_PAD(0x804, 0x3d8, 2, 0x0000, 0, 0)
785#define _MX51_PAD_GPIO1_5__CSI2_MCLK IOMUX_PAD(0x808, 0x3dc, 6, 0x0000, 0, 0)
786#define _MX51_PAD_GPIO1_5__DISP2_PIN16 IOMUX_PAD(0x808, 0x3dc, 3, 0x0000, 0, 0)
787#define _MX51_PAD_GPIO1_5__GPIO1_5 IOMUX_PAD(0x808, 0x3dc, 0, 0x0000, 0, 0)
788#define _MX51_PAD_GPIO1_5__WDOG2_WDOG_B IOMUX_PAD(0x808, 0x3dc, 2, 0x0000, 0, 0)
789#define _MX51_PAD_GPIO1_6__DISP2_PIN17 IOMUX_PAD(0x80c, 0x3e0, 4, 0x0000, 0, 0)
790#define _MX51_PAD_GPIO1_6__GPIO1_6 IOMUX_PAD(0x80c, 0x3e0, 0, 0x0000, 0, 0)
791#define _MX51_PAD_GPIO1_6__REF_EN_B IOMUX_PAD(0x80c, 0x3e0, 3, 0x0000, 0, 0)
792#define _MX51_PAD_GPIO1_7__CCM_OUT_0 IOMUX_PAD(0x810, 0x3e4, 3, 0x0000, 0, 0)
793#define _MX51_PAD_GPIO1_7__GPIO1_7 IOMUX_PAD(0x810, 0x3e4, 0, 0x0000, 0, 0)
794#define _MX51_PAD_GPIO1_7__SD2_WP IOMUX_PAD(0x810, 0x3e4, 6, 0x0000, 0, 0)
795#define _MX51_PAD_GPIO1_7__SPDIF_OUT1 IOMUX_PAD(0x810, 0x3e4, 2, 0x0000, 0, 0)
796#define _MX51_PAD_GPIO1_8__CSI2_DATA_EN IOMUX_PAD(0x814, 0x3e8, 2, 0x099c, 2, 0)
797#define _MX51_PAD_GPIO1_8__GPIO1_8 IOMUX_PAD(0x814, 0x3e8, 0, 0x0000, 0, 0)
798#define _MX51_PAD_GPIO1_8__SD2_CD IOMUX_PAD(0x814, 0x3e8, 6, 0x0000, 0, 0)
799#define _MX51_PAD_GPIO1_8__USBH3_PWR IOMUX_PAD(0x814, 0x3e8, 1, 0x0000, 0, 0)
800#define _MX51_PAD_GPIO1_9__CCM_OUT_1 IOMUX_PAD(0x818, 0x3ec, 3, 0x0000, 0, 0)
801#define _MX51_PAD_GPIO1_9__DISP2_D1_CS IOMUX_PAD(0x818, 0x3ec, 2, 0x0000, 0, 0)
802#define _MX51_PAD_GPIO1_9__DISP2_SER_CS IOMUX_PAD(0x818, 0x3ec, 7, 0x0000, 0, 0)
803#define _MX51_PAD_GPIO1_9__GPIO1_9 IOMUX_PAD(0x818, 0x3ec, 0, 0x0000, 0, 0)
804#define _MX51_PAD_GPIO1_9__SD2_LCTL IOMUX_PAD(0x818, 0x3ec, 6, 0x0000, 0, 0)
805#define _MX51_PAD_GPIO1_9__USBH3_OC IOMUX_PAD(0x818, 0x3ec, 1, 0x0000, 0, 0)
806
807/* The same pins as above but with the default pad control values applied */
808#define MX51_PAD_EIM_D16__AUD4_RXFS (_MX51_PAD_EIM_D16__AUD4_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
809#define MX51_PAD_EIM_D16__AUD5_TXD (_MX51_PAD_EIM_D16__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
810#define MX51_PAD_EIM_D16__EIM_D16 (_MX51_PAD_EIM_D16__EIM_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
811#define MX51_PAD_EIM_D16__GPIO2_0 (_MX51_PAD_EIM_D16__GPIO2_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
812#define MX51_PAD_EIM_D16__I2C1_SDA (_MX51_PAD_EIM_D16__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
813#define MX51_PAD_EIM_D16__UART2_CTS (_MX51_PAD_EIM_D16__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
814#define MX51_PAD_EIM_D16__USBH2_DATA0 (_MX51_PAD_EIM_D16__USBH2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
815#define MX51_PAD_EIM_D17__AUD5_RXD (_MX51_PAD_EIM_D17__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
816#define MX51_PAD_EIM_D17__EIM_D17 (_MX51_PAD_EIM_D17__EIM_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
817#define MX51_PAD_EIM_D17__GPIO2_1 (_MX51_PAD_EIM_D17__GPIO2_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
818#define MX51_PAD_EIM_D17__UART2_RXD (_MX51_PAD_EIM_D17__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
819#define MX51_PAD_EIM_D17__UART3_CTS (_MX51_PAD_EIM_D17__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
820#define MX51_PAD_EIM_D17__USBH2_DATA1 (_MX51_PAD_EIM_D17__USBH2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
821#define MX51_PAD_EIM_D18__AUD5_TXC (_MX51_PAD_EIM_D18__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
822#define MX51_PAD_EIM_D18__EIM_D18 (_MX51_PAD_EIM_D18__EIM_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
823#define MX51_PAD_EIM_D18__GPIO2_2 (_MX51_PAD_EIM_D18__GPIO2_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
824#define MX51_PAD_EIM_D18__UART2_TXD (_MX51_PAD_EIM_D18__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
825#define MX51_PAD_EIM_D18__UART3_RTS (_MX51_PAD_EIM_D18__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
826#define MX51_PAD_EIM_D18__USBH2_DATA2 (_MX51_PAD_EIM_D18__USBH2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
827#define MX51_PAD_EIM_D19__AUD4_RXC (_MX51_PAD_EIM_D19__AUD4_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
828#define MX51_PAD_EIM_D19__AUD5_TXFS (_MX51_PAD_EIM_D19__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
829#define MX51_PAD_EIM_D19__EIM_D19 (_MX51_PAD_EIM_D19__EIM_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
830#define MX51_PAD_EIM_D19__GPIO2_3 (_MX51_PAD_EIM_D19__GPIO2_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
831#define MX51_PAD_EIM_D19__I2C1_SCL (_MX51_PAD_EIM_D19__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
832#define MX51_PAD_EIM_D19__UART2_RTS (_MX51_PAD_EIM_D19__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
833#define MX51_PAD_EIM_D19__USBH2_DATA3 (_MX51_PAD_EIM_D19__USBH2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
834#define MX51_PAD_EIM_D20__AUD4_TXD (_MX51_PAD_EIM_D20__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
835#define MX51_PAD_EIM_D20__EIM_D20 (_MX51_PAD_EIM_D20__EIM_D20 | MUX_PAD_CTRL(NO_PAD_CTRL))
836#define MX51_PAD_EIM_D20__GPIO2_4 (_MX51_PAD_EIM_D20__GPIO2_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
837#define MX51_PAD_EIM_D20__SRTC_ALARM_DEB (_MX51_PAD_EIM_D20__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
838#define MX51_PAD_EIM_D20__USBH2_DATA4 (_MX51_PAD_EIM_D20__USBH2_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
839#define MX51_PAD_EIM_D21__AUD4_RXD (_MX51_PAD_EIM_D21__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
840#define MX51_PAD_EIM_D21__EIM_D21 (_MX51_PAD_EIM_D21__EIM_D21 | MUX_PAD_CTRL(NO_PAD_CTRL))
841#define MX51_PAD_EIM_D21__GPIO2_5 (_MX51_PAD_EIM_D21__GPIO2_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
842#define MX51_PAD_EIM_D21__SRTC_ALARM_DEB (_MX51_PAD_EIM_D21__SRTC_ALARM_DEB | MUX_PAD_CTRL(NO_PAD_CTRL))
843#define MX51_PAD_EIM_D21__USBH2_DATA5 (_MX51_PAD_EIM_D21__USBH2_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
844#define MX51_PAD_EIM_D22__AUD4_TXC (_MX51_PAD_EIM_D22__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
845#define MX51_PAD_EIM_D22__EIM_D22 (_MX51_PAD_EIM_D22__EIM_D22 | MUX_PAD_CTRL(NO_PAD_CTRL))
846#define MX51_PAD_EIM_D22__GPIO2_6 (_MX51_PAD_EIM_D22__GPIO2_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
847#define MX51_PAD_EIM_D22__USBH2_DATA6 (_MX51_PAD_EIM_D22__USBH2_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
848#define MX51_PAD_EIM_D23__AUD4_TXFS (_MX51_PAD_EIM_D23__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
849#define MX51_PAD_EIM_D23__EIM_D23 (_MX51_PAD_EIM_D23__EIM_D23 | MUX_PAD_CTRL(NO_PAD_CTRL))
850#define MX51_PAD_EIM_D23__GPIO2_7 (_MX51_PAD_EIM_D23__GPIO2_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
851#define MX51_PAD_EIM_D23__SPDIF_OUT1 (_MX51_PAD_EIM_D23__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
852#define MX51_PAD_EIM_D23__USBH2_DATA7 (_MX51_PAD_EIM_D23__USBH2_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
853#define MX51_PAD_EIM_D24__AUD6_RXFS (_MX51_PAD_EIM_D24__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
854#define MX51_PAD_EIM_D24__EIM_D24 (_MX51_PAD_EIM_D24__EIM_D24 | MUX_PAD_CTRL(NO_PAD_CTRL))
855#define MX51_PAD_EIM_D24__GPIO2_8 (_MX51_PAD_EIM_D24__GPIO2_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
856#define MX51_PAD_EIM_D24__I2C2_SDA (_MX51_PAD_EIM_D24__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
857#define MX51_PAD_EIM_D24__UART3_CTS (_MX51_PAD_EIM_D24__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
858#define MX51_PAD_EIM_D24__USBOTG_DATA0 (_MX51_PAD_EIM_D24__USBOTG_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
859#define MX51_PAD_EIM_D25__EIM_D25 (_MX51_PAD_EIM_D25__EIM_D25 | MUX_PAD_CTRL(NO_PAD_CTRL))
860#define MX51_PAD_EIM_D25__KEY_COL6 (_MX51_PAD_EIM_D25__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL))
861#define MX51_PAD_EIM_D25__UART2_CTS (_MX51_PAD_EIM_D25__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
862#define MX51_PAD_EIM_D25__UART3_RXD (_MX51_PAD_EIM_D25__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
863#define MX51_PAD_EIM_D25__USBOTG_DATA1 (_MX51_PAD_EIM_D25__USBOTG_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
864#define MX51_PAD_EIM_D26__EIM_D26 (_MX51_PAD_EIM_D26__EIM_D26 | MUX_PAD_CTRL(NO_PAD_CTRL))
865#define MX51_PAD_EIM_D26__KEY_COL7 (_MX51_PAD_EIM_D26__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL))
866#define MX51_PAD_EIM_D26__UART2_RTS (_MX51_PAD_EIM_D26__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
867#define MX51_PAD_EIM_D26__UART3_TXD (_MX51_PAD_EIM_D26__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
868#define MX51_PAD_EIM_D26__USBOTG_DATA2 (_MX51_PAD_EIM_D26__USBOTG_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
869#define MX51_PAD_EIM_D27__AUD6_RXC (_MX51_PAD_EIM_D27__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
870#define MX51_PAD_EIM_D27__EIM_D27 (_MX51_PAD_EIM_D27__EIM_D27 | MUX_PAD_CTRL(NO_PAD_CTRL))
871#define MX51_PAD_EIM_D27__GPIO2_9 (_MX51_PAD_EIM_D27__GPIO2_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
872#define MX51_PAD_EIM_D27__I2C2_SCL (_MX51_PAD_EIM_D27__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
873#define MX51_PAD_EIM_D27__UART3_RTS (_MX51_PAD_EIM_D27__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
874#define MX51_PAD_EIM_D27__USBOTG_DATA3 (_MX51_PAD_EIM_D27__USBOTG_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
875#define MX51_PAD_EIM_D28__AUD6_TXD (_MX51_PAD_EIM_D28__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
876#define MX51_PAD_EIM_D28__EIM_D28 (_MX51_PAD_EIM_D28__EIM_D28 | MUX_PAD_CTRL(NO_PAD_CTRL))
877#define MX51_PAD_EIM_D28__KEY_ROW4 (_MX51_PAD_EIM_D28__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL))
878#define MX51_PAD_EIM_D28__USBOTG_DATA4 (_MX51_PAD_EIM_D28__USBOTG_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
879#define MX51_PAD_EIM_D29__AUD6_RXD (_MX51_PAD_EIM_D29__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
880#define MX51_PAD_EIM_D29__EIM_D29 (_MX51_PAD_EIM_D29__EIM_D29 | MUX_PAD_CTRL(NO_PAD_CTRL))
881#define MX51_PAD_EIM_D29__KEY_ROW5 (_MX51_PAD_EIM_D29__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL))
882#define MX51_PAD_EIM_D29__USBOTG_DATA5 (_MX51_PAD_EIM_D29__USBOTG_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
883#define MX51_PAD_EIM_D30__AUD6_TXC (_MX51_PAD_EIM_D30__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
884#define MX51_PAD_EIM_D30__EIM_D30 (_MX51_PAD_EIM_D30__EIM_D30 | MUX_PAD_CTRL(NO_PAD_CTRL))
885#define MX51_PAD_EIM_D30__KEY_ROW6 (_MX51_PAD_EIM_D30__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL))
886#define MX51_PAD_EIM_D30__USBOTG_DATA6 (_MX51_PAD_EIM_D30__USBOTG_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
887#define MX51_PAD_EIM_D31__AUD6_TXFS (_MX51_PAD_EIM_D31__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
888#define MX51_PAD_EIM_D31__EIM_D31 (_MX51_PAD_EIM_D31__EIM_D31 | MUX_PAD_CTRL(NO_PAD_CTRL))
889#define MX51_PAD_EIM_D31__KEY_ROW7 (_MX51_PAD_EIM_D31__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL))
890#define MX51_PAD_EIM_D31__USBOTG_DATA7 (_MX51_PAD_EIM_D31__USBOTG_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
891#define MX51_PAD_EIM_A16__EIM_A16 (_MX51_PAD_EIM_A16__EIM_A16 | MUX_PAD_CTRL(NO_PAD_CTRL))
892#define MX51_PAD_EIM_A16__GPIO2_10 (_MX51_PAD_EIM_A16__GPIO2_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
893#define MX51_PAD_EIM_A16__OSC_FREQ_SEL0 (_MX51_PAD_EIM_A16__OSC_FREQ_SEL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
894#define MX51_PAD_EIM_A17__EIM_A17 (_MX51_PAD_EIM_A17__EIM_A17 | MUX_PAD_CTRL(NO_PAD_CTRL))
895#define MX51_PAD_EIM_A17__GPIO2_11 (_MX51_PAD_EIM_A17__GPIO2_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
896#define MX51_PAD_EIM_A17__OSC_FREQ_SEL1 (_MX51_PAD_EIM_A17__OSC_FREQ_SEL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
897#define MX51_PAD_EIM_A18__BOOT_LPB0 (_MX51_PAD_EIM_A18__BOOT_LPB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
898#define MX51_PAD_EIM_A18__EIM_A18 (_MX51_PAD_EIM_A18__EIM_A18 | MUX_PAD_CTRL(NO_PAD_CTRL))
899#define MX51_PAD_EIM_A18__GPIO2_12 (_MX51_PAD_EIM_A18__GPIO2_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
900#define MX51_PAD_EIM_A19__BOOT_LPB1 (_MX51_PAD_EIM_A19__BOOT_LPB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
901#define MX51_PAD_EIM_A19__EIM_A19 (_MX51_PAD_EIM_A19__EIM_A19 | MUX_PAD_CTRL(NO_PAD_CTRL))
902#define MX51_PAD_EIM_A19__GPIO2_13 (_MX51_PAD_EIM_A19__GPIO2_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
903#define MX51_PAD_EIM_A20__BOOT_UART_SRC0 (_MX51_PAD_EIM_A20__BOOT_UART_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL))
904#define MX51_PAD_EIM_A20__EIM_A20 (_MX51_PAD_EIM_A20__EIM_A20 | MUX_PAD_CTRL(NO_PAD_CTRL))
905#define MX51_PAD_EIM_A20__GPIO2_14 (_MX51_PAD_EIM_A20__GPIO2_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
906#define MX51_PAD_EIM_A21__BOOT_UART_SRC1 (_MX51_PAD_EIM_A21__BOOT_UART_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL))
907#define MX51_PAD_EIM_A21__EIM_A21 (_MX51_PAD_EIM_A21__EIM_A21 | MUX_PAD_CTRL(NO_PAD_CTRL))
908#define MX51_PAD_EIM_A21__GPIO2_15 (_MX51_PAD_EIM_A21__GPIO2_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
909#define MX51_PAD_EIM_A22__EIM_A22 (_MX51_PAD_EIM_A22__EIM_A22 | MUX_PAD_CTRL(NO_PAD_CTRL))
910#define MX51_PAD_EIM_A22__GPIO2_16 (_MX51_PAD_EIM_A22__GPIO2_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
911#define MX51_PAD_EIM_A23__BOOT_HPN_EN (_MX51_PAD_EIM_A23__BOOT_HPN_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
912#define MX51_PAD_EIM_A23__EIM_A23 (_MX51_PAD_EIM_A23__EIM_A23 | MUX_PAD_CTRL(NO_PAD_CTRL))
913#define MX51_PAD_EIM_A23__GPIO2_17 (_MX51_PAD_EIM_A23__GPIO2_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
914#define MX51_PAD_EIM_A24__EIM_A24 (_MX51_PAD_EIM_A24__EIM_A24 | MUX_PAD_CTRL(NO_PAD_CTRL))
915#define MX51_PAD_EIM_A24__GPIO2_18 (_MX51_PAD_EIM_A24__GPIO2_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
916#define MX51_PAD_EIM_A24__USBH2_CLK (_MX51_PAD_EIM_A24__USBH2_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
917#define MX51_PAD_EIM_A25__DISP1_PIN4 (_MX51_PAD_EIM_A25__DISP1_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
918#define MX51_PAD_EIM_A25__EIM_A25 (_MX51_PAD_EIM_A25__EIM_A25 | MUX_PAD_CTRL(NO_PAD_CTRL))
919#define MX51_PAD_EIM_A25__GPIO2_19 (_MX51_PAD_EIM_A25__GPIO2_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
920#define MX51_PAD_EIM_A25__USBH2_DIR (_MX51_PAD_EIM_A25__USBH2_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
921#define MX51_PAD_EIM_A26__CSI1_DATA_EN (_MX51_PAD_EIM_A26__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
922#define MX51_PAD_EIM_A26__DISP2_EXT_CLK (_MX51_PAD_EIM_A26__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
923#define MX51_PAD_EIM_A26__EIM_A26 (_MX51_PAD_EIM_A26__EIM_A26 | MUX_PAD_CTRL(NO_PAD_CTRL))
924#define MX51_PAD_EIM_A26__GPIO2_20 (_MX51_PAD_EIM_A26__GPIO2_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
925#define MX51_PAD_EIM_A26__USBH2_STP (_MX51_PAD_EIM_A26__USBH2_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
926#define MX51_PAD_EIM_A27__CSI2_DATA_EN (_MX51_PAD_EIM_A27__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
927#define MX51_PAD_EIM_A27__DISP1_PIN1 (_MX51_PAD_EIM_A27__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
928#define MX51_PAD_EIM_A27__EIM_A27 (_MX51_PAD_EIM_A27__EIM_A27 | MUX_PAD_CTRL(NO_PAD_CTRL))
929#define MX51_PAD_EIM_A27__GPIO2_21 (_MX51_PAD_EIM_A27__GPIO2_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
930#define MX51_PAD_EIM_A27__USBH2_NXT (_MX51_PAD_EIM_A27__USBH2_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
931#define MX51_PAD_EIM_EB0__EIM_EB0 (_MX51_PAD_EIM_EB0__EIM_EB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
932#define MX51_PAD_EIM_EB1__EIM_EB1 (_MX51_PAD_EIM_EB1__EIM_EB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
933#define MX51_PAD_EIM_EB2__AUD5_RXFS (_MX51_PAD_EIM_EB2__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
934#define MX51_PAD_EIM_EB2__CSI1_D2 (_MX51_PAD_EIM_EB2__CSI1_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
935#define MX51_PAD_EIM_EB2__EIM_EB2 (_MX51_PAD_EIM_EB2__EIM_EB2 | MUX_PAD_CTRL(NO_PAD_CTRL))
936#define MX51_PAD_EIM_EB2__FEC_MDIO (_MX51_PAD_EIM_EB2__FEC_MDIO | \
937 MUX_PAD_CTRL(PAD_CTL_PUS_22K_UP | PAD_CTL_PKE | PAD_CTL_SRE_FAST | \
938 PAD_CTL_DSE_HIGH | PAD_CTL_PUE | PAD_CTL_HYS))
939#define MX51_PAD_EIM_EB2__GPIO2_22 (_MX51_PAD_EIM_EB2__GPIO2_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
940#define MX51_PAD_EIM_EB2__GPT_CMPOUT1 (_MX51_PAD_EIM_EB2__GPT_CMPOUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
941#define MX51_PAD_EIM_EB3__AUD5_RXC (_MX51_PAD_EIM_EB3__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
942#define MX51_PAD_EIM_EB3__CSI1_D3 (_MX51_PAD_EIM_EB3__CSI1_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
943#define MX51_PAD_EIM_EB3__EIM_EB3 (_MX51_PAD_EIM_EB3__EIM_EB3 | MUX_PAD_CTRL(NO_PAD_CTRL))
944#define MX51_PAD_EIM_EB3__FEC_RDATA1 (_MX51_PAD_EIM_EB3__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
945#define MX51_PAD_EIM_EB3__GPIO2_23 (_MX51_PAD_EIM_EB3__GPIO2_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
946#define MX51_PAD_EIM_EB3__GPT_CMPOUT2 (_MX51_PAD_EIM_EB3__GPT_CMPOUT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
947#define MX51_PAD_EIM_OE__EIM_OE (_MX51_PAD_EIM_OE__EIM_OE | MUX_PAD_CTRL(NO_PAD_CTRL))
948#define MX51_PAD_EIM_OE__GPIO2_24 (_MX51_PAD_EIM_OE__GPIO2_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
949#define MX51_PAD_EIM_CS0__EIM_CS0 (_MX51_PAD_EIM_CS0__EIM_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
950#define MX51_PAD_EIM_CS0__GPIO2_25 (_MX51_PAD_EIM_CS0__GPIO2_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
951#define MX51_PAD_EIM_CS1__EIM_CS1 (_MX51_PAD_EIM_CS1__EIM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
952#define MX51_PAD_EIM_CS1__GPIO2_26 (_MX51_PAD_EIM_CS1__GPIO2_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
953#define MX51_PAD_EIM_CS2__AUD5_TXD (_MX51_PAD_EIM_CS2__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
954#define MX51_PAD_EIM_CS2__CSI1_D4 (_MX51_PAD_EIM_CS2__CSI1_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
955#define MX51_PAD_EIM_CS2__EIM_CS2 (_MX51_PAD_EIM_CS2__EIM_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
956#define MX51_PAD_EIM_CS2__FEC_RDATA2 (_MX51_PAD_EIM_CS2__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
957#define MX51_PAD_EIM_CS2__GPIO2_27 (_MX51_PAD_EIM_CS2__GPIO2_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
958#define MX51_PAD_EIM_CS2__USBOTG_STP (_MX51_PAD_EIM_CS2__USBOTG_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
959#define MX51_PAD_EIM_CS3__AUD5_RXD (_MX51_PAD_EIM_CS3__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
960#define MX51_PAD_EIM_CS3__CSI1_D5 (_MX51_PAD_EIM_CS3__CSI1_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
961#define MX51_PAD_EIM_CS3__EIM_CS3 (_MX51_PAD_EIM_CS3__EIM_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
962#define MX51_PAD_EIM_CS3__FEC_RDATA3 (_MX51_PAD_EIM_CS3__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
963#define MX51_PAD_EIM_CS3__GPIO2_28 (_MX51_PAD_EIM_CS3__GPIO2_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
964#define MX51_PAD_EIM_CS3__USBOTG_NXT (_MX51_PAD_EIM_CS3__USBOTG_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
965#define MX51_PAD_EIM_CS4__AUD5_TXC (_MX51_PAD_EIM_CS4__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
966#define MX51_PAD_EIM_CS4__CSI1_D6 (_MX51_PAD_EIM_CS4__CSI1_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
967#define MX51_PAD_EIM_CS4__EIM_CS4 (_MX51_PAD_EIM_CS4__EIM_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
968#define MX51_PAD_EIM_CS4__FEC_RX_ER (_MX51_PAD_EIM_CS4__FEC_RX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
969#define MX51_PAD_EIM_CS4__GPIO2_29 (_MX51_PAD_EIM_CS4__GPIO2_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
970#define MX51_PAD_EIM_CS4__USBOTG_CLK (_MX51_PAD_EIM_CS4__USBOTG_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
971#define MX51_PAD_EIM_CS5__AUD5_TXFS (_MX51_PAD_EIM_CS5__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
972#define MX51_PAD_EIM_CS5__CSI1_D7 (_MX51_PAD_EIM_CS5__CSI1_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
973#define MX51_PAD_EIM_CS5__DISP1_EXT_CLK (_MX51_PAD_EIM_CS5__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
974#define MX51_PAD_EIM_CS5__EIM_CS5 (_MX51_PAD_EIM_CS5__EIM_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
975#define MX51_PAD_EIM_CS5__FEC_CRS (_MX51_PAD_EIM_CS5__FEC_CRS | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
976#define MX51_PAD_EIM_CS5__GPIO2_30 (_MX51_PAD_EIM_CS5__GPIO2_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
977#define MX51_PAD_EIM_CS5__USBOTG_DIR (_MX51_PAD_EIM_CS5__USBOTG_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
978#define MX51_PAD_EIM_DTACK__EIM_DTACK (_MX51_PAD_EIM_DTACK__EIM_DTACK | MUX_PAD_CTRL(NO_PAD_CTRL))
979#define MX51_PAD_EIM_DTACK__GPIO2_31 (_MX51_PAD_EIM_DTACK__GPIO2_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
980#define MX51_PAD_EIM_LBA__EIM_LBA (_MX51_PAD_EIM_LBA__EIM_LBA | MUX_PAD_CTRL(NO_PAD_CTRL))
981#define MX51_PAD_EIM_LBA__GPIO3_1 (_MX51_PAD_EIM_LBA__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
982#define MX51_PAD_EIM_CRE__EIM_CRE (_MX51_PAD_EIM_CRE__EIM_CRE | MUX_PAD_CTRL(NO_PAD_CTRL))
983#define MX51_PAD_EIM_CRE__GPIO3_2 (_MX51_PAD_EIM_CRE__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
984#define MX51_PAD_DRAM_CS1__DRAM_CS1 (_MX51_PAD_DRAM_CS1__DRAM_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
985#define MX51_PAD_NANDF_WE_B__GPIO3_3 (_MX51_PAD_NANDF_WE_B__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
986#define MX51_PAD_NANDF_WE_B__NANDF_WE_B (_MX51_PAD_NANDF_WE_B__NANDF_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
987#define MX51_PAD_NANDF_WE_B__PATA_DIOW (_MX51_PAD_NANDF_WE_B__PATA_DIOW | MUX_PAD_CTRL(NO_PAD_CTRL))
988#define MX51_PAD_NANDF_WE_B__SD3_DATA0 (_MX51_PAD_NANDF_WE_B__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
989#define MX51_PAD_NANDF_RE_B__GPIO3_4 (_MX51_PAD_NANDF_RE_B__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
990#define MX51_PAD_NANDF_RE_B__NANDF_RE_B (_MX51_PAD_NANDF_RE_B__NANDF_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL))
991#define MX51_PAD_NANDF_RE_B__PATA_DIOR (_MX51_PAD_NANDF_RE_B__PATA_DIOR | MUX_PAD_CTRL(NO_PAD_CTRL))
992#define MX51_PAD_NANDF_RE_B__SD3_DATA1 (_MX51_PAD_NANDF_RE_B__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
993#define MX51_PAD_NANDF_ALE__GPIO3_5 (_MX51_PAD_NANDF_ALE__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
994#define MX51_PAD_NANDF_ALE__NANDF_ALE (_MX51_PAD_NANDF_ALE__NANDF_ALE | MUX_PAD_CTRL(NO_PAD_CTRL))
995#define MX51_PAD_NANDF_ALE__PATA_BUFFER_EN (_MX51_PAD_NANDF_ALE__PATA_BUFFER_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
996#define MX51_PAD_NANDF_CLE__GPIO3_6 (_MX51_PAD_NANDF_CLE__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
997#define MX51_PAD_NANDF_CLE__NANDF_CLE (_MX51_PAD_NANDF_CLE__NANDF_CLE | MUX_PAD_CTRL(NO_PAD_CTRL))
998#define MX51_PAD_NANDF_CLE__PATA_RESET_B (_MX51_PAD_NANDF_CLE__PATA_RESET_B | MUX_PAD_CTRL(NO_PAD_CTRL))
999#define MX51_PAD_NANDF_WP_B__GPIO3_7 (_MX51_PAD_NANDF_WP_B__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1000#define MX51_PAD_NANDF_WP_B__NANDF_WP_B (_MX51_PAD_NANDF_WP_B__NANDF_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1001#define MX51_PAD_NANDF_WP_B__PATA_DMACK (_MX51_PAD_NANDF_WP_B__PATA_DMACK | MUX_PAD_CTRL(NO_PAD_CTRL))
1002#define MX51_PAD_NANDF_WP_B__SD3_DATA2 (_MX51_PAD_NANDF_WP_B__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1003#define MX51_PAD_NANDF_RB0__ECSPI2_SS1 (_MX51_PAD_NANDF_RB0__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1004#define MX51_PAD_NANDF_RB0__GPIO3_8 (_MX51_PAD_NANDF_RB0__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1005#define MX51_PAD_NANDF_RB0__NANDF_RB0 (_MX51_PAD_NANDF_RB0__NANDF_RB0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1006#define MX51_PAD_NANDF_RB0__PATA_DMARQ (_MX51_PAD_NANDF_RB0__PATA_DMARQ | MUX_PAD_CTRL(NO_PAD_CTRL))
1007#define MX51_PAD_NANDF_RB0__SD3_DATA3 (_MX51_PAD_NANDF_RB0__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1008#define MX51_PAD_NANDF_RB1__CSPI_MOSI (_MX51_PAD_NANDF_RB1__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1009#define MX51_PAD_NANDF_RB1__ECSPI2_RDY (_MX51_PAD_NANDF_RB1__ECSPI2_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1010#define MX51_PAD_NANDF_RB1__GPIO3_9 (_MX51_PAD_NANDF_RB1__GPIO3_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1011#define MX51_PAD_NANDF_RB1__NANDF_RB1 (_MX51_PAD_NANDF_RB1__NANDF_RB1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1012#define MX51_PAD_NANDF_RB1__PATA_IORDY (_MX51_PAD_NANDF_RB1__PATA_IORDY | MUX_PAD_CTRL(NO_PAD_CTRL))
1013#define MX51_PAD_NANDF_RB1__SD4_CMD (_MX51_PAD_NANDF_RB1__SD4_CMD | MUX_PAD_CTRL(NO_PAD_CTRL))
1014#define MX51_PAD_NANDF_RB2__DISP2_WAIT (_MX51_PAD_NANDF_RB2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
1015#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK (_MX51_PAD_NANDF_RB2__ECSPI2_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1016#define MX51_PAD_NANDF_RB2__FEC_COL (_MX51_PAD_NANDF_RB2__FEC_COL | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
1017#define MX51_PAD_NANDF_RB2__GPIO3_10 (_MX51_PAD_NANDF_RB2__GPIO3_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1018#define MX51_PAD_NANDF_RB2__NANDF_RB2 (_MX51_PAD_NANDF_RB2__NANDF_RB2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1019#define MX51_PAD_NANDF_RB2__USBH3_H3_DP (_MX51_PAD_NANDF_RB2__USBH3_H3_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1020#define MX51_PAD_NANDF_RB2__USBH3_NXT (_MX51_PAD_NANDF_RB2__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
1021#define MX51_PAD_NANDF_RB3__DISP1_WAIT (_MX51_PAD_NANDF_RB3__DISP1_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
1022#define MX51_PAD_NANDF_RB3__ECSPI2_MISO (_MX51_PAD_NANDF_RB3__ECSPI2_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1023#define MX51_PAD_NANDF_RB3__FEC_RX_CLK (_MX51_PAD_NANDF_RB3__FEC_RX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_2))
1024#define MX51_PAD_NANDF_RB3__GPIO3_11 (_MX51_PAD_NANDF_RB3__GPIO3_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1025#define MX51_PAD_NANDF_RB3__NANDF_RB3 (_MX51_PAD_NANDF_RB3__NANDF_RB3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1026#define MX51_PAD_NANDF_RB3__USBH3_CLK (_MX51_PAD_NANDF_RB3__USBH3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1027#define MX51_PAD_NANDF_RB3__USBH3_H3_DM (_MX51_PAD_NANDF_RB3__USBH3_H3_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1028#define MX51_PAD_GPIO_NAND__GPIO_NAND (_MX51_PAD_GPIO_NAND__GPIO_NAND | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1029#define MX51_PAD_GPIO_NAND__PATA_INTRQ (_MX51_PAD_GPIO_NAND__PATA_INTRQ | MUX_PAD_CTRL(NO_PAD_CTRL))
1030#define MX51_PAD_NANDF_CS0__GPIO3_16 (_MX51_PAD_NANDF_CS0__GPIO3_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1031#define MX51_PAD_NANDF_CS0__NANDF_CS0 (_MX51_PAD_NANDF_CS0__NANDF_CS0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1032#define MX51_PAD_NANDF_CS1__GPIO3_17 (_MX51_PAD_NANDF_CS1__GPIO3_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1033#define MX51_PAD_NANDF_CS1__NANDF_CS1 (_MX51_PAD_NANDF_CS1__NANDF_CS1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1034#define MX51_PAD_NANDF_CS2__CSPI_SCLK (_MX51_PAD_NANDF_CS2__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1035#define MX51_PAD_NANDF_CS2__FEC_TX_ER (_MX51_PAD_NANDF_CS2__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1036#define MX51_PAD_NANDF_CS2__GPIO3_18 (_MX51_PAD_NANDF_CS2__GPIO3_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1037#define MX51_PAD_NANDF_CS2__NANDF_CS2 (_MX51_PAD_NANDF_CS2__NANDF_CS2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1038#define MX51_PAD_NANDF_CS2__PATA_CS_0 (_MX51_PAD_NANDF_CS2__PATA_CS_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1039#define MX51_PAD_NANDF_CS2__SD4_CLK (_MX51_PAD_NANDF_CS2__SD4_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1040#define MX51_PAD_NANDF_CS2__USBH3_H1_DP (_MX51_PAD_NANDF_CS2__USBH3_H1_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1041#define MX51_PAD_NANDF_CS3__FEC_MDC (_MX51_PAD_NANDF_CS3__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1042#define MX51_PAD_NANDF_CS3__GPIO3_19 (_MX51_PAD_NANDF_CS3__GPIO3_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1043#define MX51_PAD_NANDF_CS3__NANDF_CS3 (_MX51_PAD_NANDF_CS3__NANDF_CS3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1044#define MX51_PAD_NANDF_CS3__PATA_CS_1 (_MX51_PAD_NANDF_CS3__PATA_CS_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1045#define MX51_PAD_NANDF_CS3__SD4_DAT0 (_MX51_PAD_NANDF_CS3__SD4_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1046#define MX51_PAD_NANDF_CS3__USBH3_H1_DM (_MX51_PAD_NANDF_CS3__USBH3_H1_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1047#define MX51_PAD_NANDF_CS4__FEC_TDATA1 (_MX51_PAD_NANDF_CS4__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1048#define MX51_PAD_NANDF_CS4__GPIO3_20 (_MX51_PAD_NANDF_CS4__GPIO3_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1049#define MX51_PAD_NANDF_CS4__NANDF_CS4 (_MX51_PAD_NANDF_CS4__NANDF_CS4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1050#define MX51_PAD_NANDF_CS4__PATA_DA_0 (_MX51_PAD_NANDF_CS4__PATA_DA_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1051#define MX51_PAD_NANDF_CS4__SD4_DAT1 (_MX51_PAD_NANDF_CS4__SD4_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1052#define MX51_PAD_NANDF_CS4__USBH3_STP (_MX51_PAD_NANDF_CS4__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
1053#define MX51_PAD_NANDF_CS5__FEC_TDATA2 (_MX51_PAD_NANDF_CS5__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1054#define MX51_PAD_NANDF_CS5__GPIO3_21 (_MX51_PAD_NANDF_CS5__GPIO3_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1055#define MX51_PAD_NANDF_CS5__NANDF_CS5 (_MX51_PAD_NANDF_CS5__NANDF_CS5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1056#define MX51_PAD_NANDF_CS5__PATA_DA_1 (_MX51_PAD_NANDF_CS5__PATA_DA_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1057#define MX51_PAD_NANDF_CS5__SD4_DAT2 (_MX51_PAD_NANDF_CS5__SD4_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1058#define MX51_PAD_NANDF_CS5__USBH3_DIR (_MX51_PAD_NANDF_CS5__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
1059#define MX51_PAD_NANDF_CS6__CSPI_SS3 (_MX51_PAD_NANDF_CS6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1060#define MX51_PAD_NANDF_CS6__FEC_TDATA3 (_MX51_PAD_NANDF_CS6__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1061#define MX51_PAD_NANDF_CS6__GPIO3_22 (_MX51_PAD_NANDF_CS6__GPIO3_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1062#define MX51_PAD_NANDF_CS6__NANDF_CS6 (_MX51_PAD_NANDF_CS6__NANDF_CS6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1063#define MX51_PAD_NANDF_CS6__PATA_DA_2 (_MX51_PAD_NANDF_CS6__PATA_DA_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1064#define MX51_PAD_NANDF_CS6__SD4_DAT3 (_MX51_PAD_NANDF_CS6__SD4_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1065#define MX51_PAD_NANDF_CS7__FEC_TX_EN (_MX51_PAD_NANDF_CS7__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1066#define MX51_PAD_NANDF_CS7__GPIO3_23 (_MX51_PAD_NANDF_CS7__GPIO3_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1067#define MX51_PAD_NANDF_CS7__NANDF_CS7 (_MX51_PAD_NANDF_CS7__NANDF_CS7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1068#define MX51_PAD_NANDF_CS7__SD3_CLK (_MX51_PAD_NANDF_CS7__SD3_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1069#define MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 (_MX51_PAD_NANDF_RDY_INT__ECSPI2_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1070#define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK (_MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
1071#define MX51_PAD_NANDF_RDY_INT__GPIO3_24 (_MX51_PAD_NANDF_RDY_INT__GPIO3_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1072#define MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT (_MX51_PAD_NANDF_RDY_INT__NANDF_RDY_INT | MUX_PAD_CTRL(NO_PAD_CTRL))
1073#define MX51_PAD_NANDF_RDY_INT__SD3_CMD (_MX51_PAD_NANDF_RDY_INT__SD3_CMD | MUX_PAD_CTRL(NO_PAD_CTRL))
1074#define MX51_PAD_NANDF_D15__ECSPI2_MOSI (_MX51_PAD_NANDF_D15__ECSPI2_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1075#define MX51_PAD_NANDF_D15__GPIO3_25 (_MX51_PAD_NANDF_D15__GPIO3_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1076#define MX51_PAD_NANDF_D15__NANDF_D15 (_MX51_PAD_NANDF_D15__NANDF_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1077#define MX51_PAD_NANDF_D15__PATA_DATA15 (_MX51_PAD_NANDF_D15__PATA_DATA15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1078#define MX51_PAD_NANDF_D15__SD3_DAT7 (_MX51_PAD_NANDF_D15__SD3_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1079#define MX51_PAD_NANDF_D14__ECSPI2_SS3 (_MX51_PAD_NANDF_D14__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1080#define MX51_PAD_NANDF_D14__GPIO3_26 (_MX51_PAD_NANDF_D14__GPIO3_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1081#define MX51_PAD_NANDF_D14__NANDF_D14 (_MX51_PAD_NANDF_D14__NANDF_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1082#define MX51_PAD_NANDF_D14__PATA_DATA14 (_MX51_PAD_NANDF_D14__PATA_DATA14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1083#define MX51_PAD_NANDF_D14__SD3_DAT6 (_MX51_PAD_NANDF_D14__SD3_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1084#define MX51_PAD_NANDF_D13__ECSPI2_SS2 (_MX51_PAD_NANDF_D13__ECSPI2_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1085#define MX51_PAD_NANDF_D13__GPIO3_27 (_MX51_PAD_NANDF_D13__GPIO3_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1086#define MX51_PAD_NANDF_D13__NANDF_D13 (_MX51_PAD_NANDF_D13__NANDF_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1087#define MX51_PAD_NANDF_D13__PATA_DATA13 (_MX51_PAD_NANDF_D13__PATA_DATA13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1088#define MX51_PAD_NANDF_D13__SD3_DAT5 (_MX51_PAD_NANDF_D13__SD3_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1089#define MX51_PAD_NANDF_D12__ECSPI2_SS1 (_MX51_PAD_NANDF_D12__ECSPI2_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1090#define MX51_PAD_NANDF_D12__GPIO3_28 (_MX51_PAD_NANDF_D12__GPIO3_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1091#define MX51_PAD_NANDF_D12__NANDF_D12 (_MX51_PAD_NANDF_D12__NANDF_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1092#define MX51_PAD_NANDF_D12__PATA_DATA12 (_MX51_PAD_NANDF_D12__PATA_DATA12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1093#define MX51_PAD_NANDF_D12__SD3_DAT4 (_MX51_PAD_NANDF_D12__SD3_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1094#define MX51_PAD_NANDF_D11__FEC_RX_DV (_MX51_PAD_NANDF_D11__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
1095#define MX51_PAD_NANDF_D11__GPIO3_29 (_MX51_PAD_NANDF_D11__GPIO3_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1096#define MX51_PAD_NANDF_D11__NANDF_D11 (_MX51_PAD_NANDF_D11__NANDF_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1097#define MX51_PAD_NANDF_D11__PATA_DATA11 (_MX51_PAD_NANDF_D11__PATA_DATA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1098#define MX51_PAD_NANDF_D11__SD3_DATA3 (_MX51_PAD_NANDF_D11__SD3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1099#define MX51_PAD_NANDF_D10__GPIO3_30 (_MX51_PAD_NANDF_D10__GPIO3_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1100#define MX51_PAD_NANDF_D10__NANDF_D10 (_MX51_PAD_NANDF_D10__NANDF_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1101#define MX51_PAD_NANDF_D10__PATA_DATA10 (_MX51_PAD_NANDF_D10__PATA_DATA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1102#define MX51_PAD_NANDF_D10__SD3_DATA2 (_MX51_PAD_NANDF_D10__SD3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1103#define MX51_PAD_NANDF_D9__FEC_RDATA0 (_MX51_PAD_NANDF_D9__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
1104#define MX51_PAD_NANDF_D9__GPIO3_31 (_MX51_PAD_NANDF_D9__GPIO3_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1105#define MX51_PAD_NANDF_D9__NANDF_D9 (_MX51_PAD_NANDF_D9__NANDF_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1106#define MX51_PAD_NANDF_D9__PATA_DATA9 (_MX51_PAD_NANDF_D9__PATA_DATA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1107#define MX51_PAD_NANDF_D9__SD3_DATA1 (_MX51_PAD_NANDF_D9__SD3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1108#define MX51_PAD_NANDF_D8__FEC_TDATA0 (_MX51_PAD_NANDF_D8__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1109#define MX51_PAD_NANDF_D8__GPIO4_0 (_MX51_PAD_NANDF_D8__GPIO4_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1110#define MX51_PAD_NANDF_D8__NANDF_D8 (_MX51_PAD_NANDF_D8__NANDF_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1111#define MX51_PAD_NANDF_D8__PATA_DATA8 (_MX51_PAD_NANDF_D8__PATA_DATA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1112#define MX51_PAD_NANDF_D8__SD3_DATA0 (_MX51_PAD_NANDF_D8__SD3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1113#define MX51_PAD_NANDF_D7__GPIO4_1 (_MX51_PAD_NANDF_D7__GPIO4_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1114#define MX51_PAD_NANDF_D7__NANDF_D7 (_MX51_PAD_NANDF_D7__NANDF_D7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1115#define MX51_PAD_NANDF_D7__PATA_DATA7 (_MX51_PAD_NANDF_D7__PATA_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1116#define MX51_PAD_NANDF_D7__USBH3_DATA0 (_MX51_PAD_NANDF_D7__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1117#define MX51_PAD_NANDF_D6__GPIO4_2 (_MX51_PAD_NANDF_D6__GPIO4_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1118#define MX51_PAD_NANDF_D6__NANDF_D6 (_MX51_PAD_NANDF_D6__NANDF_D6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1119#define MX51_PAD_NANDF_D6__PATA_DATA6 (_MX51_PAD_NANDF_D6__PATA_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1120#define MX51_PAD_NANDF_D6__SD4_LCTL (_MX51_PAD_NANDF_D6__SD4_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
1121#define MX51_PAD_NANDF_D6__USBH3_DATA1 (_MX51_PAD_NANDF_D6__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1122#define MX51_PAD_NANDF_D5__GPIO4_3 (_MX51_PAD_NANDF_D5__GPIO4_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1123#define MX51_PAD_NANDF_D5__NANDF_D5 (_MX51_PAD_NANDF_D5__NANDF_D5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1124#define MX51_PAD_NANDF_D5__PATA_DATA5 (_MX51_PAD_NANDF_D5__PATA_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1125#define MX51_PAD_NANDF_D5__SD4_WP (_MX51_PAD_NANDF_D5__SD4_WP | MUX_PAD_CTRL(NO_PAD_CTRL))
1126#define MX51_PAD_NANDF_D5__USBH3_DATA2 (_MX51_PAD_NANDF_D5__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1127#define MX51_PAD_NANDF_D4__GPIO4_4 (_MX51_PAD_NANDF_D4__GPIO4_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1128#define MX51_PAD_NANDF_D4__NANDF_D4 (_MX51_PAD_NANDF_D4__NANDF_D4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1129#define MX51_PAD_NANDF_D4__PATA_DATA4 (_MX51_PAD_NANDF_D4__PATA_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1130#define MX51_PAD_NANDF_D4__SD4_CD (_MX51_PAD_NANDF_D4__SD4_CD | MUX_PAD_CTRL(NO_PAD_CTRL))
1131#define MX51_PAD_NANDF_D4__USBH3_DATA3 (_MX51_PAD_NANDF_D4__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1132#define MX51_PAD_NANDF_D3__GPIO4_5 (_MX51_PAD_NANDF_D3__GPIO4_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1133#define MX51_PAD_NANDF_D3__NANDF_D3 (_MX51_PAD_NANDF_D3__NANDF_D3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1134#define MX51_PAD_NANDF_D3__PATA_DATA3 (_MX51_PAD_NANDF_D3__PATA_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1135#define MX51_PAD_NANDF_D3__SD4_DAT4 (_MX51_PAD_NANDF_D3__SD4_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1136#define MX51_PAD_NANDF_D3__USBH3_DATA4 (_MX51_PAD_NANDF_D3__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1137#define MX51_PAD_NANDF_D2__GPIO4_6 (_MX51_PAD_NANDF_D2__GPIO4_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1138#define MX51_PAD_NANDF_D2__NANDF_D2 (_MX51_PAD_NANDF_D2__NANDF_D2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1139#define MX51_PAD_NANDF_D2__PATA_DATA2 (_MX51_PAD_NANDF_D2__PATA_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1140#define MX51_PAD_NANDF_D2__SD4_DAT5 (_MX51_PAD_NANDF_D2__SD4_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1141#define MX51_PAD_NANDF_D2__USBH3_DATA5 (_MX51_PAD_NANDF_D2__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1142#define MX51_PAD_NANDF_D1__GPIO4_7 (_MX51_PAD_NANDF_D1__GPIO4_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1143#define MX51_PAD_NANDF_D1__NANDF_D1 (_MX51_PAD_NANDF_D1__NANDF_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1144#define MX51_PAD_NANDF_D1__PATA_DATA1 (_MX51_PAD_NANDF_D1__PATA_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1145#define MX51_PAD_NANDF_D1__SD4_DAT6 (_MX51_PAD_NANDF_D1__SD4_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1146#define MX51_PAD_NANDF_D1__USBH3_DATA6 (_MX51_PAD_NANDF_D1__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1147#define MX51_PAD_NANDF_D0__GPIO4_8 (_MX51_PAD_NANDF_D0__GPIO4_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1148#define MX51_PAD_NANDF_D0__NANDF_D0 (_MX51_PAD_NANDF_D0__NANDF_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1149#define MX51_PAD_NANDF_D0__PATA_DATA0 (_MX51_PAD_NANDF_D0__PATA_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1150#define MX51_PAD_NANDF_D0__SD4_DAT7 (_MX51_PAD_NANDF_D0__SD4_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1151#define MX51_PAD_NANDF_D0__USBH3_DATA7 (_MX51_PAD_NANDF_D0__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1152#define MX51_PAD_CSI1_D8__CSI1_D8 (_MX51_PAD_CSI1_D8__CSI1_D8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1153#define MX51_PAD_CSI1_D8__GPIO3_12 (_MX51_PAD_CSI1_D8__GPIO3_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1154#define MX51_PAD_CSI1_D9__CSI1_D9 (_MX51_PAD_CSI1_D9__CSI1_D9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1155#define MX51_PAD_CSI1_D9__GPIO3_13 (_MX51_PAD_CSI1_D9__GPIO3_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1156#define MX51_PAD_CSI1_D10__CSI1_D10 (_MX51_PAD_CSI1_D10__CSI1_D10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1157#define MX51_PAD_CSI1_D11__CSI1_D11 (_MX51_PAD_CSI1_D11__CSI1_D11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1158#define MX51_PAD_CSI1_D12__CSI1_D12 (_MX51_PAD_CSI1_D12__CSI1_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1159#define MX51_PAD_CSI1_D13__CSI1_D13 (_MX51_PAD_CSI1_D13__CSI1_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1160#define MX51_PAD_CSI1_D14__CSI1_D14 (_MX51_PAD_CSI1_D14__CSI1_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1161#define MX51_PAD_CSI1_D15__CSI1_D15 (_MX51_PAD_CSI1_D15__CSI1_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1162#define MX51_PAD_CSI1_D16__CSI1_D16 (_MX51_PAD_CSI1_D16__CSI1_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1163#define MX51_PAD_CSI1_D17__CSI1_D17 (_MX51_PAD_CSI1_D17__CSI1_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1164#define MX51_PAD_CSI1_D18__CSI1_D18 (_MX51_PAD_CSI1_D18__CSI1_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1165#define MX51_PAD_CSI1_D19__CSI1_D19 (_MX51_PAD_CSI1_D19__CSI1_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1166#define MX51_PAD_CSI1_VSYNC__CSI1_VSYNC (_MX51_PAD_CSI1_VSYNC__CSI1_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1167#define MX51_PAD_CSI1_VSYNC__GPIO3_14 (_MX51_PAD_CSI1_VSYNC__GPIO3_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1168#define MX51_PAD_CSI1_HSYNC__CSI1_HSYNC (_MX51_PAD_CSI1_HSYNC__CSI1_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1169#define MX51_PAD_CSI1_HSYNC__GPIO3_15 (_MX51_PAD_CSI1_HSYNC__GPIO3_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1170#define MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK (_MX51_PAD_CSI1_PIXCLK__CSI1_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1171#define MX51_PAD_CSI1_MCLK__CSI1_MCLK (_MX51_PAD_CSI1_MCLK__CSI1_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1172#define MX51_PAD_CSI2_D12__CSI2_D12 (_MX51_PAD_CSI2_D12__CSI2_D12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1173#define MX51_PAD_CSI2_D12__GPIO4_9 (_MX51_PAD_CSI2_D12__GPIO4_9 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1174#define MX51_PAD_CSI2_D13__CSI2_D13 (_MX51_PAD_CSI2_D13__CSI2_D13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1175#define MX51_PAD_CSI2_D13__GPIO4_10 (_MX51_PAD_CSI2_D13__GPIO4_10 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1176#define MX51_PAD_CSI2_D14__CSI2_D14 (_MX51_PAD_CSI2_D14__CSI2_D14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1177#define MX51_PAD_CSI2_D15__CSI2_D15 (_MX51_PAD_CSI2_D15__CSI2_D15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1178#define MX51_PAD_CSI2_D16__CSI2_D16 (_MX51_PAD_CSI2_D16__CSI2_D16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1179#define MX51_PAD_CSI2_D17__CSI2_D17 (_MX51_PAD_CSI2_D17__CSI2_D17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1180#define MX51_PAD_CSI2_D18__CSI2_D18 (_MX51_PAD_CSI2_D18__CSI2_D18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1181#define MX51_PAD_CSI2_D18__GPIO4_11 (_MX51_PAD_CSI2_D18__GPIO4_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1182#define MX51_PAD_CSI2_D19__CSI2_D19 (_MX51_PAD_CSI2_D19__CSI2_D19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1183#define MX51_PAD_CSI2_D19__GPIO4_12 (_MX51_PAD_CSI2_D19__GPIO4_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1184#define MX51_PAD_CSI2_VSYNC__CSI2_VSYNC (_MX51_PAD_CSI2_VSYNC__CSI2_VSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1185#define MX51_PAD_CSI2_VSYNC__GPIO4_13 (_MX51_PAD_CSI2_VSYNC__GPIO4_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1186#define MX51_PAD_CSI2_HSYNC__CSI2_HSYNC (_MX51_PAD_CSI2_HSYNC__CSI2_HSYNC | MUX_PAD_CTRL(NO_PAD_CTRL))
1187#define MX51_PAD_CSI2_HSYNC__GPIO4_14 (_MX51_PAD_CSI2_HSYNC__GPIO4_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1188#define MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK (_MX51_PAD_CSI2_PIXCLK__CSI2_PIXCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1189#define MX51_PAD_CSI2_PIXCLK__GPIO4_15 (_MX51_PAD_CSI2_PIXCLK__GPIO4_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1190#define MX51_PAD_I2C1_CLK__GPIO4_16 (_MX51_PAD_I2C1_CLK__GPIO4_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1191#define MX51_PAD_I2C1_CLK__I2C1_CLK (_MX51_PAD_I2C1_CLK__I2C1_CLK | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1192#define MX51_PAD_I2C1_DAT__GPIO4_17 (_MX51_PAD_I2C1_DAT__GPIO4_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1193#define MX51_PAD_I2C1_DAT__I2C1_DAT (_MX51_PAD_I2C1_DAT__I2C1_DAT | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1194#define MX51_PAD_AUD3_BB_TXD__AUD3_TXD (_MX51_PAD_AUD3_BB_TXD__AUD3_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1195#define MX51_PAD_AUD3_BB_TXD__GPIO4_18 (_MX51_PAD_AUD3_BB_TXD__GPIO4_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1196#define MX51_PAD_AUD3_BB_RXD__AUD3_RXD (_MX51_PAD_AUD3_BB_RXD__AUD3_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1197#define MX51_PAD_AUD3_BB_RXD__GPIO4_19 (_MX51_PAD_AUD3_BB_RXD__GPIO4_19 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1198#define MX51_PAD_AUD3_BB_RXD__UART3_RXD (_MX51_PAD_AUD3_BB_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1199#define MX51_PAD_AUD3_BB_CK__AUD3_TXC (_MX51_PAD_AUD3_BB_CK__AUD3_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1200#define MX51_PAD_AUD3_BB_CK__GPIO4_20 (_MX51_PAD_AUD3_BB_CK__GPIO4_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1201#define MX51_PAD_AUD3_BB_FS__AUD3_TXFS (_MX51_PAD_AUD3_BB_FS__AUD3_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1202#define MX51_PAD_AUD3_BB_FS__GPIO4_21 (_MX51_PAD_AUD3_BB_FS__GPIO4_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1203#define MX51_PAD_AUD3_BB_FS__UART3_TXD (_MX51_PAD_AUD3_BB_FS__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1204#define MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI (_MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1205#define MX51_PAD_CSPI1_MOSI__GPIO4_22 (_MX51_PAD_CSPI1_MOSI__GPIO4_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1206#define MX51_PAD_CSPI1_MOSI__I2C1_SDA (_MX51_PAD_CSPI1_MOSI__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1207#define MX51_PAD_CSPI1_MISO__AUD4_RXD (_MX51_PAD_CSPI1_MISO__AUD4_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1208#define MX51_PAD_CSPI1_MISO__ECSPI1_MISO (_MX51_PAD_CSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1209#define MX51_PAD_CSPI1_MISO__GPIO4_23 (_MX51_PAD_CSPI1_MISO__GPIO4_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1210#define MX51_PAD_CSPI1_SS0__AUD4_TXC (_MX51_PAD_CSPI1_SS0__AUD4_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1211#define MX51_PAD_CSPI1_SS0__ECSPI1_SS0 (_MX51_PAD_CSPI1_SS0__ECSPI1_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1212#define MX51_PAD_CSPI1_SS0__GPIO4_24 (_MX51_PAD_CSPI1_SS0__GPIO4_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1213#define MX51_PAD_CSPI1_SS1__AUD4_TXD (_MX51_PAD_CSPI1_SS1__AUD4_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1214#define MX51_PAD_CSPI1_SS1__ECSPI1_SS1 (_MX51_PAD_CSPI1_SS1__ECSPI1_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1215#define MX51_PAD_CSPI1_SS1__GPIO4_25 (_MX51_PAD_CSPI1_SS1__GPIO4_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1216#define MX51_PAD_CSPI1_RDY__AUD4_TXFS (_MX51_PAD_CSPI1_RDY__AUD4_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1217#define MX51_PAD_CSPI1_RDY__ECSPI1_RDY (_MX51_PAD_CSPI1_RDY__ECSPI1_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1218#define MX51_PAD_CSPI1_RDY__GPIO4_26 (_MX51_PAD_CSPI1_RDY__GPIO4_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1219#define MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK (_MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1220#define MX51_PAD_CSPI1_SCLK__GPIO4_27 (_MX51_PAD_CSPI1_SCLK__GPIO4_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1221#define MX51_PAD_CSPI1_SCLK__I2C1_SCL (_MX51_PAD_CSPI1_SCLK__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1222#define MX51_PAD_UART1_RXD__GPIO4_28 (_MX51_PAD_UART1_RXD__GPIO4_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1223#define MX51_PAD_UART1_RXD__UART1_RXD (_MX51_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1224#define MX51_PAD_UART1_TXD__GPIO4_29 (_MX51_PAD_UART1_TXD__GPIO4_29 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1225#define MX51_PAD_UART1_TXD__PWM2_PWMO (_MX51_PAD_UART1_TXD__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
1226#define MX51_PAD_UART1_TXD__UART1_TXD (_MX51_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1227#define MX51_PAD_UART1_RTS__GPIO4_30 (_MX51_PAD_UART1_RTS__GPIO4_30 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1228#define MX51_PAD_UART1_RTS__UART1_RTS (_MX51_PAD_UART1_RTS__UART1_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1229#define MX51_PAD_UART1_CTS__GPIO4_31 (_MX51_PAD_UART1_CTS__GPIO4_31 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1230#define MX51_PAD_UART1_CTS__UART1_CTS (_MX51_PAD_UART1_CTS__UART1_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1231#define MX51_PAD_UART2_RXD__FIRI_TXD (_MX51_PAD_UART2_RXD__FIRI_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1232#define MX51_PAD_UART2_RXD__GPIO1_20 (_MX51_PAD_UART2_RXD__GPIO1_20 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1233#define MX51_PAD_UART2_RXD__UART2_RXD (_MX51_PAD_UART2_RXD__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1234#define MX51_PAD_UART2_TXD__FIRI_RXD (_MX51_PAD_UART2_TXD__FIRI_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1235#define MX51_PAD_UART2_TXD__GPIO1_21 (_MX51_PAD_UART2_TXD__GPIO1_21 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1236#define MX51_PAD_UART2_TXD__UART2_TXD (_MX51_PAD_UART2_TXD__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1237#define MX51_PAD_UART3_RXD__CSI1_D0 (_MX51_PAD_UART3_RXD__CSI1_D0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1238#define MX51_PAD_UART3_RXD__GPIO1_22 (_MX51_PAD_UART3_RXD__GPIO1_22 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1239#define MX51_PAD_UART3_RXD__UART1_DTR (_MX51_PAD_UART3_RXD__UART1_DTR | MUX_PAD_CTRL(NO_PAD_CTRL))
1240#define MX51_PAD_UART3_RXD__UART3_RXD (_MX51_PAD_UART3_RXD__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1241#define MX51_PAD_UART3_TXD__CSI1_D1 (_MX51_PAD_UART3_TXD__CSI1_D1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1242#define MX51_PAD_UART3_TXD__GPIO1_23 (_MX51_PAD_UART3_TXD__GPIO1_23 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1243#define MX51_PAD_UART3_TXD__UART1_DSR (_MX51_PAD_UART3_TXD__UART1_DSR | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1244#define MX51_PAD_UART3_TXD__UART3_TXD (_MX51_PAD_UART3_TXD__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1245#define MX51_PAD_OWIRE_LINE__GPIO1_24 (_MX51_PAD_OWIRE_LINE__GPIO1_24 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1246#define MX51_PAD_OWIRE_LINE__OWIRE_LINE (_MX51_PAD_OWIRE_LINE__OWIRE_LINE | MUX_PAD_CTRL(NO_PAD_CTRL))
1247#define MX51_PAD_OWIRE_LINE__SPDIF_OUT (_MX51_PAD_OWIRE_LINE__SPDIF_OUT | MUX_PAD_CTRL(NO_PAD_CTRL))
1248#define MX51_PAD_KEY_ROW0__KEY_ROW0 (_MX51_PAD_KEY_ROW0__KEY_ROW0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1249#define MX51_PAD_KEY_ROW1__KEY_ROW1 (_MX51_PAD_KEY_ROW1__KEY_ROW1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1250#define MX51_PAD_KEY_ROW2__KEY_ROW2 (_MX51_PAD_KEY_ROW2__KEY_ROW2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1251#define MX51_PAD_KEY_ROW3__KEY_ROW3 (_MX51_PAD_KEY_ROW3__KEY_ROW3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1252#define MX51_PAD_KEY_COL0__KEY_COL0 (_MX51_PAD_KEY_COL0__KEY_COL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1253#define MX51_PAD_KEY_COL0__PLL1_BYP (_MX51_PAD_KEY_COL0__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1254#define MX51_PAD_KEY_COL1__KEY_COL1 (_MX51_PAD_KEY_COL1__KEY_COL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1255#define MX51_PAD_KEY_COL1__PLL2_BYP (_MX51_PAD_KEY_COL1__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1256#define MX51_PAD_KEY_COL2__KEY_COL2 (_MX51_PAD_KEY_COL2__KEY_COL2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1257#define MX51_PAD_KEY_COL2__PLL3_BYP (_MX51_PAD_KEY_COL2__PLL3_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1258#define MX51_PAD_KEY_COL3__KEY_COL3 (_MX51_PAD_KEY_COL3__KEY_COL3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1259#define MX51_PAD_KEY_COL4__I2C2_SCL (_MX51_PAD_KEY_COL4__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1260#define MX51_PAD_KEY_COL4__KEY_COL4 (_MX51_PAD_KEY_COL4__KEY_COL4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1261#define MX51_PAD_KEY_COL4__SPDIF_OUT1 (_MX51_PAD_KEY_COL4__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1262#define MX51_PAD_KEY_COL4__UART1_RI (_MX51_PAD_KEY_COL4__UART1_RI | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1263#define MX51_PAD_KEY_COL4__UART3_RTS (_MX51_PAD_KEY_COL4__UART3_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1264#define MX51_PAD_KEY_COL5__I2C2_SDA (_MX51_PAD_KEY_COL5__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1265#define MX51_PAD_KEY_COL5__KEY_COL5 (_MX51_PAD_KEY_COL5__KEY_COL5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1266#define MX51_PAD_KEY_COL5__UART1_DCD (_MX51_PAD_KEY_COL5__UART1_DCD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1267#define MX51_PAD_KEY_COL5__UART3_CTS (_MX51_PAD_KEY_COL5__UART3_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1268#define MX51_PAD_USBH1_CLK__CSPI_SCLK (_MX51_PAD_USBH1_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1269#define MX51_PAD_USBH1_CLK__GPIO1_25 (_MX51_PAD_USBH1_CLK__GPIO1_25 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1270#define MX51_PAD_USBH1_CLK__I2C2_SCL (_MX51_PAD_USBH1_CLK__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1271#define MX51_PAD_USBH1_CLK__USBH1_CLK (_MX51_PAD_USBH1_CLK__USBH1_CLK | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1272#define MX51_PAD_USBH1_DIR__CSPI_MOSI (_MX51_PAD_USBH1_DIR__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1273#define MX51_PAD_USBH1_DIR__GPIO1_26 (_MX51_PAD_USBH1_DIR__GPIO1_26 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1274#define MX51_PAD_USBH1_DIR__I2C2_SDA (_MX51_PAD_USBH1_DIR__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1275#define MX51_PAD_USBH1_DIR__USBH1_DIR (_MX51_PAD_USBH1_DIR__USBH1_DIR | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1276#define MX51_PAD_USBH1_STP__CSPI_RDY (_MX51_PAD_USBH1_STP__CSPI_RDY | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1277#define MX51_PAD_USBH1_STP__GPIO1_27 (_MX51_PAD_USBH1_STP__GPIO1_27 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1278#define MX51_PAD_USBH1_STP__UART3_RXD (_MX51_PAD_USBH1_STP__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1279#define MX51_PAD_USBH1_STP__USBH1_STP (_MX51_PAD_USBH1_STP__USBH1_STP | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1280#define MX51_PAD_USBH1_NXT__CSPI_MISO (_MX51_PAD_USBH1_NXT__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1281#define MX51_PAD_USBH1_NXT__GPIO1_28 (_MX51_PAD_USBH1_NXT__GPIO1_28 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1282#define MX51_PAD_USBH1_NXT__UART3_TXD (_MX51_PAD_USBH1_NXT__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1283#define MX51_PAD_USBH1_NXT__USBH1_NXT (_MX51_PAD_USBH1_NXT__USBH1_NXT | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1284#define MX51_PAD_USBH1_DATA0__GPIO1_11 (_MX51_PAD_USBH1_DATA0__GPIO1_11 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1285#define MX51_PAD_USBH1_DATA0__UART2_CTS (_MX51_PAD_USBH1_DATA0__UART2_CTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1286#define MX51_PAD_USBH1_DATA0__USBH1_DATA0 (_MX51_PAD_USBH1_DATA0__USBH1_DATA0 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1287#define MX51_PAD_USBH1_DATA1__GPIO1_12 (_MX51_PAD_USBH1_DATA1__GPIO1_12 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1288#define MX51_PAD_USBH1_DATA1__UART2_RXD (_MX51_PAD_USBH1_DATA1__UART2_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1289#define MX51_PAD_USBH1_DATA1__USBH1_DATA1 (_MX51_PAD_USBH1_DATA1__USBH1_DATA1 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1290#define MX51_PAD_USBH1_DATA2__GPIO1_13 (_MX51_PAD_USBH1_DATA2__GPIO1_13 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1291#define MX51_PAD_USBH1_DATA2__UART2_TXD (_MX51_PAD_USBH1_DATA2__UART2_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1292#define MX51_PAD_USBH1_DATA2__USBH1_DATA2 (_MX51_PAD_USBH1_DATA2__USBH1_DATA2 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1293#define MX51_PAD_USBH1_DATA3__GPIO1_14 (_MX51_PAD_USBH1_DATA3__GPIO1_14 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1294#define MX51_PAD_USBH1_DATA3__UART2_RTS (_MX51_PAD_USBH1_DATA3__UART2_RTS | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1295#define MX51_PAD_USBH1_DATA3__USBH1_DATA3 (_MX51_PAD_USBH1_DATA3__USBH1_DATA3 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1296#define MX51_PAD_USBH1_DATA4__CSPI_SS0 (_MX51_PAD_USBH1_DATA4__CSPI_SS0 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1297#define MX51_PAD_USBH1_DATA4__GPIO1_15 (_MX51_PAD_USBH1_DATA4__GPIO1_15 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1298#define MX51_PAD_USBH1_DATA4__USBH1_DATA4 (_MX51_PAD_USBH1_DATA4__USBH1_DATA4 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1299#define MX51_PAD_USBH1_DATA5__CSPI_SS1 (_MX51_PAD_USBH1_DATA5__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1300#define MX51_PAD_USBH1_DATA5__GPIO1_16 (_MX51_PAD_USBH1_DATA5__GPIO1_16 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1301#define MX51_PAD_USBH1_DATA5__USBH1_DATA5 (_MX51_PAD_USBH1_DATA5__USBH1_DATA5 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1302#define MX51_PAD_USBH1_DATA6__CSPI_SS3 (_MX51_PAD_USBH1_DATA6__CSPI_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1303#define MX51_PAD_USBH1_DATA6__GPIO1_17 (_MX51_PAD_USBH1_DATA6__GPIO1_17 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1304#define MX51_PAD_USBH1_DATA6__USBH1_DATA6 (_MX51_PAD_USBH1_DATA6__USBH1_DATA6 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1305#define MX51_PAD_USBH1_DATA7__ECSPI1_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI1_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1306#define MX51_PAD_USBH1_DATA7__ECSPI2_SS3 (_MX51_PAD_USBH1_DATA7__ECSPI2_SS3 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1307#define MX51_PAD_USBH1_DATA7__GPIO1_18 (_MX51_PAD_USBH1_DATA7__GPIO1_18 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1308#define MX51_PAD_USBH1_DATA7__USBH1_DATA7 (_MX51_PAD_USBH1_DATA7__USBH1_DATA7 | MUX_PAD_CTRL(MX51_USBH1_PAD_CTRL))
1309#define MX51_PAD_DI1_PIN11__DI1_PIN11 (_MX51_PAD_DI1_PIN11__DI1_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1310#define MX51_PAD_DI1_PIN11__ECSPI1_SS2 (_MX51_PAD_DI1_PIN11__ECSPI1_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1311#define MX51_PAD_DI1_PIN11__GPIO3_0 (_MX51_PAD_DI1_PIN11__GPIO3_0 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1312#define MX51_PAD_DI1_PIN12__DI1_PIN12 (_MX51_PAD_DI1_PIN12__DI1_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1313#define MX51_PAD_DI1_PIN12__GPIO3_1 (_MX51_PAD_DI1_PIN12__GPIO3_1 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1314#define MX51_PAD_DI1_PIN13__DI1_PIN13 (_MX51_PAD_DI1_PIN13__DI1_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1315#define MX51_PAD_DI1_PIN13__GPIO3_2 (_MX51_PAD_DI1_PIN13__GPIO3_2 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1316#define MX51_PAD_DI1_D0_CS__DI1_D0_CS (_MX51_PAD_DI1_D0_CS__DI1_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1317#define MX51_PAD_DI1_D0_CS__GPIO3_3 (_MX51_PAD_DI1_D0_CS__GPIO3_3 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1318#define MX51_PAD_DI1_D1_CS__DI1_D1_CS (_MX51_PAD_DI1_D1_CS__DI1_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1319#define MX51_PAD_DI1_D1_CS__DISP1_PIN14 (_MX51_PAD_DI1_D1_CS__DISP1_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1320#define MX51_PAD_DI1_D1_CS__DISP1_PIN5 (_MX51_PAD_DI1_D1_CS__DISP1_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1321#define MX51_PAD_DI1_D1_CS__GPIO3_4 (_MX51_PAD_DI1_D1_CS__GPIO3_4 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1322#define MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 (_MX51_PAD_DISPB2_SER_DIN__DISP1_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1323#define MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN (_MX51_PAD_DISPB2_SER_DIN__DISPB2_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
1324#define MX51_PAD_DISPB2_SER_DIN__GPIO3_5 (_MX51_PAD_DISPB2_SER_DIN__GPIO3_5 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1325#define MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 (_MX51_PAD_DISPB2_SER_DIO__DISP1_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1326#define MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO (_MX51_PAD_DISPB2_SER_DIO__DISPB2_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1327#define MX51_PAD_DISPB2_SER_DIO__GPIO3_6 (_MX51_PAD_DISPB2_SER_DIO__GPIO3_6 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1328#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1329#define MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 (_MX51_PAD_DISPB2_SER_CLK__DISP1_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1330#define MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK (_MX51_PAD_DISPB2_SER_CLK__DISPB2_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1331#define MX51_PAD_DISPB2_SER_CLK__GPIO3_7 (_MX51_PAD_DISPB2_SER_CLK__GPIO3_7 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1332#define MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK (_MX51_PAD_DISPB2_SER_RS__DISP1_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1333#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1334#define MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 (_MX51_PAD_DISPB2_SER_RS__DISP1_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1335#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
1336#define MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS (_MX51_PAD_DISPB2_SER_RS__DISPB2_SER_RS | MUX_PAD_CTRL(NO_PAD_CTRL))
1337#define MX51_PAD_DISPB2_SER_RS__GPIO3_8 (_MX51_PAD_DISPB2_SER_RS__GPIO3_8 | MUX_PAD_CTRL(MX51_GPIO_PAD_CTRL))
1338#define MX51_PAD_DISP1_DAT0__DISP1_DAT0 (_MX51_PAD_DISP1_DAT0__DISP1_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1339#define MX51_PAD_DISP1_DAT1__DISP1_DAT1 (_MX51_PAD_DISP1_DAT1__DISP1_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1340#define MX51_PAD_DISP1_DAT2__DISP1_DAT2 (_MX51_PAD_DISP1_DAT2__DISP1_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1341#define MX51_PAD_DISP1_DAT3__DISP1_DAT3 (_MX51_PAD_DISP1_DAT3__DISP1_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1342#define MX51_PAD_DISP1_DAT4__DISP1_DAT4 (_MX51_PAD_DISP1_DAT4__DISP1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1343#define MX51_PAD_DISP1_DAT5__DISP1_DAT5 (_MX51_PAD_DISP1_DAT5__DISP1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1344#define MX51_PAD_DISP1_DAT6__BOOT_USB_SRC (_MX51_PAD_DISP1_DAT6__BOOT_USB_SRC | MUX_PAD_CTRL(NO_PAD_CTRL))
1345#define MX51_PAD_DISP1_DAT6__DISP1_DAT6 (_MX51_PAD_DISP1_DAT6__DISP1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1346#define MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG (_MX51_PAD_DISP1_DAT7__BOOT_EEPROM_CFG | MUX_PAD_CTRL(NO_PAD_CTRL))
1347#define MX51_PAD_DISP1_DAT7__DISP1_DAT7 (_MX51_PAD_DISP1_DAT7__DISP1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1348#define MX51_PAD_DISP1_DAT8__BOOT_SRC0 (_MX51_PAD_DISP1_DAT8__BOOT_SRC0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1349#define MX51_PAD_DISP1_DAT8__DISP1_DAT8 (_MX51_PAD_DISP1_DAT8__DISP1_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1350#define MX51_PAD_DISP1_DAT9__BOOT_SRC1 (_MX51_PAD_DISP1_DAT9__BOOT_SRC1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1351#define MX51_PAD_DISP1_DAT9__DISP1_DAT9 (_MX51_PAD_DISP1_DAT9__DISP1_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1352#define MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE (_MX51_PAD_DISP1_DAT10__BOOT_SPARE_SIZE | MUX_PAD_CTRL(NO_PAD_CTRL))
1353#define MX51_PAD_DISP1_DAT10__DISP1_DAT10 (_MX51_PAD_DISP1_DAT10__DISP1_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1354#define MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 (_MX51_PAD_DISP1_DAT11__BOOT_LPB_FREQ2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1355#define MX51_PAD_DISP1_DAT11__DISP1_DAT11 (_MX51_PAD_DISP1_DAT11__DISP1_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1356#define MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL (_MX51_PAD_DISP1_DAT12__BOOT_MLC_SEL | MUX_PAD_CTRL(NO_PAD_CTRL))
1357#define MX51_PAD_DISP1_DAT12__DISP1_DAT12 (_MX51_PAD_DISP1_DAT12__DISP1_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1358#define MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 (_MX51_PAD_DISP1_DAT13__BOOT_MEM_CTL0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1359#define MX51_PAD_DISP1_DAT13__DISP1_DAT13 (_MX51_PAD_DISP1_DAT13__DISP1_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1360#define MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 (_MX51_PAD_DISP1_DAT14__BOOT_MEM_CTL1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1361#define MX51_PAD_DISP1_DAT14__DISP1_DAT14 (_MX51_PAD_DISP1_DAT14__DISP1_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1362#define MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH (_MX51_PAD_DISP1_DAT15__BOOT_BUS_WIDTH | MUX_PAD_CTRL(NO_PAD_CTRL))
1363#define MX51_PAD_DISP1_DAT15__DISP1_DAT15 (_MX51_PAD_DISP1_DAT15__DISP1_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1364#define MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 (_MX51_PAD_DISP1_DAT16__BOOT_PAGE_SIZE0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1365#define MX51_PAD_DISP1_DAT16__DISP1_DAT16 (_MX51_PAD_DISP1_DAT16__DISP1_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1366#define MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 (_MX51_PAD_DISP1_DAT17__BOOT_PAGE_SIZE1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1367#define MX51_PAD_DISP1_DAT17__DISP1_DAT17 (_MX51_PAD_DISP1_DAT17__DISP1_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1368#define MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 (_MX51_PAD_DISP1_DAT18__BOOT_WEIM_MUXED0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1369#define MX51_PAD_DISP1_DAT18__DISP1_DAT18 (_MX51_PAD_DISP1_DAT18__DISP1_DAT18 | MUX_PAD_CTRL(NO_PAD_CTRL))
1370#define MX51_PAD_DISP1_DAT18__DISP2_PIN11 (_MX51_PAD_DISP1_DAT18__DISP2_PIN11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1371#define MX51_PAD_DISP1_DAT18__DISP2_PIN5 (_MX51_PAD_DISP1_DAT18__DISP2_PIN5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1372#define MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 (_MX51_PAD_DISP1_DAT19__BOOT_WEIM_MUXED1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1373#define MX51_PAD_DISP1_DAT19__DISP1_DAT19 (_MX51_PAD_DISP1_DAT19__DISP1_DAT19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1374#define MX51_PAD_DISP1_DAT19__DISP2_PIN12 (_MX51_PAD_DISP1_DAT19__DISP2_PIN12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1375#define MX51_PAD_DISP1_DAT19__DISP2_PIN6 (_MX51_PAD_DISP1_DAT19__DISP2_PIN6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1376#define MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 (_MX51_PAD_DISP1_DAT20__BOOT_MEM_TYPE0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1377#define MX51_PAD_DISP1_DAT20__DISP1_DAT20 (_MX51_PAD_DISP1_DAT20__DISP1_DAT20 | MUX_PAD_CTRL(NO_PAD_CTRL))
1378#define MX51_PAD_DISP1_DAT20__DISP2_PIN13 (_MX51_PAD_DISP1_DAT20__DISP2_PIN13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1379#define MX51_PAD_DISP1_DAT20__DISP2_PIN7 (_MX51_PAD_DISP1_DAT20__DISP2_PIN7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1380#define MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 (_MX51_PAD_DISP1_DAT21__BOOT_MEM_TYPE1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1381#define MX51_PAD_DISP1_DAT21__DISP1_DAT21 (_MX51_PAD_DISP1_DAT21__DISP1_DAT21 | MUX_PAD_CTRL(NO_PAD_CTRL))
1382#define MX51_PAD_DISP1_DAT21__DISP2_PIN14 (_MX51_PAD_DISP1_DAT21__DISP2_PIN14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1383#define MX51_PAD_DISP1_DAT21__DISP2_PIN8 (_MX51_PAD_DISP1_DAT21__DISP2_PIN8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1384#define MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 (_MX51_PAD_DISP1_DAT22__BOOT_LPB_FREQ0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1385#define MX51_PAD_DISP1_DAT22__DISP1_DAT22 (_MX51_PAD_DISP1_DAT22__DISP1_DAT22 | MUX_PAD_CTRL(NO_PAD_CTRL))
1386#define MX51_PAD_DISP1_DAT22__DISP2_D0_CS (_MX51_PAD_DISP1_DAT22__DISP2_D0_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1387#define MX51_PAD_DISP1_DAT22__DISP2_DAT16 (_MX51_PAD_DISP1_DAT22__DISP2_DAT16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1388#define MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 (_MX51_PAD_DISP1_DAT23__BOOT_LPB_FREQ1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1389#define MX51_PAD_DISP1_DAT23__DISP1_DAT23 (_MX51_PAD_DISP1_DAT23__DISP1_DAT23 | MUX_PAD_CTRL(NO_PAD_CTRL))
1390#define MX51_PAD_DISP1_DAT23__DISP2_D1_CS (_MX51_PAD_DISP1_DAT23__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1391#define MX51_PAD_DISP1_DAT23__DISP2_DAT17 (_MX51_PAD_DISP1_DAT23__DISP2_DAT17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1392#define MX51_PAD_DISP1_DAT23__DISP2_SER_CS (_MX51_PAD_DISP1_DAT23__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1393#define MX51_PAD_DI1_PIN3__DI1_PIN3 (_MX51_PAD_DI1_PIN3__DI1_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1394#define MX51_PAD_DI1_PIN2__DI1_PIN2 (_MX51_PAD_DI1_PIN2__DI1_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1395#define MX51_PAD_DI_GP2__DISP1_SER_CLK (_MX51_PAD_DI_GP2__DISP1_SER_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1396#define MX51_PAD_DI_GP2__DISP2_WAIT (_MX51_PAD_DI_GP2__DISP2_WAIT | MUX_PAD_CTRL(NO_PAD_CTRL))
1397#define MX51_PAD_DI_GP3__CSI1_DATA_EN (_MX51_PAD_DI_GP3__CSI1_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1398#define MX51_PAD_DI_GP3__DISP1_SER_DIO (_MX51_PAD_DI_GP3__DISP1_SER_DIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1399#define MX51_PAD_DI_GP3__FEC_TX_ER (_MX51_PAD_DI_GP3__FEC_TX_ER | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1400#define MX51_PAD_DI2_PIN4__CSI2_DATA_EN (_MX51_PAD_DI2_PIN4__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1401#define MX51_PAD_DI2_PIN4__DI2_PIN4 (_MX51_PAD_DI2_PIN4__DI2_PIN4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1402#define MX51_PAD_DI2_PIN4__FEC_CRS (_MX51_PAD_DI2_PIN4__FEC_CRS | MUX_PAD_CTRL(NO_PAD_CTRL))
1403#define MX51_PAD_DI2_PIN2__DI2_PIN2 (_MX51_PAD_DI2_PIN2__DI2_PIN2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1404#define MX51_PAD_DI2_PIN2__FEC_MDC (_MX51_PAD_DI2_PIN2__FEC_MDC | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1405#define MX51_PAD_DI2_PIN3__DI2_PIN3 (_MX51_PAD_DI2_PIN3__DI2_PIN3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1406#define MX51_PAD_DI2_PIN3__FEC_MDIO (_MX51_PAD_DI2_PIN3__FEC_MDIO | MUX_PAD_CTRL(NO_PAD_CTRL))
1407#define MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK (_MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1408#define MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 (_MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1409#define MX51_PAD_DI_GP4__DI2_PIN15 (_MX51_PAD_DI_GP4__DI2_PIN15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1410#define MX51_PAD_DI_GP4__DISP1_SER_DIN (_MX51_PAD_DI_GP4__DISP1_SER_DIN | MUX_PAD_CTRL(NO_PAD_CTRL))
1411#define MX51_PAD_DI_GP4__DISP2_PIN1 (_MX51_PAD_DI_GP4__DISP2_PIN1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1412#define MX51_PAD_DI_GP4__FEC_RDATA2 (_MX51_PAD_DI_GP4__FEC_RDATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1413#define MX51_PAD_DISP2_DAT0__DISP2_DAT0 (_MX51_PAD_DISP2_DAT0__DISP2_DAT0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1414#define MX51_PAD_DISP2_DAT0__FEC_RDATA3 (_MX51_PAD_DISP2_DAT0__FEC_RDATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1415#define MX51_PAD_DISP2_DAT0__KEY_COL6 (_MX51_PAD_DISP2_DAT0__KEY_COL6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1416#define MX51_PAD_DISP2_DAT0__UART3_RXD (_MX51_PAD_DISP2_DAT0__UART3_RXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1417#define MX51_PAD_DISP2_DAT0__USBH3_CLK (_MX51_PAD_DISP2_DAT0__USBH3_CLK | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1418#define MX51_PAD_DISP2_DAT1__DISP2_DAT1 (_MX51_PAD_DISP2_DAT1__DISP2_DAT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1419#define MX51_PAD_DISP2_DAT1__FEC_RX_ER (_MX51_PAD_DISP2_DAT1__FEC_RX_ER | MUX_PAD_CTRL(NO_PAD_CTRL))
1420#define MX51_PAD_DISP2_DAT1__KEY_COL7 (_MX51_PAD_DISP2_DAT1__KEY_COL7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1421#define MX51_PAD_DISP2_DAT1__UART3_TXD (_MX51_PAD_DISP2_DAT1__UART3_TXD | MUX_PAD_CTRL(MX51_UART_PAD_CTRL))
1422#define MX51_PAD_DISP2_DAT1__USBH3_DIR (_MX51_PAD_DISP2_DAT1__USBH3_DIR | MUX_PAD_CTRL(NO_PAD_CTRL))
1423#define MX51_PAD_DISP2_DAT2__DISP2_DAT2 (_MX51_PAD_DISP2_DAT2__DISP2_DAT2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1424#define MX51_PAD_DISP2_DAT3__DISP2_DAT3 (_MX51_PAD_DISP2_DAT3__DISP2_DAT3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1425#define MX51_PAD_DISP2_DAT4__DISP2_DAT4 (_MX51_PAD_DISP2_DAT4__DISP2_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1426#define MX51_PAD_DISP2_DAT5__DISP2_DAT5 (_MX51_PAD_DISP2_DAT5__DISP2_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1427#define MX51_PAD_DISP2_DAT6__DISP2_DAT6 (_MX51_PAD_DISP2_DAT6__DISP2_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1428#define MX51_PAD_DISP2_DAT6__FEC_TDATA1 (_MX51_PAD_DISP2_DAT6__FEC_TDATA1 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1429#define MX51_PAD_DISP2_DAT6__GPIO1_19 (_MX51_PAD_DISP2_DAT6__GPIO1_19 | MUX_PAD_CTRL(NO_PAD_CTRL))
1430#define MX51_PAD_DISP2_DAT6__KEY_ROW4 (_MX51_PAD_DISP2_DAT6__KEY_ROW4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1431#define MX51_PAD_DISP2_DAT6__USBH3_STP (_MX51_PAD_DISP2_DAT6__USBH3_STP | MUX_PAD_CTRL(NO_PAD_CTRL))
1432#define MX51_PAD_DISP2_DAT7__DISP2_DAT7 (_MX51_PAD_DISP2_DAT7__DISP2_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1433#define MX51_PAD_DISP2_DAT7__FEC_TDATA2 (_MX51_PAD_DISP2_DAT7__FEC_TDATA2 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1434#define MX51_PAD_DISP2_DAT7__GPIO1_29 (_MX51_PAD_DISP2_DAT7__GPIO1_29 | MUX_PAD_CTRL(NO_PAD_CTRL))
1435#define MX51_PAD_DISP2_DAT7__KEY_ROW5 (_MX51_PAD_DISP2_DAT7__KEY_ROW5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1436#define MX51_PAD_DISP2_DAT7__USBH3_NXT (_MX51_PAD_DISP2_DAT7__USBH3_NXT | MUX_PAD_CTRL(NO_PAD_CTRL))
1437#define MX51_PAD_DISP2_DAT8__DISP2_DAT8 (_MX51_PAD_DISP2_DAT8__DISP2_DAT8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1438#define MX51_PAD_DISP2_DAT8__FEC_TDATA3 (_MX51_PAD_DISP2_DAT8__FEC_TDATA3 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1439#define MX51_PAD_DISP2_DAT8__GPIO1_30 (_MX51_PAD_DISP2_DAT8__GPIO1_30 | MUX_PAD_CTRL(NO_PAD_CTRL))
1440#define MX51_PAD_DISP2_DAT8__KEY_ROW6 (_MX51_PAD_DISP2_DAT8__KEY_ROW6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1441#define MX51_PAD_DISP2_DAT8__USBH3_DATA0 (_MX51_PAD_DISP2_DAT8__USBH3_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1442#define MX51_PAD_DISP2_DAT9__AUD6_RXC (_MX51_PAD_DISP2_DAT9__AUD6_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1443#define MX51_PAD_DISP2_DAT9__DISP2_DAT9 (_MX51_PAD_DISP2_DAT9__DISP2_DAT9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1444#define MX51_PAD_DISP2_DAT9__FEC_TX_EN (_MX51_PAD_DISP2_DAT9__FEC_TX_EN | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1445#define MX51_PAD_DISP2_DAT9__GPIO1_31 (_MX51_PAD_DISP2_DAT9__GPIO1_31 | MUX_PAD_CTRL(NO_PAD_CTRL))
1446#define MX51_PAD_DISP2_DAT9__USBH3_DATA1 (_MX51_PAD_DISP2_DAT9__USBH3_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1447#define MX51_PAD_DISP2_DAT10__DISP2_DAT10 (_MX51_PAD_DISP2_DAT10__DISP2_DAT10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1448#define MX51_PAD_DISP2_DAT10__DISP2_SER_CS (_MX51_PAD_DISP2_DAT10__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1449#define MX51_PAD_DISP2_DAT10__FEC_COL (_MX51_PAD_DISP2_DAT10__FEC_COL | MUX_PAD_CTRL(NO_PAD_CTRL))
1450#define MX51_PAD_DISP2_DAT10__KEY_ROW7 (_MX51_PAD_DISP2_DAT10__KEY_ROW7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1451#define MX51_PAD_DISP2_DAT10__USBH3_DATA2 (_MX51_PAD_DISP2_DAT10__USBH3_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1452#define MX51_PAD_DISP2_DAT11__AUD6_TXD (_MX51_PAD_DISP2_DAT11__AUD6_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1453#define MX51_PAD_DISP2_DAT11__DISP2_DAT11 (_MX51_PAD_DISP2_DAT11__DISP2_DAT11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1454#define MX51_PAD_DISP2_DAT11__FEC_RX_CLK (_MX51_PAD_DISP2_DAT11__FEC_RX_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1455#define MX51_PAD_DISP2_DAT11__GPIO1_10 (_MX51_PAD_DISP2_DAT11__GPIO1_10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1456#define MX51_PAD_DISP2_DAT11__USBH3_DATA3 (_MX51_PAD_DISP2_DAT11__USBH3_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1457#define MX51_PAD_DISP2_DAT12__AUD6_RXD (_MX51_PAD_DISP2_DAT12__AUD6_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1458#define MX51_PAD_DISP2_DAT12__DISP2_DAT12 (_MX51_PAD_DISP2_DAT12__DISP2_DAT12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1459#define MX51_PAD_DISP2_DAT12__FEC_RX_DV (_MX51_PAD_DISP2_DAT12__FEC_RX_DV | MUX_PAD_CTRL(NO_PAD_CTRL))
1460#define MX51_PAD_DISP2_DAT12__USBH3_DATA4 (_MX51_PAD_DISP2_DAT12__USBH3_DATA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1461#define MX51_PAD_DISP2_DAT13__AUD6_TXC (_MX51_PAD_DISP2_DAT13__AUD6_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1462#define MX51_PAD_DISP2_DAT13__DISP2_DAT13 (_MX51_PAD_DISP2_DAT13__DISP2_DAT13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1463#define MX51_PAD_DISP2_DAT13__FEC_TX_CLK (_MX51_PAD_DISP2_DAT13__FEC_TX_CLK | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
1464#define MX51_PAD_DISP2_DAT13__USBH3_DATA5 (_MX51_PAD_DISP2_DAT13__USBH3_DATA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1465#define MX51_PAD_DISP2_DAT14__AUD6_TXFS (_MX51_PAD_DISP2_DAT14__AUD6_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1466#define MX51_PAD_DISP2_DAT14__DISP2_DAT14 (_MX51_PAD_DISP2_DAT14__DISP2_DAT14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1467#define MX51_PAD_DISP2_DAT14__FEC_RDATA0 (_MX51_PAD_DISP2_DAT14__FEC_RDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_4))
1468#define MX51_PAD_DISP2_DAT14__USBH3_DATA6 (_MX51_PAD_DISP2_DAT14__USBH3_DATA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1469#define MX51_PAD_DISP2_DAT15__AUD6_RXFS (_MX51_PAD_DISP2_DAT15__AUD6_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1470#define MX51_PAD_DISP2_DAT15__DISP1_SER_CS (_MX51_PAD_DISP2_DAT15__DISP1_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1471#define MX51_PAD_DISP2_DAT15__DISP2_DAT15 (_MX51_PAD_DISP2_DAT15__DISP2_DAT15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1472#define MX51_PAD_DISP2_DAT15__FEC_TDATA0 (_MX51_PAD_DISP2_DAT15__FEC_TDATA0 | MUX_PAD_CTRL(MX51_PAD_CTRL_5))
1473#define MX51_PAD_DISP2_DAT15__USBH3_DATA7 (_MX51_PAD_DISP2_DAT15__USBH3_DATA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1474#define MX51_PAD_SD1_CMD__AUD5_RXFS (_MX51_PAD_SD1_CMD__AUD5_RXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1475#define MX51_PAD_SD1_CMD__CSPI_MOSI (_MX51_PAD_SD1_CMD__CSPI_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL))
1476#define MX51_PAD_SD1_CMD__SD1_CMD (_MX51_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1477#define MX51_PAD_SD1_CLK__AUD5_RXC (_MX51_PAD_SD1_CLK__AUD5_RXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1478#define MX51_PAD_SD1_CLK__CSPI_SCLK (_MX51_PAD_SD1_CLK__CSPI_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1479#define MX51_PAD_SD1_CLK__SD1_CLK (_MX51_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1480#define MX51_PAD_SD1_DATA0__AUD5_TXD (_MX51_PAD_SD1_DATA0__AUD5_TXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1481#define MX51_PAD_SD1_DATA0__CSPI_MISO (_MX51_PAD_SD1_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1482#define MX51_PAD_SD1_DATA0__SD1_DATA0 (_MX51_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1483#define MX51_PAD_EIM_DA0__EIM_DA0 (_MX51_PAD_EIM_DA0__EIM_DA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1484#define MX51_PAD_EIM_DA1__EIM_DA1 (_MX51_PAD_EIM_DA1__EIM_DA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1485#define MX51_PAD_EIM_DA2__EIM_DA2 (_MX51_PAD_EIM_DA2__EIM_DA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1486#define MX51_PAD_EIM_DA3__EIM_DA3 (_MX51_PAD_EIM_DA3__EIM_DA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1487#define MX51_PAD_SD1_DATA1__AUD5_RXD (_MX51_PAD_SD1_DATA1__AUD5_RXD | MUX_PAD_CTRL(NO_PAD_CTRL))
1488#define MX51_PAD_SD1_DATA1__SD1_DATA1 (_MX51_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1489#define MX51_PAD_EIM_DA4__EIM_DA4 (_MX51_PAD_EIM_DA4__EIM_DA4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1490#define MX51_PAD_EIM_DA5__EIM_DA5 (_MX51_PAD_EIM_DA5__EIM_DA5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1491#define MX51_PAD_EIM_DA6__EIM_DA6 (_MX51_PAD_EIM_DA6__EIM_DA6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1492#define MX51_PAD_EIM_DA7__EIM_DA7 (_MX51_PAD_EIM_DA7__EIM_DA7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1493#define MX51_PAD_SD1_DATA2__AUD5_TXC (_MX51_PAD_SD1_DATA2__AUD5_TXC | MUX_PAD_CTRL(NO_PAD_CTRL))
1494#define MX51_PAD_SD1_DATA2__SD1_DATA2 (_MX51_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1495#define MX51_PAD_EIM_DA10__EIM_DA10 (_MX51_PAD_EIM_DA10__EIM_DA10 | MUX_PAD_CTRL(NO_PAD_CTRL))
1496#define MX51_PAD_EIM_DA11__EIM_DA11 (_MX51_PAD_EIM_DA11__EIM_DA11 | MUX_PAD_CTRL(NO_PAD_CTRL))
1497#define MX51_PAD_EIM_DA8__EIM_DA8 (_MX51_PAD_EIM_DA8__EIM_DA8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1498#define MX51_PAD_EIM_DA9__EIM_DA9 (_MX51_PAD_EIM_DA9__EIM_DA9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1499#define MX51_PAD_SD1_DATA3__AUD5_TXFS (_MX51_PAD_SD1_DATA3__AUD5_TXFS | MUX_PAD_CTRL(NO_PAD_CTRL))
1500#define MX51_PAD_SD1_DATA3__CSPI_SS1 (_MX51_PAD_SD1_DATA3__CSPI_SS1 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1501#define MX51_PAD_SD1_DATA3__SD1_DATA3 (_MX51_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1502#define MX51_PAD_GPIO1_0__CSPI_SS2 (_MX51_PAD_GPIO1_0__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1503#define MX51_PAD_GPIO1_0__GPIO1_0 (_MX51_PAD_GPIO1_0__GPIO1_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1504#define MX51_PAD_GPIO1_0__SD1_CD (_MX51_PAD_GPIO1_0__SD1_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
1505#define MX51_PAD_GPIO1_1__CSPI_MISO (_MX51_PAD_GPIO1_1__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1506#define MX51_PAD_GPIO1_1__GPIO1_1 (_MX51_PAD_GPIO1_1__GPIO1_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1507#define MX51_PAD_GPIO1_1__SD1_WP (_MX51_PAD_GPIO1_1__SD1_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
1508#define MX51_PAD_EIM_DA12__EIM_DA12 (_MX51_PAD_EIM_DA12__EIM_DA12 | MUX_PAD_CTRL(NO_PAD_CTRL))
1509#define MX51_PAD_EIM_DA13__EIM_DA13 (_MX51_PAD_EIM_DA13__EIM_DA13 | MUX_PAD_CTRL(NO_PAD_CTRL))
1510#define MX51_PAD_EIM_DA14__EIM_DA14 (_MX51_PAD_EIM_DA14__EIM_DA14 | MUX_PAD_CTRL(NO_PAD_CTRL))
1511#define MX51_PAD_EIM_DA15__EIM_DA15 (_MX51_PAD_EIM_DA15__EIM_DA15 | MUX_PAD_CTRL(NO_PAD_CTRL))
1512#define MX51_PAD_SD2_CMD__CSPI_MOSI (_MX51_PAD_SD2_CMD__CSPI_MOSI | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1513#define MX51_PAD_SD2_CMD__I2C1_SCL (_MX51_PAD_SD2_CMD__I2C1_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1514#define MX51_PAD_SD2_CMD__SD2_CMD (_MX51_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL))
1515#define MX51_PAD_SD2_CLK__CSPI_SCLK (_MX51_PAD_SD2_CLK__CSPI_SCLK | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1516#define MX51_PAD_SD2_CLK__I2C1_SDA (_MX51_PAD_SD2_CLK__I2C1_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1517#define MX51_PAD_SD2_CLK__SD2_CLK (_MX51_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS))
1518#define MX51_PAD_SD2_DATA0__CSPI_MISO (_MX51_PAD_SD2_DATA0__CSPI_MISO | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1519#define MX51_PAD_SD2_DATA0__SD1_DAT4 (_MX51_PAD_SD2_DATA0__SD1_DAT4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1520#define MX51_PAD_SD2_DATA0__SD2_DATA0 (_MX51_PAD_SD2_DATA0__SD2_DATA0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1521#define MX51_PAD_SD2_DATA1__SD1_DAT5 (_MX51_PAD_SD2_DATA1__SD1_DAT5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1522#define MX51_PAD_SD2_DATA1__SD2_DATA1 (_MX51_PAD_SD2_DATA1__SD2_DATA1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1523#define MX51_PAD_SD2_DATA1__USBH3_H2_DP (_MX51_PAD_SD2_DATA1__USBH3_H2_DP | MUX_PAD_CTRL(NO_PAD_CTRL))
1524#define MX51_PAD_SD2_DATA2__SD1_DAT6 (_MX51_PAD_SD2_DATA2__SD1_DAT6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1525#define MX51_PAD_SD2_DATA2__SD2_DATA2 (_MX51_PAD_SD2_DATA2__SD2_DATA2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1526#define MX51_PAD_SD2_DATA2__USBH3_H2_DM (_MX51_PAD_SD2_DATA2__USBH3_H2_DM | MUX_PAD_CTRL(NO_PAD_CTRL))
1527#define MX51_PAD_SD2_DATA3__CSPI_SS2 (_MX51_PAD_SD2_DATA3__CSPI_SS2 | MUX_PAD_CTRL(MX51_ECSPI_PAD_CTRL))
1528#define MX51_PAD_SD2_DATA3__SD1_DAT7 (_MX51_PAD_SD2_DATA3__SD1_DAT7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1529#define MX51_PAD_SD2_DATA3__SD2_DATA3 (_MX51_PAD_SD2_DATA3__SD2_DATA3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1530#define MX51_PAD_GPIO1_2__CCM_OUT_2 (_MX51_PAD_GPIO1_2__CCM_OUT_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1531#define MX51_PAD_GPIO1_2__GPIO1_2 (_MX51_PAD_GPIO1_2__GPIO1_2 | MUX_PAD_CTRL(NO_PAD_CTRL))
1532#define MX51_PAD_GPIO1_2__I2C2_SCL (_MX51_PAD_GPIO1_2__I2C2_SCL | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1533#define MX51_PAD_GPIO1_2__PLL1_BYP (_MX51_PAD_GPIO1_2__PLL1_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1534#define MX51_PAD_GPIO1_2__PWM1_PWMO (_MX51_PAD_GPIO1_2__PWM1_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
1535#define MX51_PAD_GPIO1_3__GPIO1_3 (_MX51_PAD_GPIO1_3__GPIO1_3 | MUX_PAD_CTRL(NO_PAD_CTRL))
1536#define MX51_PAD_GPIO1_3__I2C2_SDA (_MX51_PAD_GPIO1_3__I2C2_SDA | MUX_PAD_CTRL(MX51_I2C_PAD_CTRL))
1537#define MX51_PAD_GPIO1_3__PLL2_BYP (_MX51_PAD_GPIO1_3__PLL2_BYP | MUX_PAD_CTRL(NO_PAD_CTRL))
1538#define MX51_PAD_GPIO1_3__PWM2_PWMO (_MX51_PAD_GPIO1_3__PWM2_PWMO | MUX_PAD_CTRL(NO_PAD_CTRL))
1539#define MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ (_MX51_PAD_PMIC_INT_REQ__PMIC_INT_REQ | MUX_PAD_CTRL(NO_PAD_CTRL))
1540#define MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B (_MX51_PAD_PMIC_INT_REQ__PMIC_PMU_IRQ_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1541#define MX51_PAD_GPIO1_4__DISP2_EXT_CLK (_MX51_PAD_GPIO1_4__DISP2_EXT_CLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1542#define MX51_PAD_GPIO1_4__EIM_RDY (_MX51_PAD_GPIO1_4__EIM_RDY | MUX_PAD_CTRL(NO_PAD_CTRL))
1543#define MX51_PAD_GPIO1_4__GPIO1_4 (_MX51_PAD_GPIO1_4__GPIO1_4 | MUX_PAD_CTRL(NO_PAD_CTRL))
1544#define MX51_PAD_GPIO1_4__WDOG1_WDOG_B (_MX51_PAD_GPIO1_4__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1545#define MX51_PAD_GPIO1_5__CSI2_MCLK (_MX51_PAD_GPIO1_5__CSI2_MCLK | MUX_PAD_CTRL(NO_PAD_CTRL))
1546#define MX51_PAD_GPIO1_5__DISP2_PIN16 (_MX51_PAD_GPIO1_5__DISP2_PIN16 | MUX_PAD_CTRL(NO_PAD_CTRL))
1547#define MX51_PAD_GPIO1_5__GPIO1_5 (_MX51_PAD_GPIO1_5__GPIO1_5 | MUX_PAD_CTRL(NO_PAD_CTRL))
1548#define MX51_PAD_GPIO1_5__WDOG2_WDOG_B (_MX51_PAD_GPIO1_5__WDOG2_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1549#define MX51_PAD_GPIO1_6__DISP2_PIN17 (_MX51_PAD_GPIO1_6__DISP2_PIN17 | MUX_PAD_CTRL(NO_PAD_CTRL))
1550#define MX51_PAD_GPIO1_6__GPIO1_6 (_MX51_PAD_GPIO1_6__GPIO1_6 | MUX_PAD_CTRL(NO_PAD_CTRL))
1551#define MX51_PAD_GPIO1_6__REF_EN_B (_MX51_PAD_GPIO1_6__REF_EN_B | MUX_PAD_CTRL(NO_PAD_CTRL))
1552#define MX51_PAD_GPIO1_7__CCM_OUT_0 (_MX51_PAD_GPIO1_7__CCM_OUT_0 | MUX_PAD_CTRL(NO_PAD_CTRL))
1553#define MX51_PAD_GPIO1_7__GPIO1_7 (_MX51_PAD_GPIO1_7__GPIO1_7 | MUX_PAD_CTRL(NO_PAD_CTRL))
1554#define MX51_PAD_GPIO1_7__SD2_WP (_MX51_PAD_GPIO1_7__SD2_WP | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
1555#define MX51_PAD_GPIO1_7__SPDIF_OUT1 (_MX51_PAD_GPIO1_7__SPDIF_OUT1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1556#define MX51_PAD_GPIO1_8__CSI2_DATA_EN (_MX51_PAD_GPIO1_8__CSI2_DATA_EN | MUX_PAD_CTRL(NO_PAD_CTRL))
1557#define MX51_PAD_GPIO1_8__GPIO1_8 (_MX51_PAD_GPIO1_8__GPIO1_8 | MUX_PAD_CTRL(NO_PAD_CTRL))
1558#define MX51_PAD_GPIO1_8__SD2_CD (_MX51_PAD_GPIO1_8__SD2_CD | MUX_PAD_CTRL(MX51_ESDHC_PAD_CTRL))
1559#define MX51_PAD_GPIO1_8__USBH3_PWR (_MX51_PAD_GPIO1_8__USBH3_PWR | MUX_PAD_CTRL(NO_PAD_CTRL))
1560#define MX51_PAD_GPIO1_9__CCM_OUT_1 (_MX51_PAD_GPIO1_9__CCM_OUT_1 | MUX_PAD_CTRL(NO_PAD_CTRL))
1561#define MX51_PAD_GPIO1_9__DISP2_D1_CS (_MX51_PAD_GPIO1_9__DISP2_D1_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1562#define MX51_PAD_GPIO1_9__DISP2_SER_CS (_MX51_PAD_GPIO1_9__DISP2_SER_CS | MUX_PAD_CTRL(NO_PAD_CTRL))
1563#define MX51_PAD_GPIO1_9__GPIO1_9 (_MX51_PAD_GPIO1_9__GPIO1_9 | MUX_PAD_CTRL(NO_PAD_CTRL))
1564#define MX51_PAD_GPIO1_9__SD2_LCTL (_MX51_PAD_GPIO1_9__SD2_LCTL | MUX_PAD_CTRL(NO_PAD_CTRL))
1565#define MX51_PAD_GPIO1_9__USBH3_OC (_MX51_PAD_GPIO1_9__USBH3_OC | MUX_PAD_CTRL(NO_PAD_CTRL))
386 1566
387#endif /* __MACH_IOMUX_MX51_H__ */ 1567#endif /* __MACH_IOMUX_MX51_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx53.h b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
new file mode 100644
index 000000000000..5deee019c29e
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx53.h
@@ -0,0 +1,323 @@
1/*
2 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc..
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#ifndef __MACH_IOMUX_MX53_H__
20#define __MACH_IOMUX_MX53_H__
21
22#include <mach/iomux-v3.h>
23
24/*
25 * various IOMUX alternate output functions (1-7)
26 */
27typedef enum iomux_config {
28 IOMUX_CONFIG_ALT0,
29 IOMUX_CONFIG_ALT1,
30 IOMUX_CONFIG_ALT2,
31 IOMUX_CONFIG_ALT3,
32 IOMUX_CONFIG_ALT4,
33 IOMUX_CONFIG_ALT5,
34 IOMUX_CONFIG_ALT6,
35 IOMUX_CONFIG_ALT7,
36 IOMUX_CONFIG_GPIO, /* added to help user use GPIO mode */
37 IOMUX_CONFIG_SION = 0x1 << 4, /* LOOPBACK:MUX SION bit */
38} iomux_pin_cfg_t;
39
40/* These 2 defines are for pins that may not have a mux register, but could
41 * have a pad setting register, and vice-versa. */
42#define NON_MUX_I 0x00
43#define NON_PAD_I 0x00
44
45#define MX53_UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
46 PAD_CTL_DSE_HIGH | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
47/* UART1 */
48#define MX53_PAD_CSI0_D10__UART1_TXD IOMUX_PAD(0x414, 0xE8, 2, 0x0, 0, MX53_UART_PAD_CTRL)
49#define MX53_PAD_CSI0_D11__UART1_RXD IOMUX_PAD(0x418, 0xEC, 2, 0x878, 1, MX53_UART_PAD_CTRL)
50#define MX53_PAD_ATA_DIOW__UART1_TXD IOMUX_PAD(0x5F0, 0x270, 3, 0x0, 0, MX53_UART_PAD_CTRL)
51#define MX53_PAD_ATA_DMACK__UART1_RXD IOMUX_PAD(0x5F4, 0x274, 3, 0x880, 3, MX53_UART_PAD_CTRL)
52
53/* UART2 */
54#define MX53_PAD_ATA_BUFFER_EN__UART2_RXD IOMUX_PAD(0x5FC, 0x27C, 3, 0x880, 3, MX53_UART_PAD_CTRL)
55#define MX53_PAD_ATA_DMARQ__UART2_TXD IOMUX_PAD(0x5F8, 0x278, 3, 0x0, 0, MX53_UART_PAD_CTRL)
56#define MX53_PAD_ATA_DIOR__UART2_RTS IOMUX_PAD(0x604, 0x284, 3, 0x87C, 3, MX53_UART_PAD_CTRL)
57#define MX53_PAD_ATA_INTRQ__UART2_CTS IOMUX_PAD(0x600, 0x280, 3, 0x0, 0, MX53_UART_PAD_CTRL)
58
59/* UART3 */
60#define MX53_PAD_ATA_CS_0__UART3_TXD IOMUX_PAD(0x61C, 0x29C, 4, 0x0, 0, MX53_UART_PAD_CTRL)
61#define MX53_PAD_ATA_CS_1__UART3_RXD IOMUX_PAD(0x620, 0x2A0, 4, 0x888, 3, MX53_UART_PAD_CTRL)
62#define MX53_PAD_ATA_DA_1__UART3_CTS IOMUX_PAD(0x614, 0x294, 4, 0x0, 0, MX53_UART_PAD_CTRL)
63#define MX53_PAD_ATA_DA_2__UART3_RTS IOMUX_PAD(0x618, 0x298, 4, 0x884, 5, MX53_UART_PAD_CTRL)
64
65#define MX53_PAD_GPIO_19__GPIO_4_5 IOMUX_PAD(0x348, 0x20,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
66#define MX53_PAD_KEY_COL0__GPIO_4_6 IOMUX_PAD(0x34C, 0x24,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
67#define MX53_PAD_KEY_ROW0__GPIO_4_7 IOMUX_PAD(0x350, 0x28,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
68#define MX53_PAD_KEY_COL1__GPIO_4_8 IOMUX_PAD(0x354, 0x2C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
69#define MX53_PAD_KEY_ROW1__GPIO_4_9 IOMUX_PAD(0x358, 0x30,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
70#define MX53_PAD_KEY_COL2__GPIO_4_10 IOMUX_PAD(0x35C, 0x34,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
71#define MX53_PAD_KEY_ROW2__GPIO_4_11 IOMUX_PAD(0x360, 0x38,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
72#define MX53_PAD_KEY_COL3__GPIO_4_12 IOMUX_PAD(0x364, 0x3C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
73#define MX53_PAD_KEY_ROW3__GPIO_4_13 IOMUX_PAD(0x368, 0x40,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
74#define MX53_PAD_KEY_COL4__GPIO_4_14 IOMUX_PAD(0x36C, 0x44,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
75#define MX53_PAD_KEY_ROW4__GPIO_4_15 IOMUX_PAD(0x370, 0x48,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
76#define MX53_PAD_NVCC_KEYPAD__NVCC_KEYPAD IOMUX_PAD(0x374, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
77#define MX53_PAD_DI0_DISP_CLK__GPIO_4_16 IOMUX_PAD(0x378, 0x4C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
78#define MX53_PAD_DI0_PIN15__GPIO_4_17 IOMUX_PAD(0x37C, 0x50,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
79#define MX53_PAD_DI0_PIN2__GPIO_4_18 IOMUX_PAD(0x380, 0x54,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
80#define MX53_PAD_DI0_PIN3__GPIO_4_19 IOMUX_PAD(0x384, 0x58,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
81#define MX53_PAD_DI0_PIN4__GPIO_4_20 IOMUX_PAD(0x388, 0x5C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
82#define MX53_PAD_DISP0_DAT0__GPIO_4_21 IOMUX_PAD(0x38C, 0x60,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
83#define MX53_PAD_DISP0_DAT1__GPIO_4_22 IOMUX_PAD(0x390, 0x64,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
84#define MX53_PAD_DISP0_DAT2__GPIO_4_23 IOMUX_PAD(0x394, 0x68,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
85#define MX53_PAD_DISP0_DAT3__GPIO_4_24 IOMUX_PAD(0x398, 0x6C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
86#define MX53_PAD_DISP0_DAT4__GPIO_4_25 IOMUX_PAD(0x39C, 0x70,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
87#define MX53_PAD_DISP0_DAT5__GPIO_4_26 IOMUX_PAD(0x3A0, 0x74,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
88#define MX53_PAD_DISP0_DAT6__GPIO_4_27 IOMUX_PAD(0x3A4, 0x78,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
89#define MX53_PAD_DISP0_DAT7__GPIO_4_28 IOMUX_PAD(0x3A8, 0x7C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
90#define MX53_PAD_DISP0_DAT8__GPIO_4_29 IOMUX_PAD(0x3AC, 0x80,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
91#define MX53_PAD_DISP0_DAT9__GPIO_4_30 IOMUX_PAD(0x3B0, 0x84,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
92#define MX53_PAD_DISP0_DAT10__GPIO_4_31 IOMUX_PAD(0x3B4, 0x88,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
93#define MX53_PAD_DISP0_DAT11__GPIO_5_5 IOMUX_PAD(0x3B8, 0x8C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
94#define MX53_PAD_DISP0_DAT12__GPIO_5_6 IOMUX_PAD(0x3BC, 0x90,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
95#define MX53_PAD_DISP0_DAT13__GPIO_5_7 IOMUX_PAD(0x3C0, 0x94,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
96#define MX53_PAD_DISP0_DAT14__GPIO_5_8 IOMUX_PAD(0x3C4, 0x98,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
97#define MX53_PAD_DISP0_DAT15__GPIO_5_9 IOMUX_PAD(0x3C8, 0x9C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
98#define MX53_PAD_DISP0_DAT16__GPIO_5_10 IOMUX_PAD(0x3CC, 0xA0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
99#define MX53_PAD_DISP0_DAT17__GPIO_5_11 IOMUX_PAD(0x3D0, 0xA4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
100#define MX53_PAD_DISP0_DAT18__GPIO_5_12 IOMUX_PAD(0x3D4, 0xA8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
101#define MX53_PAD_DISP0_DAT19__GPIO_5_13 IOMUX_PAD(0x3D8, 0xAC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
102#define MX53_PAD_DISP0_DAT20__GPIO_5_14 IOMUX_PAD(0x3DC, 0xB0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
103#define MX53_PAD_DISP0_DAT21__GPIO_5_15 IOMUX_PAD(0x3E0, 0xB4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
104#define MX53_PAD_DISP0_DAT22__GPIO_5_16 IOMUX_PAD(0x3E4, 0xB8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
105#define MX53_PAD_DISP0_DAT23__GPIO_5_17 IOMUX_PAD(0x3E8, 0xBC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
106#define MX53_PAD_CSI0_PIXCLK__GPIO_5_18 IOMUX_PAD(0x3EC, 0xC0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
107#define MX53_PAD_CSI0_MCLK__GPIO_5_19 IOMUX_PAD(0x3F0, 0xC4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
108#define MX53_PAD_CSI0_DATA_EN__GPIO_5_20 IOMUX_PAD(0x3F4, 0xC8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
109#define MX53_PAD_CSI0_VSYNC__GPIO_5_21 IOMUX_PAD(0x3F8, 0xCC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
110#define MX53_PAD_CSI0_D4__GPIO_5_22 IOMUX_PAD(0x3FC, 0xD0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
111#define MX53_PAD_CSI0_D5__GPIO_5_23 IOMUX_PAD(0x400, 0xD4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
112#define MX53_PAD_CSI0_D6__GPIO_5_24 IOMUX_PAD(0x404, 0xD8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
113#define MX53_PAD_CSI0_D7__GPIO_5_25 IOMUX_PAD(0x408, 0xDC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
114#define MX53_PAD_CSI0_D8__GPIO_5_26 IOMUX_PAD(0x40C, 0xE0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
115#define MX53_PAD_CSI0_D9__GPIO_5_27 IOMUX_PAD(0x410, 0xE4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
116#define MX53_PAD_CSI0_D10__GPIO_5_28 IOMUX_PAD(0x414, 0xE8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
117#define MX53_PAD_CSI0_D11__GPIO_5_29 IOMUX_PAD(0x418, 0xEC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
118#define MX53_PAD_CSI0_D12__GPIO_5_30 IOMUX_PAD(0x41C, 0xF0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
119#define MX53_PAD_CSI0_D13__GPIO_5_31 IOMUX_PAD(0x420, 0xF4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
120#define MX53_PAD_CSI0_D14__GPIO_6_0 IOMUX_PAD(0x424, 0xF8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
121#define MX53_PAD_CSI0_D15__GPIO_6_1 IOMUX_PAD(0x428, 0xFC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
122#define MX53_PAD_CSI0_D16__GPIO_6_2 IOMUX_PAD(0x42C, 0x100,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
123#define MX53_PAD_CSI0_D17__GPIO_6_3 IOMUX_PAD(0x430, 0x104,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
124#define MX53_PAD_CSI0_D18__GPIO_6_4 IOMUX_PAD(0x434, 0x108,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
125#define MX53_PAD_CSI0_D19__GPIO_6_5 IOMUX_PAD(0x438, 0x10C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
126#define MX53_PAD_NVCC_CSI0__NVCC_CSI0 IOMUX_PAD(0x43C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
127#define MX53_PAD_JTAG_TMS__JTAG_TMS IOMUX_PAD(0x440, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
128#define MX53_PAD_JTAG_MOD__JTAG_MOD IOMUX_PAD(0x444, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
129#define MX53_PAD_JTAG_TRSTB__JTAG_TRSTB IOMUX_PAD(0x448, NON_MUX_I,IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
130#define MX53_PAD_JTAG_TDI__JTAG_TDI IOMUX_PAD(0x44C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
131#define MX53_PAD_JTAG_TCK__JTAG_TCK IOMUX_PAD(0x450, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
132#define MX53_PAD_JTAG_TDO__JTAG_TDO IOMUX_PAD(0x454, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
133#define MX53_PAD_EIM_A25__GPIO_5_2 IOMUX_PAD(0x458, 0x110,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
134#define MX53_PAD_EIM_EB2__GPIO_2_30 IOMUX_PAD(0x45C, 0x114,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
135#define MX53_PAD_EIM_D16__GPIO_3_16 IOMUX_PAD(0x460, 0x118,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
136#define MX53_PAD_EIM_D17__GPIO_3_17 IOMUX_PAD(0x464, 0x11C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
137#define MX53_PAD_EIM_D18__GPIO_3_18 IOMUX_PAD(0x468, 0x120,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
138#define MX53_PAD_EIM_D19__GPIO_3_19 IOMUX_PAD(0x46C, 0x124,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
139#define MX53_PAD_EIM_D20__GPIO_3_20 IOMUX_PAD(0x470, 0x128,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
140#define MX53_PAD_EIM_D21__GPIO_3_21 IOMUX_PAD(0x474, 0x12C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
141#define MX53_PAD_EIM_D22__GPIO_3_22 IOMUX_PAD(0x478, 0x130,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
142#define MX53_PAD_EIM_D23__GPIO_3_23 IOMUX_PAD(0x47C, 0x134,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
143#define MX53_PAD_EIM_EB3__GPIO_2_31 IOMUX_PAD(0x480, 0x138,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
144#define MX53_PAD_EIM_D24__GPIO_3_24 IOMUX_PAD(0x484, 0x13C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
145#define MX53_PAD_EIM_D25__GPIO_3_25 IOMUX_PAD(0x488, 0x140,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
146#define MX53_PAD_EIM_D26__GPIO_3_26 IOMUX_PAD(0x48C, 0x144,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
147#define MX53_PAD_EIM_D27__GPIO_3_27 IOMUX_PAD(0x490, 0x148,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
148#define MX53_PAD_EIM_D28__GPIO_3_28 IOMUX_PAD(0x494, 0x14C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
149#define MX53_PAD_EIM_D29__GPIO_3_29 IOMUX_PAD(0x498, 0x150,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
150#define MX53_PAD_EIM_D30__GPIO_3_30 IOMUX_PAD(0x49C, 0x154,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
151#define MX53_PAD_EIM_D31__GPIO_3_31 IOMUX_PAD(0x4A0, 0x158,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
152#define MX53_PAD_NVCC_EIM1__NVCC_EIM1 IOMUX_PAD(0x4A4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
153#define MX53_PAD_EIM_A24__GPIO_5_4 IOMUX_PAD(0x4A8, 0x15C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
154#define MX53_PAD_EIM_A23__GPIO_6_6 IOMUX_PAD(0x4AC, 0x160,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
155#define MX53_PAD_EIM_A22__GPIO_2_16 IOMUX_PAD(0x4B0, 0x164,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
156#define MX53_PAD_EIM_A21__GPIO_2_17 IOMUX_PAD(0x4B4, 0x168,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
157#define MX53_PAD_EIM_A20__GPIO_2_18 IOMUX_PAD(0x4B8, 0x16C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
158#define MX53_PAD_EIM_A19__GPIO_2_19 IOMUX_PAD(0x4BC, 0x170,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
159#define MX53_PAD_EIM_A18__GPIO_2_20 IOMUX_PAD(0x4C0, 0x174,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
160#define MX53_PAD_EIM_A17__GPIO_2_21 IOMUX_PAD(0x4C4, 0x178,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
161#define MX53_PAD_EIM_A16__GPIO_2_22 IOMUX_PAD(0x4C8, 0x17C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
162#define MX53_PAD_EIM_CS0__GPIO_2_23 IOMUX_PAD(0x4CC, 0x180,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
163#define MX53_PAD_EIM_CS1__GPIO_2_24 IOMUX_PAD(0x4D0, 0x184,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
164#define MX53_PAD_EIM_OE__GPIO_2_25 IOMUX_PAD(0x4D4, 0x188,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
165#define MX53_PAD_EIM_RW__GPIO_2_26 IOMUX_PAD(0x4D8, 0x18C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
166#define MX53_PAD_EIM_LBA__GPIO_2_27 IOMUX_PAD(0x4DC, 0x190,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
167#define MX53_PAD_NVCC_EIM4__NVCC_EIM4 IOMUX_PAD(0x4E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
168#define MX53_PAD_EIM_EB0__GPIO_2_28 IOMUX_PAD(0x4E4, 0x194,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
169#define MX53_PAD_EIM_EB1__GPIO_2_29 IOMUX_PAD(0x4E8, 0x198,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
170#define MX53_PAD_EIM_DA0__GPIO_3_0 IOMUX_PAD(0x4EC, 0x19C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
171#define MX53_PAD_EIM_DA1__GPIO_3_1 IOMUX_PAD(0x4F0, 0x1A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
172#define MX53_PAD_EIM_DA2__GPIO_3_2 IOMUX_PAD(0x4F4, 0x1A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
173#define MX53_PAD_EIM_DA3__GPIO_3_3 IOMUX_PAD(0x4F8, 0x1A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
174#define MX53_PAD_EIM_DA4__GPIO_3_4 IOMUX_PAD(0x4FC, 0x1AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
175#define MX53_PAD_EIM_DA5__GPIO_3_5 IOMUX_PAD(0x500, 0x1B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
176#define MX53_PAD_EIM_DA6__GPIO_3_6 IOMUX_PAD(0x504, 0x1B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
177#define MX53_PAD_EIM_DA7__GPIO_3_7 IOMUX_PAD(0x508, 0x1B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
178#define MX53_PAD_EIM_DA8__GPIO_3_8 IOMUX_PAD(0x50C, 0x1BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
179#define MX53_PAD_EIM_DA9__GPIO_3_9 IOMUX_PAD(0x510, 0x1C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
180#define MX53_PAD_EIM_DA10__GPIO_3_10 IOMUX_PAD(0x514, 0x1C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
181#define MX53_PAD_EIM_DA11__GPIO_3_11 IOMUX_PAD(0x518, 0x1C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
182#define MX53_PAD_EIM_DA12__GPIO_3_12 IOMUX_PAD(0x51C, 0x1CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
183#define MX53_PAD_EIM_DA13__GPIO_3_13 IOMUX_PAD(0x520, 0x1D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
184#define MX53_PAD_EIM_DA14__GPIO_3_14 IOMUX_PAD(0x524, 0x1D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
185#define MX53_PAD_EIM_DA15__GPIO_3_15 IOMUX_PAD(0x528, 0x1D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
186#define MX53_PAD_NANDF_WE_B__GPIO_6_12 IOMUX_PAD(0x52C, 0x1DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
187#define MX53_PAD_NANDF_RE_B__GPIO_6_13 IOMUX_PAD(0x530, 0x1E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
188#define MX53_PAD_EIM_WAIT__GPIO_5_0 IOMUX_PAD(0x534, 0x1E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
189#define MX53_PAD_EIM_BCLK__EIM_BCLK IOMUX_PAD(0x538, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
190#define MX53_PAD_NVCC_EIM7__NVCC_EIM7 IOMUX_PAD(0x53C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
191#define MX53_PAD_LVDS1_TX3_P__GPIO_6_22 IOMUX_PAD(NON_PAD_I, 0x1EC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
192#define MX53_PAD_LVDS1_TX2_P__GPIO_6_24 IOMUX_PAD(NON_PAD_I, 0x1F0, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
193#define MX53_PAD_LVDS1_CLK_P__GPIO_6_26 IOMUX_PAD(NON_PAD_I, 0x1F4, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
194#define MX53_PAD_LVDS1_TX1_P__GPIO_6_28 IOMUX_PAD(NON_PAD_I, 0x1F8, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
195#define MX53_PAD_LVDS1_TX0_P__GPIO_6_30 IOMUX_PAD(NON_PAD_I, 0x1FC, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
196#define MX53_PAD_LVDS0_TX3_P__GPIO_7_22 IOMUX_PAD(NON_PAD_I, 0x200, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
197#define MX53_PAD_LVDS0_CLK_P__GPIO_7_24 IOMUX_PAD(NON_PAD_I, 0x204, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
198#define MX53_PAD_LVDS0_TX2_P__GPIO_7_26 IOMUX_PAD(NON_PAD_I, 0x208, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
199#define MX53_PAD_LVDS0_TX1_P__GPIO_7_28 IOMUX_PAD(NON_PAD_I, 0x20C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
200#define MX53_PAD_LVDS0_TX0_P__GPIO_7_30 IOMUX_PAD(NON_PAD_I, 0x210, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
201#define MX53_PAD_GPIO_10__GPIO_4_0 IOMUX_PAD(0x540, 0x214, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
202#define MX53_PAD_GPIO_11__GPIO_4_1 IOMUX_PAD(0x544, 0x218, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
203#define MX53_PAD_GPIO_12__GPIO_4_2 IOMUX_PAD(0x548, 0x21C, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
204#define MX53_PAD_GPIO_13__GPIO_4_3 IOMUX_PAD(0x54C, 0x220, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
205#define MX53_PAD_GPIO_14__GPIO_4_4 IOMUX_PAD(0x550, 0x224, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
206#define MX53_PAD_DRAM_DQM3__DRAM_DQM3 IOMUX_PAD(0x554, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
207#define MX53_PAD_DRAM_SDQS3__DRAM_SDQS3 IOMUX_PAD(0x558, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
208#define MX53_PAD_DRAM_SDCKE1__DRAM_SDCKE1 IOMUX_PAD(0x55C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
209#define MX53_PAD_DRAM_DQM2__DRAM_DQM2 IOMUX_PAD(0x560, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
210#define MX53_PAD_DRAM_SDODT1__DRAM_SDODT1 IOMUX_PAD(0x564, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
211#define MX53_PAD_DRAM_SDQS2__DRAM_SDQS2 IOMUX_PAD(0x568, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
212#define MX53_PAD_DRAM_RESET__DRAM_RESET IOMUX_PAD(0x56C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
213#define MX53_PAD_DRAM_SDCLK1__DRAM_SDCLK1 IOMUX_PAD(0x570, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
214#define MX53_PAD_DRAM_CAS__DRAM_CAS IOMUX_PAD(0x574, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
215#define MX53_PAD_DRAM_SDCLK0__DRAM_SDCLK0 IOMUX_PAD(0x578, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
216#define MX53_PAD_DRAM_SDQS0__DRAM_SDQS0 IOMUX_PAD(0x57C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
217#define MX53_PAD_DRAM_SDODT0__DRAM_SDODT0 IOMUX_PAD(0x580, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
218#define MX53_PAD_DRAM_DQM0__DRAM_DQM0 IOMUX_PAD(0x584, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
219#define MX53_PAD_DRAM_RAS__DRAM_RAS IOMUX_PAD(0x588, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
220#define MX53_PAD_DRAM_SDCKE0__DRAM_SDCKE0 IOMUX_PAD(0x58C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
221#define MX53_PAD_DRAM_SDQS1__DRAM_SDQS1 IOMUX_PAD(0x590, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
222#define MX53_PAD_DRAM_DQM1__DRAM_DQM1 IOMUX_PAD(0x594, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
223#define MX53_PAD_PMIC_ON_REQ__PMIC_ON_REQ IOMUX_PAD(0x598, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
224#define MX53_PAD_PMIC_STBY_REQ__PMIC_STBY_REQ IOMUX_PAD(0x59C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
225#define MX53_PAD_NANDF_CLE__GPIO_6_7 IOMUX_PAD(0x5A0, 0x228,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
226#define MX53_PAD_NANDF_ALE__GPIO_6_8 IOMUX_PAD(0x5A4, 0x22C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
227#define MX53_PAD_NANDF_WP_B__GPIO_6_9 IOMUX_PAD(0x5A8, 0x230,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
228#define MX53_PAD_NANDF_RB0__GPIO_6_10 IOMUX_PAD(0x5AC, 0x234,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
229#define MX53_PAD_NANDF_CS0__GPIO_6_11 IOMUX_PAD(0x5B0, 0x238,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
230#define MX53_PAD_NANDF_CS1__GPIO_6_14 IOMUX_PAD(0x5B4, 0x23C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
231#define MX53_PAD_NANDF_CS2__GPIO_6_15 IOMUX_PAD(0x5B8, 0x240,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
232#define MX53_PAD_NANDF_CS3__GPIO_6_16 IOMUX_PAD(0x5BC, 0x244,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
233#define MX53_PAD_NVCC_NANDF__NVCC_NANDF IOMUX_PAD(0x5C0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
234#define MX53_PAD_FEC_MDIO__GPIO_1_22 IOMUX_PAD(0x5C4, 0x248,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
235#define MX53_PAD_FEC_REF_CLK__GPIO_1_23 IOMUX_PAD(0x5C8, 0x24C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
236#define MX53_PAD_FEC_RX_ER__GPIO_1_24 IOMUX_PAD(0x5CC, 0x250,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
237#define MX53_PAD_FEC_CRS_DV__GPIO_1_25 IOMUX_PAD(0x5D0, 0x254,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
238#define MX53_PAD_FEC_RXD1__GPIO_1_26 IOMUX_PAD(0x5D4, 0x258,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
239#define MX53_PAD_FEC_RXD0__GPIO_1_27 IOMUX_PAD(0x5D8, 0x25C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
240#define MX53_PAD_FEC_TX_EN__GPIO_1_28 IOMUX_PAD(0x5DC, 0x260,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
241#define MX53_PAD_FEC_TXD1__GPIO_1_29 IOMUX_PAD(0x5E0, 0x264,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
242#define MX53_PAD_FEC_TXD0__GPIO_1_30 IOMUX_PAD(0x5E4, 0x268,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
243#define MX53_PAD_FEC_MDC__GPIO_1_31 IOMUX_PAD(0x5E8, 0x26C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
244#define MX53_PAD_NVCC_FEC__NVCC_FEC IOMUX_PAD(0x5EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
245#define MX53_PAD_ATA_DIOW__GPIO_6_17 IOMUX_PAD(0x5F0, 0x270,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
246#define MX53_PAD_ATA_DMACK__GPIO_6_18 IOMUX_PAD(0x5F4, 0x274,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
247#define MX53_PAD_ATA_DMARQ__GPIO_7_0 IOMUX_PAD(0x5F8, 0x278,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
248#define MX53_PAD_ATA_BUFFER_EN__GPIO_7_1 IOMUX_PAD(0x5FC, 0x27C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
249#define MX53_PAD_ATA_INTRQ__GPIO_7_2 IOMUX_PAD(0x600, 0x280,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
250#define MX53_PAD_ATA_DIOR__GPIO_7_3 IOMUX_PAD(0x604, 0x284,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
251#define MX53_PAD_ATA_RESET_B__GPIO_7_4 IOMUX_PAD(0x608, 0x288,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
252#define MX53_PAD_ATA_IORDY__GPIO_7_5 IOMUX_PAD(0x60C, 0x28C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
253#define MX53_PAD_ATA_DA_0__GPIO_7_6 IOMUX_PAD(0x610, 0x290,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
254#define MX53_PAD_ATA_DA_1__GPIO_7_7 IOMUX_PAD(0x614, 0x294,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
255#define MX53_PAD_ATA_DA_2__GPIO_7_8 IOMUX_PAD(0x618, 0x298,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
256#define MX53_PAD_ATA_CS_0__GPIO_7_9 IOMUX_PAD(0x61C, 0x29C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
257#define MX53_PAD_ATA_CS_1__GPIO_7_10 IOMUX_PAD(0x620, 0x2A0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
258#define MX53_PAD_NVCC_ATA2__NVCC_ATA2 IOMUX_PAD(0x624, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
259#define MX53_PAD_ATA_DATA0__GPIO_2_0 IOMUX_PAD(0x628, 0x2A4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
260#define MX53_PAD_ATA_DATA1__GPIO_2_1 IOMUX_PAD(0x62C, 0x2A8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
261#define MX53_PAD_ATA_DATA2__GPIO_2_2 IOMUX_PAD(0x630, 0x2AC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
262#define MX53_PAD_ATA_DATA3__GPIO_2_3 IOMUX_PAD(0x634, 0x2B0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
263#define MX53_PAD_ATA_DATA4__GPIO_2_4 IOMUX_PAD(0x638, 0x2B4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
264#define MX53_PAD_ATA_DATA5__GPIO_2_5 IOMUX_PAD(0x63C, 0x2B8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
265#define MX53_PAD_ATA_DATA6__GPIO_2_6 IOMUX_PAD(0x640, 0x2BC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
266#define MX53_PAD_ATA_DATA7__GPIO_2_7 IOMUX_PAD(0x644, 0x2C0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
267#define MX53_PAD_ATA_DATA8__GPIO_2_8 IOMUX_PAD(0x648, 0x2C4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
268#define MX53_PAD_ATA_DATA9__GPIO_2_9 IOMUX_PAD(0x64C, 0x2C8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
269#define MX53_PAD_ATA_DATA10__GPIO_2_10 IOMUX_PAD(0x650, 0x2CC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
270#define MX53_PAD_ATA_DATA11__GPIO_2_11 IOMUX_PAD(0x654, 0x2D0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
271#define MX53_PAD_ATA_DATA12__GPIO_2_12 IOMUX_PAD(0x658, 0x2D4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
272#define MX53_PAD_ATA_DATA13__GPIO_2_13 IOMUX_PAD(0x65C, 0x2D8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
273#define MX53_PAD_ATA_DATA14__GPIO_2_14 IOMUX_PAD(0x660, 0x2DC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
274#define MX53_PAD_ATA_DATA15__GPIO_2_15 IOMUX_PAD(0x664, 0x2E0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
275#define MX53_PAD_NVCC_ATA0__NVCC_ATA0 IOMUX_PAD(0x668, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
276#define MX53_PAD_SD1_DATA0__GPIO_1_16 IOMUX_PAD(0x66C, 0x2E4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
277#define MX53_PAD_SD1_DATA1__GPIO_1_17 IOMUX_PAD(0x670, 0x2E8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
278#define MX53_PAD_SD1_CMD__GPIO_1_18 IOMUX_PAD(0x674, 0x2EC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
279#define MX53_PAD_SD1_DATA2__GPIO_1_19 IOMUX_PAD(0x678, 0x2F0,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
280#define MX53_PAD_SD1_CLK__GPIO_1_20 IOMUX_PAD(0x67C, 0x2F4,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
281#define MX53_PAD_SD1_DATA3__GPIO_1_21 IOMUX_PAD(0x680, 0x2F8,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
282#define MX53_PAD_NVCC_SD1__NVCC_SD1 IOMUX_PAD(0x684, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
283#define MX53_PAD_SD2_CLK__GPIO_1_10 IOMUX_PAD(0x688, 0x2FC,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
284#define MX53_PAD_SD2_CMD__GPIO_1_11 IOMUX_PAD(0x68C, 0x300,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
285#define MX53_PAD_SD2_DATA3__GPIO_1_12 IOMUX_PAD(0x690, 0x304,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
286#define MX53_PAD_SD2_DATA2__GPIO_1_13 IOMUX_PAD(0x694, 0x308,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
287#define MX53_PAD_SD2_DATA1__GPIO_1_14 IOMUX_PAD(0x698, 0x30C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
288#define MX53_PAD_SD2_DATA0__GPIO_1_15 IOMUX_PAD(0x69C, 0x310,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
289#define MX53_PAD_NVCC_SD2__NVCC_SD2 IOMUX_PAD(0x6A0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
290#define MX53_PAD_GPIO_0__GPIO_1_0 IOMUX_PAD(0x6A4, 0x314,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
291#define MX53_PAD_GPIO_1__GPIO_1_1 IOMUX_PAD(0x6A8, 0x318,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
292#define MX53_PAD_GPIO_9__GPIO_1_9 IOMUX_PAD(0x6AC, 0x31C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
293#define MX53_PAD_GPIO_3__GPIO_1_3 IOMUX_PAD(0x6B0, 0x320,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
294#define MX53_PAD_GPIO_6__GPIO_1_6 IOMUX_PAD(0x6B4, 0x324,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
295#define MX53_PAD_GPIO_2__GPIO_1_2 IOMUX_PAD(0x6B8, 0x328,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
296#define MX53_PAD_GPIO_4__GPIO_1_4 IOMUX_PAD(0x6BC, 0x32C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
297#define MX53_PAD_GPIO_5__GPIO_1_5 IOMUX_PAD(0x6C0, 0x330,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
298#define MX53_PAD_GPIO_7__GPIO_1_7 IOMUX_PAD(0x6C4, 0x334,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
299#define MX53_PAD_GPIO_8__GPIO_1_8 IOMUX_PAD(0x6C8, 0x338,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
300#define MX53_PAD_GPIO_16__GPIO_7_11 IOMUX_PAD(0x6CC, 0x33C,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
301#define MX53_PAD_GPIO_17__GPIO_7_12 IOMUX_PAD(0x6D0, 0x340,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
302#define MX53_PAD_GPIO_18__GPIO_7_13 IOMUX_PAD(0x6D4, 0x344,IOMUX_CONFIG_ALT1, 0x0, 0, NO_PAD_CTRL)
303#define MX53_PAD_NVCC_GPIO__NVCC_GPIO IOMUX_PAD(0x6D8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
304#define MX53_PAD_POR_B__POR_B IOMUX_PAD(0x6DC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
305#define MX53_PAD_BOOT_MODE1__BOOT_MODE1 IOMUX_PAD(0x6E0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
306#define MX53_PAD_RESET_IN_B__RESET_IN_B IOMUX_PAD(0x6E4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
307#define MX53_PAD_BOOT_MODE0__BOOT_MODE0 IOMUX_PAD(0x6E8, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
308#define MX53_PAD_TEST_MODE__TEST_MODE IOMUX_PAD(0x6EC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
309#define MX53_PAD_GRP_ADDDS__GRP_ADDDS IOMUX_PAD(0x6F0, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
310#define MX53_PAD_GRP_DDRMODE_CTL__GRP_DDRMODE_CTL IOMUX_PAD(0x6F4, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
311#define MX53_PAD_GRP_DDRPKE__GRP_DDRPKE IOMUX_PAD(0x6FC, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
312#define MX53_PAD_GRP_DDRPK__GRP_DDRPK IOMUX_PAD(0x708, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
313#define MX53_PAD_GRP_TERM_CTL3__GRP_TERM_CTL3 IOMUX_PAD(0x70C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
314#define MX53_PAD_GRP_DDRHYS__GRP_DDRHYS IOMUX_PAD(0x710, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
315#define MX53_PAD_GRP_DDRMODE__GRP_DDRMODE IOMUX_PAD(0x714, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
316#define MX53_PAD_GRP_B0DS__GRP_B0DS IOMUX_PAD(0x718, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
317#define MX53_PAD_GRP_B1DS__GRP_B1DS IOMUX_PAD(0x71C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
318#define MX53_PAD_GRP_CTLDS__GRP_CTLDS IOMUX_PAD(0x720, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
319#define MX53_PAD_GRP_DDR_TYPE__GRP_DDR_TYPE IOMUX_PAD(0x724, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
320#define MX53_PAD_GRP_B2DS__GRP_B2DS IOMUX_PAD(0x728, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
321#define MX53_PAD_GRP_B3DS__GRP_B3DS IOMUX_PAD(0x72C, NON_MUX_I, IOMUX_CONFIG_ALT0, 0x0, 0, NO_PAD_CTRL)
322
323#endif /* __MACH_IOMUX_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/iomux-v3.h b/arch/arm/plat-mxc/include/mach/iomux-v3.h
index 0880a4a1aed1..2277b01c855d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-v3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-v3.h
@@ -42,28 +42,44 @@
42 * If <padname> or <padmode> refers to a GPIO, it is named 42 * If <padname> or <padmode> refers to a GPIO, it is named
43 * GPIO_<unit>_<num> 43 * GPIO_<unit>_<num>
44 * 44 *
45 */ 45 * IOMUX/PAD Bit field definitions
46 46 *
47struct pad_desc { 47 * MUX_CTRL_OFS: 0..11 (12)
48 unsigned mux_ctrl_ofs:12; /* IOMUXC_SW_MUX_CTL_PAD offset */ 48 * PAD_CTRL_OFS: 12..23 (12)
49 unsigned mux_mode:8; 49 * SEL_INPUT_OFS: 24..35 (12)
50 unsigned pad_ctrl_ofs:12; /* IOMUXC_SW_PAD_CTRL offset */ 50 * MUX_MODE + SION: 36..40 (5)
51#define NO_PAD_CTRL (1 << 16) 51 * PAD_CTRL + NO_PAD_CTRL: 41..57 (17)
52 unsigned pad_ctrl:17; 52 * SEL_INP: 58..61 (4)
53 unsigned select_input_ofs:12; /* IOMUXC_SELECT_INPUT offset */ 53 * reserved: 63 (1)
54 unsigned select_input:3; 54*/
55}; 55
56 56typedef u64 iomux_v3_cfg_t;
57#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _select_input_ofs, \ 57
58 _select_input, _pad_ctrl) \ 58#define MUX_CTRL_OFS_SHIFT 0
59 { \ 59#define MUX_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_CTRL_OFS_SHIFT)
60 .mux_ctrl_ofs = _mux_ctrl_ofs, \ 60#define MUX_PAD_CTRL_OFS_SHIFT 12
61 .mux_mode = _mux_mode, \ 61#define MUX_PAD_CTRL_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_PAD_CTRL_OFS_SHIFT)
62 .pad_ctrl_ofs = _pad_ctrl_ofs, \ 62#define MUX_SEL_INPUT_OFS_SHIFT 24
63 .pad_ctrl = _pad_ctrl, \ 63#define MUX_SEL_INPUT_OFS_MASK ((iomux_v3_cfg_t)0xfff << MUX_SEL_INPUT_OFS_SHIFT)
64 .select_input_ofs = _select_input_ofs, \ 64
65 .select_input = _select_input, \ 65#define MUX_MODE_SHIFT 36
66 } 66#define MUX_MODE_MASK ((iomux_v3_cfg_t)0x1f << MUX_MODE_SHIFT)
67#define MUX_PAD_CTRL_SHIFT 41
68#define MUX_PAD_CTRL_MASK ((iomux_v3_cfg_t)0x1ffff << MUX_PAD_CTRL_SHIFT)
69#define NO_PAD_CTRL ((iomux_v3_cfg_t)1 << (MUX_PAD_CTRL_SHIFT + 16))
70#define MUX_SEL_INPUT_SHIFT 58
71#define MUX_SEL_INPUT_MASK ((iomux_v3_cfg_t)0xf << MUX_SEL_INPUT_SHIFT)
72
73#define MUX_PAD_CTRL(x) ((iomux_v3_cfg_t)(x) << MUX_PAD_CTRL_SHIFT)
74
75#define IOMUX_PAD(_pad_ctrl_ofs, _mux_ctrl_ofs, _mux_mode, _sel_input_ofs, \
76 _sel_input, _pad_ctrl) \
77 (((iomux_v3_cfg_t)(_mux_ctrl_ofs) << MUX_CTRL_OFS_SHIFT) | \
78 ((iomux_v3_cfg_t)(_mux_mode) << MUX_MODE_SHIFT) | \
79 ((iomux_v3_cfg_t)(_pad_ctrl_ofs) << MUX_PAD_CTRL_OFS_SHIFT) | \
80 ((iomux_v3_cfg_t)(_pad_ctrl) << MUX_PAD_CTRL_SHIFT) | \
81 ((iomux_v3_cfg_t)(_sel_input_ofs) << MUX_SEL_INPUT_OFS_SHIFT) | \
82 ((iomux_v3_cfg_t)(_sel_input) << MUX_SEL_INPUT_SHIFT))
67 83
68/* 84/*
69 * Use to set PAD control 85 * Use to set PAD control
@@ -107,13 +123,13 @@ struct pad_desc {
107/* 123/*
108 * setups a single pad in the iomuxer 124 * setups a single pad in the iomuxer
109 */ 125 */
110int mxc_iomux_v3_setup_pad(struct pad_desc *pad); 126int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad);
111 127
112/* 128/*
113 * setups mutliple pads 129 * setups mutliple pads
114 * convenient way to call the above function with tables 130 * convenient way to call the above function with tables
115 */ 131 */
116int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count); 132int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count);
117 133
118/* 134/*
119 * Initialise the iomux controller 135 * Initialise the iomux controller
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index 86781f7b0c0c..58a49cc83797 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -23,13 +23,17 @@
23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS 23#define MXC_GPIO_IRQ_START MXC_INTERNAL_IRQS
24 24
25/* these are ordered by size to support multi-SoC kernels */ 25/* these are ordered by size to support multi-SoC kernels */
26#if defined CONFIG_ARCH_MX2 26#if defined CONFIG_ARCH_MX53
27#define MXC_GPIO_IRQS (32 * 7)
28#elif defined CONFIG_ARCH_MX2
29#define MXC_GPIO_IRQS (32 * 6)
30#elif defined CONFIG_ARCH_MX50
27#define MXC_GPIO_IRQS (32 * 6) 31#define MXC_GPIO_IRQS (32 * 6)
28#elif defined CONFIG_ARCH_MX1 32#elif defined CONFIG_ARCH_MX1
29#define MXC_GPIO_IRQS (32 * 4) 33#define MXC_GPIO_IRQS (32 * 4)
30#elif defined CONFIG_ARCH_MX25 34#elif defined CONFIG_ARCH_MX25
31#define MXC_GPIO_IRQS (32 * 4) 35#define MXC_GPIO_IRQS (32 * 4)
32#elif defined CONFIG_ARCH_MX5 36#elif defined CONFIG_ARCH_MX51
33#define MXC_GPIO_IRQS (32 * 4) 37#define MXC_GPIO_IRQS (32 * 4)
34#elif defined CONFIG_ARCH_MXC91231 38#elif defined CONFIG_ARCH_MXC91231
35#define MXC_GPIO_IRQS (32 * 4) 39#define MXC_GPIO_IRQS (32 * 4)
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 564ec9dbc93d..83861408133f 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -16,7 +16,9 @@
16#define MX25_PHYS_OFFSET UL(0x80000000) 16#define MX25_PHYS_OFFSET UL(0x80000000)
17#define MX27_PHYS_OFFSET UL(0xa0000000) 17#define MX27_PHYS_OFFSET UL(0xa0000000)
18#define MX3x_PHYS_OFFSET UL(0x80000000) 18#define MX3x_PHYS_OFFSET UL(0x80000000)
19#define MX50_PHYS_OFFSET UL(0x70000000)
19#define MX51_PHYS_OFFSET UL(0x90000000) 20#define MX51_PHYS_OFFSET UL(0x90000000)
21#define MX53_PHYS_OFFSET UL(0x70000000)
20#define MXC91231_PHYS_OFFSET UL(0x90000000) 22#define MXC91231_PHYS_OFFSET UL(0x90000000)
21 23
22#if !defined(CONFIG_RUNTIME_PHYS_OFFSET) 24#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
@@ -32,8 +34,12 @@
32# define PHYS_OFFSET MX3x_PHYS_OFFSET 34# define PHYS_OFFSET MX3x_PHYS_OFFSET
33# elif defined CONFIG_ARCH_MXC91231 35# elif defined CONFIG_ARCH_MXC91231
34# define PHYS_OFFSET MXC91231_PHYS_OFFSET 36# define PHYS_OFFSET MXC91231_PHYS_OFFSET
35# elif defined CONFIG_ARCH_MX5 37# elif defined CONFIG_ARCH_MX50
38# define PHYS_OFFSET MX50_PHYS_OFFSET
39# elif defined CONFIG_ARCH_MX51
36# define PHYS_OFFSET MX51_PHYS_OFFSET 40# define PHYS_OFFSET MX51_PHYS_OFFSET
41# elif defined CONFIG_ARCH_MX53
42# define PHYS_OFFSET MX53_PHYS_OFFSET
37# endif 43# endif
38#endif 44#endif
39 45
diff --git a/arch/arm/plat-mxc/include/mach/mx1.h b/arch/arm/plat-mxc/include/mach/mx1.h
index 641b24618239..75d96214b831 100644
--- a/arch/arm/plat-mxc/include/mach/mx1.h
+++ b/arch/arm/plat-mxc/include/mach/mx1.h
@@ -19,7 +19,6 @@
19 */ 19 */
20#define MX1_IO_BASE_ADDR 0x00200000 20#define MX1_IO_BASE_ADDR 0x00200000
21#define MX1_IO_SIZE SZ_1M 21#define MX1_IO_SIZE SZ_1M
22#define MX1_IO_BASE_ADDR_VIRT VMALLOC_END
23 22
24#define MX1_CS0_PHYS 0x10000000 23#define MX1_CS0_PHYS 0x10000000
25#define MX1_CS0_SIZE 0x02000000 24#define MX1_CS0_SIZE 0x02000000
@@ -66,6 +65,10 @@
66#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR) 65#define MX1_CCM_BASE_ADDR (0x1B000 + MX1_IO_BASE_ADDR)
67#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR) 66#define MX1_SCM_BASE_ADDR (0x1B804 + MX1_IO_BASE_ADDR)
68#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR) 67#define MX1_GPIO_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
68#define MX1_GPIO1_BASE_ADDR (0x1C000 + MX1_IO_BASE_ADDR)
69#define MX1_GPIO2_BASE_ADDR (0x1C100 + MX1_IO_BASE_ADDR)
70#define MX1_GPIO3_BASE_ADDR (0x1C200 + MX1_IO_BASE_ADDR)
71#define MX1_GPIO4_BASE_ADDR (0x1C300 + MX1_IO_BASE_ADDR)
69#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR) 72#define MX1_EIM_BASE_ADDR (0x20000 + MX1_IO_BASE_ADDR)
70#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR) 73#define MX1_SDRAMC_BASE_ADDR (0x21000 + MX1_IO_BASE_ADDR)
71#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR) 74#define MX1_MMA_BASE_ADDR (0x22000 + MX1_IO_BASE_ADDR)
@@ -73,12 +76,12 @@
73#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR) 76#define MX1_CSI_BASE_ADDR (0x24000 + MX1_IO_BASE_ADDR)
74 77
75/* macro to get at IO space when running virtually */ 78/* macro to get at IO space when running virtually */
76#define MX1_IO_ADDRESS(x) ( \ 79#define MX1_IO_P2V(x) IMX_IO_P2V(x)
77 IMX_IO_ADDRESS(x, MX1_IO)) 80#define MX1_IO_ADDRESS(x) IOMEM(MX1_IO_P2V(x))
78 81
79/* fixed interrput numbers */ 82/* fixed interrput numbers */
80#define MX1_INT_SOFTINT 0 83#define MX1_INT_SOFTINT 0
81#define MX1_CSI_INT 6 84#define MX1_INT_CSI 6
82#define MX1_DSPA_MAC_INT 7 85#define MX1_DSPA_MAC_INT 7
83#define MX1_DSPA_INT 8 86#define MX1_DSPA_INT 8
84#define MX1_COMP_INT 9 87#define MX1_COMP_INT 9
@@ -115,13 +118,13 @@
115#define MX1_SSI_RX_INT 44 118#define MX1_SSI_RX_INT 44
116#define MX1_SSI_RX_ERR_INT 45 119#define MX1_SSI_RX_ERR_INT 45
117#define MX1_TOUCH_INT 46 120#define MX1_TOUCH_INT 46
118#define MX1_USBD_INT0 47 121#define MX1_INT_USBD0 47
119#define MX1_USBD_INT1 48 122#define MX1_INT_USBD1 48
120#define MX1_USBD_INT2 49 123#define MX1_INT_USBD2 49
121#define MX1_USBD_INT3 50 124#define MX1_INT_USBD3 50
122#define MX1_USBD_INT4 51 125#define MX1_INT_USBD4 51
123#define MX1_USBD_INT5 52 126#define MX1_INT_USBD5 52
124#define MX1_USBD_INT6 53 127#define MX1_INT_USBD6 53
125#define MX1_BTSYS_INT 55 128#define MX1_BTSYS_INT 55
126#define MX1_BTTIM_INT 56 129#define MX1_BTTIM_INT 56
127#define MX1_BTWUI_INT 57 130#define MX1_BTWUI_INT 57
@@ -164,134 +167,6 @@
164 * to not break drivers/usb/gadget/imx_udc. Should go 167 * to not break drivers/usb/gadget/imx_udc. Should go
165 * away after this driver uses the new name. 168 * away after this driver uses the new name.
166 */ 169 */
167#define USBD_INT0 MX1_USBD_INT0 170#define USBD_INT0 MX1_INT_USBD0
168
169#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
170/* these should go away */
171#define IMX_IO_PHYS MX1_IO_BASE_ADDR
172#define IMX_IO_SIZE MX1_IO_SIZE
173#define IMX_IO_BASE MX1_IO_BASE_ADDR_VIRT
174#define IMX_CS0_PHYS MX1_CS0_PHYS
175#define IMX_CS0_SIZE MX1_CS0_SIZE
176#define IMX_CS1_PHYS MX1_CS1_PHYS
177#define IMX_CS1_SIZE MX1_CS1_SIZE
178#define IMX_CS2_PHYS MX1_CS2_PHYS
179#define IMX_CS2_SIZE MX1_CS2_SIZE
180#define IMX_CS3_PHYS MX1_CS3_PHYS
181#define IMX_CS3_SIZE MX1_CS3_SIZE
182#define IMX_CS4_PHYS MX1_CS4_PHYS
183#define IMX_CS4_SIZE MX1_CS4_SIZE
184#define IMX_CS5_PHYS MX1_CS5_PHYS
185#define IMX_CS5_SIZE MX1_CS5_SIZE
186#define AIPI1_BASE_ADDR MX1_AIPI1_BASE_ADDR
187#define WDT_BASE_ADDR MX1_WDT_BASE_ADDR
188#define TIM1_BASE_ADDR MX1_TIM1_BASE_ADDR
189#define TIM2_BASE_ADDR MX1_TIM2_BASE_ADDR
190#define RTC_BASE_ADDR MX1_RTC_BASE_ADDR
191#define LCDC_BASE_ADDR MX1_LCDC_BASE_ADDR
192#define UART1_BASE_ADDR MX1_UART1_BASE_ADDR
193#define UART2_BASE_ADDR MX1_UART2_BASE_ADDR
194#define PWM_BASE_ADDR MX1_PWM_BASE_ADDR
195#define DMA_BASE_ADDR MX1_DMA_BASE_ADDR
196#define AIPI2_BASE_ADDR MX1_AIPI2_BASE_ADDR
197#define SIM_BASE_ADDR MX1_SIM_BASE_ADDR
198#define USBD_BASE_ADDR MX1_USBD_BASE_ADDR
199#define SPI1_BASE_ADDR MX1_SPI1_BASE_ADDR
200#define MMC_BASE_ADDR MX1_MMC_BASE_ADDR
201#define ASP_BASE_ADDR MX1_ASP_BASE_ADDR
202#define BTA_BASE_ADDR MX1_BTA_BASE_ADDR
203#define I2C_BASE_ADDR MX1_I2C_BASE_ADDR
204#define SSI_BASE_ADDR MX1_SSI_BASE_ADDR
205#define SPI2_BASE_ADDR MX1_SPI2_BASE_ADDR
206#define MSHC_BASE_ADDR MX1_MSHC_BASE_ADDR
207#define CCM_BASE_ADDR MX1_CCM_BASE_ADDR
208#define SCM_BASE_ADDR MX1_SCM_BASE_ADDR
209#define GPIO_BASE_ADDR MX1_GPIO_BASE_ADDR
210#define EIM_BASE_ADDR MX1_EIM_BASE_ADDR
211#define SDRAMC_BASE_ADDR MX1_SDRAMC_BASE_ADDR
212#define MMA_BASE_ADDR MX1_MMA_BASE_ADDR
213#define AVIC_BASE_ADDR MX1_AVIC_BASE_ADDR
214#define CSI_BASE_ADDR MX1_CSI_BASE_ADDR
215#define IO_ADDRESS(x) MX1_IO_ADDRESS(x)
216#define AVIC_IO_ADDRESS(x) IO_ADDRESS(x)
217#define INT_SOFTINT MX1_INT_SOFTINT
218#define CSI_INT MX1_CSI_INT
219#define DSPA_MAC_INT MX1_DSPA_MAC_INT
220#define DSPA_INT MX1_DSPA_INT
221#define COMP_INT MX1_COMP_INT
222#define MSHC_XINT MX1_MSHC_XINT
223#define GPIO_INT_PORTA MX1_GPIO_INT_PORTA
224#define GPIO_INT_PORTB MX1_GPIO_INT_PORTB
225#define GPIO_INT_PORTC MX1_GPIO_INT_PORTC
226#define LCDC_INT MX1_LCDC_INT
227#define SIM_INT MX1_SIM_INT
228#define SIM_DATA_INT MX1_SIM_DATA_INT
229#define RTC_INT MX1_RTC_INT
230#define RTC_SAMINT MX1_RTC_SAMINT
231#define UART2_MINT_PFERR MX1_UART2_MINT_PFERR
232#define UART2_MINT_RTS MX1_UART2_MINT_RTS
233#define UART2_MINT_DTR MX1_UART2_MINT_DTR
234#define UART2_MINT_UARTC MX1_UART2_MINT_UARTC
235#define UART2_MINT_TX MX1_UART2_MINT_TX
236#define UART2_MINT_RX MX1_UART2_MINT_RX
237#define UART1_MINT_PFERR MX1_UART1_MINT_PFERR
238#define UART1_MINT_RTS MX1_UART1_MINT_RTS
239#define UART1_MINT_DTR MX1_UART1_MINT_DTR
240#define UART1_MINT_UARTC MX1_UART1_MINT_UARTC
241#define UART1_MINT_TX MX1_UART1_MINT_TX
242#define UART1_MINT_RX MX1_UART1_MINT_RX
243#define VOICE_DAC_INT MX1_VOICE_DAC_INT
244#define VOICE_ADC_INT MX1_VOICE_ADC_INT
245#define PEN_DATA_INT MX1_PEN_DATA_INT
246#define PWM_INT MX1_PWM_INT
247#define SDHC_INT MX1_SDHC_INT
248#define I2C_INT MX1_INT_I2C
249#define CSPI_INT MX1_CSPI_INT
250#define SSI_TX_INT MX1_SSI_TX_INT
251#define SSI_TX_ERR_INT MX1_SSI_TX_ERR_INT
252#define SSI_RX_INT MX1_SSI_RX_INT
253#define SSI_RX_ERR_INT MX1_SSI_RX_ERR_INT
254#define TOUCH_INT MX1_TOUCH_INT
255#define USBD_INT1 MX1_USBD_INT1
256#define USBD_INT2 MX1_USBD_INT2
257#define USBD_INT3 MX1_USBD_INT3
258#define USBD_INT4 MX1_USBD_INT4
259#define USBD_INT5 MX1_USBD_INT5
260#define USBD_INT6 MX1_USBD_INT6
261#define BTSYS_INT MX1_BTSYS_INT
262#define BTTIM_INT MX1_BTTIM_INT
263#define BTWUI_INT MX1_BTWUI_INT
264#define TIM2_INT MX1_TIM2_INT
265#define TIM1_INT MX1_TIM1_INT
266#define DMA_ERR MX1_DMA_ERR
267#define DMA_INT MX1_DMA_INT
268#define GPIO_INT_PORTD MX1_GPIO_INT_PORTD
269#define WDT_INT MX1_WDT_INT
270#define DMA_REQ_UART3_T MX1_DMA_REQ_UART3_T
271#define DMA_REQ_UART3_R MX1_DMA_REQ_UART3_R
272#define DMA_REQ_SSI2_T MX1_DMA_REQ_SSI2_T
273#define DMA_REQ_SSI2_R MX1_DMA_REQ_SSI2_R
274#define DMA_REQ_CSI_STAT MX1_DMA_REQ_CSI_STAT
275#define DMA_REQ_CSI_R MX1_DMA_REQ_CSI_R
276#define DMA_REQ_MSHC MX1_DMA_REQ_MSHC
277#define DMA_REQ_DSPA_DCT_DOUT MX1_DMA_REQ_DSPA_DCT_DOUT
278#define DMA_REQ_DSPA_DCT_DIN MX1_DMA_REQ_DSPA_DCT_DIN
279#define DMA_REQ_DSPA_MAC MX1_DMA_REQ_DSPA_MAC
280#define DMA_REQ_EXT MX1_DMA_REQ_EXT
281#define DMA_REQ_SDHC MX1_DMA_REQ_SDHC
282#define DMA_REQ_SPI1_R MX1_DMA_REQ_SPI1_R
283#define DMA_REQ_SPI1_T MX1_DMA_REQ_SPI1_T
284#define DMA_REQ_SSI_T MX1_DMA_REQ_SSI_T
285#define DMA_REQ_SSI_R MX1_DMA_REQ_SSI_R
286#define DMA_REQ_ASP_DAC MX1_DMA_REQ_ASP_DAC
287#define DMA_REQ_ASP_ADC MX1_DMA_REQ_ASP_ADC
288#define DMA_REQ_USP_EP(x) MX1_DMA_REQ_USP_EP(x)
289#define DMA_REQ_SPI2_R MX1_DMA_REQ_SPI2_R
290#define DMA_REQ_SPI2_T MX1_DMA_REQ_SPI2_T
291#define DMA_REQ_UART2_T MX1_DMA_REQ_UART2_T
292#define DMA_REQ_UART2_R MX1_DMA_REQ_UART2_R
293#define DMA_REQ_UART1_T MX1_DMA_REQ_UART1_T
294#define DMA_REQ_UART1_R MX1_DMA_REQ_UART1_R
295#endif /* ifdef IMX_NEEDS_DEPRECATED_SYMBOLS */
296 171
297#endif /* ifndef __MACH_MX1_H__ */ 172#endif /* ifndef __MACH_MX1_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx21.h b/arch/arm/plat-mxc/include/mach/mx21.h
index 8bc59720b6e4..6cd049ebbd8d 100644
--- a/arch/arm/plat-mxc/include/mach/mx21.h
+++ b/arch/arm/plat-mxc/include/mach/mx21.h
@@ -26,7 +26,6 @@
26#define __MACH_MX21_H__ 26#define __MACH_MX21_H__
27 27
28#define MX21_AIPI_BASE_ADDR 0x10000000 28#define MX21_AIPI_BASE_ADDR 0x10000000
29#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
30#define MX21_AIPI_SIZE SZ_1M 29#define MX21_AIPI_SIZE SZ_1M
31#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000) 30#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
32#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000) 31#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
@@ -49,6 +48,12 @@
49#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000) 48#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
50#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000) 49#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
51#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000) 50#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
51#define MX21_GPIO1_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x000)
52#define MX21_GPIO2_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x100)
53#define MX21_GPIO3_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x200)
54#define MX21_GPIO4_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x300)
55#define MX21_GPIO5_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x400)
56#define MX21_GPIO6_BASE_ADDR (MX21_GPIO_BASE_ADDR + 0x500)
52#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000) 57#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
53#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000) 58#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
54#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000) 59#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
@@ -64,7 +69,6 @@
64#define MX21_AVIC_BASE_ADDR 0x10040000 69#define MX21_AVIC_BASE_ADDR 0x10040000
65 70
66#define MX21_SAHB1_BASE_ADDR 0x80000000 71#define MX21_SAHB1_BASE_ADDR 0x80000000
67#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
68#define MX21_SAHB1_SIZE SZ_1M 72#define MX21_SAHB1_SIZE SZ_1M
69#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) 73#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
70 74
@@ -82,7 +86,6 @@
82 86
83/* NAND, SDRAM, WEIM etc controllers */ 87/* NAND, SDRAM, WEIM etc controllers */
84#define MX21_X_MEMC_BASE_ADDR 0xdf000000 88#define MX21_X_MEMC_BASE_ADDR 0xdf000000
85#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
86#define MX21_X_MEMC_SIZE SZ_256K 89#define MX21_X_MEMC_SIZE SZ_256K
87 90
88#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000) 91#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
@@ -92,10 +95,8 @@
92 95
93#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */ 96#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
94 97
95#define MX21_IO_ADDRESS(x) ( \ 98#define MX21_IO_P2V(x) IMX_IO_P2V(x)
96 IMX_IO_ADDRESS(x, MX21_AIPI) ?: \ 99#define MX21_IO_ADDRESS(x) IOMEM(MX21_IO_P2V(x))
97 IMX_IO_ADDRESS(x, MX21_SAHB1) ?: \
98 IMX_IO_ADDRESS(x, MX21_X_MEMC))
99 100
100/* fixed interrupt numbers */ 101/* fixed interrupt numbers */
101#define MX21_INT_CSPI3 6 102#define MX21_INT_CSPI3 6
@@ -184,39 +185,4 @@
184#define MX21_DMA_REQ_CSI_STAT 30 185#define MX21_DMA_REQ_CSI_STAT 30
185#define MX21_DMA_REQ_CSI_RX 31 186#define MX21_DMA_REQ_CSI_RX 31
186 187
187#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
188/* these should go away */
189#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
190#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
191#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
192#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
193#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
194#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
195#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
196#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
197#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
198#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
199#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
200#define X_MEMC_SIZE MX21_X_MEMC_SIZE
201#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
202#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
203#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
204#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
205#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
206#define MXC_INT_FIRI MX21_INT_FIRI
207#define MXC_INT_BMI MX21_INT_BMI
208#define MXC_INT_EMMAENC MX21_INT_EMMAENC
209#define MXC_INT_EMMADEC MX21_INT_EMMADEC
210#define MXC_INT_USBWKUP MX21_INT_USBWKUP
211#define MXC_INT_USBDMA MX21_INT_USBDMA
212#define MXC_INT_USBHOST MX21_INT_USBHOST
213#define MXC_INT_USBFUNC MX21_INT_USBFUNC
214#define MXC_INT_USBMNP MX21_INT_USBMNP
215#define MXC_INT_USBCTRL MX21_INT_USBCTRL
216#define MXC_INT_USBCTRL MX21_INT_USBCTRL
217#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
218#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
219#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
220#endif
221
222#endif /* ifndef __MACH_MX21_H__ */ 188#endif /* ifndef __MACH_MX21_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx25.h b/arch/arm/plat-mxc/include/mach/mx25.h
index cf46a45b0d4e..087cd7ac8d52 100644
--- a/arch/arm/plat-mxc/include/mach/mx25.h
+++ b/arch/arm/plat-mxc/include/mach/mx25.h
@@ -2,13 +2,10 @@
2#define __MACH_MX25_H__ 2#define __MACH_MX25_H__
3 3
4#define MX25_AIPS1_BASE_ADDR 0x43f00000 4#define MX25_AIPS1_BASE_ADDR 0x43f00000
5#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
6#define MX25_AIPS1_SIZE SZ_1M 5#define MX25_AIPS1_SIZE SZ_1M
7#define MX25_AIPS2_BASE_ADDR 0x53f00000 6#define MX25_AIPS2_BASE_ADDR 0x53f00000
8#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
9#define MX25_AIPS2_SIZE SZ_1M 7#define MX25_AIPS2_SIZE SZ_1M
10#define MX25_AVIC_BASE_ADDR 0x68000000 8#define MX25_AVIC_BASE_ADDR 0x68000000
11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
12#define MX25_AVIC_SIZE SZ_1M 9#define MX25_AVIC_SIZE SZ_1M
13 10
14#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) 11#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
@@ -21,20 +18,15 @@
21 18
22#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) 19#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
23#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) 20#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
21#define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000)
22#define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000)
23#define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000)
24#define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000)
25#define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000)
26#define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000)
27#define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000)
24#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) 28#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
25 29#define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000)
26#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
27#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
28#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
29#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
30
31#define MX25_IO_ADDRESS(x) ( \
32 IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \
33 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
34 IMX_IO_ADDRESS(x, MX25_AVIC))
35
36#define MX25_AIPS1_IO_ADDRESS(x) \
37 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
38 30
39#define MX25_UART1_BASE_ADDR 0x43f90000 31#define MX25_UART1_BASE_ADDR 0x43f90000
40#define MX25_UART2_BASE_ADDR 0x43f94000 32#define MX25_UART2_BASE_ADDR 0x43f94000
@@ -55,9 +47,19 @@
55#define MX25_LCDC_BASE_ADDR 0x53fbc000 47#define MX25_LCDC_BASE_ADDR 0x53fbc000
56#define MX25_KPP_BASE_ADDR 0x43fa8000 48#define MX25_KPP_BASE_ADDR 0x43fa8000
57#define MX25_SDMA_BASE_ADDR 0x53fd4000 49#define MX25_SDMA_BASE_ADDR 0x53fd4000
58#define MX25_OTG_BASE_ADDR 0x53ff4000 50#define MX25_USB_BASE_ADDR 0x53ff4000
51#define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000)
52/*
53 * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200
54 * for the host controller. Early documentation drafts specified 0x400 and
55 * Freescale internal sources confirm only the latter value to work.
56 */
57#define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400)
59#define MX25_CSI_BASE_ADDR 0x53ff8000 58#define MX25_CSI_BASE_ADDR 0x53ff8000
60 59
60#define MX25_IO_P2V(x) IMX_IO_P2V(x)
61#define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x))
62
61#define MX25_INT_CSPI3 0 63#define MX25_INT_CSPI3 0
62#define MX25_INT_I2C1 3 64#define MX25_INT_I2C1 3
63#define MX25_INT_I2C2 4 65#define MX25_INT_I2C2 4
@@ -69,18 +71,28 @@
69#define MX25_INT_SSI1 12 71#define MX25_INT_SSI1 12
70#define MX25_INT_CSPI2 13 72#define MX25_INT_CSPI2 13
71#define MX25_INT_CSPI1 14 73#define MX25_INT_CSPI1 14
74#define MX25_INT_GPIO3 16
72#define MX25_INT_CSI 17 75#define MX25_INT_CSI 17
73#define MX25_INT_UART3 18 76#define MX25_INT_UART3 18
77#define MX25_INT_GPIO4 23
74#define MX25_INT_KPP 24 78#define MX25_INT_KPP 24
75#define MX25_INT_DRYICE 25 79#define MX25_INT_DRYICE 25
80#define MX25_INT_PWM1 26
76#define MX25_INT_UART2 32 81#define MX25_INT_UART2 32
77#define MX25_INT_NFC 33 82#define MX25_INT_NFC 33
78#define MX25_INT_SDMA 34 83#define MX25_INT_SDMA 34
84#define MX25_INT_USB_HS 35
85#define MX25_INT_PWM2 36
86#define MX25_INT_USB_OTG 37
79#define MX25_INT_LCDC 39 87#define MX25_INT_LCDC 39
80#define MX25_INT_UART5 40 88#define MX25_INT_UART5 40
89#define MX25_INT_PWM3 41
90#define MX25_INT_PWM4 42
81#define MX25_INT_CAN1 43 91#define MX25_INT_CAN1 43
82#define MX25_INT_CAN2 44 92#define MX25_INT_CAN2 44
83#define MX25_INT_UART1 45 93#define MX25_INT_UART1 45
94#define MX25_INT_GPIO2 51
95#define MX25_INT_GPIO1 52
84#define MX25_INT_FEC 57 96#define MX25_INT_FEC 57
85 97
86#define MX25_DMA_REQ_SSI2_RX1 22 98#define MX25_DMA_REQ_SSI2_RX1 22
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index 2237ba2e5351..cbc43ad5ef48 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -29,7 +29,6 @@
29#endif 29#endif
30 30
31#define MX27_AIPI_BASE_ADDR 0x10000000 31#define MX27_AIPI_BASE_ADDR 0x10000000
32#define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000
33#define MX27_AIPI_SIZE SZ_1M 32#define MX27_AIPI_SIZE SZ_1M
34#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) 33#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
35#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) 34#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
@@ -52,6 +51,12 @@
52#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) 51#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
53#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) 52#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
54#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) 53#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
54#define MX27_GPIO1_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x000)
55#define MX27_GPIO2_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x100)
56#define MX27_GPIO3_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x200)
57#define MX27_GPIO4_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x300)
58#define MX27_GPIO5_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x400)
59#define MX27_GPIO6_BASE_ADDR (MX27_GPIO_BASE_ADDR + 0x500)
55#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) 60#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
56#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) 61#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
57#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) 62#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
@@ -65,11 +70,13 @@
65#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) 70#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
66#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) 71#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
67#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) 72#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
68#define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) 73#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
69#define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR 74#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
75#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
76#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
70#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) 77#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
71#define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) 78#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
72#define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) 79#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
73#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) 80#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
74#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) 81#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
75#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) 82#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
@@ -87,7 +94,6 @@
87#define MX27_ROMP_BASE_ADDR 0x10041000 94#define MX27_ROMP_BASE_ADDR 0x10041000
88 95
89#define MX27_SAHB1_BASE_ADDR 0x80000000 96#define MX27_SAHB1_BASE_ADDR 0x80000000
90#define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000
91#define MX27_SAHB1_SIZE SZ_1M 97#define MX27_SAHB1_SIZE SZ_1M
92#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) 98#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
93#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) 99#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
@@ -105,7 +111,6 @@
105 111
106/* NAND, SDRAM, WEIM, M3IF, EMI controllers */ 112/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
107#define MX27_X_MEMC_BASE_ADDR 0xd8000000 113#define MX27_X_MEMC_BASE_ADDR 0xd8000000
108#define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000
109#define MX27_X_MEMC_SIZE SZ_1M 114#define MX27_X_MEMC_SIZE SZ_1M
110#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) 115#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
111#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) 116#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
@@ -123,10 +128,8 @@
123/* IRAM */ 128/* IRAM */
124#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ 129#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
125 130
126#define MX27_IO_ADDRESS(x) ( \ 131#define MX27_IO_P2V(x) IMX_IO_P2V(x)
127 IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ 132#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
128 IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \
129 IMX_IO_ADDRESS(x, MX27_X_MEMC))
130 133
131#ifndef __ASSEMBLER__ 134#ifndef __ASSEMBLER__
132static inline void mx27_setup_weimcs(size_t cs, 135static inline void mx27_setup_weimcs(size_t cs,
@@ -192,9 +195,9 @@ static inline void mx27_setup_weimcs(size_t cs,
192#define MX27_INT_EMMAPRP 51 195#define MX27_INT_EMMAPRP 51
193#define MX27_INT_EMMAPP 52 196#define MX27_INT_EMMAPP 52
194#define MX27_INT_VPU 53 197#define MX27_INT_VPU 53
195#define MX27_INT_USB1 54 198#define MX27_INT_USB_HS1 54
196#define MX27_INT_USB2 55 199#define MX27_INT_USB_HS2 55
197#define MX27_INT_USB3 56 200#define MX27_INT_USB_OTG 56
198#define MX27_INT_SCC_SMN 57 201#define MX27_INT_SCC_SMN 57
199#define MX27_INT_SCC_SCM 58 202#define MX27_INT_SCC_SCM 58
200#define MX27_INT_SAHARA 59 203#define MX27_INT_SAHARA 59
@@ -241,82 +244,8 @@ static inline void mx27_setup_weimcs(size_t cs,
241#define MX27_DMA_REQ_SDHC3 36 244#define MX27_DMA_REQ_SDHC3 36
242#define MX27_DMA_REQ_NFC 37 245#define MX27_DMA_REQ_NFC 37
243 246
244/* silicon revisions specific to i.MX27 */
245#define CHIP_REV_1_0 0x00
246#define CHIP_REV_2_0 0x01
247
248#ifndef __ASSEMBLY__ 247#ifndef __ASSEMBLY__
249extern int mx27_revision(void); 248extern int mx27_revision(void);
250#endif 249#endif
251 250
252#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
253/* these should go away */
254#define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR
255#define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR
256#define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR
257#define UART5_BASE_ADDR MX27_UART5_BASE_ADDR
258#define UART6_BASE_ADDR MX27_UART6_BASE_ADDR
259#define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR
260#define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR
261#define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR
262#define VPU_BASE_ADDR MX27_VPU_BASE_ADDR
263#define OTG_BASE_ADDR MX27_OTG_BASE_ADDR
264#define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR
265#define IIM_BASE_ADDR MX27_IIM_BASE_ADDR
266#define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR
267#define FEC_BASE_ADDR MX27_FEC_BASE_ADDR
268#define SCC_BASE_ADDR MX27_SCC_BASE_ADDR
269#define ETB_BASE_ADDR MX27_ETB_BASE_ADDR
270#define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR
271#define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR
272#define ATA_BASE_ADDR MX27_ATA_BASE_ADDR
273#define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR
274#define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR
275#define CS0_BASE_ADDR MX27_CS0_BASE_ADDR
276#define CS1_BASE_ADDR MX27_CS1_BASE_ADDR
277#define CS2_BASE_ADDR MX27_CS2_BASE_ADDR
278#define CS3_BASE_ADDR MX27_CS3_BASE_ADDR
279#define CS4_BASE_ADDR MX27_CS4_BASE_ADDR
280#define CS5_BASE_ADDR MX27_CS5_BASE_ADDR
281#define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR
282#define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT
283#define X_MEMC_SIZE MX27_X_MEMC_SIZE
284#define NFC_BASE_ADDR MX27_NFC_BASE_ADDR
285#define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR
286#define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR
287#define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR
288#define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR
289#define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR
290#define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR
291#define MXC_INT_I2C2 MX27_INT_I2C2
292#define MXC_INT_GPT6 MX27_INT_GPT6
293#define MXC_INT_GPT5 MX27_INT_GPT5
294#define MXC_INT_GPT4 MX27_INT_GPT4
295#define MXC_INT_RTIC MX27_INT_RTIC
296#define MXC_INT_SDHC MX27_INT_SDHC
297#define MXC_INT_SDHC3 MX27_INT_SDHC3
298#define MXC_INT_ATA MX27_INT_ATA
299#define MXC_INT_UART6 MX27_INT_UART6
300#define MXC_INT_UART5 MX27_INT_UART5
301#define MXC_INT_FEC MX27_INT_FEC
302#define MXC_INT_VPU MX27_INT_VPU
303#define MXC_INT_USB1 MX27_INT_USB1
304#define MXC_INT_USB2 MX27_INT_USB2
305#define MXC_INT_USB3 MX27_INT_USB3
306#define MXC_INT_SCC_SMN MX27_INT_SCC_SMN
307#define MXC_INT_SCC_SCM MX27_INT_SCC_SCM
308#define MXC_INT_SAHARA MX27_INT_SAHARA
309#define MXC_INT_IIM MX27_INT_IIM
310#define MXC_INT_CCM MX27_INT_CCM
311#define DMA_REQ_MSHC MX27_DMA_REQ_MSHC
312#define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX
313#define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV
314#define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX
315#define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX
316#define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX
317#define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX
318#define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3
319#define DMA_REQ_NFC MX27_DMA_REQ_NFC
320#endif
321
322#endif /* ifndef __MACH_MX27_H__ */ 251#endif /* ifndef __MACH_MX27_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx2x.h b/arch/arm/plat-mxc/include/mach/mx2x.h
index afb895a0b5b8..6d07839fdec2 100644
--- a/arch/arm/plat-mxc/include/mach/mx2x.h
+++ b/arch/arm/plat-mxc/include/mach/mx2x.h
@@ -27,7 +27,6 @@
27 27
28/* Register offsets */ 28/* Register offsets */
29#define MX2x_AIPI_BASE_ADDR 0x10000000 29#define MX2x_AIPI_BASE_ADDR 0x10000000
30#define MX2x_AIPI_BASE_ADDR_VIRT 0xf4000000
31#define MX2x_AIPI_SIZE SZ_1M 30#define MX2x_AIPI_SIZE SZ_1M
32#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000) 31#define MX2x_DMA_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x01000)
33#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000) 32#define MX2x_WDOG_BASE_ADDR (MX2x_AIPI_BASE_ADDR + 0x02000)
@@ -65,43 +64,9 @@
65#define MX2x_AVIC_BASE_ADDR 0x10040000 64#define MX2x_AVIC_BASE_ADDR 0x10040000
66 65
67#define MX2x_SAHB1_BASE_ADDR 0x80000000 66#define MX2x_SAHB1_BASE_ADDR 0x80000000
68#define MX2x_SAHB1_BASE_ADDR_VIRT 0xf4100000
69#define MX2x_SAHB1_SIZE SZ_1M 67#define MX2x_SAHB1_SIZE SZ_1M
70#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000) 68#define MX2x_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
71 69
72/*
73 * This macro defines the physical to virtual address mapping for all the
74 * peripheral modules. It is used by passing in the physical address as x
75 * and returning the virtual address. If the physical address is not mapped,
76 * it returns 0xDEADBEEF
77 */
78#define IO_ADDRESS(x) \
79 (void __force __iomem *) \
80 (((x >= AIPI_BASE_ADDR) && (x < (AIPI_BASE_ADDR + AIPI_SIZE))) ? \
81 AIPI_IO_ADDRESS(x) : \
82 ((x >= SAHB1_BASE_ADDR) && (x < (SAHB1_BASE_ADDR + SAHB1_SIZE))) ? \
83 SAHB1_IO_ADDRESS(x) : \
84 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? \
85 X_MEMC_IO_ADDRESS(x) : 0xDEADBEEF)
86
87/* define the address mapping macros: in physical address order */
88#define AIPI_IO_ADDRESS(x) \
89 (((x) - AIPI_BASE_ADDR) + AIPI_BASE_ADDR_VIRT)
90
91#define AVIC_IO_ADDRESS(x) AIPI_IO_ADDRESS(x)
92
93#define SAHB1_IO_ADDRESS(x) \
94 (((x) - SAHB1_BASE_ADDR) + SAHB1_BASE_ADDR_VIRT)
95
96#define CS4_IO_ADDRESS(x) \
97 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
98
99#define X_MEMC_IO_ADDRESS(x) \
100 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
101
102#define PCMCIA_IO_ADDRESS(x) \
103 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
104
105/* fixed interrupt numbers */ 70/* fixed interrupt numbers */
106#define MX2x_INT_CSPI3 6 71#define MX2x_INT_CSPI3 6
107#define MX2x_INT_GPIO 8 72#define MX2x_INT_GPIO 8
@@ -176,118 +141,4 @@
176#define MX2x_DMA_REQ_CSI_STAT 30 141#define MX2x_DMA_REQ_CSI_STAT 30
177#define MX2x_DMA_REQ_CSI_RX 31 142#define MX2x_DMA_REQ_CSI_RX 31
178 143
179#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
180/* these should go away */
181#define AIPI_BASE_ADDR MX2x_AIPI_BASE_ADDR
182#define AIPI_BASE_ADDR_VIRT MX2x_AIPI_BASE_ADDR_VIRT
183#define AIPI_SIZE MX2x_AIPI_SIZE
184#define DMA_BASE_ADDR MX2x_DMA_BASE_ADDR
185#define WDOG_BASE_ADDR MX2x_WDOG_BASE_ADDR
186#define GPT1_BASE_ADDR MX2x_GPT1_BASE_ADDR
187#define GPT2_BASE_ADDR MX2x_GPT2_BASE_ADDR
188#define GPT3_BASE_ADDR MX2x_GPT3_BASE_ADDR
189#define PWM_BASE_ADDR MX2x_PWM_BASE_ADDR
190#define RTC_BASE_ADDR MX2x_RTC_BASE_ADDR
191#define KPP_BASE_ADDR MX2x_KPP_BASE_ADDR
192#define OWIRE_BASE_ADDR MX2x_OWIRE_BASE_ADDR
193#define UART1_BASE_ADDR MX2x_UART1_BASE_ADDR
194#define UART2_BASE_ADDR MX2x_UART2_BASE_ADDR
195#define UART3_BASE_ADDR MX2x_UART3_BASE_ADDR
196#define UART4_BASE_ADDR MX2x_UART4_BASE_ADDR
197#define CSPI1_BASE_ADDR MX2x_CSPI1_BASE_ADDR
198#define CSPI2_BASE_ADDR MX2x_CSPI2_BASE_ADDR
199#define SSI1_BASE_ADDR MX2x_SSI1_BASE_ADDR
200#define SSI2_BASE_ADDR MX2x_SSI2_BASE_ADDR
201#define I2C_BASE_ADDR MX2x_I2C_BASE_ADDR
202#define SDHC1_BASE_ADDR MX2x_SDHC1_BASE_ADDR
203#define SDHC2_BASE_ADDR MX2x_SDHC2_BASE_ADDR
204#define GPIO_BASE_ADDR MX2x_GPIO_BASE_ADDR
205#define AUDMUX_BASE_ADDR MX2x_AUDMUX_BASE_ADDR
206#define CSPI3_BASE_ADDR MX2x_CSPI3_BASE_ADDR
207#define LCDC_BASE_ADDR MX2x_LCDC_BASE_ADDR
208#define SLCDC_BASE_ADDR MX2x_SLCDC_BASE_ADDR
209#define USBOTG_BASE_ADDR MX2x_USBOTG_BASE_ADDR
210#define EMMA_PP_BASE_ADDR MX2x_EMMA_PP_BASE_ADDR
211#define EMMA_PRP_BASE_ADDR MX2x_EMMA_PRP_BASE_ADDR
212#define CCM_BASE_ADDR MX2x_CCM_BASE_ADDR
213#define SYSCTRL_BASE_ADDR MX2x_SYSCTRL_BASE_ADDR
214#define JAM_BASE_ADDR MX2x_JAM_BASE_ADDR
215#define MAX_BASE_ADDR MX2x_MAX_BASE_ADDR
216#define AVIC_BASE_ADDR MX2x_AVIC_BASE_ADDR
217#define SAHB1_BASE_ADDR MX2x_SAHB1_BASE_ADDR
218#define SAHB1_BASE_ADDR_VIRT MX2x_SAHB1_BASE_ADDR_VIRT
219#define SAHB1_SIZE MX2x_SAHB1_SIZE
220#define CSI_BASE_ADDR MX2x_CSI_BASE_ADDR
221#define MXC_INT_CSPI3 MX2x_INT_CSPI3
222#define MXC_INT_GPIO MX2x_INT_GPIO
223#define MXC_INT_SDHC2 MX2x_INT_SDHC2
224#define MXC_INT_SDHC1 MX2x_INT_SDHC1
225#define MXC_INT_I2C MX2x_INT_I2C
226#define MXC_INT_SSI2 MX2x_INT_SSI2
227#define MXC_INT_SSI1 MX2x_INT_SSI1
228#define MXC_INT_CSPI2 MX2x_INT_CSPI2
229#define MXC_INT_CSPI1 MX2x_INT_CSPI1
230#define MXC_INT_UART4 MX2x_INT_UART4
231#define MXC_INT_UART3 MX2x_INT_UART3
232#define MXC_INT_UART2 MX2x_INT_UART2
233#define MXC_INT_UART1 MX2x_INT_UART1
234#define MXC_INT_KPP MX2x_INT_KPP
235#define MXC_INT_RTC MX2x_INT_RTC
236#define MXC_INT_PWM MX2x_INT_PWM
237#define MXC_INT_GPT3 MX2x_INT_GPT3
238#define MXC_INT_GPT2 MX2x_INT_GPT2
239#define MXC_INT_GPT1 MX2x_INT_GPT1
240#define MXC_INT_WDOG MX2x_INT_WDOG
241#define MXC_INT_PCMCIA MX2x_INT_PCMCIA
242#define MXC_INT_NANDFC MX2x_INT_NANDFC
243#define MXC_INT_CSI MX2x_INT_CSI
244#define MXC_INT_DMACH0 MX2x_INT_DMACH0
245#define MXC_INT_DMACH1 MX2x_INT_DMACH1
246#define MXC_INT_DMACH2 MX2x_INT_DMACH2
247#define MXC_INT_DMACH3 MX2x_INT_DMACH3
248#define MXC_INT_DMACH4 MX2x_INT_DMACH4
249#define MXC_INT_DMACH5 MX2x_INT_DMACH5
250#define MXC_INT_DMACH6 MX2x_INT_DMACH6
251#define MXC_INT_DMACH7 MX2x_INT_DMACH7
252#define MXC_INT_DMACH8 MX2x_INT_DMACH8
253#define MXC_INT_DMACH9 MX2x_INT_DMACH9
254#define MXC_INT_DMACH10 MX2x_INT_DMACH10
255#define MXC_INT_DMACH11 MX2x_INT_DMACH11
256#define MXC_INT_DMACH12 MX2x_INT_DMACH12
257#define MXC_INT_DMACH13 MX2x_INT_DMACH13
258#define MXC_INT_DMACH14 MX2x_INT_DMACH14
259#define MXC_INT_DMACH15 MX2x_INT_DMACH15
260#define MXC_INT_EMMAPRP MX2x_INT_EMMAPRP
261#define MXC_INT_EMMAPP MX2x_INT_EMMAPP
262#define MXC_INT_SLCDC MX2x_INT_SLCDC
263#define MXC_INT_LCDC MX2x_INT_LCDC
264#define DMA_REQ_CSPI3_RX MX2x_DMA_REQ_CSPI3_RX
265#define DMA_REQ_CSPI3_TX MX2x_DMA_REQ_CSPI3_TX
266#define DMA_REQ_EXT MX2x_DMA_REQ_EXT
267#define DMA_REQ_SDHC2 MX2x_DMA_REQ_SDHC2
268#define DMA_REQ_SDHC1 MX2x_DMA_REQ_SDHC1
269#define DMA_REQ_SSI2_RX0 MX2x_DMA_REQ_SSI2_RX0
270#define DMA_REQ_SSI2_TX0 MX2x_DMA_REQ_SSI2_TX0
271#define DMA_REQ_SSI2_RX1 MX2x_DMA_REQ_SSI2_RX1
272#define DMA_REQ_SSI2_TX1 MX2x_DMA_REQ_SSI2_TX1
273#define DMA_REQ_SSI1_RX0 MX2x_DMA_REQ_SSI1_RX0
274#define DMA_REQ_SSI1_TX0 MX2x_DMA_REQ_SSI1_TX0
275#define DMA_REQ_SSI1_RX1 MX2x_DMA_REQ_SSI1_RX1
276#define DMA_REQ_SSI1_TX1 MX2x_DMA_REQ_SSI1_TX1
277#define DMA_REQ_CSPI2_RX MX2x_DMA_REQ_CSPI2_RX
278#define DMA_REQ_CSPI2_TX MX2x_DMA_REQ_CSPI2_TX
279#define DMA_REQ_CSPI1_RX MX2x_DMA_REQ_CSPI1_RX
280#define DMA_REQ_CSPI1_TX MX2x_DMA_REQ_CSPI1_TX
281#define DMA_REQ_UART4_RX MX2x_DMA_REQ_UART4_RX
282#define DMA_REQ_UART4_TX MX2x_DMA_REQ_UART4_TX
283#define DMA_REQ_UART3_RX MX2x_DMA_REQ_UART3_RX
284#define DMA_REQ_UART3_TX MX2x_DMA_REQ_UART3_TX
285#define DMA_REQ_UART2_RX MX2x_DMA_REQ_UART2_RX
286#define DMA_REQ_UART2_TX MX2x_DMA_REQ_UART2_TX
287#define DMA_REQ_UART1_RX MX2x_DMA_REQ_UART1_RX
288#define DMA_REQ_UART1_TX MX2x_DMA_REQ_UART1_TX
289#define DMA_REQ_CSI_STAT MX2x_DMA_REQ_CSI_STAT
290#define DMA_REQ_CSI_RX MX2x_DMA_REQ_CSI_RX
291#endif
292
293#endif /* ifndef __MACH_MX2x_H__ */ 144#endif /* ifndef __MACH_MX2x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx31.h b/arch/arm/plat-mxc/include/mach/mx31.h
index 61cfe827498b..79e7fc01bb59 100644
--- a/arch/arm/plat-mxc/include/mach/mx31.h
+++ b/arch/arm/plat-mxc/include/mach/mx31.h
@@ -15,7 +15,6 @@
15#define MX31_L2CC_SIZE SZ_1M 15#define MX31_L2CC_SIZE SZ_1M
16 16
17#define MX31_AIPS1_BASE_ADDR 0x43f00000 17#define MX31_AIPS1_BASE_ADDR 0x43f00000
18#define MX31_AIPS1_BASE_ADDR_VIRT 0xfc000000
19#define MX31_AIPS1_SIZE SZ_1M 18#define MX31_AIPS1_SIZE SZ_1M
20#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000) 19#define MX31_MAX_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x04000)
21#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000) 20#define MX31_EVTMON_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x08000)
@@ -25,7 +24,10 @@
25#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000) 24#define MX31_ECT_CTIO_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x18000)
26#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000) 25#define MX31_I2C1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x80000)
27#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000) 26#define MX31_I2C3_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x84000)
28#define MX31_OTG_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000) 27#define MX31_USB_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x88000)
28#define MX31_USB_OTG_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0000)
29#define MX31_USB_HS1_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0200)
30#define MX31_USB_HS2_BASE_ADDR (MX31_USB_BASE_ADDR + 0x0400)
29#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000) 31#define MX31_ATA_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x8c000)
30#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000) 32#define MX31_UART1_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x90000)
31#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000) 33#define MX31_UART2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0x94000)
@@ -41,10 +43,9 @@
41#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000) 43#define MX31_ECT_IP2_BASE_ADDR (MX31_AIPS1_BASE_ADDR + 0xbc000)
42 44
43#define MX31_SPBA0_BASE_ADDR 0x50000000 45#define MX31_SPBA0_BASE_ADDR 0x50000000
44#define MX31_SPBA0_BASE_ADDR_VIRT 0xfc100000
45#define MX31_SPBA0_SIZE SZ_1M 46#define MX31_SPBA0_SIZE SZ_1M
46#define MX31_MMC_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000) 47#define MX31_SDHC1_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x04000)
47#define MX31_MMC_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000) 48#define MX31_SDHC2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x08000)
48#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000) 49#define MX31_UART3_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x0c000)
49#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000) 50#define MX31_CSPI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x10000)
50#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000) 51#define MX31_SSI2_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x14000)
@@ -55,7 +56,6 @@
55#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000) 56#define MX31_SPBA_CTRL_BASE_ADDR (MX31_SPBA0_BASE_ADDR + 0x3c000)
56 57
57#define MX31_AIPS2_BASE_ADDR 0x53f00000 58#define MX31_AIPS2_BASE_ADDR 0x53f00000
58#define MX31_AIPS2_BASE_ADDR_VIRT 0xfc200000
59#define MX31_AIPS2_SIZE SZ_1M 59#define MX31_AIPS2_SIZE SZ_1M
60#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000) 60#define MX31_CCM_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x80000)
61#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000) 61#define MX31_CSPI3_BASE_ADDR (MX31_AIPS2_BASE_ADDR + 0x84000)
@@ -84,7 +84,6 @@
84#define MX31_ROMP_SIZE SZ_1M 84#define MX31_ROMP_SIZE SZ_1M
85 85
86#define MX31_AVIC_BASE_ADDR 0x68000000 86#define MX31_AVIC_BASE_ADDR 0x68000000
87#define MX31_AVIC_BASE_ADDR_VIRT 0xfc400000
88#define MX31_AVIC_SIZE SZ_1M 87#define MX31_AVIC_SIZE SZ_1M
89 88
90#define MX31_IPU_MEM_BASE_ADDR 0x70000000 89#define MX31_IPU_MEM_BASE_ADDR 0x70000000
@@ -97,15 +96,14 @@
97#define MX31_CS3_BASE_ADDR 0xb2000000 96#define MX31_CS3_BASE_ADDR 0xb2000000
98 97
99#define MX31_CS4_BASE_ADDR 0xb4000000 98#define MX31_CS4_BASE_ADDR 0xb4000000
100#define MX31_CS4_BASE_ADDR_VIRT 0xf4000000 99#define MX31_CS4_BASE_ADDR_VIRT 0xf6000000
101#define MX31_CS4_SIZE SZ_32M 100#define MX31_CS4_SIZE SZ_32M
102 101
103#define MX31_CS5_BASE_ADDR 0xb6000000 102#define MX31_CS5_BASE_ADDR 0xb6000000
104#define MX31_CS5_BASE_ADDR_VIRT 0xf6000000 103#define MX31_CS5_BASE_ADDR_VIRT 0xf8000000
105#define MX31_CS5_SIZE SZ_32M 104#define MX31_CS5_SIZE SZ_32M
106 105
107#define MX31_X_MEMC_BASE_ADDR 0xb8000000 106#define MX31_X_MEMC_BASE_ADDR 0xb8000000
108#define MX31_X_MEMC_BASE_ADDR_VIRT 0xfc320000
109#define MX31_X_MEMC_SIZE SZ_64K 107#define MX31_X_MEMC_SIZE SZ_64K
110#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000) 108#define MX31_NFC_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x0000)
111#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000) 109#define MX31_ESDCTL_BASE_ADDR (MX31_X_MEMC_BASE_ADDR + 0x1000)
@@ -121,12 +119,8 @@
121 119
122#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000 120#define MX31_PCMCIA_MEM_BASE_ADDR 0xbc000000
123 121
124#define MX31_IO_ADDRESS(x) ( \ 122#define MX31_IO_P2V(x) IMX_IO_P2V(x)
125 IMX_IO_ADDRESS(x, MX31_AIPS1) ?: \ 123#define MX31_IO_ADDRESS(x) IOMEM(MX31_IO_P2V(x))
126 IMX_IO_ADDRESS(x, MX31_AIPS2) ?: \
127 IMX_IO_ADDRESS(x, MX31_AVIC) ?: \
128 IMX_IO_ADDRESS(x, MX31_X_MEMC) ?: \
129 IMX_IO_ADDRESS(x, MX31_SPBA0))
130 124
131#ifndef __ASSEMBLER__ 125#ifndef __ASSEMBLER__
132static inline void mx31_setup_weimcs(size_t cs, 126static inline void mx31_setup_weimcs(size_t cs,
@@ -143,8 +137,8 @@ static inline void mx31_setup_weimcs(size_t cs,
143#define MX31_INT_MPEG4_ENCODER 5 137#define MX31_INT_MPEG4_ENCODER 5
144#define MX31_INT_RTIC 6 138#define MX31_INT_RTIC 6
145#define MX31_INT_FIRI 7 139#define MX31_INT_FIRI 7
146#define MX31_INT_MMC_SDHC2 8 140#define MX31_INT_SDHC2 8
147#define MX31_INT_MMC_SDHC1 9 141#define MX31_INT_SDHC1 9
148#define MX31_INT_I2C1 10 142#define MX31_INT_I2C1 10
149#define MX31_INT_SSI2 11 143#define MX31_INT_SSI2 11
150#define MX31_INT_SSI1 12 144#define MX31_INT_SSI1 12
@@ -170,10 +164,9 @@ static inline void mx31_setup_weimcs(size_t cs,
170#define MX31_INT_UART2 32 164#define MX31_INT_UART2 32
171#define MX31_INT_NFC 33 165#define MX31_INT_NFC 33
172#define MX31_INT_SDMA 34 166#define MX31_INT_SDMA 34
173#define MX31_INT_USB1 35 167#define MX31_INT_USB_HS1 35
174#define MX31_INT_USB2 36 168#define MX31_INT_USB_HS2 36
175#define MX31_INT_USB3 37 169#define MX31_INT_USB_OTG 37
176#define MX31_INT_USB4 38
177#define MX31_INT_MSHC1 39 170#define MX31_INT_MSHC1 39
178#define MX31_INT_MSHC2 40 171#define MX31_INT_MSHC2 40
179#define MX31_INT_IPU_ERR 41 172#define MX31_INT_IPU_ERR 41
@@ -197,6 +190,8 @@ static inline void mx31_setup_weimcs(size_t cs,
197#define MX31_INT_EXT_WDOG 62 190#define MX31_INT_EXT_WDOG 62
198#define MX31_INT_EXT_TV 63 191#define MX31_INT_EXT_TV 63
199 192
193#define MX31_DMA_REQ_SDHC1 20
194#define MX31_DMA_REQ_SDHC2 21
200#define MX31_DMA_REQ_SSI2_RX1 22 195#define MX31_DMA_REQ_SSI2_RX1 22
201#define MX31_DMA_REQ_SSI2_TX1 23 196#define MX31_DMA_REQ_SSI2_TX1 23
202#define MX31_DMA_REQ_SSI2_RX0 24 197#define MX31_DMA_REQ_SSI2_RX0 24
@@ -208,52 +203,4 @@ static inline void mx31_setup_weimcs(size_t cs,
208 203
209#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */ 204#define MX31_PROD_SIGNATURE 0x1 /* For MX31 */
210 205
211/* silicon revisions specific to i.MX31 */
212#define MX31_CHIP_REV_1_0 0x10
213#define MX31_CHIP_REV_1_1 0x11
214#define MX31_CHIP_REV_1_2 0x12
215#define MX31_CHIP_REV_1_3 0x13
216#define MX31_CHIP_REV_2_0 0x20
217#define MX31_CHIP_REV_2_1 0x21
218#define MX31_CHIP_REV_2_2 0x22
219#define MX31_CHIP_REV_2_3 0x23
220#define MX31_CHIP_REV_3_0 0x30
221#define MX31_CHIP_REV_3_1 0x31
222#define MX31_CHIP_REV_3_2 0x32
223
224#define MX31_SYSTEM_REV_MIN MX31_CHIP_REV_1_0
225#define MX31_SYSTEM_REV_NUM 3
226
227#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
228/* these should go away */
229#define ATA_BASE_ADDR MX31_ATA_BASE_ADDR
230#define UART4_BASE_ADDR MX31_UART4_BASE_ADDR
231#define UART5_BASE_ADDR MX31_UART5_BASE_ADDR
232#define MMC_SDHC1_BASE_ADDR MX31_MMC_SDHC1_BASE_ADDR
233#define MMC_SDHC2_BASE_ADDR MX31_MMC_SDHC2_BASE_ADDR
234#define SIM1_BASE_ADDR MX31_SIM1_BASE_ADDR
235#define IIM_BASE_ADDR MX31_IIM_BASE_ADDR
236#define CSPI3_BASE_ADDR MX31_CSPI3_BASE_ADDR
237#define FIRI_BASE_ADDR MX31_FIRI_BASE_ADDR
238#define SCM_BASE_ADDR MX31_SCM_BASE_ADDR
239#define SMN_BASE_ADDR MX31_SMN_BASE_ADDR
240#define MPEG4_ENC_BASE_ADDR MX31_MPEG4_ENC_BASE_ADDR
241#define MXC_INT_MPEG4_ENCODER MX31_INT_MPEG4_ENCODER
242#define MXC_INT_FIRI MX31_INT_FIRI
243#define MXC_INT_MBX MX31_INT_MBX
244#define MXC_INT_CSPI3 MX31_INT_CSPI3
245#define MXC_INT_SIM2 MX31_INT_SIM2
246#define MXC_INT_SIM1 MX31_INT_SIM1
247#define MXC_INT_CCM_DVFS MX31_INT_CCM_DVFS
248#define MXC_INT_USB1 MX31_INT_USB1
249#define MXC_INT_USB2 MX31_INT_USB2
250#define MXC_INT_USB3 MX31_INT_USB3
251#define MXC_INT_USB4 MX31_INT_USB4
252#define MXC_INT_MSHC2 MX31_INT_MSHC2
253#define MXC_INT_UART4 MX31_INT_UART4
254#define MXC_INT_UART5 MX31_INT_UART5
255#define MXC_INT_CCM MX31_INT_CCM
256#define MXC_INT_PCMCIA MX31_INT_PCMCIA
257#endif
258
259#endif /* ifndef __MACH_MX31_H__ */ 206#endif /* ifndef __MACH_MX31_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx35.h b/arch/arm/plat-mxc/include/mach/mx35.h
index 6267cff6035d..d13dbfeef08a 100644
--- a/arch/arm/plat-mxc/include/mach/mx35.h
+++ b/arch/arm/plat-mxc/include/mach/mx35.h
@@ -11,7 +11,6 @@
11#define MX35_L2CC_SIZE SZ_1M 11#define MX35_L2CC_SIZE SZ_1M
12 12
13#define MX35_AIPS1_BASE_ADDR 0x43f00000 13#define MX35_AIPS1_BASE_ADDR 0x43f00000
14#define MX35_AIPS1_BASE_ADDR_VIRT 0xfc000000
15#define MX35_AIPS1_SIZE SZ_1M 14#define MX35_AIPS1_SIZE SZ_1M
16#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000) 15#define MX35_MAX_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x04000)
17#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000) 16#define MX35_EVTMON_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0x08000)
@@ -33,7 +32,6 @@
33#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000) 32#define MX35_ECT_IP2_BASE_ADDR (MX35_AIPS1_BASE_ADDR + 0xbc000)
34 33
35#define MX35_SPBA0_BASE_ADDR 0x50000000 34#define MX35_SPBA0_BASE_ADDR 0x50000000
36#define MX35_SPBA0_BASE_ADDR_VIRT 0xfc100000
37#define MX35_SPBA0_SIZE SZ_1M 35#define MX35_SPBA0_SIZE SZ_1M
38#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000) 36#define MX35_UART3_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x0c000)
39#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000) 37#define MX35_CSPI2_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x10000)
@@ -44,7 +42,6 @@
44#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000) 42#define MX35_SPBA_CTRL_BASE_ADDR (MX35_SPBA0_BASE_ADDR + 0x3c000)
45 43
46#define MX35_AIPS2_BASE_ADDR 0x53f00000 44#define MX35_AIPS2_BASE_ADDR 0x53f00000
47#define MX35_AIPS2_BASE_ADDR_VIRT 0xfc200000
48#define MX35_AIPS2_SIZE SZ_1M 45#define MX35_AIPS2_SIZE SZ_1M
49#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000) 46#define MX35_CCM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x80000)
50#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000) 47#define MX35_GPT1_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0x90000)
@@ -68,15 +65,19 @@
68#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000) 65#define MX35_CAN2_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xe8000)
69#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000) 66#define MX35_RTIC_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xec000)
70#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000) 67#define MX35_IIM_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf0000)
71 68#define MX35_USB_BASE_ADDR (MX35_AIPS2_BASE_ADDR + 0xf4000)
72#define MX35_OTG_BASE_ADDR 0x53ff4000 69#define MX35_USB_OTG_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0000)
70/*
71 * The Reference Manual (IMX35RM, Rev. 2, 3/2009) claims an offset of 0x200 for
72 * HS. When host support was implemented only a preliminary document was
73 * available, which told 0x400. This works fine.
74 */
75#define MX35_USB_HS_BASE_ADDR (MX35_USB_BASE_ADDR + 0x0400)
73 76
74#define MX35_ROMP_BASE_ADDR 0x60000000 77#define MX35_ROMP_BASE_ADDR 0x60000000
75#define MX35_ROMP_BASE_ADDR_VIRT 0xfc500000
76#define MX35_ROMP_SIZE SZ_1M 78#define MX35_ROMP_SIZE SZ_1M
77 79
78#define MX35_AVIC_BASE_ADDR 0x68000000 80#define MX35_AVIC_BASE_ADDR 0x68000000
79#define MX35_AVIC_BASE_ADDR_VIRT 0xfc400000
80#define MX35_AVIC_SIZE SZ_1M 81#define MX35_AVIC_SIZE SZ_1M
81 82
82/* 83/*
@@ -92,18 +93,17 @@
92#define MX35_CS3_BASE_ADDR 0xb2000000 93#define MX35_CS3_BASE_ADDR 0xb2000000
93 94
94#define MX35_CS4_BASE_ADDR 0xb4000000 95#define MX35_CS4_BASE_ADDR 0xb4000000
95#define MX35_CS4_BASE_ADDR_VIRT 0xf4000000 96#define MX35_CS4_BASE_ADDR_VIRT 0xf6000000
96#define MX35_CS4_SIZE SZ_32M 97#define MX35_CS4_SIZE SZ_32M
97 98
98#define MX35_CS5_BASE_ADDR 0xb6000000 99#define MX35_CS5_BASE_ADDR 0xb6000000
99#define MX35_CS5_BASE_ADDR_VIRT 0xf6000000 100#define MX35_CS5_BASE_ADDR_VIRT 0xf8000000
100#define MX35_CS5_SIZE SZ_32M 101#define MX35_CS5_SIZE SZ_32M
101 102
102/* 103/*
103 * NAND, SDRAM, WEIM, M3IF, EMI controllers 104 * NAND, SDRAM, WEIM, M3IF, EMI controllers
104 */ 105 */
105#define MX35_X_MEMC_BASE_ADDR 0xb8000000 106#define MX35_X_MEMC_BASE_ADDR 0xb8000000
106#define MX35_X_MEMC_BASE_ADDR_VIRT 0xfc320000
107#define MX35_X_MEMC_SIZE SZ_64K 107#define MX35_X_MEMC_SIZE SZ_64K
108#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000) 108#define MX35_ESDCTL_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x1000)
109#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000) 109#define MX35_WEIM_BASE_ADDR (MX35_X_MEMC_BASE_ADDR + 0x2000)
@@ -114,12 +114,8 @@
114#define MX35_NFC_BASE_ADDR 0xbb000000 114#define MX35_NFC_BASE_ADDR 0xbb000000
115#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000 115#define MX35_PCMCIA_MEM_BASE_ADDR 0xbc000000
116 116
117#define MX35_IO_ADDRESS(x) ( \ 117#define MX35_IO_P2V(x) IMX_IO_P2V(x)
118 IMX_IO_ADDRESS(x, MX35_AIPS1) ?: \ 118#define MX35_IO_ADDRESS(x) IOMEM(MX35_IO_P2V(x))
119 IMX_IO_ADDRESS(x, MX35_AIPS2) ?: \
120 IMX_IO_ADDRESS(x, MX35_AVIC) ?: \
121 IMX_IO_ADDRESS(x, MX35_X_MEMC) ?: \
122 IMX_IO_ADDRESS(x, MX35_SPBA0))
123 119
124/* 120/*
125 * Interrupt numbers 121 * Interrupt numbers
@@ -153,8 +149,8 @@
153#define MX35_INT_UART2 32 149#define MX35_INT_UART2 32
154#define MX35_INT_NFC 33 150#define MX35_INT_NFC 33
155#define MX35_INT_SDMA 34 151#define MX35_INT_SDMA 34
156#define MX35_INT_USBHS 35 152#define MX35_INT_USB_HS 35
157#define MX35_INT_USBOTG 37 153#define MX35_INT_USB_OTG 37
158#define MX35_INT_MSHC1 39 154#define MX35_INT_MSHC1 39
159#define MX35_INT_ESAI 40 155#define MX35_INT_ESAI 40
160#define MX35_INT_IPU_ERR 41 156#define MX35_INT_IPU_ERR 41
@@ -190,23 +186,4 @@
190 186
191#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */ 187#define MX35_PROD_SIGNATURE 0x1 /* For MX31 */
192 188
193#define MX35_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
194#define MX35_SYSTEM_REV_NUM 3
195
196#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
197/* these should go away */
198#define MXC_FEC_BASE_ADDR MX35_FEC_BASE_ADDR
199#define MXC_INT_OWIRE MX35_INT_OWIRE
200#define MXC_INT_GPU2D MX35_INT_GPU2D
201#define MXC_INT_ASRC MX35_INT_ASRC
202#define MXC_INT_USBHS MX35_INT_USBHS
203#define MXC_INT_USBOTG MX35_INT_USBOTG
204#define MXC_INT_ESAI MX35_INT_ESAI
205#define MXC_INT_CAN1 MX35_INT_CAN1
206#define MXC_INT_CAN2 MX35_INT_CAN2
207#define MXC_INT_MLB MX35_INT_MLB
208#define MXC_INT_SPDIF MX35_INT_SPDIF
209#define MXC_INT_FEC MX35_INT_FEC
210#endif
211
212#endif /* ifndef __MACH_MX35_H__ */ 189#endif /* ifndef __MACH_MX35_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx3x.h b/arch/arm/plat-mxc/include/mach/mx3x.h
index d1bd26d7b8a6..388a407d72d6 100644
--- a/arch/arm/plat-mxc/include/mach/mx3x.h
+++ b/arch/arm/plat-mxc/include/mach/mx3x.h
@@ -44,7 +44,6 @@
44 * AIPS 1 44 * AIPS 1
45 */ 45 */
46#define MX3x_AIPS1_BASE_ADDR 0x43f00000 46#define MX3x_AIPS1_BASE_ADDR 0x43f00000
47#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000
48#define MX3x_AIPS1_SIZE SZ_1M 47#define MX3x_AIPS1_SIZE SZ_1M
49#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000) 48#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
50#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000) 49#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
@@ -69,7 +68,6 @@
69 * SPBA global module enabled #0 68 * SPBA global module enabled #0
70 */ 69 */
71#define MX3x_SPBA0_BASE_ADDR 0x50000000 70#define MX3x_SPBA0_BASE_ADDR 0x50000000
72#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000
73#define MX3x_SPBA0_SIZE SZ_1M 71#define MX3x_SPBA0_SIZE SZ_1M
74#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000) 72#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
75#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000) 73#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
@@ -82,7 +80,6 @@
82 * AIPS 2 80 * AIPS 2
83 */ 81 */
84#define MX3x_AIPS2_BASE_ADDR 0x53f00000 82#define MX3x_AIPS2_BASE_ADDR 0x53f00000
85#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000
86#define MX3x_AIPS2_SIZE SZ_1M 83#define MX3x_AIPS2_SIZE SZ_1M
87#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000) 84#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
88#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000) 85#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
@@ -105,11 +102,9 @@
105 * ROMP and AVIC 102 * ROMP and AVIC
106 */ 103 */
107#define MX3x_ROMP_BASE_ADDR 0x60000000 104#define MX3x_ROMP_BASE_ADDR 0x60000000
108#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000
109#define MX3x_ROMP_SIZE SZ_1M 105#define MX3x_ROMP_SIZE SZ_1M
110 106
111#define MX3x_AVIC_BASE_ADDR 0x68000000 107#define MX3x_AVIC_BASE_ADDR 0x68000000
112#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000
113#define MX3x_AVIC_SIZE SZ_1M 108#define MX3x_AVIC_SIZE SZ_1M
114 109
115/* 110/*
@@ -125,18 +120,17 @@
125#define MX3x_CS3_BASE_ADDR 0xb2000000 120#define MX3x_CS3_BASE_ADDR 0xb2000000
126 121
127#define MX3x_CS4_BASE_ADDR 0xb4000000 122#define MX3x_CS4_BASE_ADDR 0xb4000000
128#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000 123#define MX3x_CS4_BASE_ADDR_VIRT 0xf6000000
129#define MX3x_CS4_SIZE SZ_32M 124#define MX3x_CS4_SIZE SZ_32M
130 125
131#define MX3x_CS5_BASE_ADDR 0xb6000000 126#define MX3x_CS5_BASE_ADDR 0xb6000000
132#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000 127#define MX3x_CS5_BASE_ADDR_VIRT 0xf8000000
133#define MX3x_CS5_SIZE SZ_32M 128#define MX3x_CS5_SIZE SZ_32M
134 129
135/* 130/*
136 * NAND, SDRAM, WEIM, M3IF, EMI controllers 131 * NAND, SDRAM, WEIM, M3IF, EMI controllers
137 */ 132 */
138#define MX3x_X_MEMC_BASE_ADDR 0xb8000000 133#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
139#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000
140#define MX3x_X_MEMC_SIZE SZ_64K 134#define MX3x_X_MEMC_SIZE SZ_64K
141#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000) 135#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
142#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000) 136#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
@@ -146,56 +140,6 @@
146 140
147#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000 141#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
148 142
149/*!
150 * This macro defines the physical to virtual address mapping for all the
151 * peripheral modules. It is used by passing in the physical address as x
152 * and returning the virtual address. If the physical address is not mapped,
153 * it returns 0xDEADBEEF
154 */
155#define IO_ADDRESS(x) \
156 (void __force __iomem *) \
157 (((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
158 ((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
159 ((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
160 ((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
161 ((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
162 ((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
163 ((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
164 0xDEADBEEF)
165
166/*
167 * define the address mapping macros: in physical address order
168 */
169#define L2CC_IO_ADDRESS(x) \
170 (((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
171
172#define AIPS1_IO_ADDRESS(x) \
173 (((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
174
175#define SPBA0_IO_ADDRESS(x) \
176 (((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
177
178#define AIPS2_IO_ADDRESS(x) \
179 (((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
180
181#define ROMP_IO_ADDRESS(x) \
182 (((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
183
184#define AVIC_IO_ADDRESS(x) \
185 (((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
186
187#define CS4_IO_ADDRESS(x) \
188 (((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
189
190#define CS5_IO_ADDRESS(x) \
191 (((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)
192
193#define X_MEMC_IO_ADDRESS(x) \
194 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
195
196#define PCMCIA_IO_ADDRESS(x) \
197 (((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
198
199/* 143/*
200 * Interrupt numbers 144 * Interrupt numbers
201 */ 145 */
@@ -240,22 +184,6 @@
240 184
241#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */ 185#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
242 186
243/* silicon revisions specific to i.MX31 and i.MX35 */
244#define MX3x_CHIP_REV_1_0 0x10
245#define MX3x_CHIP_REV_1_1 0x11
246#define MX3x_CHIP_REV_1_2 0x12
247#define MX3x_CHIP_REV_1_3 0x13
248#define MX3x_CHIP_REV_2_0 0x20
249#define MX3x_CHIP_REV_2_1 0x21
250#define MX3x_CHIP_REV_2_2 0x22
251#define MX3x_CHIP_REV_2_3 0x23
252#define MX3x_CHIP_REV_3_0 0x30
253#define MX3x_CHIP_REV_3_1 0x31
254#define MX3x_CHIP_REV_3_2 0x32
255
256#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
257#define MX3x_SYSTEM_REV_NUM 3
258
259/* Mandatory defines used globally */ 187/* Mandatory defines used globally */
260 188
261#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 189#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
@@ -277,126 +205,4 @@ static inline int mx35_revision(void)
277} 205}
278#endif 206#endif
279 207
280#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
281/* these should go away */
282#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
283#define L2CC_SIZE MX3x_L2CC_SIZE
284#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
285#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
286#define AIPS1_SIZE MX3x_AIPS1_SIZE
287#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
288#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
289#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
290#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
291#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
292#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
293#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
294#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
295#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
296#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
297#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
298#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
299#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
300#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
301#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
302#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
303#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
304#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
305#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
306#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
307#define SPBA0_SIZE MX3x_SPBA0_SIZE
308#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
309#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
310#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
311#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
312#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
313#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
314#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
315#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
316#define AIPS2_SIZE MX3x_AIPS2_SIZE
317#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
318#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
319#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
320#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
321#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
322#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
323#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
324#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
325#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
326#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
327#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
328#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
329#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
330#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
331#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
332#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
333#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
334#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
335#define ROMP_SIZE MX3x_ROMP_SIZE
336#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
337#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
338#define AVIC_SIZE MX3x_AVIC_SIZE
339#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
340#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
341#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
342#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
343#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
344#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
345#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
346#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
347#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
348#define CS4_SIZE MX3x_CS4_SIZE
349#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
350#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
351#define CS5_SIZE MX3x_CS5_SIZE
352#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
353#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
354#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
355#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
356#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
357#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
358#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
359#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
360#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
361#define MXC_INT_I2C3 MX3x_INT_I2C3
362#define MXC_INT_I2C2 MX3x_INT_I2C2
363#define MXC_INT_RTIC MX3x_INT_RTIC
364#define MXC_INT_I2C MX3x_INT_I2C
365#define MXC_INT_CSPI2 MX3x_INT_CSPI2
366#define MXC_INT_CSPI1 MX3x_INT_CSPI1
367#define MXC_INT_ATA MX3x_INT_ATA
368#define MXC_INT_UART3 MX3x_INT_UART3
369#define MXC_INT_IIM MX3x_INT_IIM
370#define MXC_INT_RNGA MX3x_INT_RNGA
371#define MXC_INT_EVTMON MX3x_INT_EVTMON
372#define MXC_INT_KPP MX3x_INT_KPP
373#define MXC_INT_RTC MX3x_INT_RTC
374#define MXC_INT_PWM MX3x_INT_PWM
375#define MXC_INT_EPIT2 MX3x_INT_EPIT2
376#define MXC_INT_EPIT1 MX3x_INT_EPIT1
377#define MXC_INT_GPT MX3x_INT_GPT
378#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
379#define MXC_INT_UART2 MX3x_INT_UART2
380#define MXC_INT_NANDFC MX3x_INT_NANDFC
381#define MXC_INT_SDMA MX3x_INT_SDMA
382#define MXC_INT_MSHC1 MX3x_INT_MSHC1
383#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
384#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
385#define MXC_INT_UART1 MX3x_INT_UART1
386#define MXC_INT_ECT MX3x_INT_ECT
387#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
388#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
389#define MXC_INT_GPIO2 MX3x_INT_GPIO2
390#define MXC_INT_GPIO1 MX3x_INT_GPIO1
391#define MXC_INT_WDOG MX3x_INT_WDOG
392#define MXC_INT_GPIO3 MX3x_INT_GPIO3
393#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
394#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
395#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
396#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
397#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
398#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
399#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
400#endif
401
402#endif /* ifndef __MACH_MX3x_H__ */ 208#endif /* ifndef __MACH_MX3x_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx50.h b/arch/arm/plat-mxc/include/mach/mx50.h
new file mode 100644
index 000000000000..aaec2a6e7b3a
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx50.h
@@ -0,0 +1,285 @@
1#ifndef __MACH_MX50_H__
2#define __MACH_MX50_H__
3
4/*
5 * IROM
6 */
7#define MX50_IROM_BASE_ADDR 0x0
8#define MX50_IROM_SIZE SZ_64K
9
10/* TZIC */
11#define MX50_TZIC_BASE_ADDR 0x0fffc000
12#define MX50_TZIC_SIZE SZ_16K
13
14/*
15 * IRAM
16 */
17#define MX50_IRAM_BASE_ADDR 0xf8000000 /* internal ram */
18#define MX50_IRAM_PARTITIONS 16
19#define MX50_IRAM_SIZE (MX50_IRAM_PARTITIONS * SZ_8K) /* 128KB */
20
21/*
22 * Databahn
23 */
24#define MX50_DATABAHN_BASE_ADDR 0x14000000
25
26/*
27 * Graphics Memory of GPU
28 */
29#define MX50_GPU2D_BASE_ADDR 0x20000000
30
31#define MX50_DEBUG_BASE_ADDR 0x40000000
32#define MX50_DEBUG_SIZE SZ_1M
33#define MX50_ETB_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00001000)
34#define MX50_ETM_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00002000)
35#define MX50_TPIU_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00003000)
36#define MX50_CTI0_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00004000)
37#define MX50_CTI1_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00005000)
38#define MX50_CTI2_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00006000)
39#define MX50_CTI3_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00007000)
40#define MX50_CORTEX_DBG_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x00008000)
41
42#define MX50_APBHDMA_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01000000)
43#define MX50_OCOTP_CTRL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01002000)
44#define MX50_DIGCTL_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01004000)
45#define MX50_GPMI_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01006000)
46#define MX50_BCH_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01008000)
47#define MX50_ELCDIF_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100a000)
48#define MX50_EPXP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100c000)
49#define MX50_DCP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x0100e000)
50#define MX50_EPDC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01010000)
51#define MX50_QOSC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01012000)
52#define MX50_PERFMON_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01014000)
53#define MX50_SSP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01016000)
54#define MX50_ANATOP_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x01018000)
55#define MX50_NIC_BASE_ADDR (MX50_DEBUG_BASE_ADDR + 0x08000000)
56
57/*
58 * SPBA global module enabled #0
59 */
60#define MX50_SPBA0_BASE_ADDR 0x50000000
61#define MX50_SPBA0_SIZE SZ_1M
62
63#define MX50_MMC_SDHC1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00004000)
64#define MX50_MMC_SDHC2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00008000)
65#define MX50_UART3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x0000c000)
66#define MX50_CSPI1_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00010000)
67#define MX50_SSI2_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00014000)
68#define MX50_MMC_SDHC3_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00020000)
69#define MX50_MMC_SDHC4_BASE_ADDR (MX50_SPBA0_BASE_ADDR + 0x00024000)
70
71/*
72 * AIPS 1
73 */
74#define MX50_AIPS1_BASE_ADDR 0x53f00000
75#define MX50_AIPS1_SIZE SZ_1M
76
77#define MX50_OTG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00080000)
78#define MX50_GPIO1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00084000)
79#define MX50_GPIO2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00088000)
80#define MX50_GPIO3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x0008c000)
81#define MX50_GPIO4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00090000)
82#define MX50_KPP_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00094000)
83#define MX50_WDOG_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x00098000)
84#define MX50_GPT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a0000)
85#define MX50_SRTC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a4000)
86#define MX50_IOMUXC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000a8000)
87#define MX50_EPIT1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ac000)
88#define MX50_PWM1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b4000)
89#define MX50_PWM2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000b8000)
90#define MX50_UART1_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000bc000)
91#define MX50_UART2_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000c0000)
92#define MX50_SRC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d0000)
93#define MX50_CCM_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d4000)
94#define MX50_GPC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000d8000)
95#define MX50_GPIO5_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000dc000)
96#define MX50_GPIO6_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000e0000)
97#define MX50_I2C3_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000ec000)
98#define MX50_UART4_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f0000)
99
100#define MX50_MSHC_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f4000)
101#define MX50_RNGB_BASE_ADDR (MX50_AIPS1_BASE_ADDR + 0x000f8000)
102
103/*
104 * AIPS 2
105 */
106#define MX50_AIPS2_BASE_ADDR 0x63f00000
107#define MX50_AIPS2_SIZE SZ_1M
108
109#define MX50_PLL1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00080000)
110#define MX50_PLL2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00084000)
111#define MX50_PLL3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00088000)
112#define MX50_UART5_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00090000)
113#define MX50_AHBMAX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x00094000)
114#define MX50_ARM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a0000)
115#define MX50_OWIRE_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000a4000)
116#define MX50_CSPI2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ac000)
117#define MX50_SDMA_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b0000)
118#define MX50_ROMCP_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000b8000)
119#define MX50_CSPI3_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c0000)
120#define MX50_I2C2_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c4000)
121#define MX50_I2C1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000c8000)
122#define MX50_SSI1_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000cc000)
123#define MX50_AUDMUX_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d0000)
124#define MX50_WEIM_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000d8000)
125#define MX50_FEC_BASE_ADDR (MX50_AIPS2_BASE_ADDR + 0x000ec000)
126
127/*
128 * Memory regions and CS
129 */
130#define MX50_CSD0_BASE_ADDR 0x70000000
131#define MX50_CSD1_BASE_ADDR 0xb0000000
132#define MX50_CS0_BASE_ADDR 0xf0000000
133
134#define MX50_IO_P2V(x) IMX_IO_P2V(x)
135#define MX50_IO_ADDRESS(x) IOMEM(MX50_IO_P2V(x))
136
137/*
138 * defines for SPBA modules
139 */
140#define MX50_SPBA_SDHC1 0x04
141#define MX50_SPBA_SDHC2 0x08
142#define MX50_SPBA_UART3 0x0c
143#define MX50_SPBA_CSPI1 0x10
144#define MX50_SPBA_SSI2 0x14
145#define MX50_SPBA_SDHC3 0x20
146#define MX50_SPBA_SDHC4 0x24
147#define MX50_SPBA_SPDIF 0x28
148#define MX50_SPBA_ATA 0x30
149#define MX50_SPBA_SLIM 0x34
150#define MX50_SPBA_HSI2C 0x38
151#define MX50_SPBA_CTRL 0x3c
152
153/*
154 * DMA request assignments
155 */
156#define MX50_DMA_REQ_GPC 1
157#define MX50_DMA_REQ_ATA_UART4_RX 2
158#define MX50_DMA_REQ_ATA_UART4_TX 3
159#define MX50_DMA_REQ_CSPI1_RX 6
160#define MX50_DMA_REQ_CSPI1_TX 7
161#define MX50_DMA_REQ_CSPI2_RX 8
162#define MX50_DMA_REQ_CSPI2_TX 9
163#define MX50_DMA_REQ_I2C3_SDHC3 10
164#define MX50_DMA_REQ_SDHC4 11
165#define MX50_DMA_REQ_UART2_FIRI_RX 12
166#define MX50_DMA_REQ_UART2_FIRI_TX 13
167#define MX50_DMA_REQ_EXT0 14
168#define MX50_DMA_REQ_EXT1 15
169#define MX50_DMA_REQ_UART5_RX 16
170#define MX50_DMA_REQ_UART5_TX 17
171#define MX50_DMA_REQ_UART1_RX 18
172#define MX50_DMA_REQ_UART1_TX 19
173#define MX50_DMA_REQ_I2C1_SDHC1 20
174#define MX50_DMA_REQ_I2C2_SDHC2 21
175#define MX50_DMA_REQ_SSI2_RX2 22
176#define MX50_DMA_REQ_SSI2_TX2 23
177#define MX50_DMA_REQ_SSI2_RX1 24
178#define MX50_DMA_REQ_SSI2_TX1 25
179#define MX50_DMA_REQ_SSI1_RX2 26
180#define MX50_DMA_REQ_SSI1_TX2 27
181#define MX50_DMA_REQ_SSI1_RX1 28
182#define MX50_DMA_REQ_SSI1_TX1 29
183#define MX50_DMA_REQ_CSPI_RX 38
184#define MX50_DMA_REQ_CSPI_TX 39
185#define MX50_DMA_REQ_UART3_RX 42
186#define MX50_DMA_REQ_UART3_TX 43
187
188/*
189 * Interrupt numbers
190 */
191#define MX50_INT_MMC_SDHC1 1
192#define MX50_INT_MMC_SDHC2 2
193#define MX50_INT_MMC_SDHC3 3
194#define MX50_INT_MMC_SDHC4 4
195#define MX50_INT_DAP 5
196#define MX50_INT_SDMA 6
197#define MX50_INT_IOMUX 7
198#define MX50_INT_UART4 13
199#define MX50_INT_USB_H1 14
200#define MX50_INT_USB_OTG 18
201#define MX50_INT_DATABAHN 19
202#define MX50_INT_ELCDIF 20
203#define MX50_INT_EPXP 21
204#define MX50_INT_SRTC_NTZ 24
205#define MX50_INT_SRTC_TZ 25
206#define MX50_INT_EPDC 27
207#define MX50_INT_NIC 28
208#define MX50_INT_SSI1 29
209#define MX50_INT_SSI2 30
210#define MX50_INT_UART1 31
211#define MX50_INT_UART2 32
212#define MX50_INT_UART3 33
213#define MX50_INT_RESV34 34
214#define MX50_INT_RESV35 35
215#define MX50_INT_CSPI1 36
216#define MX50_INT_CSPI2 37
217#define MX50_INT_CSPI 38
218#define MX50_INT_GPT 39
219#define MX50_INT_EPIT1 40
220#define MX50_INT_GPIO1_INT7 42
221#define MX50_INT_GPIO1_INT6 43
222#define MX50_INT_GPIO1_INT5 44
223#define MX50_INT_GPIO1_INT4 45
224#define MX50_INT_GPIO1_INT3 46
225#define MX50_INT_GPIO1_INT2 47
226#define MX50_INT_GPIO1_INT1 48
227#define MX50_INT_GPIO1_INT0 49
228#define MX50_INT_GPIO1_LOW 50
229#define MX50_INT_GPIO1_HIGH 51
230#define MX50_INT_GPIO2_LOW 52
231#define MX50_INT_GPIO2_HIGH 53
232#define MX50_INT_GPIO3_LOW 54
233#define MX50_INT_GPIO3_HIGH 55
234#define MX50_INT_GPIO4_LOW 56
235#define MX50_INT_GPIO4_HIGH 57
236#define MX50_INT_WDOG1 58
237#define MX50_INT_KPP 60
238#define MX50_INT_PWM1 61
239#define MX50_INT_I2C1 62
240#define MX50_INT_I2C2 63
241#define MX50_INT_I2C3 64
242#define MX50_INT_RESV65 65
243#define MX50_INT_DCDC 66
244#define MX50_INT_THERMAL_ALARM 67
245#define MX50_INT_ANA3 68
246#define MX50_INT_ANA4 69
247#define MX50_INT_CCM1 71
248#define MX50_INT_CCM2 72
249#define MX50_INT_GPC1 73
250#define MX50_INT_GPC2 74
251#define MX50_INT_SRC 75
252#define MX50_INT_NM 76
253#define MX50_INT_PMU 77
254#define MX50_INT_CTI_IRQ 78
255#define MX50_INT_CTI1_TG0 79
256#define MX50_INT_CTI1_TG1 80
257#define MX50_INT_GPU2_IRQ 84
258#define MX50_INT_GPU2_BUSY 85
259#define MX50_INT_UART5 86
260#define MX50_INT_FEC 87
261#define MX50_INT_OWIRE 88
262#define MX50_INT_CTI1_TG2 89
263#define MX50_INT_SJC 90
264#define MX50_INT_DCP_CHAN1_3 91
265#define MX50_INT_DCP_CHAN0 92
266#define MX50_INT_PWM2 94
267#define MX50_INT_RNGB 97
268#define MX50_INT_CTI1_TG3 98
269#define MX50_INT_RAWNAND_BCH 100
270#define MX50_INT_RAWNAND_GPMI 102
271#define MX50_INT_GPIO5_LOW 103
272#define MX50_INT_GPIO5_HIGH 104
273#define MX50_INT_GPIO6_LOW 105
274#define MX50_INT_GPIO6_HIGH 106
275#define MX50_INT_MSHC 109
276#define MX50_INT_APBHDMA_CHAN0 110
277#define MX50_INT_APBHDMA_CHAN1 111
278#define MX50_INT_APBHDMA_CHAN2 112
279#define MX50_INT_APBHDMA_CHAN3 113
280#define MX50_INT_APBHDMA_CHAN4 114
281#define MX50_INT_APBHDMA_CHAN5 115
282#define MX50_INT_APBHDMA_CHAN6 116
283#define MX50_INT_APBHDMA_CHAN7 117
284
285#endif /* ifndef __MACH_MX50_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 2af7a1056fc1..873807f96d70 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -2,31 +2,6 @@
2#define __MACH_MX51_H__ 2#define __MACH_MX51_H__
3 3
4/* 4/*
5 * MX51 memory map:
6 *
7 *
8 * Virt Phys Size What
9 * ---------------------------------------------------------------------------
10 * fa3e0000 1ffe0000 128K IRAM (SCCv2 RAM)
11 * 30000000 256M GPU
12 * 40000000 512M IPU
13 * fa200000 60000000 1M DEBUG
14 * fb100000 70000000 1M SPBA 0
15 * fb000000 73f00000 1M AIPS 1
16 * fb200000 83f00000 1M AIPS 2
17 * 8fffc000 16K TZIC (interrupt controller)
18 * 90000000 256M CSD0 SDRAM/DDR
19 * a0000000 256M CSD1 SDRAM/DDR
20 * b0000000 128M CS0 Flash
21 * b8000000 128M CS1 Flash
22 * c0000000 128M CS2 Flash
23 * c8000000 64M CS3 Flash
24 * cc000000 32M CS4 SRAM
25 * ce000000 32M CS5 SRAM
26 * cfff0000 64K NFC (NAND Flash AXI)
27 */
28
29/*
30 * IROM 5 * IROM
31 */ 6 */
32#define MX51_IROM_BASE_ADDR 0x0 7#define MX51_IROM_BASE_ADDR 0x0
@@ -36,7 +11,6 @@
36 * IRAM 11 * IRAM
37 */ 12 */
38#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */ 13#define MX51_IRAM_BASE_ADDR 0x1ffe0000 /* internal ram */
39#define MX51_IRAM_BASE_ADDR_VIRT 0xfa3e0000
40#define MX51_IRAM_PARTITIONS 16 14#define MX51_IRAM_PARTITIONS 16
41#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */ 15#define MX51_IRAM_SIZE (MX51_IRAM_PARTITIONS * SZ_8K) /* 128KB */
42 16
@@ -45,7 +19,6 @@
45#define MX51_IPU_CTRL_BASE_ADDR 0x40000000 19#define MX51_IPU_CTRL_BASE_ADDR 0x40000000
46 20
47#define MX51_DEBUG_BASE_ADDR 0x60000000 21#define MX51_DEBUG_BASE_ADDR 0x60000000
48#define MX51_DEBUG_BASE_ADDR_VIRT 0xfa200000
49#define MX51_DEBUG_SIZE SZ_1M 22#define MX51_DEBUG_SIZE SZ_1M
50 23
51#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000) 24#define MX51_ETB_BASE_ADDR (MX51_DEBUG_BASE_ADDR + 0x01000)
@@ -61,7 +34,6 @@
61 * SPBA global module enabled #0 34 * SPBA global module enabled #0
62 */ 35 */
63#define MX51_SPBA0_BASE_ADDR 0x70000000 36#define MX51_SPBA0_BASE_ADDR 0x70000000
64#define MX51_SPBA0_BASE_ADDR_VIRT 0xfb100000
65#define MX51_SPBA0_SIZE SZ_1M 37#define MX51_SPBA0_SIZE SZ_1M
66 38
67#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000) 39#define MX51_ESDHC1_BASE_ADDR (MX51_SPBA0_BASE_ADDR + 0x04000)
@@ -81,7 +53,6 @@
81 * AIPS 1 53 * AIPS 1
82 */ 54 */
83#define MX51_AIPS1_BASE_ADDR 0x73f00000 55#define MX51_AIPS1_BASE_ADDR 0x73f00000
84#define MX51_AIPS1_BASE_ADDR_VIRT 0xfb000000
85#define MX51_AIPS1_SIZE SZ_1M 56#define MX51_AIPS1_SIZE SZ_1M
86 57
87#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000) 58#define MX51_OTG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x80000)
@@ -90,7 +61,7 @@
90#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000) 61#define MX51_GPIO3_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x8c000)
91#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000) 62#define MX51_GPIO4_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x90000)
92#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000) 63#define MX51_KPP_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x94000)
93#define MX51_WDOG_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000) 64#define MX51_WDOG1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x98000)
94#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000) 65#define MX51_WDOG2_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0x9c000)
95#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000) 66#define MX51_GPT1_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa0000)
96#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000) 67#define MX51_SRTC_BASE_ADDR (MX51_AIPS1_BASE_ADDR + 0xa4000)
@@ -109,7 +80,6 @@
109 * AIPS 2 80 * AIPS 2
110 */ 81 */
111#define MX51_AIPS2_BASE_ADDR 0x83f00000 82#define MX51_AIPS2_BASE_ADDR 0x83f00000
112#define MX51_AIPS2_BASE_ADDR_VIRT 0xfb200000
113#define MX51_AIPS2_SIZE SZ_1M 83#define MX51_AIPS2_SIZE SZ_1M
114 84
115#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000) 85#define MX51_PLL1_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0x80000)
@@ -139,7 +109,7 @@
139#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000) 109#define MX51_MIPI_HSC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xdc000)
140#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000) 110#define MX51_ATA_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe0000)
141#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000) 111#define MX51_SIM_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe4000)
142#define MX51_SSI3BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000) 112#define MX51_SSI3_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xe8000)
143#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000) 113#define MX51_FEC_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xec000)
144#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000) 114#define MX51_TVE_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf0000)
145#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000) 115#define MX51_VPU_BASE_ADDR (MX51_AIPS2_BASE_ADDR + 0xf4000)
@@ -163,16 +133,8 @@
163#define MX51_GPU2D_BASE_ADDR 0xd0000000 133#define MX51_GPU2D_BASE_ADDR 0xd0000000
164#define MX51_TZIC_BASE_ADDR 0xe0000000 134#define MX51_TZIC_BASE_ADDR 0xe0000000
165 135
166#define MX51_IO_ADDRESS(x) ( \ 136#define MX51_IO_P2V(x) IMX_IO_P2V(x)
167 IMX_IO_ADDRESS(x, MX51_IRAM) ?: \ 137#define MX51_IO_ADDRESS(x) IOMEM(MX51_IO_P2V(x))
168 IMX_IO_ADDRESS(x, MX51_DEBUG) ?: \
169 IMX_IO_ADDRESS(x, MX51_SPBA0) ?: \
170 IMX_IO_ADDRESS(x, MX51_AIPS1) ?: \
171 IMX_IO_ADDRESS(x, MX51_AIPS2))
172
173/* This is currently used in <mach/debug-macro.S>, but should go away */
174#define MX51_AIPS1_IO_ADDRESS(x) \
175 (((x) - MX51_AIPS1_BASE_ADDR) + MX51_AIPS1_BASE_ADDR_VIRT)
176 138
177/* 139/*
178 * defines for SPBA modules 140 * defines for SPBA modules
@@ -261,9 +223,9 @@
261#define MX51_DMA_REQ_EMI_WR 32 223#define MX51_DMA_REQ_EMI_WR 32
262#define MX51_DMA_REQ_CTI2_1 33 224#define MX51_DMA_REQ_CTI2_1 33
263#define MX51_DMA_REQ_EPIT2 34 225#define MX51_DMA_REQ_EPIT2 34
264#define MX51_DMA_REQ_SSI3_RX2 35 226#define MX51_DMA_REQ_SSI3_RX1 35
265#define MX51_DMA_REQ_IPU 36 227#define MX51_DMA_REQ_IPU 36
266#define MX51_DMA_REQ_SSI3_TX2 37 228#define MX51_DMA_REQ_SSI3_TX1 37
267#define MX51_DMA_REQ_CSPI_RX 38 229#define MX51_DMA_REQ_CSPI_RX 38
268#define MX51_DMA_REQ_CSPI_TX 39 230#define MX51_DMA_REQ_CSPI_TX 39
269#define MX51_DMA_REQ_SDHC3 40 231#define MX51_DMA_REQ_SDHC3 40
@@ -272,8 +234,8 @@
272#define MX51_DMA_REQ_UART3_RX 43 234#define MX51_DMA_REQ_UART3_RX 43
273#define MX51_DMA_REQ_UART3_TX 44 235#define MX51_DMA_REQ_UART3_TX 44
274#define MX51_DMA_REQ_SPDIF 45 236#define MX51_DMA_REQ_SPDIF 45
275#define MX51_DMA_REQ_SSI3_RX1 46 237#define MX51_DMA_REQ_SSI3_RX0 46
276#define MX51_DMA_REQ_SSI3_TX1 47 238#define MX51_DMA_REQ_SSI3_TX0 47
277 239
278/* 240/*
279 * Interrupt numbers 241 * Interrupt numbers
@@ -289,8 +251,8 @@
289#define MX51_MXC_INT_IOMUX 7 251#define MX51_MXC_INT_IOMUX 7
290#define MX51_INT_NFC 8 252#define MX51_INT_NFC 8
291#define MX51_MXC_INT_VPU 9 253#define MX51_MXC_INT_VPU 9
292#define MX51_MXC_INT_IPU_ERR 10 254#define MX51_INT_IPU_ERR 10
293#define MX51_MXC_INT_IPU_SYN 11 255#define MX51_INT_IPU_SYN 11
294#define MX51_MXC_INT_GPU 12 256#define MX51_MXC_INT_GPU 12
295#define MX51_MXC_INT_RESV13 13 257#define MX51_MXC_INT_RESV13 13
296#define MX51_MXC_INT_USB_H1 14 258#define MX51_MXC_INT_USB_H1 14
@@ -375,7 +337,7 @@
375#define MX51_MXC_INT_FIRI 93 337#define MX51_MXC_INT_FIRI 93
376#define MX51_MXC_INT_PWM2 94 338#define MX51_MXC_INT_PWM2 94
377#define MX51_MXC_INT_SLIM_EXP 95 339#define MX51_MXC_INT_SLIM_EXP 95
378#define MX51_MXC_INT_SSI3 96 340#define MX51_INT_SSI3 96
379#define MX51_MXC_INT_EMI_BOOT 97 341#define MX51_MXC_INT_EMI_BOOT 97
380#define MX51_MXC_INT_CTI1_TG3 98 342#define MX51_MXC_INT_CTI1_TG3 98
381#define MX51_MXC_INT_SMC_RX 99 343#define MX51_MXC_INT_SMC_RX 99
@@ -383,19 +345,6 @@
383#define MX51_MXC_INT_EMI_NFC 101 345#define MX51_MXC_INT_EMI_NFC 101
384#define MX51_MXC_INT_GPU_IDLE 102 346#define MX51_MXC_INT_GPU_IDLE 102
385 347
386/* silicon revisions specific to i.MX51 */
387#define MX51_CHIP_REV_1_0 0x10
388#define MX51_CHIP_REV_1_1 0x11
389#define MX51_CHIP_REV_1_2 0x12
390#define MX51_CHIP_REV_1_3 0x13
391#define MX51_CHIP_REV_2_0 0x20
392#define MX51_CHIP_REV_2_1 0x21
393#define MX51_CHIP_REV_2_2 0x22
394#define MX51_CHIP_REV_2_3 0x23
395#define MX51_CHIP_REV_3_0 0x30
396#define MX51_CHIP_REV_3_1 0x31
397#define MX51_CHIP_REV_3_2 0x32
398
399#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS) 348#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
400extern int mx51_revision(void); 349extern int mx51_revision(void);
401#endif 350#endif
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
new file mode 100644
index 000000000000..9577cdbf7fad
--- /dev/null
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -0,0 +1,353 @@
1#ifndef __MACH_MX53_H__
2#define __MACH_MX53_H__
3
4/*
5 * IROM
6 */
7#define MX53_IROM_BASE_ADDR 0x0
8#define MX53_IROM_SIZE SZ_64K
9
10/* TZIC */
11#define MX53_TZIC_BASE_ADDR 0x0FFFC000
12
13/*
14 * AHCI SATA
15 */
16#define MX53_SATA_BASE_ADDR 0x10000000
17
18/*
19 * NFC
20 */
21#define MX53_NFC_AXI_BASE_ADDR 0xF7FF0000 /* NAND flash AXI */
22#define MX53_NFC_AXI_SIZE SZ_64K
23
24/*
25 * IRAM
26 */
27#define MX53_IRAM_BASE_ADDR 0xF8000000 /* internal ram */
28#define MX53_IRAM_PARTITIONS 16
29#define MX53_IRAM_SIZE (MX53_IRAM_PARTITIONS * SZ_8K) /* 128KB */
30
31/*
32 * Graphics Memory of GPU
33 */
34#define MX53_IPU_CTRL_BASE_ADDR 0x18000000
35#define MX53_GPU2D_BASE_ADDR 0x20000000
36#define MX53_GPU_BASE_ADDR 0x30000000
37#define MX53_GPU_GMEM_BASE_ADDR 0xF8020000
38
39#define MX53_DEBUG_BASE_ADDR 0x40000000
40#define MX53_DEBUG_SIZE SZ_1M
41#define MX53_ETB_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00001000)
42#define MX53_ETM_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00002000)
43#define MX53_TPIU_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00003000)
44#define MX53_CTI0_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00004000)
45#define MX53_CTI1_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00005000)
46#define MX53_CTI2_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00006000)
47#define MX53_CTI3_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00007000)
48#define MX53_CORTEX_DBG_BASE_ADDR (MX53_DEBUG_BASE_ADDR + 0x00008000)
49
50/*
51 * SPBA global module enabled #0
52 */
53#define MX53_SPBA0_BASE_ADDR 0x50000000
54#define MX53_SPBA0_SIZE SZ_1M
55
56#define MX53_MMC_SDHC1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00004000)
57#define MX53_MMC_SDHC2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00008000)
58#define MX53_UART3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0000C000)
59#define MX53_CSPI1_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00010000)
60#define MX53_SSI2_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00014000)
61#define MX53_MMC_SDHC3_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00020000)
62#define MX53_MMC_SDHC4_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00024000)
63#define MX53_SPDIF_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00028000)
64#define MX53_ASRC_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0002C000)
65#define MX53_ATA_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00030000)
66#define MX53_SLIM_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00034000)
67#define MX53_HSI2C_DMA_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x00038000)
68#define MX53_SPBA_CTRL_BASE_ADDR (MX53_SPBA0_BASE_ADDR + 0x0003C000)
69
70/*
71 * AIPS 1
72 */
73#define MX53_AIPS1_BASE_ADDR 0x53F00000
74#define MX53_AIPS1_SIZE SZ_1M
75
76#define MX53_OTG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00080000)
77#define MX53_GPIO1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00084000)
78#define MX53_GPIO2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00088000)
79#define MX53_GPIO3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0008C000)
80#define MX53_GPIO4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00090000)
81#define MX53_KPP_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00094000)
82#define MX53_WDOG_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x00098000)
83#define MX53_WDOG2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x0009C000)
84#define MX53_GPT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A0000)
85#define MX53_SRTC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A4000)
86#define MX53_IOMUXC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000A8000)
87#define MX53_EPIT1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000AC000)
88#define MX53_EPIT2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B0000)
89#define MX53_PWM1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B4000)
90#define MX53_PWM2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000B8000)
91#define MX53_UART1_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000BC000)
92#define MX53_UART2_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000C0000)
93#define MX53_SRC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D0000)
94#define MX53_CCM_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D4000)
95#define MX53_GPC_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000D8000)
96#define MX53_GPIO5_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000DC000)
97#define MX53_GPIO6_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E0000)
98#define MX53_GPIO7_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E4000)
99#define MX53_ATA_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000E8000)
100#define MX53_I2C3_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000EC000)
101#define MX53_UART4_BASE_ADDR (MX53_AIPS1_BASE_ADDR + 0x000F0000)
102
103/*
104 * AIPS 2
105 */
106#define MX53_AIPS2_BASE_ADDR 0x63F00000
107#define MX53_AIPS2_SIZE SZ_1M
108
109#define MX53_PLL1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00080000)
110#define MX53_PLL2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00084000)
111#define MX53_PLL3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00088000)
112#define MX53_PLL4_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0008C000)
113#define MX53_UART5_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00090000)
114#define MX53_AHBMAX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00094000)
115#define MX53_IIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x00098000)
116#define MX53_CSU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x0009C000)
117#define MX53_ARM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A0000)
118#define MX53_OWIRE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A4000)
119#define MX53_FIRI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000A8000)
120#define MX53_CSPI2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000AC000)
121#define MX53_SDMA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B0000)
122#define MX53_SCC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B4000)
123#define MX53_ROMCP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000B8000)
124#define MX53_RTIC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000BC000)
125#define MX53_CSPI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C0000)
126#define MX53_I2C2_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C4000)
127#define MX53_I2C1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000C8000)
128#define MX53_SSI1_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000CC000)
129#define MX53_AUDMUX_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D0000)
130#define MX53_RTC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D4000)
131#define MX53_M4IF_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D8000)
132#define MX53_ESDCTL_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000D9000)
133#define MX53_WEIM_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DA000)
134#define MX53_NFC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DB000)
135#define MX53_EMI_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DBF00)
136#define MX53_MIPI_HSC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000DC000)
137#define MX53_MLB_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E4000)
138#define MX53_SSI3_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000E8000)
139#define MX53_MXC_FEC_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000EC000)
140#define MX53_TVE_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F0000)
141#define MX53_VPU_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F4000)
142#define MX53_SAHARA_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000F8000)
143#define MX53_PTP_BASE_ADDR (MX53_AIPS2_BASE_ADDR + 0x000FC000)
144
145/*
146 * Memory regions and CS
147 */
148#define MX53_CSD0_BASE_ADDR 0x90000000
149#define MX53_CSD1_BASE_ADDR 0xA0000000
150#define MX53_CS0_BASE_ADDR 0xB0000000
151#define MX53_CS1_BASE_ADDR 0xB8000000
152#define MX53_CS2_BASE_ADDR 0xC0000000
153#define MX53_CS3_BASE_ADDR 0xC8000000
154#define MX53_CS4_BASE_ADDR 0xCC000000
155#define MX53_CS5_BASE_ADDR 0xCE000000
156
157#define MX53_IO_P2V(x) IMX_IO_P2V(x)
158#define MX53_IO_ADDRESS(x) IOMEM(MX53_IO_P2V(x))
159
160/*
161 * defines for SPBA modules
162 */
163#define MX53_SPBA_SDHC1 0x04
164#define MX53_SPBA_SDHC2 0x08
165#define MX53_SPBA_UART3 0x0C
166#define MX53_SPBA_CSPI1 0x10
167#define MX53_SPBA_SSI2 0x14
168#define MX53_SPBA_SDHC3 0x20
169#define MX53_SPBA_SDHC4 0x24
170#define MX53_SPBA_SPDIF 0x28
171#define MX53_SPBA_ATA 0x30
172#define MX53_SPBA_SLIM 0x34
173#define MX53_SPBA_HSI2C 0x38
174#define MX53_SPBA_CTRL 0x3C
175
176/*
177 * DMA request assignments
178 */
179#define MX53_DMA_REQ_SSI3_TX1 47
180#define MX53_DMA_REQ_SSI3_RX1 46
181#define MX53_DMA_REQ_SSI3_TX2 45
182#define MX53_DMA_REQ_SSI3_RX2 44
183#define MX53_DMA_REQ_UART3_TX 43
184#define MX53_DMA_REQ_UART3_RX 42
185#define MX53_DMA_REQ_ESAI_TX 41
186#define MX53_DMA_REQ_ESAI_RX 40
187#define MX53_DMA_REQ_CSPI_TX 39
188#define MX53_DMA_REQ_CSPI_RX 38
189#define MX53_DMA_REQ_ASRC_DMA6 37
190#define MX53_DMA_REQ_ASRC_DMA5 36
191#define MX53_DMA_REQ_ASRC_DMA4 35
192#define MX53_DMA_REQ_ASRC_DMA3 34
193#define MX53_DMA_REQ_ASRC_DMA2 33
194#define MX53_DMA_REQ_ASRC_DMA1 32
195#define MX53_DMA_REQ_EMI_WR 31
196#define MX53_DMA_REQ_EMI_RD 30
197#define MX53_DMA_REQ_SSI1_TX1 29
198#define MX53_DMA_REQ_SSI1_RX1 28
199#define MX53_DMA_REQ_SSI1_TX2 27
200#define MX53_DMA_REQ_SSI1_RX2 26
201#define MX53_DMA_REQ_SSI2_TX1 25
202#define MX53_DMA_REQ_SSI2_RX1 24
203#define MX53_DMA_REQ_SSI2_TX2 23
204#define MX53_DMA_REQ_SSI2_RX2 22
205#define MX53_DMA_REQ_I2C2_SDHC2 21
206#define MX53_DMA_REQ_I2C1_SDHC1 20
207#define MX53_DMA_REQ_UART1_TX 19
208#define MX53_DMA_REQ_UART1_RX 18
209#define MX53_DMA_REQ_UART5_TX 17
210#define MX53_DMA_REQ_UART5_RX 16
211#define MX53_DMA_REQ_SPDIF_TX 15
212#define MX53_DMA_REQ_SPDIF_RX 14
213#define MX53_DMA_REQ_UART2_FIRI_TX 13
214#define MX53_DMA_REQ_UART2_FIRI_RX 12
215#define MX53_DMA_REQ_SDHC4 11
216#define MX53_DMA_REQ_I2C3_SDHC3 10
217#define MX53_DMA_REQ_CSPI2_TX 9
218#define MX53_DMA_REQ_CSPI2_RX 8
219#define MX53_DMA_REQ_CSPI1_TX 7
220#define MX53_DMA_REQ_CSPI1_RX 6
221#define MX53_DMA_REQ_IPU 5
222#define MX53_DMA_REQ_ATA_TX_END 4
223#define MX53_DMA_REQ_ATA_UART4_TX 3
224#define MX53_DMA_REQ_ATA_UART4_RX 2
225#define MX53_DMA_REQ_GPC 1
226#define MX53_DMA_REQ_VPU 0
227
228/*
229 * Interrupt numbers
230 */
231#define MX53_INT_RESV0 0
232#define MX53_INT_MMC_SDHC1 1
233#define MX53_INT_MMC_SDHC2 2
234#define MX53_INT_MMC_SDHC3 3
235#define MX53_INT_MMC_SDHC4 4
236#define MX53_INT_RESV5 5
237#define MX53_INT_SDMA 6
238#define MX53_INT_IOMUX 7
239#define MX53_INT_NFC 8
240#define MX53_INT_VPU 9
241#define MX53_INT_IPU_ERR 10
242#define MX53_INT_IPU_SYN 11
243#define MX53_INT_GPU 12
244#define MX53_INT_RESV13 13
245#define MX53_INT_USB_H1 14
246#define MX53_INT_EMI 15
247#define MX53_INT_USB_H2 16
248#define MX53_INT_USB_H3 17
249#define MX53_INT_USB_OTG 18
250#define MX53_INT_SAHARA_H0 19
251#define MX53_INT_SAHARA_H1 20
252#define MX53_INT_SCC_SMN 21
253#define MX53_INT_SCC_STZ 22
254#define MX53_INT_SCC_SCM 23
255#define MX53_INT_SRTC_NTZ 24
256#define MX53_INT_SRTC_TZ 25
257#define MX53_INT_RTIC 26
258#define MX53_INT_CSU 27
259#define MX53_INT_SATA 28
260#define MX53_INT_SSI1 29
261#define MX53_INT_SSI2 30
262#define MX53_INT_UART1 31
263#define MX53_INT_UART2 32
264#define MX53_INT_UART3 33
265#define MX53_INT_RESV34 34
266#define MX53_INT_RESV35 35
267#define MX53_INT_CSPI1 36
268#define MX53_INT_CSPI2 37
269#define MX53_INT_CSPI 38
270#define MX53_INT_GPT 39
271#define MX53_INT_EPIT1 40
272#define MX53_INT_EPIT2 41
273#define MX53_INT_GPIO1_INT7 42
274#define MX53_INT_GPIO1_INT6 43
275#define MX53_INT_GPIO1_INT5 44
276#define MX53_INT_GPIO1_INT4 45
277#define MX53_INT_GPIO1_INT3 46
278#define MX53_INT_GPIO1_INT2 47
279#define MX53_INT_GPIO1_INT1 48
280#define MX53_INT_GPIO1_INT0 49
281#define MX53_INT_GPIO1_LOW 50
282#define MX53_INT_GPIO1_HIGH 51
283#define MX53_INT_GPIO2_LOW 52
284#define MX53_INT_GPIO2_HIGH 53
285#define MX53_INT_GPIO3_LOW 54
286#define MX53_INT_GPIO3_HIGH 55
287#define MX53_INT_GPIO4_LOW 56
288#define MX53_INT_GPIO4_HIGH 57
289#define MX53_INT_WDOG1 58
290#define MX53_INT_WDOG2 59
291#define MX53_INT_KPP 60
292#define MX53_INT_PWM1 61
293#define MX53_INT_I2C1 62
294#define MX53_INT_I2C2 63
295#define MX53_INT_I2C3 64
296#define MX53_INT_RESV65 65
297#define MX53_INT_RESV66 66
298#define MX53_INT_SPDIF 67
299#define MX53_INT_SIM_DAT 68
300#define MX53_INT_IIM 69
301#define MX53_INT_ATA 70
302#define MX53_INT_CCM1 71
303#define MX53_INT_CCM2 72
304#define MX53_INT_GPC1 73
305#define MX53_INT_GPC2 74
306#define MX53_INT_SRC 75
307#define MX53_INT_NM 76
308#define MX53_INT_PMU 77
309#define MX53_INT_CTI_IRQ 78
310#define MX53_INT_CTI1_TG0 79
311#define MX53_INT_CTI1_TG1 80
312#define MX53_INT_ESAI 81
313#define MX53_INT_CAN1 82
314#define MX53_INT_CAN2 83
315#define MX53_INT_GPU2_IRQ 84
316#define MX53_INT_GPU2_BUSY 85
317#define MX53_INT_RESV86 86
318#define MX53_INT_FEC 87
319#define MX53_INT_OWIRE 88
320#define MX53_INT_CTI1_TG2 89
321#define MX53_INT_SJC 90
322#define MX53_INT_TVE 92
323#define MX53_INT_FIRI 93
324#define MX53_INT_PWM2 94
325#define MX53_INT_SLIM_EXP 95
326#define MX53_INT_SSI3 96
327#define MX53_INT_EMI_BOOT 97
328#define MX53_INT_CTI1_TG3 98
329#define MX53_INT_SMC_RX 99
330#define MX53_INT_VPU_IDLE 100
331#define MX53_INT_EMI_NFC 101
332#define MX53_INT_GPU_IDLE 102
333#define MX53_INT_GPIO5_LOW 103
334#define MX53_INT_GPIO5_HIGH 104
335#define MX53_INT_GPIO6_LOW 105
336#define MX53_INT_GPIO6_HIGH 106
337#define MX53_INT_GPIO7_LOW 107
338#define MX53_INT_GPIO7_HIGH 108
339
340/* silicon revisions specific to i.MX53 */
341#define MX53_CHIP_REV_1_0 0x10
342#define MX53_CHIP_REV_1_1 0x11
343#define MX53_CHIP_REV_1_2 0x12
344#define MX53_CHIP_REV_1_3 0x13
345#define MX53_CHIP_REV_2_0 0x20
346#define MX53_CHIP_REV_2_1 0x21
347#define MX53_CHIP_REV_2_2 0x22
348#define MX53_CHIP_REV_2_3 0x23
349#define MX53_CHIP_REV_3_0 0x30
350#define MX53_CHIP_REV_3_1 0x31
351#define MX53_CHIP_REV_3_2 0x32
352
353#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index a42c7207082d..04c7a26b1f26 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -32,9 +32,25 @@
32#define MXC_CPU_MX27 27 32#define MXC_CPU_MX27 27
33#define MXC_CPU_MX31 31 33#define MXC_CPU_MX31 31
34#define MXC_CPU_MX35 35 34#define MXC_CPU_MX35 35
35#define MXC_CPU_MX50 50
35#define MXC_CPU_MX51 51 36#define MXC_CPU_MX51 51
37#define MXC_CPU_MX53 53
36#define MXC_CPU_MXC91231 91231 38#define MXC_CPU_MXC91231 91231
37 39
40#define IMX_CHIP_REVISION_1_0 0x10
41#define IMX_CHIP_REVISION_1_1 0x11
42#define IMX_CHIP_REVISION_1_2 0x12
43#define IMX_CHIP_REVISION_1_3 0x13
44#define IMX_CHIP_REVISION_2_0 0x20
45#define IMX_CHIP_REVISION_2_1 0x21
46#define IMX_CHIP_REVISION_2_2 0x22
47#define IMX_CHIP_REVISION_2_3 0x23
48#define IMX_CHIP_REVISION_3_0 0x30
49#define IMX_CHIP_REVISION_3_1 0x31
50#define IMX_CHIP_REVISION_3_2 0x32
51#define IMX_CHIP_REVISION_3_3 0x33
52#define IMX_CHIP_REVISION_UNKNOWN 0xff
53
38#ifndef __ASSEMBLY__ 54#ifndef __ASSEMBLY__
39extern unsigned int __mxc_cpu_type; 55extern unsigned int __mxc_cpu_type;
40#endif 56#endif
@@ -111,7 +127,19 @@ extern unsigned int __mxc_cpu_type;
111# define cpu_is_mx35() (0) 127# define cpu_is_mx35() (0)
112#endif 128#endif
113 129
114#ifdef CONFIG_ARCH_MX5 130#ifdef CONFIG_ARCH_MX50
131# ifdef mxc_cpu_type
132# undef mxc_cpu_type
133# define mxc_cpu_type __mxc_cpu_type
134# else
135# define mxc_cpu_type MXC_CPU_MX50
136# endif
137# define cpu_is_mx50() (mxc_cpu_type == MXC_CPU_MX50)
138#else
139# define cpu_is_mx50() (0)
140#endif
141
142#ifdef CONFIG_ARCH_MX51
115# ifdef mxc_cpu_type 143# ifdef mxc_cpu_type
116# undef mxc_cpu_type 144# undef mxc_cpu_type
117# define mxc_cpu_type __mxc_cpu_type 145# define mxc_cpu_type __mxc_cpu_type
@@ -123,6 +151,18 @@ extern unsigned int __mxc_cpu_type;
123# define cpu_is_mx51() (0) 151# define cpu_is_mx51() (0)
124#endif 152#endif
125 153
154#ifdef CONFIG_ARCH_MX53
155# ifdef mxc_cpu_type
156# undef mxc_cpu_type
157# define mxc_cpu_type __mxc_cpu_type
158# else
159# define mxc_cpu_type MXC_CPU_MX53
160# endif
161# define cpu_is_mx53() (mxc_cpu_type == MXC_CPU_MX53)
162#else
163# define cpu_is_mx53() (0)
164#endif
165
126#ifdef CONFIG_ARCH_MXC91231 166#ifdef CONFIG_ARCH_MXC91231
127# ifdef mxc_cpu_type 167# ifdef mxc_cpu_type
128# undef mxc_cpu_type 168# undef mxc_cpu_type
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
index 0ca3101ebf36..765190fe6332 100644
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ b/arch/arm/plat-mxc/include/mach/mxc91231.h
@@ -21,14 +21,12 @@
21 * L2CC 21 * L2CC
22 */ 22 */
23#define MXC91231_L2CC_BASE_ADDR 0x30000000 23#define MXC91231_L2CC_BASE_ADDR 0x30000000
24#define MXC91231_L2CC_BASE_ADDR_VIRT 0xF9000000
25#define MXC91231_L2CC_SIZE SZ_64K 24#define MXC91231_L2CC_SIZE SZ_64K
26 25
27/* 26/*
28 * AIPS 1 27 * AIPS 1
29 */ 28 */
30#define MXC91231_AIPS1_BASE_ADDR 0x43F00000 29#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
31#define MXC91231_AIPS1_BASE_ADDR_VIRT 0xFC000000
32#define MXC91231_AIPS1_SIZE SZ_1M 30#define MXC91231_AIPS1_SIZE SZ_1M
33 31
34#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR 32#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
@@ -53,7 +51,6 @@
53 * AIPS 2 51 * AIPS 2
54 */ 52 */
55#define MXC91231_AIPS2_BASE_ADDR 0x53F00000 53#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
56#define MXC91231_AIPS2_BASE_ADDR_VIRT 0xFC100000
57#define MXC91231_AIPS2_SIZE SZ_1M 54#define MXC91231_AIPS2_SIZE SZ_1M
58 55
59#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000) 56#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
@@ -79,7 +76,6 @@
79 * SPBA global module 0 76 * SPBA global module 0
80 */ 77 */
81#define MXC91231_SPBA0_BASE_ADDR 0x50000000 78#define MXC91231_SPBA0_BASE_ADDR 0x50000000
82#define MXC91231_SPBA0_BASE_ADDR_VIRT 0xFC200000
83#define MXC91231_SPBA0_SIZE SZ_1M 79#define MXC91231_SPBA0_SIZE SZ_1M
84 80
85#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000) 81#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
@@ -109,7 +105,6 @@
109 * SPBA global module 1 105 * SPBA global module 1
110 */ 106 */
111#define MXC91231_SPBA1_BASE_ADDR 0x52000000 107#define MXC91231_SPBA1_BASE_ADDR 0x52000000
112#define MXC91231_SPBA1_BASE_ADDR_VIRT 0xFC300000
113#define MXC91231_SPBA1_SIZE SZ_1M 108#define MXC91231_SPBA1_SIZE SZ_1M
114 109
115#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000) 110#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
@@ -144,18 +139,15 @@
144 * ROMP and AVIC 139 * ROMP and AVIC
145 */ 140 */
146#define MXC91231_ROMP_BASE_ADDR 0x60000000 141#define MXC91231_ROMP_BASE_ADDR 0x60000000
147#define MXC91231_ROMP_BASE_ADDR_VIRT 0xFC400000
148#define MXC91231_ROMP_SIZE SZ_64K 142#define MXC91231_ROMP_SIZE SZ_64K
149 143
150#define MXC91231_AVIC_BASE_ADDR 0x68000000 144#define MXC91231_AVIC_BASE_ADDR 0x68000000
151#define MXC91231_AVIC_BASE_ADDR_VIRT 0xFC410000
152#define MXC91231_AVIC_SIZE SZ_64K 145#define MXC91231_AVIC_SIZE SZ_64K
153 146
154/* 147/*
155 * NAND, SDRAM, WEIM, M3IF, EMI controllers 148 * NAND, SDRAM, WEIM, M3IF, EMI controllers
156 */ 149 */
157#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000 150#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
158#define MXC91231_X_MEMC_BASE_ADDR_VIRT 0xFC420000
159#define MXC91231_X_MEMC_SIZE SZ_64K 151#define MXC91231_X_MEMC_SIZE SZ_64K
160 152
161#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000) 153#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
@@ -183,19 +175,10 @@
183/* 175/*
184 * This macro defines the physical to virtual address mapping for all the 176 * This macro defines the physical to virtual address mapping for all the
185 * peripheral modules. It is used by passing in the physical address as x 177 * peripheral modules. It is used by passing in the physical address as x
186 * and returning the virtual address. If the physical address is not mapped, 178 * and returning the virtual address.
187 * it returns 0.
188 */ 179 */
189 180#define MXC91231_IO_P2V(x) IMX_IO_P2V(x)
190#define MXC91231_IO_ADDRESS(x) ( \ 181#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x))
191 IMX_IO_ADDRESS(x, MXC91231_L2CC) ?: \
192 IMX_IO_ADDRESS(x, MXC91231_X_MEMC) ?: \
193 IMX_IO_ADDRESS(x, MXC91231_ROMP) ?: \
194 IMX_IO_ADDRESS(x, MXC91231_AVIC) ?: \
195 IMX_IO_ADDRESS(x, MXC91231_AIPS1) ?: \
196 IMX_IO_ADDRESS(x, MXC91231_SPBA0) ?: \
197 IMX_IO_ADDRESS(x, MXC91231_SPBA1) ?: \
198 IMX_IO_ADDRESS(x, MXC91231_AIPS2))
199 182
200/* 183/*
201 * Interrupt numbers 184 * Interrupt numbers
diff --git a/arch/arm/plat-mxc/include/mach/mxc_ehci.h b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
index 7fc5f9946199..a523a4079299 100644
--- a/arch/arm/plat-mxc/include/mach/mxc_ehci.h
+++ b/arch/arm/plat-mxc/include/mach/mxc_ehci.h
@@ -31,6 +31,7 @@
31#define MXC_USBCTRL_OFFSET 0 31#define MXC_USBCTRL_OFFSET 0
32#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8 32#define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
33#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc 33#define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
34#define MXC_USBH2CTRL_OFFSET 0x14
34 35
35#define MX5_USBOTHER_REGS_OFFSET 0x800 36#define MX5_USBOTHER_REGS_OFFSET 0x800
36 37
diff --git a/arch/arm/plat-mxc/include/mach/sdma.h b/arch/arm/plat-mxc/include/mach/sdma.h
index 9be112227ac4..913e0432e40e 100644
--- a/arch/arm/plat-mxc/include/mach/sdma.h
+++ b/arch/arm/plat-mxc/include/mach/sdma.h
@@ -2,16 +2,62 @@
2#define __MACH_MXC_SDMA_H__ 2#define __MACH_MXC_SDMA_H__
3 3
4/** 4/**
5 * struct sdma_script_start_addrs - SDMA script start pointers
6 *
7 * start addresses of the different functions in the physical
8 * address space of the SDMA engine.
9 */
10struct sdma_script_start_addrs {
11 s32 ap_2_ap_addr;
12 s32 ap_2_bp_addr;
13 s32 ap_2_ap_fixed_addr;
14 s32 bp_2_ap_addr;
15 s32 loopback_on_dsp_side_addr;
16 s32 mcu_interrupt_only_addr;
17 s32 firi_2_per_addr;
18 s32 firi_2_mcu_addr;
19 s32 per_2_firi_addr;
20 s32 mcu_2_firi_addr;
21 s32 uart_2_per_addr;
22 s32 uart_2_mcu_addr;
23 s32 per_2_app_addr;
24 s32 mcu_2_app_addr;
25 s32 per_2_per_addr;
26 s32 uartsh_2_per_addr;
27 s32 uartsh_2_mcu_addr;
28 s32 per_2_shp_addr;
29 s32 mcu_2_shp_addr;
30 s32 ata_2_mcu_addr;
31 s32 mcu_2_ata_addr;
32 s32 app_2_per_addr;
33 s32 app_2_mcu_addr;
34 s32 shp_2_per_addr;
35 s32 shp_2_mcu_addr;
36 s32 mshc_2_mcu_addr;
37 s32 mcu_2_mshc_addr;
38 s32 spdif_2_mcu_addr;
39 s32 mcu_2_spdif_addr;
40 s32 asrc_2_mcu_addr;
41 s32 ext_mem_2_ipu_addr;
42 s32 descrambler_addr;
43 s32 dptc_dvfs_addr;
44 s32 utra_addr;
45 s32 ram_code_start_addr;
46};
47
48/**
5 * struct sdma_platform_data - platform specific data for SDMA engine 49 * struct sdma_platform_data - platform specific data for SDMA engine
6 * 50 *
7 * @sdma_version The version of this SDMA engine 51 * @sdma_version The version of this SDMA engine
8 * @cpu_name used to generate the firmware name 52 * @cpu_name used to generate the firmware name
9 * @to_version CPU Tape out version 53 * @to_version CPU Tape out version
54 * @script_addrs SDMA scripts addresses in SDMA ROM
10 */ 55 */
11struct sdma_platform_data { 56struct sdma_platform_data {
12 int sdma_version; 57 int sdma_version;
13 char *cpu_name; 58 char *cpu_name;
14 int to_version; 59 int to_version;
60 struct sdma_script_start_addrs *script_addrs;
15}; 61};
16 62
17#endif /* __MACH_MXC_SDMA_H__ */ 63#endif /* __MACH_MXC_SDMA_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 9dd9c2085aad..3a70ebf0477f 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -63,6 +63,8 @@ static inline void flush(void)
63#define MX3X_UART1_BASE_ADDR 0x43F90000 63#define MX3X_UART1_BASE_ADDR 0x43F90000
64#define MX3X_UART2_BASE_ADDR 0x43F94000 64#define MX3X_UART2_BASE_ADDR 0x43F94000
65#define MX51_UART1_BASE_ADDR 0x73fbc000 65#define MX51_UART1_BASE_ADDR 0x73fbc000
66#define MX50_UART1_BASE_ADDR 0x53fbc000
67#define MX53_UART1_BASE_ADDR 0x53fbc000
66 68
67static __inline__ void __arch_decomp_setup(unsigned long arch_id) 69static __inline__ void __arch_decomp_setup(unsigned long arch_id)
68{ 70{
@@ -102,6 +104,12 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
102 case MACH_TYPE_EUKREA_CPUIMX51SD: 104 case MACH_TYPE_EUKREA_CPUIMX51SD:
103 uart_base = MX51_UART1_BASE_ADDR; 105 uart_base = MX51_UART1_BASE_ADDR;
104 break; 106 break;
107 case MACH_TYPE_MX50_RDP:
108 uart_base = MX50_UART1_BASE_ADDR;
109 break;
110 case MACH_TYPE_MX53_EVK:
111 uart_base = MX53_UART1_BASE_ADDR;
112 break;
105 default: 113 default:
106 break; 114 break;
107 } 115 }
diff --git a/arch/arm/plat-mxc/iomux-v3.c b/arch/arm/plat-mxc/iomux-v3.c
index b318c6a222d5..99a9cdb9d6be 100644
--- a/arch/arm/plat-mxc/iomux-v3.c
+++ b/arch/arm/plat-mxc/iomux-v3.c
@@ -32,31 +32,38 @@
32static void __iomem *base; 32static void __iomem *base;
33 33
34/* 34/*
35 * setups a single pad in the iomuxer 35 * configures a single pad in the iomuxer
36 */ 36 */
37int mxc_iomux_v3_setup_pad(struct pad_desc *pad) 37int mxc_iomux_v3_setup_pad(iomux_v3_cfg_t pad)
38{ 38{
39 if (pad->mux_ctrl_ofs) 39 u32 mux_ctrl_ofs = (pad & MUX_CTRL_OFS_MASK) >> MUX_CTRL_OFS_SHIFT;
40 __raw_writel(pad->mux_mode, base + pad->mux_ctrl_ofs); 40 u32 mux_mode = (pad & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
41 u32 sel_input_ofs = (pad & MUX_SEL_INPUT_OFS_MASK) >> MUX_SEL_INPUT_OFS_SHIFT;
42 u32 sel_input = (pad & MUX_SEL_INPUT_MASK) >> MUX_SEL_INPUT_SHIFT;
43 u32 pad_ctrl_ofs = (pad & MUX_PAD_CTRL_OFS_MASK) >> MUX_PAD_CTRL_OFS_SHIFT;
44 u32 pad_ctrl = (pad & MUX_PAD_CTRL_MASK) >> MUX_PAD_CTRL_SHIFT;
41 45
42 if (pad->select_input_ofs) 46 if (mux_ctrl_ofs)
43 __raw_writel(pad->select_input, 47 __raw_writel(mux_mode, base + mux_ctrl_ofs);
44 base + pad->select_input_ofs); 48
49 if (sel_input_ofs)
50 __raw_writel(sel_input, base + sel_input_ofs);
51
52 if (!(pad_ctrl & NO_PAD_CTRL) && pad_ctrl_ofs)
53 __raw_writel(pad_ctrl, base + pad_ctrl_ofs);
45 54
46 if (!(pad->pad_ctrl & NO_PAD_CTRL) && pad->pad_ctrl_ofs)
47 __raw_writel(pad->pad_ctrl, base + pad->pad_ctrl_ofs);
48 return 0; 55 return 0;
49} 56}
50EXPORT_SYMBOL(mxc_iomux_v3_setup_pad); 57EXPORT_SYMBOL(mxc_iomux_v3_setup_pad);
51 58
52int mxc_iomux_v3_setup_multiple_pads(struct pad_desc *pad_list, unsigned count) 59int mxc_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t *pad_list, unsigned count)
53{ 60{
54 struct pad_desc *p = pad_list; 61 iomux_v3_cfg_t *p = pad_list;
55 int i; 62 int i;
56 int ret; 63 int ret;
57 64
58 for (i = 0; i < count; i++) { 65 for (i = 0; i < count; i++) {
59 ret = mxc_iomux_v3_setup_pad(p); 66 ret = mxc_iomux_v3_setup_pad(*p);
60 if (ret) 67 if (ret)
61 return ret; 68 return ret;
62 p++; 69 p++;
diff --git a/arch/arm/plat-mxc/irq-common.c b/arch/arm/plat-mxc/irq-common.c
new file mode 100644
index 000000000000..0c799ac27730
--- /dev/null
+++ b/arch/arm/plat-mxc/irq-common.c
@@ -0,0 +1,60 @@
1/*
2 * Copyright (C) BitBox Ltd 2010
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#include <linux/module.h>
20#include <linux/irq.h>
21
22#include "irq-common.h"
23
24int imx_irq_set_priority(unsigned char irq, unsigned char prio)
25{
26 struct mxc_irq_chip *chip;
27 struct irq_chip *base;
28 int ret;
29
30 ret = -ENOSYS;
31
32 base = get_irq_chip(irq);
33 if (base) {
34 chip = container_of(base, struct mxc_irq_chip, base);
35 if (chip->set_priority)
36 ret = chip->set_priority(irq, prio);
37 }
38
39 return ret;
40}
41EXPORT_SYMBOL(imx_irq_set_priority);
42
43int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
44{
45 struct mxc_irq_chip *chip;
46 struct irq_chip *base;
47 int ret;
48
49 ret = -ENOSYS;
50
51 base = get_irq_chip(irq);
52 if (base) {
53 chip = container_of(base, struct mxc_irq_chip, base);
54 if (chip->set_irq_fiq)
55 ret = chip->set_irq_fiq(irq, type);
56 }
57
58 return ret;
59}
60EXPORT_SYMBOL(mxc_set_irq_fiq);
diff --git a/arch/arm/plat-mxc/irq-common.h b/arch/arm/plat-mxc/irq-common.h
new file mode 100644
index 000000000000..7203543fb1b3
--- /dev/null
+++ b/arch/arm/plat-mxc/irq-common.h
@@ -0,0 +1,29 @@
1/*
2 * Copyright (C) BitBox Ltd 2010
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
16 * MA 02110-1301, USA.
17 */
18
19#ifndef __PLAT_MXC_IRQ_COMMON_H__
20#define __PLAT_MXC_IRQ_COMMON_H__
21
22struct mxc_irq_chip
23{
24 struct irq_chip base;
25 int (*set_priority)(unsigned char irq, unsigned char prio);
26 int (*set_irq_fiq)(unsigned int irq, unsigned int type);
27};
28
29#endif
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 925bce4607e7..3455fc0575a6 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -26,6 +26,7 @@
26#include <mach/common.h> 26#include <mach/common.h>
27#include <asm/proc-fns.h> 27#include <asm/proc-fns.h>
28#include <asm/system.h> 28#include <asm/system.h>
29#include <asm/mach-types.h>
29 30
30static void __iomem *wdog_base; 31static void __iomem *wdog_base;
31 32
@@ -42,12 +43,19 @@ void arch_reset(char mode, const char *cmd)
42 return; 43 return;
43 } 44 }
44#endif 45#endif
46#ifdef CONFIG_MACH_MX51_EFIKAMX
47 if (machine_is_mx51_efikamx()) {
48 mx51_efikamx_reset();
49 return;
50 }
51#endif
52
45 if (cpu_is_mx1()) { 53 if (cpu_is_mx1()) {
46 wcr_enable = (1 << 0); 54 wcr_enable = (1 << 0);
47 } else { 55 } else {
48 struct clk *clk; 56 struct clk *clk;
49 57
50 clk = clk_get_sys("imx-wdt.0", NULL); 58 clk = clk_get_sys("imx2-wdt.0", NULL);
51 if (!IS_ERR(clk)) 59 if (!IS_ERR(clk))
52 clk_enable(clk); 60 clk_enable(clk);
53 wcr_enable = (1 << 2); 61 wcr_enable = (1 << 2);
diff --git a/arch/arm/plat-mxc/tzic.c b/arch/arm/plat-mxc/tzic.c
index 3703ab28257f..e69ed8a8c203 100644
--- a/arch/arm/plat-mxc/tzic.c
+++ b/arch/arm/plat-mxc/tzic.c
@@ -21,6 +21,8 @@
21#include <mach/hardware.h> 21#include <mach/hardware.h>
22#include <mach/common.h> 22#include <mach/common.h>
23 23
24#include "irq-common.h"
25
24/* 26/*
25 ***************************************** 27 *****************************************
26 * TZIC Registers * 28 * TZIC Registers *
@@ -47,6 +49,25 @@
47 49
48void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */ 50void __iomem *tzic_base; /* Used as irq controller base in entry-macro.S */
49 51
52#ifdef CONFIG_FIQ
53static int tzic_set_irq_fiq(unsigned int irq, unsigned int type)
54{
55 unsigned int index, mask, value;
56
57 index = irq >> 5;
58 if (unlikely(index >= 4))
59 return -EINVAL;
60 mask = 1U << (irq & 0x1F);
61
62 value = __raw_readl(tzic_base + TZIC_INTSEC0(index)) | mask;
63 if (type)
64 value &= ~mask;
65 __raw_writel(value, tzic_base + TZIC_INTSEC0(index));
66
67 return 0;
68}
69#endif
70
50/** 71/**
51 * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC 72 * tzic_mask_irq() - Disable interrupt number "irq" in the TZIC
52 * 73 *
@@ -104,12 +125,17 @@ static int tzic_set_wake_irq(unsigned int irq, unsigned int enable)
104 return 0; 125 return 0;
105} 126}
106 127
107static struct irq_chip mxc_tzic_chip = { 128static struct mxc_irq_chip mxc_tzic_chip = {
108 .name = "MXC_TZIC", 129 .base = {
109 .ack = tzic_mask_irq, 130 .name = "MXC_TZIC",
110 .mask = tzic_mask_irq, 131 .ack = tzic_mask_irq,
111 .unmask = tzic_unmask_irq, 132 .mask = tzic_mask_irq,
112 .set_wake = tzic_set_wake_irq, 133 .unmask = tzic_unmask_irq,
134 .set_wake = tzic_set_wake_irq,
135 },
136#ifdef CONFIG_FIQ
137 .set_irq_fiq = tzic_set_irq_fiq,
138#endif
113}; 139};
114 140
115/* 141/*
@@ -141,10 +167,16 @@ void __init tzic_init_irq(void __iomem *irqbase)
141 /* all IRQ no FIQ Warning :: No selection */ 167 /* all IRQ no FIQ Warning :: No selection */
142 168
143 for (i = 0; i < MXC_INTERNAL_IRQS; i++) { 169 for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
144 set_irq_chip(i, &mxc_tzic_chip); 170 set_irq_chip(i, &mxc_tzic_chip.base);
145 set_irq_handler(i, handle_level_irq); 171 set_irq_handler(i, handle_level_irq);
146 set_irq_flags(i, IRQF_VALID); 172 set_irq_flags(i, IRQF_VALID);
147 } 173 }
174
175#ifdef CONFIG_FIQ
176 /* Initialize FIQ */
177 init_FIQ();
178#endif
179
148 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n"); 180 pr_info("TrustZone Interrupt Controller (TZIC) initialized\n");
149} 181}
150 182