Merge nommu tree

Fix merge conflict in arch/arm/mm/proc-xscale.S

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

20 files changed, 78 insertions, 51 deletions

diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index db3389d8e027..491c7e4c9ac6 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -358,7 +358,7 @@ __setup_mmu:	sub	r3, r4, #16384		@ Page directory size
                 str     r1, [r0]
                 mov     pc, lr
 
-__armv4_cache_on:
+__armv4_mmu_cache_on:
                 mov     r12, lr
                 bl      __setup_mmu
                 mov     r0, #0
@@ -367,24 +367,24 @@ __armv4_cache_on:
                 mrc     p15, 0, r0, c1, c0, 0   @ read control reg
                 orr     r0, r0, #0x5000         @ I-cache enable, RR cache replacement
                 orr     r0, r0, #0x0030
-                bl      __common_cache_on
+                bl      __common_mmu_cache_on
                 mov     r0, #0
                 mcr     p15, 0, r0, c8, c7, 0   @ flush I,D TLBs
                 mov     pc, r12
 
-__arm6_cache_on:
+__arm6_mmu_cache_on:
                 mov     r12, lr
                 bl      __setup_mmu
                 mov     r0, #0
                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
                 mcr     p15, 0, r0, c5, c0, 0   @ invalidate whole TLB v3
                 mov     r0, #0x30
-                bl      __common_cache_on
+                bl      __common_mmu_cache_on
                 mov     r0, #0
                 mcr     p15, 0, r0, c5, c0, 0   @ invalidate whole TLB v3
                 mov     pc, r12
 
-__common_cache_on:
+__common_mmu_cache_on:
 #ifndef DEBUG
                 orr     r0, r0, #0x000d         @ Write buffer, mmu
 #endif
@@ -471,12 +471,12 @@ call_cache_fn:	adr	r12, proc_types
 proc_types:
                 .word   0x41560600              @ ARM6/610
                 .word   0xffffffe0
-                b       __arm6_cache_off        @ works, but slow
-                b       __arm6_cache_off
+                b       __arm6_mmu_cache_off    @ works, but slow
+                b       __arm6_mmu_cache_off
                 mov     pc, lr
-@               b       __arm6_cache_on         @ untested
-@               b       __arm6_cache_off
-@               b       __armv3_cache_flush
+@               b       __arm6_mmu_cache_on             @ untested
+@               b       __arm6_mmu_cache_off
+@               b       __armv3_mmu_cache_flush
 
                 .word   0x00000000              @ old ARM ID
                 .word   0x0000f000
@@ -486,14 +486,14 @@ proc_types:
 
                 .word   0x41007000              @ ARM7/710
                 .word   0xfff8fe00
-                b       __arm7_cache_off
-                b       __arm7_cache_off
+                b       __arm7_mmu_cache_off
+                b       __arm7_mmu_cache_off
                 mov     pc, lr
 
                 .word   0x41807200              @ ARM720T (writethrough)
                 .word   0xffffff00
-                b       __armv4_cache_on
-                b       __armv4_cache_off
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
                 mov     pc, lr
 
                 .word   0x00007000              @ ARM7 IDs
@@ -506,41 +506,41 @@ proc_types:
 
                 .word   0x4401a100              @ sa110 / sa1100
                 .word   0xffffffe0
-                b       __armv4_cache_on
-                b       __armv4_cache_off
-                b       __armv4_cache_flush
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
+                b       __armv4_mmu_cache_flush
 
                 .word   0x6901b110              @ sa1110
                 .word   0xfffffff0
-                b       __armv4_cache_on
-                b       __armv4_cache_off
-                b       __armv4_cache_flush
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
+                b       __armv4_mmu_cache_flush
 
                 @ These match on the architecture ID
 
                 .word   0x00020000              @ ARMv4T
                 .word   0x000f0000
-                b       __armv4_cache_on
-                b       __armv4_cache_off
-                b       __armv4_cache_flush
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
+                b       __armv4_mmu_cache_flush
 
                 .word   0x00050000              @ ARMv5TE
                 .word   0x000f0000
-                b       __armv4_cache_on
-                b       __armv4_cache_off
-                b       __armv4_cache_flush
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
+                b       __armv4_mmu_cache_flush
 
                 .word   0x00060000              @ ARMv5TEJ
                 .word   0x000f0000
-                b       __armv4_cache_on
-                b       __armv4_cache_off
-                b       __armv4_cache_flush
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
+                b       __armv4_mmu_cache_flush
 
                 .word   0x00070000              @ ARMv6
                 .word   0x000f0000
-                b       __armv4_cache_on
-                b       __armv4_cache_off
-                b       __armv6_cache_flush
+                b       __armv4_mmu_cache_on
+                b       __armv4_mmu_cache_off
+                b       __armv6_mmu_cache_flush
 
                 .word   0                       @ unrecognised type
                 .word   0
@@ -562,7 +562,7 @@ proc_types:
 cache_off:      mov     r3, #12                 @ cache_off function
                 b       call_cache_fn
 
-__armv4_cache_off:
+__armv4_mmu_cache_off:
                 mrc     p15, 0, r0, c1, c0
                 bic     r0, r0, #0x000d
                 mcr     p15, 0, r0, c1, c0      @ turn MMU and cache off
@@ -571,15 +571,15 @@ __armv4_cache_off:
                 mcr     p15, 0, r0, c8, c7      @ invalidate whole TLB v4
                 mov     pc, lr
 
-__arm6_cache_off:
+__arm6_mmu_cache_off:
                 mov     r0, #0x00000030         @ ARM6 control reg.
-                b       __armv3_cache_off
+                b       __armv3_mmu_cache_off
 
-__arm7_cache_off:
+__arm7_mmu_cache_off:
                 mov     r0, #0x00000070         @ ARM7 control reg.
-                b       __armv3_cache_off
+                b       __armv3_mmu_cache_off
 
-__armv3_cache_off:
+__armv3_mmu_cache_off:
                 mcr     p15, 0, r0, c1, c0, 0   @ turn MMU and cache off
                 mov     r0, #0
                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
@@ -601,7 +601,7 @@ cache_clean_flush:
                 mov     r3, #16
                 b       call_cache_fn
 
-__armv6_cache_flush:
+__armv6_mmu_cache_flush:
                 mov     r1, #0
                 mcr     p15, 0, r1, c7, c14, 0  @ clean+invalidate D
                 mcr     p15, 0, r1, c7, c5, 0   @ invalidate I+BTB
@@ -609,7 +609,7 @@ __armv6_cache_flush:
                 mcr     p15, 0, r1, c7, c10, 4  @ drain WB
                 mov     pc, lr
 
-__armv4_cache_flush:
+__armv4_mmu_cache_flush:
                 mov     r2, #64*1024            @ default: 32K dcache size (*2)
                 mov     r11, #32                @ default: 32 byte line size
                 mrc     p15, 0, r3, c0, c0, 1   @ read cache type
@@ -637,7 +637,7 @@ no_cache_id:
                 mcr     p15, 0, r1, c7, c10, 4  @ drain WB
                 mov     pc, lr
 
-__armv3_cache_flush:
+__armv3_mmu_cache_flush:
                 mov     r1, #0
                 mcr     p15, 0, r0, c7, c0, 0   @ invalidate whole cache v3
                 mov     pc, lr
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 84277fe818a1..53b6901f70a6 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -81,6 +81,7 @@
 ENTRY(stext)
         msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC @ ensure svc mode
                                                 @ and irqs disabled
+        mrc     p15, 0, r9, c0, c0              @ get processor id
         bl      __lookup_processor_type         @ r5=procinfo r9=cpuid
         movs    r10, r5                         @ invalid processor (r5=0)?
         beq     __error_p                       @ yes, error 'p'
@@ -155,6 +156,7 @@ ENTRY(secondary_startup)
          * as it has already been validated by the primary processor.
          */
         msr     cpsr_c, #PSR_F_BIT | PSR_I_BIT | MODE_SVC
+        mrc     p15, 0, r9, c0, c0              @ get processor id
         bl      __lookup_processor_type
         movs    r10, r5                         @ invalid processor?
         moveq   r0, #'p'                        @ yes, error 'p'
@@ -449,19 +451,19 @@ __error:
  * (and therefore, we are not in the correct address space).  We have to
  * calculate the offset.
  *
+ *      r9 = cpuid
  * Returns:
  *      r3, r4, r6 corrupted
  *      r5 = proc_info pointer in physical address space
- *      r9 = cpuid
+ *      r9 = cpuid (preserved)
  */
         .type   __lookup_processor_type, %function
 __lookup_processor_type:
         adr     r3, 3f
-        ldmda   r3, {r5, r6, r9}
-        sub     r3, r3, r9                      @ get offset between virt&phys
+        ldmda   r3, {r5 - r7}
+        sub     r3, r3, r7                      @ get offset between virt&phys
         add     r5, r5, r3                      @ convert virt addresses to
         add     r6, r6, r3                      @ physical address space
-        mrc     p15, 0, r9, c0, c0              @ get processor id
 1:      ldmia   r5, {r3, r4}                    @ value, mask
         and     r4, r4, r9                      @ mask wanted bits
         teq     r3, r4
@@ -476,10 +478,11 @@ __lookup_processor_type:
  * This provides a C-API version of the above function.
  */
 ENTRY(lookup_processor_type)
-        stmfd   sp!, {r4 - r6, r9, lr}
+        stmfd   sp!, {r4 - r7, r9, lr}
+        mov     r9, r0
         bl      __lookup_processor_type
         mov     r0, r5
-        ldmfd   sp!, {r4 - r6, r9, pc}
+        ldmfd   sp!, {r4 - r7, r9, pc}
 
 /*
  * Look in include/asm-arm/procinfo.h and arch/arm/kernel/arch.[ch] for
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 08974cbe9824..b7cd280bfd63 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -278,7 +278,7 @@ int cpu_architecture(void)
  * These functions re-use the assembly code in head.S, which
  * already provide the required functionality.
  */
-extern struct proc_info_list *lookup_processor_type(void);
+extern struct proc_info_list *lookup_processor_type(unsigned int);
 extern struct machine_desc *lookup_machine_type(unsigned int);
 
 static void __init setup_processor(void)
@@ -290,7 +290,7 @@ static void __init setup_processor(void)
          * types.  The linker builds this table for us from the
          * entries in arch/arm/mm/proc-*.S
          */
-        list = lookup_processor_type();
+        list = lookup_processor_type(processor_id);
         if (!list) {
                 printk("CPU configuration botched (ID %08x), unable "
                        "to continue.\n", processor_id);
diff --git a/arch/arm/kernel/sys_arm.c b/arch/arm/kernel/sys_arm.c
index a491de2d9024..8170af471439 100644
--- a/arch/arm/kernel/sys_arm.c
+++ b/arch/arm/kernel/sys_arm.c
@@ -234,7 +234,12 @@ asmlinkage int sys_ipc(uint call, int first, int second, int third,
  */
 asmlinkage int sys_fork(struct pt_regs *regs)
 {
+#ifdef CONFIG_MMU
         return do_fork(SIGCHLD, regs->ARM_sp, regs, 0, NULL, NULL);
+#else
+        /* can not support in nommu mode */
+        return(-EINVAL);
+#endif
 }
 
 /* Clone a task - this clones the calling program thread.
diff --git a/arch/arm/mach-sa1100/assabet.c b/arch/arm/mach-sa1100/assabet.c
index a599bb0d4ab8..c58f12ba7a93 100644
--- a/arch/arm/mach-sa1100/assabet.c
+++ b/arch/arm/mach-sa1100/assabet.c
@@ -26,6 +26,7 @@
 #include <asm/irq.h>
 #include <asm/setup.h>
 #include <asm/page.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/tlbflush.h>
 
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index eaaec90db972..e680c5fd93b5 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -266,12 +266,18 @@ config CPU_32v6K
 # This defines the compiler instruction set which depends on the machine type.
 config CPU_32v3
         bool
+        select TLS_REG_EMUL if SMP
+        select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 
 config CPU_32v4
         bool
+        select TLS_REG_EMUL if SMP
+        select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 
 config CPU_32v5
         bool
+        select TLS_REG_EMUL if SMP
+        select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
 
 config CPU_32v6
         bool
@@ -417,7 +423,6 @@ config CPU_BPREDICT_DISABLE
 
 config TLS_REG_EMUL
         bool
-        default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
         help
           An SMP system using a pre-ARMv6 processor (there are apparently
           a few prototypes like that in existence) and therefore access to
@@ -436,7 +441,6 @@ config HAS_TLS_REG
 
 config NEEDS_SYSCALL_FOR_CMPXCHG
         bool
-        default y if SMP && (CPU_32v5 || CPU_32v4 || CPU_32v3)
         help
           SMP on a pre-ARMv6 processor?  Well OK then.
           Forget about fast user space cmpxchg support.
diff --git a/arch/arm/mm/proc-arm1020.S b/arch/arm/mm/proc-arm1020.S
index 3aa80094012c..959588884fa5 100644
--- a/arch/arm/mm/proc-arm1020.S
+++ b/arch/arm/mm/proc-arm1020.S
@@ -29,6 +29,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm1020e.S b/arch/arm/mm/proc-arm1020e.S
index 767d158f211a..be6d081ff2b7 100644
--- a/arch/arm/mm/proc-arm1020e.S
+++ b/arch/arm/mm/proc-arm1020e.S
@@ -29,6 +29,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm1022.S b/arch/arm/mm/proc-arm1022.S
index 6ca639094d6f..f778545d57a2 100644
--- a/arch/arm/mm/proc-arm1022.S
+++ b/arch/arm/mm/proc-arm1022.S
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm1026.S b/arch/arm/mm/proc-arm1026.S
index 10317e4f55d2..148c111fde73 100644
--- a/arch/arm/mm/proc-arm1026.S
+++ b/arch/arm/mm/proc-arm1026.S
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm6_7.S b/arch/arm/mm/proc-arm6_7.S
index 8e7e1e70ab05..540359b475d0 100644
--- a/arch/arm/mm/proc-arm6_7.S
+++ b/arch/arm/mm/proc-arm6_7.S
@@ -14,6 +14,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm720.S b/arch/arm/mm/proc-arm720.S
index 471286fdf78f..26f00ee2ad9a 100644
--- a/arch/arm/mm/proc-arm720.S
+++ b/arch/arm/mm/proc-arm720.S
@@ -34,6 +34,7 @@
 #include <linux/init.h>
 #include <asm/assembler.h>
 #include <asm/asm-offsets.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/ptrace.h>
diff --git a/arch/arm/mm/proc-arm920.S b/arch/arm/mm/proc-arm920.S
index 950d3b664c1e..a17f79e0199c 100644
--- a/arch/arm/mm/proc-arm920.S
+++ b/arch/arm/mm/proc-arm920.S
@@ -28,6 +28,7 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/page.h>
diff --git a/arch/arm/mm/proc-arm922.S b/arch/arm/mm/proc-arm922.S
index 410b032faa3b..bbde4a024a48 100644
--- a/arch/arm/mm/proc-arm922.S
+++ b/arch/arm/mm/proc-arm922.S
@@ -29,6 +29,7 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/page.h>
diff --git a/arch/arm/mm/proc-arm925.S b/arch/arm/mm/proc-arm925.S
index 6dd2be7cd050..224ce226a01b 100644
--- a/arch/arm/mm/proc-arm925.S
+++ b/arch/arm/mm/proc-arm925.S
@@ -51,6 +51,7 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/page.h>
diff --git a/arch/arm/mm/proc-arm926.S b/arch/arm/mm/proc-arm926.S
index 022e86842041..4e2a087cf388 100644
--- a/arch/arm/mm/proc-arm926.S
+++ b/arch/arm/mm/proc-arm926.S
@@ -28,6 +28,7 @@
 #include <linux/config.h>
 #include <linux/init.h>
 #include <asm/assembler.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/procinfo.h>
 #include <asm/page.h>
diff --git a/arch/arm/mm/proc-sa110.S b/arch/arm/mm/proc-sa110.S
index bd330c4075a1..c916a6cae404 100644
--- a/arch/arm/mm/proc-sa110.S
+++ b/arch/arm/mm/proc-sa110.S
@@ -18,6 +18,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/procinfo.h>
 #include <asm/hardware.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 #include <asm/ptrace.h>
 
diff --git a/arch/arm/mm/proc-sa1100.S b/arch/arm/mm/proc-sa1100.S
index 91b89124c0d7..41f21f2dd8ff 100644
--- a/arch/arm/mm/proc-sa1100.S
+++ b/arch/arm/mm/proc-sa1100.S
@@ -23,6 +23,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/procinfo.h>
 #include <asm/hardware.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
 /*
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 92f3ca31b7b9..9a7e7c096aa9 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -14,6 +14,7 @@
 #include <asm/asm-offsets.h>
 #include <asm/hardware/arm_scu.h>
 #include <asm/procinfo.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/pgtable.h>
 
 #include "proc-macros.S"
diff --git a/arch/arm/mm/proc-xscale.S b/arch/arm/mm/proc-xscale.S
index b50f87a0ee76..29bcc4dd6517 100644
--- a/arch/arm/mm/proc-xscale.S
+++ b/arch/arm/mm/proc-xscale.S
@@ -25,6 +25,7 @@
 #include <asm/assembler.h>
 #include <asm/procinfo.h>
 #include <asm/pgtable.h>
+#include <asm/pgtable-hwdef.h>
 #include <asm/page.h>
 #include <asm/ptrace.h>
 #include "proc-macros.S"