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authorLinus Torvalds <torvalds@linux-foundation.org>2011-03-25 23:24:05 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2011-03-25 23:24:05 -0400
commit0dd61be7ec1be1b6820af978f901b9ae2c244dc6 (patch)
tree1f49edaa21351034e7d1dff6511424e9a949cf6b /arch
parent8dd90265ac0754da0df47d9c597f25187bb1c947 (diff)
parentab7798ffcf98b11a9525cf65bacdae3fd58d357f (diff)
Merge branch 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'irq-cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (23 commits) genirq: Expand generic show_interrupts() gpio: Fold irq_set_chip/irq_set_handler to irq_set_chip_and_handler gpio: Cleanup genirq namespace arm: ep93xx: Add basic interrupt info arm/gpio: Remove three copies of broken and racy debug code xtensa: Use generic show_interrupts() xtensa: Convert genirq namespace xtensa: Use generic IRQ Kconfig and set GENERIC_HARDIRQS_NO_DEPRECATED xtensa: Convert s6000 gpio irq_chip to new functions xtensa: Convert main irq_chip to new functions um: Use generic show_interrupts() um: Convert genirq namespace m32r: Use generic show_interrupts() m32r: Convert genirq namespace h8300: Use generic show_interrupts() h8300: Convert genirq namespace avr32: Cleanup eic_set_irq_type() avr32: Use generic show_interrupts() avr: Cleanup genirq namespace avr32: Use generic IRQ config, enable GENERIC_HARDIRQS_NO_DEPRECATED ... Fix up trivial conflict in drivers/gpio/timbgpio.c
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-ep93xx/gpio.c46
-rw-r--r--arch/arm/plat-nomadik/gpio.c45
-rw-r--r--arch/avr32/Kconfig14
-rw-r--r--arch/avr32/boards/atngw100/mrmt.c2
-rw-r--r--arch/avr32/boards/atngw100/setup.c2
-rw-r--r--arch/avr32/kernel/irq.c37
-rw-r--r--arch/avr32/mach-at32ap/extint.c82
-rw-r--r--arch/avr32/mach-at32ap/intc.c14
-rw-r--r--arch/avr32/mach-at32ap/pio.c37
-rw-r--r--arch/h8300/Kconfig1
-rw-r--r--arch/h8300/kernel/irq.c33
-rw-r--r--arch/m32r/Kconfig1
-rw-r--r--arch/m32r/kernel/irq.c45
-rw-r--r--arch/m32r/platforms/m32104ut/setup.c8
-rw-r--r--arch/m32r/platforms/m32700ut/setup.c28
-rw-r--r--arch/m32r/platforms/mappi/setup.c16
-rw-r--r--arch/m32r/platforms/mappi2/setup.c20
-rw-r--r--arch/m32r/platforms/mappi3/setup.c20
-rw-r--r--arch/m32r/platforms/oaks32r/setup.c12
-rw-r--r--arch/m32r/platforms/opsput/setup.c28
-rw-r--r--arch/m32r/platforms/usrv/setup.c18
-rw-r--r--arch/um/Kconfig.common1
-rw-r--r--arch/um/kernel/irq.c53
-rw-r--r--arch/xtensa/Kconfig6
-rw-r--r--arch/xtensa/kernel/irq.c106
-rw-r--r--arch/xtensa/platforms/s6105/device.c2
-rw-r--r--arch/xtensa/variants/s6000/gpio.c45
27 files changed, 214 insertions, 508 deletions
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index a889fa7c3ba1..34e071d79761 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -360,52 +360,14 @@ static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
360 gpio = ep93xx_chip->chip.base; 360 gpio = ep93xx_chip->chip.base;
361 for (i = 0; i < chip->ngpio; i++, gpio++) { 361 for (i = 0; i < chip->ngpio; i++, gpio++) {
362 int is_out = data_dir_reg & (1 << i); 362 int is_out = data_dir_reg & (1 << i);
363 int irq = gpio_to_irq(gpio);
363 364
364 seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s", 365 seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s %s\n",
365 chip->label, i, gpio, 366 chip->label, i, gpio,
366 gpiochip_is_requested(chip, i) ? : "", 367 gpiochip_is_requested(chip, i) ? : "",
367 is_out ? "out" : "in ", 368 is_out ? "out" : "in ",
368 (data_reg & (1 << i)) ? "hi" : "lo"); 369 (data_reg & (1<< i)) ? "hi" : "lo",
369 370 (!is_out && irq>= 0) ? "(interrupt)" : "");
370 if (!is_out) {
371 int irq = gpio_to_irq(gpio);
372 struct irq_desc *desc = irq_desc + irq;
373
374 if (irq >= 0 && desc->action) {
375 char *trigger;
376
377 switch (desc->status & IRQ_TYPE_SENSE_MASK) {
378 case IRQ_TYPE_NONE:
379 trigger = "(default)";
380 break;
381 case IRQ_TYPE_EDGE_FALLING:
382 trigger = "edge-falling";
383 break;
384 case IRQ_TYPE_EDGE_RISING:
385 trigger = "edge-rising";
386 break;
387 case IRQ_TYPE_EDGE_BOTH:
388 trigger = "edge-both";
389 break;
390 case IRQ_TYPE_LEVEL_HIGH:
391 trigger = "level-high";
392 break;
393 case IRQ_TYPE_LEVEL_LOW:
394 trigger = "level-low";
395 break;
396 default:
397 trigger = "?trigger?";
398 break;
399 }
400
401 seq_printf(s, " irq-%d %s%s",
402 irq, trigger,
403 (desc->status & IRQ_WAKEUP)
404 ? " wakeup" : "");
405 }
406 }
407
408 seq_printf(s, "\n");
409 } 371 }
410} 372}
411 373
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index 70620426ee55..80643bc38e10 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -832,51 +832,6 @@ static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
832 : "? ", 832 : "? ",
833 (mode < 0) ? "unknown" : modes[mode], 833 (mode < 0) ? "unknown" : modes[mode],
834 pull ? "pull" : "none"); 834 pull ? "pull" : "none");
835
836 if (!is_out) {
837 int irq = gpio_to_irq(gpio);
838 struct irq_desc *desc = irq_to_desc(irq);
839
840 /* This races with request_irq(), set_irq_type(),
841 * and set_irq_wake() ... but those are "rare".
842 *
843 * More significantly, trigger type flags aren't
844 * currently maintained by genirq.
845 */
846 if (irq >= 0 && desc->action) {
847 char *trigger;
848
849 switch (desc->status & IRQ_TYPE_SENSE_MASK) {
850 case IRQ_TYPE_NONE:
851 trigger = "(default)";
852 break;
853 case IRQ_TYPE_EDGE_FALLING:
854 trigger = "edge-falling";
855 break;
856 case IRQ_TYPE_EDGE_RISING:
857 trigger = "edge-rising";
858 break;
859 case IRQ_TYPE_EDGE_BOTH:
860 trigger = "edge-both";
861 break;
862 case IRQ_TYPE_LEVEL_HIGH:
863 trigger = "level-high";
864 break;
865 case IRQ_TYPE_LEVEL_LOW:
866 trigger = "level-low";
867 break;
868 default:
869 trigger = "?trigger?";
870 break;
871 }
872
873 seq_printf(s, " irq-%d %s%s",
874 irq, trigger,
875 (desc->status & IRQ_WAKEUP)
876 ? " wakeup" : "");
877 }
878 }
879
880 seq_printf(s, "\n"); 835 seq_printf(s, "\n");
881 } 836 }
882} 837}
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index cd2062fe0f61..49642b59f73d 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -6,6 +6,11 @@ config AVR32
6 select HAVE_CLK 6 select HAVE_CLK
7 select HAVE_OPROFILE 7 select HAVE_OPROFILE
8 select HAVE_KPROBES 8 select HAVE_KPROBES
9 select HAVE_GENERIC_HARDIRQS
10 select GENERIC_IRQ_PROBE
11 select HARDIRQS_SW_RESEND
12 select GENERIC_IRQ_SHOW
13 select GENERIC_HARDIRQS_NO_DEPRECATED
9 help 14 help
10 AVR32 is a high-performance 32-bit RISC microprocessor core, 15 AVR32 is a high-performance 32-bit RISC microprocessor core,
11 designed for cost-sensitive embedded applications, with particular 16 designed for cost-sensitive embedded applications, with particular
@@ -17,9 +22,6 @@ config AVR32
17config GENERIC_GPIO 22config GENERIC_GPIO
18 def_bool y 23 def_bool y
19 24
20config GENERIC_HARDIRQS
21 def_bool y
22
23config STACKTRACE_SUPPORT 25config STACKTRACE_SUPPORT
24 def_bool y 26 def_bool y
25 27
@@ -29,12 +31,6 @@ config LOCKDEP_SUPPORT
29config TRACE_IRQFLAGS_SUPPORT 31config TRACE_IRQFLAGS_SUPPORT
30 def_bool y 32 def_bool y
31 33
32config HARDIRQS_SW_RESEND
33 def_bool y
34
35config GENERIC_IRQ_PROBE
36 def_bool y
37
38config RWSEM_GENERIC_SPINLOCK 34config RWSEM_GENERIC_SPINLOCK
39 def_bool y 35 def_bool y
40 36
diff --git a/arch/avr32/boards/atngw100/mrmt.c b/arch/avr32/boards/atngw100/mrmt.c
index 7919be311f4a..f91431963452 100644
--- a/arch/avr32/boards/atngw100/mrmt.c
+++ b/arch/avr32/boards/atngw100/mrmt.c
@@ -301,7 +301,7 @@ static int __init mrmt1_init(void)
301 /* Select the Touchscreen interrupt pin mode */ 301 /* Select the Touchscreen interrupt pin mode */
302 at32_select_periph( GPIO_PIOB_BASE, 1 << (PB_EXTINT_BASE+TS_IRQ), 302 at32_select_periph( GPIO_PIOB_BASE, 1 << (PB_EXTINT_BASE+TS_IRQ),
303 GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH); 303 GPIO_PERIPH_A, AT32_GPIOF_DEGLITCH);
304 set_irq_type( AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING ); 304 irq_set_irq_type(AT32_EXTINT(TS_IRQ), IRQ_TYPE_EDGE_FALLING);
305 at32_spi_setup_slaves(0,spi01_board_info,ARRAY_SIZE(spi01_board_info)); 305 at32_spi_setup_slaves(0,spi01_board_info,ARRAY_SIZE(spi01_board_info));
306 spi_register_board_info(spi01_board_info,ARRAY_SIZE(spi01_board_info)); 306 spi_register_board_info(spi01_board_info,ARRAY_SIZE(spi01_board_info));
307#endif 307#endif
diff --git a/arch/avr32/boards/atngw100/setup.c b/arch/avr32/boards/atngw100/setup.c
index 659d119ce712..fafed4c38fd2 100644
--- a/arch/avr32/boards/atngw100/setup.c
+++ b/arch/avr32/boards/atngw100/setup.c
@@ -322,6 +322,6 @@ static int __init atngw100_arch_init(void)
322 /* set_irq_type() after the arch_initcall for EIC has run, and 322 /* set_irq_type() after the arch_initcall for EIC has run, and
323 * before the I2C subsystem could try using this IRQ. 323 * before the I2C subsystem could try using this IRQ.
324 */ 324 */
325 return set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING); 325 return irq_set_irq_type(AT32_EXTINT(3), IRQ_TYPE_EDGE_FALLING);
326} 326}
327arch_initcall(atngw100_arch_init); 327arch_initcall(atngw100_arch_init);
diff --git a/arch/avr32/kernel/irq.c b/arch/avr32/kernel/irq.c
index 9604f7758f9a..bc3aa18293df 100644
--- a/arch/avr32/kernel/irq.c
+++ b/arch/avr32/kernel/irq.c
@@ -26,40 +26,3 @@ void __weak nmi_disable(void)
26{ 26{
27 27
28} 28}
29
30#ifdef CONFIG_PROC_FS
31int show_interrupts(struct seq_file *p, void *v)
32{
33 int i = *(loff_t *)v, cpu;
34 struct irqaction *action;
35 unsigned long flags;
36
37 if (i == 0) {
38 seq_puts(p, " ");
39 for_each_online_cpu(cpu)
40 seq_printf(p, "CPU%d ", cpu);
41 seq_putc(p, '\n');
42 }
43
44 if (i < NR_IRQS) {
45 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
46 action = irq_desc[i].action;
47 if (!action)
48 goto unlock;
49
50 seq_printf(p, "%3d: ", i);
51 for_each_online_cpu(cpu)
52 seq_printf(p, "%10u ", kstat_irqs_cpu(i, cpu));
53 seq_printf(p, " %8s", irq_desc[i].chip->name ? : "-");
54 seq_printf(p, " %s", action->name);
55 for (action = action->next; action; action = action->next)
56 seq_printf(p, ", %s", action->name);
57
58 seq_putc(p, '\n');
59 unlock:
60 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
61 }
62
63 return 0;
64}
65#endif
diff --git a/arch/avr32/mach-at32ap/extint.c b/arch/avr32/mach-at32ap/extint.c
index e9d12058ffd3..47ba4b9b6db1 100644
--- a/arch/avr32/mach-at32ap/extint.c
+++ b/arch/avr32/mach-at32ap/extint.c
@@ -61,45 +61,42 @@ struct eic {
61static struct eic *nmi_eic; 61static struct eic *nmi_eic;
62static bool nmi_enabled; 62static bool nmi_enabled;
63 63
64static void eic_ack_irq(unsigned int irq) 64static void eic_ack_irq(struct irq_chip *d)
65{ 65{
66 struct eic *eic = get_irq_chip_data(irq); 66 struct eic *eic = irq_data_get_irq_chip_data(data);
67 eic_writel(eic, ICR, 1 << (irq - eic->first_irq)); 67 eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
68} 68}
69 69
70static void eic_mask_irq(unsigned int irq) 70static void eic_mask_irq(struct irq_chip *d)
71{ 71{
72 struct eic *eic = get_irq_chip_data(irq); 72 struct eic *eic = irq_data_get_irq_chip_data(data);
73 eic_writel(eic, IDR, 1 << (irq - eic->first_irq)); 73 eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
74} 74}
75 75
76static void eic_mask_ack_irq(unsigned int irq) 76static void eic_mask_ack_irq(struct irq_chip *d)
77{ 77{
78 struct eic *eic = get_irq_chip_data(irq); 78 struct eic *eic = irq_data_get_irq_chip_data(data);
79 eic_writel(eic, ICR, 1 << (irq - eic->first_irq)); 79 eic_writel(eic, ICR, 1 << (d->irq - eic->first_irq));
80 eic_writel(eic, IDR, 1 << (irq - eic->first_irq)); 80 eic_writel(eic, IDR, 1 << (d->irq - eic->first_irq));
81} 81}
82 82
83static void eic_unmask_irq(unsigned int irq) 83static void eic_unmask_irq(struct irq_chip *d)
84{ 84{
85 struct eic *eic = get_irq_chip_data(irq); 85 struct eic *eic = irq_data_get_irq_chip_data(data);
86 eic_writel(eic, IER, 1 << (irq - eic->first_irq)); 86 eic_writel(eic, IER, 1 << (d->irq - eic->first_irq));
87} 87}
88 88
89static int eic_set_irq_type(unsigned int irq, unsigned int flow_type) 89static int eic_set_irq_type(struct irq_chip *d, unsigned int flow_type)
90{ 90{
91 struct eic *eic = get_irq_chip_data(irq); 91 struct eic *eic = irq_data_get_irq_chip_data(data);
92 struct irq_desc *desc; 92 unsigned int irq = d->irq;
93 unsigned int i = irq - eic->first_irq; 93 unsigned int i = irq - eic->first_irq;
94 u32 mode, edge, level; 94 u32 mode, edge, level;
95 int ret = 0;
96 95
97 flow_type &= IRQ_TYPE_SENSE_MASK; 96 flow_type &= IRQ_TYPE_SENSE_MASK;
98 if (flow_type == IRQ_TYPE_NONE) 97 if (flow_type == IRQ_TYPE_NONE)
99 flow_type = IRQ_TYPE_LEVEL_LOW; 98 flow_type = IRQ_TYPE_LEVEL_LOW;
100 99
101 desc = &irq_desc[irq];
102
103 mode = eic_readl(eic, MODE); 100 mode = eic_readl(eic, MODE);
104 edge = eic_readl(eic, EDGE); 101 edge = eic_readl(eic, EDGE);
105 level = eic_readl(eic, LEVEL); 102 level = eic_readl(eic, LEVEL);
@@ -122,39 +119,34 @@ static int eic_set_irq_type(unsigned int irq, unsigned int flow_type)
122 edge &= ~(1 << i); 119 edge &= ~(1 << i);
123 break; 120 break;
124 default: 121 default:
125 ret = -EINVAL; 122 return -EINVAL;
126 break;
127 } 123 }
128 124
129 if (ret == 0) { 125 eic_writel(eic, MODE, mode);
130 eic_writel(eic, MODE, mode); 126 eic_writel(eic, EDGE, edge);
131 eic_writel(eic, EDGE, edge); 127 eic_writel(eic, LEVEL, level);
132 eic_writel(eic, LEVEL, level);
133
134 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
135 flow_type |= IRQ_LEVEL;
136 __set_irq_handler_unlocked(irq, handle_level_irq);
137 } else
138 __set_irq_handler_unlocked(irq, handle_edge_irq);
139 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
140 desc->status |= flow_type;
141 }
142 128
143 return ret; 129 irqd_set_trigger_type(d, flow_type);
130 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
131 __irq_set_handler_locked(irq, handle_level_irq);
132 else
133 __irq_set_handler_locked(irq, handle_edge_irq);
134
135 return IRQ_SET_MASK_OK_NOCOPY;
144} 136}
145 137
146static struct irq_chip eic_chip = { 138static struct irq_chip eic_chip = {
147 .name = "eic", 139 .name = "eic",
148 .ack = eic_ack_irq, 140 .irq_ack = eic_ack_irq,
149 .mask = eic_mask_irq, 141 .irq_mask = eic_mask_irq,
150 .mask_ack = eic_mask_ack_irq, 142 .irq_mask_ack = eic_mask_ack_irq,
151 .unmask = eic_unmask_irq, 143 .irq_unmask = eic_unmask_irq,
152 .set_type = eic_set_irq_type, 144 .irq_set_type = eic_set_irq_type,
153}; 145};
154 146
155static void demux_eic_irq(unsigned int irq, struct irq_desc *desc) 147static void demux_eic_irq(unsigned int irq, struct irq_desc *desc)
156{ 148{
157 struct eic *eic = desc->handler_data; 149 struct eic *eic = irq_desc_get_handler_data(desc);
158 unsigned long status, pending; 150 unsigned long status, pending;
159 unsigned int i; 151 unsigned int i;
160 152
@@ -234,13 +226,13 @@ static int __init eic_probe(struct platform_device *pdev)
234 eic->chip = &eic_chip; 226 eic->chip = &eic_chip;
235 227
236 for (i = 0; i < nr_of_irqs; i++) { 228 for (i = 0; i < nr_of_irqs; i++) {
237 set_irq_chip_and_handler(eic->first_irq + i, &eic_chip, 229 irq_set_chip_and_handler(eic->first_irq + i, &eic_chip,
238 handle_level_irq); 230 handle_level_irq);
239 set_irq_chip_data(eic->first_irq + i, eic); 231 irq_set_chip_data(eic->first_irq + i, eic);
240 } 232 }
241 233
242 set_irq_chained_handler(int_irq, demux_eic_irq); 234 irq_set_chained_handler(int_irq, demux_eic_irq);
243 set_irq_data(int_irq, eic); 235 irq_set_handler_data(int_irq, eic);
244 236
245 if (pdev->id == 0) { 237 if (pdev->id == 0) {
246 nmi_eic = eic; 238 nmi_eic = eic;
diff --git a/arch/avr32/mach-at32ap/intc.c b/arch/avr32/mach-at32ap/intc.c
index 994c4545e2b7..21ce35f33aa5 100644
--- a/arch/avr32/mach-at32ap/intc.c
+++ b/arch/avr32/mach-at32ap/intc.c
@@ -34,12 +34,12 @@ extern struct platform_device at32_intc0_device;
34 * TODO: We may be able to implement mask/unmask by setting IxM flags 34 * TODO: We may be able to implement mask/unmask by setting IxM flags
35 * in the status register. 35 * in the status register.
36 */ 36 */
37static void intc_mask_irq(unsigned int irq) 37static void intc_mask_irq(struct irq_data *d)
38{ 38{
39 39
40} 40}
41 41
42static void intc_unmask_irq(unsigned int irq) 42static void intc_unmask_irq(struct irq_data *d)
43{ 43{
44 44
45} 45}
@@ -47,8 +47,8 @@ static void intc_unmask_irq(unsigned int irq)
47static struct intc intc0 = { 47static struct intc intc0 = {
48 .chip = { 48 .chip = {
49 .name = "intc", 49 .name = "intc",
50 .mask = intc_mask_irq, 50 .irq_mask = intc_mask_irq,
51 .unmask = intc_unmask_irq, 51 .irq_unmask = intc_unmask_irq,
52 }, 52 },
53}; 53};
54 54
@@ -57,7 +57,6 @@ static struct intc intc0 = {
57 */ 57 */
58asmlinkage void do_IRQ(int level, struct pt_regs *regs) 58asmlinkage void do_IRQ(int level, struct pt_regs *regs)
59{ 59{
60 struct irq_desc *desc;
61 struct pt_regs *old_regs; 60 struct pt_regs *old_regs;
62 unsigned int irq; 61 unsigned int irq;
63 unsigned long status_reg; 62 unsigned long status_reg;
@@ -69,8 +68,7 @@ asmlinkage void do_IRQ(int level, struct pt_regs *regs)
69 irq_enter(); 68 irq_enter();
70 69
71 irq = intc_readl(&intc0, INTCAUSE0 - 4 * level); 70 irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
72 desc = irq_desc + irq; 71 generic_handle_irq(irq);
73 desc->handle_irq(irq, desc);
74 72
75 /* 73 /*
76 * Clear all interrupt level masks so that we may handle 74 * Clear all interrupt level masks so that we may handle
@@ -128,7 +126,7 @@ void __init init_IRQ(void)
128 intc_writel(&intc0, INTPR0 + 4 * i, offset); 126 intc_writel(&intc0, INTPR0 + 4 * i, offset);
129 readback = intc_readl(&intc0, INTPR0 + 4 * i); 127 readback = intc_readl(&intc0, INTPR0 + 4 * i);
130 if (readback == offset) 128 if (readback == offset)
131 set_irq_chip_and_handler(i, &intc0.chip, 129 irq_set_chip_and_handler(i, &intc0.chip,
132 handle_simple_irq); 130 handle_simple_irq);
133 } 131 }
134 132
diff --git a/arch/avr32/mach-at32ap/pio.c b/arch/avr32/mach-at32ap/pio.c
index 09a274c9d0b7..37534103574e 100644
--- a/arch/avr32/mach-at32ap/pio.c
+++ b/arch/avr32/mach-at32ap/pio.c
@@ -249,23 +249,23 @@ static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
249 249
250/* GPIO IRQ support */ 250/* GPIO IRQ support */
251 251
252static void gpio_irq_mask(unsigned irq) 252static void gpio_irq_mask(struct irq_data *d)
253{ 253{
254 unsigned gpio = irq_to_gpio(irq); 254 unsigned gpio = irq_to_gpio(d->irq);
255 struct pio_device *pio = &pio_dev[gpio >> 5]; 255 struct pio_device *pio = &pio_dev[gpio >> 5];
256 256
257 pio_writel(pio, IDR, 1 << (gpio & 0x1f)); 257 pio_writel(pio, IDR, 1 << (gpio & 0x1f));
258} 258}
259 259
260static void gpio_irq_unmask(unsigned irq) 260static void gpio_irq_unmask(struct irq_data *d))
261{ 261{
262 unsigned gpio = irq_to_gpio(irq); 262 unsigned gpio = irq_to_gpio(d->irq);
263 struct pio_device *pio = &pio_dev[gpio >> 5]; 263 struct pio_device *pio = &pio_dev[gpio >> 5];
264 264
265 pio_writel(pio, IER, 1 << (gpio & 0x1f)); 265 pio_writel(pio, IER, 1 << (gpio & 0x1f));
266} 266}
267 267
268static int gpio_irq_type(unsigned irq, unsigned type) 268static int gpio_irq_type(struct irq_data *d, unsigned type)
269{ 269{
270 if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE) 270 if (type != IRQ_TYPE_EDGE_BOTH && type != IRQ_TYPE_NONE)
271 return -EINVAL; 271 return -EINVAL;
@@ -275,20 +275,19 @@ static int gpio_irq_type(unsigned irq, unsigned type)
275 275
276static struct irq_chip gpio_irqchip = { 276static struct irq_chip gpio_irqchip = {
277 .name = "gpio", 277 .name = "gpio",
278 .mask = gpio_irq_mask, 278 .irq_mask = gpio_irq_mask,
279 .unmask = gpio_irq_unmask, 279 .irq_unmask = gpio_irq_unmask,
280 .set_type = gpio_irq_type, 280 .irq_set_type = gpio_irq_type,
281}; 281};
282 282
283static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 283static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
284{ 284{
285 struct pio_device *pio = get_irq_chip_data(irq); 285 struct pio_device *pio = get_irq_desc_chip_data(desc);
286 unsigned gpio_irq; 286 unsigned gpio_irq;
287 287
288 gpio_irq = (unsigned) get_irq_data(irq); 288 gpio_irq = (unsigned) irq_get_handler_data(irq);
289 for (;;) { 289 for (;;) {
290 u32 isr; 290 u32 isr;
291 struct irq_desc *d;
292 291
293 /* ack pending GPIO interrupts */ 292 /* ack pending GPIO interrupts */
294 isr = pio_readl(pio, ISR) & pio_readl(pio, IMR); 293 isr = pio_readl(pio, ISR) & pio_readl(pio, IMR);
@@ -301,9 +300,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
301 isr &= ~(1 << i); 300 isr &= ~(1 << i);
302 301
303 i += gpio_irq; 302 i += gpio_irq;
304 d = &irq_desc[i]; 303 generic_handle_irq(i);
305
306 d->handle_irq(i, d);
307 } while (isr); 304 } while (isr);
308 } 305 }
309} 306}
@@ -313,16 +310,16 @@ gpio_irq_setup(struct pio_device *pio, int irq, int gpio_irq)
313{ 310{
314 unsigned i; 311 unsigned i;
315 312
316 set_irq_chip_data(irq, pio); 313 irq_set_chip_data(irq, pio);
317 set_irq_data(irq, (void *) gpio_irq); 314 irq_set_handler_data(irq, (void *)gpio_irq);
318 315
319 for (i = 0; i < 32; i++, gpio_irq++) { 316 for (i = 0; i < 32; i++, gpio_irq++) {
320 set_irq_chip_data(gpio_irq, pio); 317 irq_set_chip_data(gpio_irq, pio);
321 set_irq_chip_and_handler(gpio_irq, &gpio_irqchip, 318 irq_set_chip_and_handler(gpio_irq, &gpio_irqchip,
322 handle_simple_irq); 319 handle_simple_irq);
323 } 320 }
324 321
325 set_irq_chained_handler(irq, gpio_irq_handler); 322 irq_set_chained_handler(irq, gpio_irq_handler);
326} 323}
327 324
328/*--------------------------------------------------------------------------*/ 325/*--------------------------------------------------------------------------*/
diff --git a/arch/h8300/Kconfig b/arch/h8300/Kconfig
index 9624db193e3c..931a1ac99ff1 100644
--- a/arch/h8300/Kconfig
+++ b/arch/h8300/Kconfig
@@ -4,6 +4,7 @@ config H8300
4 select HAVE_IDE 4 select HAVE_IDE
5 select HAVE_GENERIC_HARDIRQS 5 select HAVE_GENERIC_HARDIRQS
6 select GENERIC_HARDIRQS_NO_DEPRECATED 6 select GENERIC_HARDIRQS_NO_DEPRECATED
7 select GENERIC_IRQ_SHOW
7 8
8config SYMBOL_PREFIX 9config SYMBOL_PREFIX
9 string 10 string
diff --git a/arch/h8300/kernel/irq.c b/arch/h8300/kernel/irq.c
index 7643d39925d6..1f67fed476af 100644
--- a/arch/h8300/kernel/irq.c
+++ b/arch/h8300/kernel/irq.c
@@ -155,7 +155,7 @@ void __init init_IRQ(void)
155 setup_vector(); 155 setup_vector();
156 156
157 for (c = 0; c < NR_IRQS; c++) 157 for (c = 0; c < NR_IRQS; c++)
158 set_irq_chip_and_handler(c, &h8300irq_chip, handle_simple_irq); 158 irq_set_chip_and_handler(c, &h8300irq_chip, handle_simple_irq);
159} 159}
160 160
161asmlinkage void do_IRQ(int irq) 161asmlinkage void do_IRQ(int irq)
@@ -164,34 +164,3 @@ asmlinkage void do_IRQ(int irq)
164 generic_handle_irq(irq); 164 generic_handle_irq(irq);
165 irq_exit(); 165 irq_exit();
166} 166}
167
168#if defined(CONFIG_PROC_FS)
169int show_interrupts(struct seq_file *p, void *v)
170{
171 int i = *(loff_t *) v;
172 struct irqaction * action;
173 unsigned long flags;
174
175 if (i == 0)
176 seq_puts(p, " CPU0");
177
178 if (i < NR_IRQS) {
179 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
180 action = irq_desc[i].action;
181 if (!action)
182 goto unlock;
183 seq_printf(p, "%3d: ",i);
184 seq_printf(p, "%10u ", kstat_irqs(i));
185 seq_printf(p, " %14s", irq_desc[i].irq_data.chip->name);
186 seq_printf(p, "-%-8s", irq_desc[i].name);
187 seq_printf(p, " %s", action->name);
188
189 for (action=action->next; action; action = action->next)
190 seq_printf(p, ", %s", action->name);
191 seq_putc(p, '\n');
192unlock:
193 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
194 }
195 return 0;
196}
197#endif
diff --git a/arch/m32r/Kconfig b/arch/m32r/Kconfig
index 62afe23c9a49..b28d0908a402 100644
--- a/arch/m32r/Kconfig
+++ b/arch/m32r/Kconfig
@@ -10,6 +10,7 @@ config M32R
10 select HAVE_GENERIC_HARDIRQS 10 select HAVE_GENERIC_HARDIRQS
11 select GENERIC_HARDIRQS_NO_DEPRECATED 11 select GENERIC_HARDIRQS_NO_DEPRECATED
12 select GENERIC_IRQ_PROBE 12 select GENERIC_IRQ_PROBE
13 select GENERIC_IRQ_SHOW
13 14
14config SBUS 15config SBUS
15 bool 16 bool
diff --git a/arch/m32r/kernel/irq.c b/arch/m32r/kernel/irq.c
index 76eaf3883fbd..c7272b894283 100644
--- a/arch/m32r/kernel/irq.c
+++ b/arch/m32r/kernel/irq.c
@@ -18,55 +18,10 @@
18 18
19#include <linux/kernel_stat.h> 19#include <linux/kernel_stat.h>
20#include <linux/interrupt.h> 20#include <linux/interrupt.h>
21#include <linux/seq_file.h>
22#include <linux/module.h> 21#include <linux/module.h>
23#include <asm/uaccess.h> 22#include <asm/uaccess.h>
24 23
25/* 24/*
26 * Generic, controller-independent functions:
27 */
28
29int show_interrupts(struct seq_file *p, void *v)
30{
31 int i = *(loff_t *) v, j;
32 struct irqaction * action;
33 unsigned long flags;
34
35 if (i == 0) {
36 seq_printf(p, " ");
37 for_each_online_cpu(j)
38 seq_printf(p, "CPU%d ",j);
39 seq_putc(p, '\n');
40 }
41
42 if (i < NR_IRQS) {
43 struct irq_desc *desc = irq_to_desc(i);
44
45 raw_spin_lock_irqsave(&desc->lock, flags);
46 action = desc->action;
47 if (!action)
48 goto skip;
49 seq_printf(p, "%3d: ",i);
50#ifndef CONFIG_SMP
51 seq_printf(p, "%10u ", kstat_irqs(i));
52#else
53 for_each_online_cpu(j)
54 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
55#endif
56 seq_printf(p, " %14s", desc->irq_data.chip->name);
57 seq_printf(p, " %s", action->name);
58
59 for (action=action->next; action; action = action->next)
60 seq_printf(p, ", %s", action->name);
61
62 seq_putc(p, '\n');
63skip:
64 raw_spin_unlock_irqrestore(&desc->lock, flags);
65 }
66 return 0;
67}
68
69/*
70 * do_IRQ handles all normal device IRQs (the special 25 * do_IRQ handles all normal device IRQs (the special
71 * SMP cross-CPU interrupts have their own specific 26 * SMP cross-CPU interrupts have their own specific
72 * handlers). 27 * handlers).
diff --git a/arch/m32r/platforms/m32104ut/setup.c b/arch/m32r/platforms/m32104ut/setup.c
index 4a693d02c1e1..34671d32cefc 100644
--- a/arch/m32r/platforms/m32104ut/setup.c
+++ b/arch/m32r/platforms/m32104ut/setup.c
@@ -76,7 +76,7 @@ void __init init_IRQ(void)
76 76
77#if defined(CONFIG_SMC91X) 77#if defined(CONFIG_SMC91X)
78 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/ 78 /* INT#0: LAN controller on M32104UT-LAN (SMC91C111)*/
79 set_irq_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type, 79 irq_set_chip_and_handler(M32R_IRQ_INT0, &m32104ut_irq_type,
80 handle_level_irq); 80 handle_level_irq);
81 /* "H" level sense */ 81 /* "H" level sense */
82 cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11; 82 cu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD11;
@@ -84,20 +84,20 @@ void __init init_IRQ(void)
84#endif /* CONFIG_SMC91X */ 84#endif /* CONFIG_SMC91X */
85 85
86 /* MFT2 : system timer */ 86 /* MFT2 : system timer */
87 set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type, 87 irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32104ut_irq_type,
88 handle_level_irq); 88 handle_level_irq);
89 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 89 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
90 disable_m32104ut_irq(M32R_IRQ_MFT2); 90 disable_m32104ut_irq(M32R_IRQ_MFT2);
91 91
92#ifdef CONFIG_SERIAL_M32R_SIO 92#ifdef CONFIG_SERIAL_M32R_SIO
93 /* SIO0_R : uart receive data */ 93 /* SIO0_R : uart receive data */
94 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type, 94 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32104ut_irq_type,
95 handle_level_irq); 95 handle_level_irq);
96 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN; 96 icu_data[M32R_IRQ_SIO0_R].icucr = M32R_ICUCR_IEN;
97 disable_m32104ut_irq(M32R_IRQ_SIO0_R); 97 disable_m32104ut_irq(M32R_IRQ_SIO0_R);
98 98
99 /* SIO0_S : uart send data */ 99 /* SIO0_S : uart send data */
100 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type, 100 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32104ut_irq_type,
101 handle_level_irq); 101 handle_level_irq);
102 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN; 102 icu_data[M32R_IRQ_SIO0_S].icucr = M32R_ICUCR_IEN;
103 disable_m32104ut_irq(M32R_IRQ_SIO0_S); 103 disable_m32104ut_irq(M32R_IRQ_SIO0_S);
diff --git a/arch/m32r/platforms/m32700ut/setup.c b/arch/m32r/platforms/m32700ut/setup.c
index 2074bcc841eb..1053e1cb7401 100644
--- a/arch/m32r/platforms/m32700ut/setup.c
+++ b/arch/m32r/platforms/m32700ut/setup.c
@@ -259,76 +259,76 @@ void __init init_IRQ(void)
259{ 259{
260#if defined(CONFIG_SMC91X) 260#if defined(CONFIG_SMC91X)
261 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/ 261 /* INT#0: LAN controller on M32700UT-LAN (SMC91C111)*/
262 set_irq_chip_and_handler(M32700UT_LAN_IRQ_LAN, 262 irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN,
263 &m32700ut_lanpld_irq_type, handle_level_irq); 263 &m32700ut_lanpld_irq_type, handle_level_irq);
264 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 264 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
265 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN); 265 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
266#endif /* CONFIG_SMC91X */ 266#endif /* CONFIG_SMC91X */
267 267
268 /* MFT2 : system timer */ 268 /* MFT2 : system timer */
269 set_irq_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type, 269 irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
270 handle_level_irq); 270 handle_level_irq);
271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
272 disable_m32700ut_irq(M32R_IRQ_MFT2); 272 disable_m32700ut_irq(M32R_IRQ_MFT2);
273 273
274 /* SIO0 : receive */ 274 /* SIO0 : receive */
275 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type, 275 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
276 handle_level_irq); 276 handle_level_irq);
277 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 277 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
278 disable_m32700ut_irq(M32R_IRQ_SIO0_R); 278 disable_m32700ut_irq(M32R_IRQ_SIO0_R);
279 279
280 /* SIO0 : send */ 280 /* SIO0 : send */
281 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type, 281 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
282 handle_level_irq); 282 handle_level_irq);
283 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 283 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
284 disable_m32700ut_irq(M32R_IRQ_SIO0_S); 284 disable_m32700ut_irq(M32R_IRQ_SIO0_S);
285 285
286 /* SIO1 : receive */ 286 /* SIO1 : receive */
287 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type, 287 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
288 handle_level_irq); 288 handle_level_irq);
289 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 289 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
290 disable_m32700ut_irq(M32R_IRQ_SIO1_R); 290 disable_m32700ut_irq(M32R_IRQ_SIO1_R);
291 291
292 /* SIO1 : send */ 292 /* SIO1 : send */
293 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type, 293 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
294 handle_level_irq); 294 handle_level_irq);
295 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 295 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
296 disable_m32700ut_irq(M32R_IRQ_SIO1_S); 296 disable_m32700ut_irq(M32R_IRQ_SIO1_S);
297 297
298 /* DMA1 : */ 298 /* DMA1 : */
299 set_irq_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type, 299 irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
300 handle_level_irq); 300 handle_level_irq);
301 icu_data[M32R_IRQ_DMA1].icucr = 0; 301 icu_data[M32R_IRQ_DMA1].icucr = 0;
302 disable_m32700ut_irq(M32R_IRQ_DMA1); 302 disable_m32700ut_irq(M32R_IRQ_DMA1);
303 303
304#ifdef CONFIG_SERIAL_M32R_PLDSIO 304#ifdef CONFIG_SERIAL_M32R_PLDSIO
305 /* INT#1: SIO0 Receive on PLD */ 305 /* INT#1: SIO0 Receive on PLD */
306 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type, 306 irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
307 handle_level_irq); 307 handle_level_irq);
308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
309 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV); 309 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
310 310
311 /* INT#1: SIO0 Send on PLD */ 311 /* INT#1: SIO0 Send on PLD */
312 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type, 312 irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
313 handle_level_irq); 313 handle_level_irq);
314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
315 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND); 315 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
316#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 316#endif /* CONFIG_SERIAL_M32R_PLDSIO */
317 317
318 /* INT#1: CFC IREQ on PLD */ 318 /* INT#1: CFC IREQ on PLD */
319 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type, 319 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
320 handle_level_irq); 320 handle_level_irq);
321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
322 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ); 322 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
323 323
324 /* INT#1: CFC Insert on PLD */ 324 /* INT#1: CFC Insert on PLD */
325 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type, 325 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
326 handle_level_irq); 326 handle_level_irq);
327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
328 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT); 328 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
329 329
330 /* INT#1: CFC Eject on PLD */ 330 /* INT#1: CFC Eject on PLD */
331 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type, 331 irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
332 handle_level_irq); 332 handle_level_irq);
333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
334 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT); 334 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
@@ -349,7 +349,7 @@ void __init init_IRQ(void)
349 349
350#if defined(CONFIG_USB) 350#if defined(CONFIG_USB)
351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
352 set_irq_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1, 352 irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
353 &m32700ut_lcdpld_irq_type, handle_level_irq); 353 &m32700ut_lcdpld_irq_type, handle_level_irq);
354 354
355 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ 355 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
@@ -366,7 +366,7 @@ void __init init_IRQ(void)
366 /* 366 /*
367 * INT3# is used for AR 367 * INT3# is used for AR
368 */ 368 */
369 set_irq_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type, 369 irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
370 handle_level_irq); 370 handle_level_irq);
371 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 371 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
372 disable_m32700ut_irq(M32R_IRQ_INT3); 372 disable_m32700ut_irq(M32R_IRQ_INT3);
diff --git a/arch/m32r/platforms/mappi/setup.c b/arch/m32r/platforms/mappi/setup.c
index cdd8c4574027..35130ac3f8d1 100644
--- a/arch/m32r/platforms/mappi/setup.c
+++ b/arch/m32r/platforms/mappi/setup.c
@@ -75,39 +75,39 @@ void __init init_IRQ(void)
75 75
76#ifdef CONFIG_NE2000 76#ifdef CONFIG_NE2000
77 /* INT0 : LAN controller (RTL8019AS) */ 77 /* INT0 : LAN controller (RTL8019AS) */
78 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type, 78 irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi_irq_type,
79 handle_level_irq); 79 handle_level_irq);
80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11; 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
81 disable_mappi_irq(M32R_IRQ_INT0); 81 disable_mappi_irq(M32R_IRQ_INT0);
82#endif /* CONFIG_M32R_NE2000 */ 82#endif /* CONFIG_M32R_NE2000 */
83 83
84 /* MFT2 : system timer */ 84 /* MFT2 : system timer */
85 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, 85 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
86 handle_level_irq); 86 handle_level_irq);
87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
88 disable_mappi_irq(M32R_IRQ_MFT2); 88 disable_mappi_irq(M32R_IRQ_MFT2);
89 89
90#ifdef CONFIG_SERIAL_M32R_SIO 90#ifdef CONFIG_SERIAL_M32R_SIO
91 /* SIO0_R : uart receive data */ 91 /* SIO0_R : uart receive data */
92 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, 92 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
93 handle_level_irq); 93 handle_level_irq);
94 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
95 disable_mappi_irq(M32R_IRQ_SIO0_R); 95 disable_mappi_irq(M32R_IRQ_SIO0_R);
96 96
97 /* SIO0_S : uart send data */ 97 /* SIO0_S : uart send data */
98 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, 98 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
99 handle_level_irq); 99 handle_level_irq);
100 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
101 disable_mappi_irq(M32R_IRQ_SIO0_S); 101 disable_mappi_irq(M32R_IRQ_SIO0_S);
102 102
103 /* SIO1_R : uart receive data */ 103 /* SIO1_R : uart receive data */
104 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, 104 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
105 handle_level_irq); 105 handle_level_irq);
106 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
107 disable_mappi_irq(M32R_IRQ_SIO1_R); 107 disable_mappi_irq(M32R_IRQ_SIO1_R);
108 108
109 /* SIO1_S : uart send data */ 109 /* SIO1_S : uart send data */
110 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, 110 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
111 handle_level_irq); 111 handle_level_irq);
112 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
113 disable_mappi_irq(M32R_IRQ_SIO1_S); 113 disable_mappi_irq(M32R_IRQ_SIO1_S);
@@ -115,13 +115,13 @@ void __init init_IRQ(void)
115 115
116#if defined(CONFIG_M32R_PCC) 116#if defined(CONFIG_M32R_PCC)
117 /* INT1 : pccard0 interrupt */ 117 /* INT1 : pccard0 interrupt */
118 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type, 118 irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi_irq_type,
119 handle_level_irq); 119 handle_level_irq);
120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
121 disable_mappi_irq(M32R_IRQ_INT1); 121 disable_mappi_irq(M32R_IRQ_INT1);
122 122
123 /* INT2 : pccard1 interrupt */ 123 /* INT2 : pccard1 interrupt */
124 set_irq_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type, 124 irq_set_chip_and_handler(M32R_IRQ_INT2, &mappi_irq_type,
125 handle_level_irq); 125 handle_level_irq);
126 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00; 126 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN | M32R_ICUCR_ISMOD00;
127 disable_mappi_irq(M32R_IRQ_INT2); 127 disable_mappi_irq(M32R_IRQ_INT2);
diff --git a/arch/m32r/platforms/mappi2/setup.c b/arch/m32r/platforms/mappi2/setup.c
index 9117c30ea365..f3ed6b60a5f8 100644
--- a/arch/m32r/platforms/mappi2/setup.c
+++ b/arch/m32r/platforms/mappi2/setup.c
@@ -76,38 +76,38 @@ void __init init_IRQ(void)
76{ 76{
77#if defined(CONFIG_SMC91X) 77#if defined(CONFIG_SMC91X)
78 /* INT0 : LAN controller (SMC91111) */ 78 /* INT0 : LAN controller (SMC91111) */
79 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type, 79 irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi2_irq_type,
80 handle_level_irq); 80 handle_level_irq);
81 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 81 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
82 disable_mappi2_irq(M32R_IRQ_INT0); 82 disable_mappi2_irq(M32R_IRQ_INT0);
83#endif /* CONFIG_SMC91X */ 83#endif /* CONFIG_SMC91X */
84 84
85 /* MFT2 : system timer */ 85 /* MFT2 : system timer */
86 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type, 86 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi2_irq_type,
87 handle_level_irq); 87 handle_level_irq);
88 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 88 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
89 disable_mappi2_irq(M32R_IRQ_MFT2); 89 disable_mappi2_irq(M32R_IRQ_MFT2);
90 90
91#ifdef CONFIG_SERIAL_M32R_SIO 91#ifdef CONFIG_SERIAL_M32R_SIO
92 /* SIO0_R : uart receive data */ 92 /* SIO0_R : uart receive data */
93 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type, 93 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi2_irq_type,
94 handle_level_irq); 94 handle_level_irq);
95 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 95 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
96 disable_mappi2_irq(M32R_IRQ_SIO0_R); 96 disable_mappi2_irq(M32R_IRQ_SIO0_R);
97 97
98 /* SIO0_S : uart send data */ 98 /* SIO0_S : uart send data */
99 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type, 99 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi2_irq_type,
100 handle_level_irq); 100 handle_level_irq);
101 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 101 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
102 disable_mappi2_irq(M32R_IRQ_SIO0_S); 102 disable_mappi2_irq(M32R_IRQ_SIO0_S);
103 /* SIO1_R : uart receive data */ 103 /* SIO1_R : uart receive data */
104 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type, 104 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi2_irq_type,
105 handle_level_irq); 105 handle_level_irq);
106 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 106 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
107 disable_mappi2_irq(M32R_IRQ_SIO1_R); 107 disable_mappi2_irq(M32R_IRQ_SIO1_R);
108 108
109 /* SIO1_S : uart send data */ 109 /* SIO1_S : uart send data */
110 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type, 110 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi2_irq_type,
111 handle_level_irq); 111 handle_level_irq);
112 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 112 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
113 disable_mappi2_irq(M32R_IRQ_SIO1_S); 113 disable_mappi2_irq(M32R_IRQ_SIO1_S);
@@ -115,27 +115,27 @@ void __init init_IRQ(void)
115 115
116#if defined(CONFIG_USB) 116#if defined(CONFIG_USB)
117 /* INT1 : USB Host controller interrupt */ 117 /* INT1 : USB Host controller interrupt */
118 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type, 118 irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi2_irq_type,
119 handle_level_irq); 119 handle_level_irq);
120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 120 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
121 disable_mappi2_irq(M32R_IRQ_INT1); 121 disable_mappi2_irq(M32R_IRQ_INT1);
122#endif /* CONFIG_USB */ 122#endif /* CONFIG_USB */
123 123
124 /* ICUCR40: CFC IREQ */ 124 /* ICUCR40: CFC IREQ */
125 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type, 125 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi2_irq_type,
126 handle_level_irq); 126 handle_level_irq);
127 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 127 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
128 disable_mappi2_irq(PLD_IRQ_CFIREQ); 128 disable_mappi2_irq(PLD_IRQ_CFIREQ);
129 129
130#if defined(CONFIG_M32R_CFC) 130#if defined(CONFIG_M32R_CFC)
131 /* ICUCR41: CFC Insert */ 131 /* ICUCR41: CFC Insert */
132 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type, 132 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi2_irq_type,
133 handle_level_irq); 133 handle_level_irq);
134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 134 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
135 disable_mappi2_irq(PLD_IRQ_CFC_INSERT); 135 disable_mappi2_irq(PLD_IRQ_CFC_INSERT);
136 136
137 /* ICUCR42: CFC Eject */ 137 /* ICUCR42: CFC Eject */
138 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type, 138 irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &mappi2_irq_type,
139 handle_level_irq); 139 handle_level_irq);
140 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 140 icu_data[PLD_IRQ_CFC_EJECT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
141 disable_mappi2_irq(PLD_IRQ_CFC_EJECT); 141 disable_mappi2_irq(PLD_IRQ_CFC_EJECT);
diff --git a/arch/m32r/platforms/mappi3/setup.c b/arch/m32r/platforms/mappi3/setup.c
index b44f5ded2bbe..2408e356ad10 100644
--- a/arch/m32r/platforms/mappi3/setup.c
+++ b/arch/m32r/platforms/mappi3/setup.c
@@ -75,38 +75,38 @@ void __init init_IRQ(void)
75{ 75{
76#if defined(CONFIG_SMC91X) 76#if defined(CONFIG_SMC91X)
77 /* INT0 : LAN controller (SMC91111) */ 77 /* INT0 : LAN controller (SMC91111) */
78 set_irq_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type, 78 irq_set_chip_and_handler(M32R_IRQ_INT0, &mappi3_irq_type,
79 handle_level_irq); 79 handle_level_irq);
80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 80 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
81 disable_mappi3_irq(M32R_IRQ_INT0); 81 disable_mappi3_irq(M32R_IRQ_INT0);
82#endif /* CONFIG_SMC91X */ 82#endif /* CONFIG_SMC91X */
83 83
84 /* MFT2 : system timer */ 84 /* MFT2 : system timer */
85 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type, 85 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi3_irq_type,
86 handle_level_irq); 86 handle_level_irq);
87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 87 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
88 disable_mappi3_irq(M32R_IRQ_MFT2); 88 disable_mappi3_irq(M32R_IRQ_MFT2);
89 89
90#ifdef CONFIG_SERIAL_M32R_SIO 90#ifdef CONFIG_SERIAL_M32R_SIO
91 /* SIO0_R : uart receive data */ 91 /* SIO0_R : uart receive data */
92 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type, 92 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi3_irq_type,
93 handle_level_irq); 93 handle_level_irq);
94 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 94 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
95 disable_mappi3_irq(M32R_IRQ_SIO0_R); 95 disable_mappi3_irq(M32R_IRQ_SIO0_R);
96 96
97 /* SIO0_S : uart send data */ 97 /* SIO0_S : uart send data */
98 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type, 98 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi3_irq_type,
99 handle_level_irq); 99 handle_level_irq);
100 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 100 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
101 disable_mappi3_irq(M32R_IRQ_SIO0_S); 101 disable_mappi3_irq(M32R_IRQ_SIO0_S);
102 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
103 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type, 103 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi3_irq_type,
104 handle_level_irq); 104 handle_level_irq);
105 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
106 disable_mappi3_irq(M32R_IRQ_SIO1_R); 106 disable_mappi3_irq(M32R_IRQ_SIO1_R);
107 107
108 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
109 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type, 109 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi3_irq_type,
110 handle_level_irq); 110 handle_level_irq);
111 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
112 disable_mappi3_irq(M32R_IRQ_SIO1_S); 112 disable_mappi3_irq(M32R_IRQ_SIO1_S);
@@ -114,21 +114,21 @@ void __init init_IRQ(void)
114 114
115#if defined(CONFIG_USB) 115#if defined(CONFIG_USB)
116 /* INT1 : USB Host controller interrupt */ 116 /* INT1 : USB Host controller interrupt */
117 set_irq_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type, 117 irq_set_chip_and_handler(M32R_IRQ_INT1, &mappi3_irq_type,
118 handle_level_irq); 118 handle_level_irq);
119 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01; 119 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_ISMOD01;
120 disable_mappi3_irq(M32R_IRQ_INT1); 120 disable_mappi3_irq(M32R_IRQ_INT1);
121#endif /* CONFIG_USB */ 121#endif /* CONFIG_USB */
122 122
123 /* CFC IREQ */ 123 /* CFC IREQ */
124 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type, 124 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &mappi3_irq_type,
125 handle_level_irq); 125 handle_level_irq);
126 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01; 126 icu_data[PLD_IRQ_CFIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
127 disable_mappi3_irq(PLD_IRQ_CFIREQ); 127 disable_mappi3_irq(PLD_IRQ_CFIREQ);
128 128
129#if defined(CONFIG_M32R_CFC) 129#if defined(CONFIG_M32R_CFC)
130 /* ICUCR41: CFC Insert & eject */ 130 /* ICUCR41: CFC Insert & eject */
131 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type, 131 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &mappi3_irq_type,
132 handle_level_irq); 132 handle_level_irq);
133 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00; 133 icu_data[PLD_IRQ_CFC_INSERT].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD00;
134 disable_mappi3_irq(PLD_IRQ_CFC_INSERT); 134 disable_mappi3_irq(PLD_IRQ_CFC_INSERT);
@@ -136,7 +136,7 @@ void __init init_IRQ(void)
136#endif /* CONFIG_M32R_CFC */ 136#endif /* CONFIG_M32R_CFC */
137 137
138 /* IDE IREQ */ 138 /* IDE IREQ */
139 set_irq_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type, 139 irq_set_chip_and_handler(PLD_IRQ_IDEIREQ, &mappi3_irq_type,
140 handle_level_irq); 140 handle_level_irq);
141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 141 icu_data[PLD_IRQ_IDEIREQ].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
142 disable_mappi3_irq(PLD_IRQ_IDEIREQ); 142 disable_mappi3_irq(PLD_IRQ_IDEIREQ);
diff --git a/arch/m32r/platforms/oaks32r/setup.c b/arch/m32r/platforms/oaks32r/setup.c
index 19a02db7b818..83b46b067a17 100644
--- a/arch/m32r/platforms/oaks32r/setup.c
+++ b/arch/m32r/platforms/oaks32r/setup.c
@@ -74,39 +74,39 @@ void __init init_IRQ(void)
74 74
75#ifdef CONFIG_NE2000 75#ifdef CONFIG_NE2000
76 /* INT3 : LAN controller (RTL8019AS) */ 76 /* INT3 : LAN controller (RTL8019AS) */
77 set_irq_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type, 77 irq_set_chip_and_handler(M32R_IRQ_INT3, &oaks32r_irq_type,
78 handle_level_irq); 78 handle_level_irq);
79 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 79 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
80 disable_oaks32r_irq(M32R_IRQ_INT3); 80 disable_oaks32r_irq(M32R_IRQ_INT3);
81#endif /* CONFIG_M32R_NE2000 */ 81#endif /* CONFIG_M32R_NE2000 */
82 82
83 /* MFT2 : system timer */ 83 /* MFT2 : system timer */
84 set_irq_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type, 84 irq_set_chip_and_handler(M32R_IRQ_MFT2, &oaks32r_irq_type,
85 handle_level_irq); 85 handle_level_irq);
86 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 86 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
87 disable_oaks32r_irq(M32R_IRQ_MFT2); 87 disable_oaks32r_irq(M32R_IRQ_MFT2);
88 88
89#ifdef CONFIG_SERIAL_M32R_SIO 89#ifdef CONFIG_SERIAL_M32R_SIO
90 /* SIO0_R : uart receive data */ 90 /* SIO0_R : uart receive data */
91 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type, 91 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &oaks32r_irq_type,
92 handle_level_irq); 92 handle_level_irq);
93 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 93 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
94 disable_oaks32r_irq(M32R_IRQ_SIO0_R); 94 disable_oaks32r_irq(M32R_IRQ_SIO0_R);
95 95
96 /* SIO0_S : uart send data */ 96 /* SIO0_S : uart send data */
97 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type, 97 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &oaks32r_irq_type,
98 handle_level_irq); 98 handle_level_irq);
99 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 99 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
100 disable_oaks32r_irq(M32R_IRQ_SIO0_S); 100 disable_oaks32r_irq(M32R_IRQ_SIO0_S);
101 101
102 /* SIO1_R : uart receive data */ 102 /* SIO1_R : uart receive data */
103 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type, 103 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &oaks32r_irq_type,
104 handle_level_irq); 104 handle_level_irq);
105 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 105 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
106 disable_oaks32r_irq(M32R_IRQ_SIO1_R); 106 disable_oaks32r_irq(M32R_IRQ_SIO1_R);
107 107
108 /* SIO1_S : uart send data */ 108 /* SIO1_S : uart send data */
109 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type, 109 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &oaks32r_irq_type,
110 handle_level_irq); 110 handle_level_irq);
111 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 111 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
112 disable_oaks32r_irq(M32R_IRQ_SIO1_S); 112 disable_oaks32r_irq(M32R_IRQ_SIO1_S);
diff --git a/arch/m32r/platforms/opsput/setup.c b/arch/m32r/platforms/opsput/setup.c
index 12731547e8bf..32660705f5fd 100644
--- a/arch/m32r/platforms/opsput/setup.c
+++ b/arch/m32r/platforms/opsput/setup.c
@@ -259,76 +259,76 @@ void __init init_IRQ(void)
259{ 259{
260#if defined(CONFIG_SMC91X) 260#if defined(CONFIG_SMC91X)
261 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/ 261 /* INT#0: LAN controller on OPSPUT-LAN (SMC91C111)*/
262 set_irq_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type, 262 irq_set_chip_and_handler(OPSPUT_LAN_IRQ_LAN, &opsput_lanpld_irq_type,
263 handle_level_irq); 263 handle_level_irq);
264 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */ 264 lanpld_icu_data[irq2lanpldirq(OPSPUT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* "H" edge sense */
265 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN); 265 disable_opsput_lanpld_irq(OPSPUT_LAN_IRQ_LAN);
266#endif /* CONFIG_SMC91X */ 266#endif /* CONFIG_SMC91X */
267 267
268 /* MFT2 : system timer */ 268 /* MFT2 : system timer */
269 set_irq_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type, 269 irq_set_chip_and_handler(M32R_IRQ_MFT2, &opsput_irq_type,
270 handle_level_irq); 270 handle_level_irq);
271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 271 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
272 disable_opsput_irq(M32R_IRQ_MFT2); 272 disable_opsput_irq(M32R_IRQ_MFT2);
273 273
274 /* SIO0 : receive */ 274 /* SIO0 : receive */
275 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type, 275 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &opsput_irq_type,
276 handle_level_irq); 276 handle_level_irq);
277 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 277 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
278 disable_opsput_irq(M32R_IRQ_SIO0_R); 278 disable_opsput_irq(M32R_IRQ_SIO0_R);
279 279
280 /* SIO0 : send */ 280 /* SIO0 : send */
281 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type, 281 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &opsput_irq_type,
282 handle_level_irq); 282 handle_level_irq);
283 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 283 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
284 disable_opsput_irq(M32R_IRQ_SIO0_S); 284 disable_opsput_irq(M32R_IRQ_SIO0_S);
285 285
286 /* SIO1 : receive */ 286 /* SIO1 : receive */
287 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type, 287 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &opsput_irq_type,
288 handle_level_irq); 288 handle_level_irq);
289 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 289 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
290 disable_opsput_irq(M32R_IRQ_SIO1_R); 290 disable_opsput_irq(M32R_IRQ_SIO1_R);
291 291
292 /* SIO1 : send */ 292 /* SIO1 : send */
293 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type, 293 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &opsput_irq_type,
294 handle_level_irq); 294 handle_level_irq);
295 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 295 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
296 disable_opsput_irq(M32R_IRQ_SIO1_S); 296 disable_opsput_irq(M32R_IRQ_SIO1_S);
297 297
298 /* DMA1 : */ 298 /* DMA1 : */
299 set_irq_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type, 299 irq_set_chip_and_handler(M32R_IRQ_DMA1, &opsput_irq_type,
300 handle_level_irq); 300 handle_level_irq);
301 icu_data[M32R_IRQ_DMA1].icucr = 0; 301 icu_data[M32R_IRQ_DMA1].icucr = 0;
302 disable_opsput_irq(M32R_IRQ_DMA1); 302 disable_opsput_irq(M32R_IRQ_DMA1);
303 303
304#ifdef CONFIG_SERIAL_M32R_PLDSIO 304#ifdef CONFIG_SERIAL_M32R_PLDSIO
305 /* INT#1: SIO0 Receive on PLD */ 305 /* INT#1: SIO0 Receive on PLD */
306 set_irq_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type, 306 irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &opsput_pld_irq_type,
307 handle_level_irq); 307 handle_level_irq);
308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 308 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
309 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV); 309 disable_opsput_pld_irq(PLD_IRQ_SIO0_RCV);
310 310
311 /* INT#1: SIO0 Send on PLD */ 311 /* INT#1: SIO0 Send on PLD */
312 set_irq_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type, 312 irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &opsput_pld_irq_type,
313 handle_level_irq); 313 handle_level_irq);
314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03; 314 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
315 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND); 315 disable_opsput_pld_irq(PLD_IRQ_SIO0_SND);
316#endif /* CONFIG_SERIAL_M32R_PLDSIO */ 316#endif /* CONFIG_SERIAL_M32R_PLDSIO */
317 317
318 /* INT#1: CFC IREQ on PLD */ 318 /* INT#1: CFC IREQ on PLD */
319 set_irq_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type, 319 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &opsput_pld_irq_type,
320 handle_level_irq); 320 handle_level_irq);
321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */ 321 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* 'L' level sense */
322 disable_opsput_pld_irq(PLD_IRQ_CFIREQ); 322 disable_opsput_pld_irq(PLD_IRQ_CFIREQ);
323 323
324 /* INT#1: CFC Insert on PLD */ 324 /* INT#1: CFC Insert on PLD */
325 set_irq_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type, 325 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &opsput_pld_irq_type,
326 handle_level_irq); 326 handle_level_irq);
327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */ 327 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00; /* 'L' edge sense */
328 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT); 328 disable_opsput_pld_irq(PLD_IRQ_CFC_INSERT);
329 329
330 /* INT#1: CFC Eject on PLD */ 330 /* INT#1: CFC Eject on PLD */
331 set_irq_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type, 331 irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &opsput_pld_irq_type,
332 handle_level_irq); 332 handle_level_irq);
333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */ 333 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02; /* 'H' edge sense */
334 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT); 334 disable_opsput_pld_irq(PLD_IRQ_CFC_EJECT);
@@ -349,7 +349,7 @@ void __init init_IRQ(void)
349 349
350#if defined(CONFIG_USB) 350#if defined(CONFIG_USB)
351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */ 351 outw(USBCR_OTGS, USBCR); /* USBCR: non-OTG */
352 set_irq_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1, 352 irq_set_chip_and_handler(OPSPUT_LCD_IRQ_USB_INT1,
353 &opsput_lcdpld_irq_type, handle_level_irq); 353 &opsput_lcdpld_irq_type, handle_level_irq);
354 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */ 354 lcdpld_icu_data[irq2lcdpldirq(OPSPUT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01; /* "L" level sense */
355 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1); 355 disable_opsput_lcdpld_irq(OPSPUT_LCD_IRQ_USB_INT1);
@@ -365,7 +365,7 @@ void __init init_IRQ(void)
365 /* 365 /*
366 * INT3# is used for AR 366 * INT3# is used for AR
367 */ 367 */
368 set_irq_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type, 368 irq_set_chip_and_handler(M32R_IRQ_INT3, &opsput_irq_type,
369 handle_level_irq); 369 handle_level_irq);
370 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10; 370 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
371 disable_opsput_irq(M32R_IRQ_INT3); 371 disable_opsput_irq(M32R_IRQ_INT3);
diff --git a/arch/m32r/platforms/usrv/setup.c b/arch/m32r/platforms/usrv/setup.c
index f3cff26d6e74..0c7a1e8c77b0 100644
--- a/arch/m32r/platforms/usrv/setup.c
+++ b/arch/m32r/platforms/usrv/setup.c
@@ -138,32 +138,32 @@ void __init init_IRQ(void)
138 once++; 138 once++;
139 139
140 /* MFT2 : system timer */ 140 /* MFT2 : system timer */
141 set_irq_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type, 141 irq_set_chip_and_handler(M32R_IRQ_MFT2, &mappi_irq_type,
142 handle_level_irq); 142 handle_level_irq);
143 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN; 143 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
144 disable_mappi_irq(M32R_IRQ_MFT2); 144 disable_mappi_irq(M32R_IRQ_MFT2);
145 145
146#if defined(CONFIG_SERIAL_M32R_SIO) 146#if defined(CONFIG_SERIAL_M32R_SIO)
147 /* SIO0_R : uart receive data */ 147 /* SIO0_R : uart receive data */
148 set_irq_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type, 148 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &mappi_irq_type,
149 handle_level_irq); 149 handle_level_irq);
150 icu_data[M32R_IRQ_SIO0_R].icucr = 0; 150 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
151 disable_mappi_irq(M32R_IRQ_SIO0_R); 151 disable_mappi_irq(M32R_IRQ_SIO0_R);
152 152
153 /* SIO0_S : uart send data */ 153 /* SIO0_S : uart send data */
154 set_irq_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type, 154 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &mappi_irq_type,
155 handle_level_irq); 155 handle_level_irq);
156 icu_data[M32R_IRQ_SIO0_S].icucr = 0; 156 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
157 disable_mappi_irq(M32R_IRQ_SIO0_S); 157 disable_mappi_irq(M32R_IRQ_SIO0_S);
158 158
159 /* SIO1_R : uart receive data */ 159 /* SIO1_R : uart receive data */
160 set_irq_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type, 160 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &mappi_irq_type,
161 handle_level_irq); 161 handle_level_irq);
162 icu_data[M32R_IRQ_SIO1_R].icucr = 0; 162 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
163 disable_mappi_irq(M32R_IRQ_SIO1_R); 163 disable_mappi_irq(M32R_IRQ_SIO1_R);
164 164
165 /* SIO1_S : uart send data */ 165 /* SIO1_S : uart send data */
166 set_irq_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type, 166 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &mappi_irq_type,
167 handle_level_irq); 167 handle_level_irq);
168 icu_data[M32R_IRQ_SIO1_S].icucr = 0; 168 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
169 disable_mappi_irq(M32R_IRQ_SIO1_S); 169 disable_mappi_irq(M32R_IRQ_SIO1_S);
@@ -171,7 +171,7 @@ void __init init_IRQ(void)
171 171
172 /* INT#67-#71: CFC#0 IREQ on PLD */ 172 /* INT#67-#71: CFC#0 IREQ on PLD */
173 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) { 173 for (i = 0 ; i < CONFIG_M32R_CFC_NUM ; i++ ) {
174 set_irq_chip_and_handler(PLD_IRQ_CF0 + i, 174 irq_set_chip_and_handler(PLD_IRQ_CF0 + i,
175 &m32700ut_pld_irq_type, 175 &m32700ut_pld_irq_type,
176 handle_level_irq); 176 handle_level_irq);
177 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr 177 pld_icu_data[irq2pldirq(PLD_IRQ_CF0 + i)].icucr
@@ -181,14 +181,14 @@ void __init init_IRQ(void)
181 181
182#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE) 182#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
183 /* INT#76: 16552D#0 IREQ on PLD */ 183 /* INT#76: 16552D#0 IREQ on PLD */
184 set_irq_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type, 184 irq_set_chip_and_handler(PLD_IRQ_UART0, &m32700ut_pld_irq_type,
185 handle_level_irq); 185 handle_level_irq);
186 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr 186 pld_icu_data[irq2pldirq(PLD_IRQ_UART0)].icucr
187 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 187 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
188 disable_m32700ut_pld_irq(PLD_IRQ_UART0); 188 disable_m32700ut_pld_irq(PLD_IRQ_UART0);
189 189
190 /* INT#77: 16552D#1 IREQ on PLD */ 190 /* INT#77: 16552D#1 IREQ on PLD */
191 set_irq_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type, 191 irq_set_chip_and_handler(PLD_IRQ_UART1, &m32700ut_pld_irq_type,
192 handle_level_irq); 192 handle_level_irq);
193 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr 193 pld_icu_data[irq2pldirq(PLD_IRQ_UART1)].icucr
194 = PLD_ICUCR_ISMOD03; /* 'H' level sense */ 194 = PLD_ICUCR_ISMOD03; /* 'H' level sense */
@@ -197,7 +197,7 @@ void __init init_IRQ(void)
197 197
198#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE) 198#if defined(CONFIG_IDC_AK4524) || defined(CONFIG_IDC_AK4524_MODULE)
199 /* INT#80: AK4524 IREQ on PLD */ 199 /* INT#80: AK4524 IREQ on PLD */
200 set_irq_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type, 200 irq_set_chip_and_handler(PLD_IRQ_SNDINT, &m32700ut_pld_irq_type,
201 handle_level_irq); 201 handle_level_irq);
202 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr 202 pld_icu_data[irq2pldirq(PLD_IRQ_SNDINT)].icucr
203 = PLD_ICUCR_ISMOD01; /* 'L' level sense */ 203 = PLD_ICUCR_ISMOD01; /* 'L' level sense */
diff --git a/arch/um/Kconfig.common b/arch/um/Kconfig.common
index 1e78940218c0..109ddc0071c6 100644
--- a/arch/um/Kconfig.common
+++ b/arch/um/Kconfig.common
@@ -8,6 +8,7 @@ config UML
8 default y 8 default y
9 select HAVE_GENERIC_HARDIRQS 9 select HAVE_GENERIC_HARDIRQS
10 select GENERIC_HARDIRQS_NO_DEPRECATED 10 select GENERIC_HARDIRQS_NO_DEPRECATED
11 select GENERIC_IRQ_SHOW
11 12
12config MMU 13config MMU
13 bool 14 bool
diff --git a/arch/um/kernel/irq.c b/arch/um/kernel/irq.c
index 64cfea80cfe2..9e485c770308 100644
--- a/arch/um/kernel/irq.c
+++ b/arch/um/kernel/irq.c
@@ -18,52 +18,6 @@
18#include "os.h" 18#include "os.h"
19 19
20/* 20/*
21 * Generic, controller-independent functions:
22 */
23
24int show_interrupts(struct seq_file *p, void *v)
25{
26 int i = *(loff_t *) v, j;
27 struct irqaction * action;
28 unsigned long flags;
29
30 if (i == 0) {
31 seq_printf(p, " ");
32 for_each_online_cpu(j)
33 seq_printf(p, "CPU%d ",j);
34 seq_putc(p, '\n');
35 }
36
37 if (i < NR_IRQS) {
38 struct irq_desc *desc = irq_to_desc(i);
39
40 raw_spin_lock_irqsave(&desc->lock, flags);
41 action = desc->action;
42 if (!action)
43 goto skip;
44 seq_printf(p, "%3d: ",i);
45#ifndef CONFIG_SMP
46 seq_printf(p, "%10u ", kstat_irqs(i));
47#else
48 for_each_online_cpu(j)
49 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
50#endif
51 seq_printf(p, " %14s", get_irq_desc_chip(desc)->name);
52 seq_printf(p, " %s", action->name);
53
54 for (action=action->next; action; action = action->next)
55 seq_printf(p, ", %s", action->name);
56
57 seq_putc(p, '\n');
58skip:
59 raw_spin_unlock_irqrestore(&desc->lock, flags);
60 } else if (i == NR_IRQS)
61 seq_putc(p, '\n');
62
63 return 0;
64}
65
66/*
67 * This list is accessed under irq_lock, except in sigio_handler, 21 * This list is accessed under irq_lock, except in sigio_handler,
68 * where it is safe from being modified. IRQ handlers won't change it - 22 * where it is safe from being modified. IRQ handlers won't change it -
69 * if an IRQ source has vanished, it will be freed by free_irqs just 23 * if an IRQ source has vanished, it will be freed by free_irqs just
@@ -390,11 +344,10 @@ void __init init_IRQ(void)
390{ 344{
391 int i; 345 int i;
392 346
393 set_irq_chip_and_handler(TIMER_IRQ, &SIGVTALRM_irq_type, handle_edge_irq); 347 irq_set_chip_and_handler(TIMER_IRQ, &SIGVTALRM_irq_type, handle_edge_irq);
394 348
395 for (i = 1; i < NR_IRQS; i++) { 349 for (i = 1; i < NR_IRQS; i++)
396 set_irq_chip_and_handler(i, &normal_irq_type, handle_edge_irq); 350 irq_set_chip_and_handler(i, &normal_irq_type, handle_edge_irq);
397 }
398} 351}
399 352
400/* 353/*
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 72839190f503..1d730b5579a0 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -7,6 +7,9 @@ config ZONE_DMA
7config XTENSA 7config XTENSA
8 def_bool y 8 def_bool y
9 select HAVE_IDE 9 select HAVE_IDE
10 select HAVE_GENERIC_HARDIRQS
11 select GENERIC_IRQ_SHOW
12 select GENERIC_HARDIRQS_NO_DEPRECATED
10 help 13 help
11 Xtensa processors are 32-bit RISC machines designed by Tensilica 14 Xtensa processors are 32-bit RISC machines designed by Tensilica
12 primarily for embedded systems. These processors are both 15 primarily for embedded systems. These processors are both
@@ -27,9 +30,6 @@ config GENERIC_FIND_BIT_LE
27config GENERIC_HWEIGHT 30config GENERIC_HWEIGHT
28 def_bool y 31 def_bool y
29 32
30config GENERIC_HARDIRQS
31 def_bool y
32
33config GENERIC_GPIO 33config GENERIC_GPIO
34 def_bool y 34 def_bool y
35 35
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c
index 87508886cbbd..d77089df412e 100644
--- a/arch/xtensa/kernel/irq.c
+++ b/arch/xtensa/kernel/irq.c
@@ -35,7 +35,6 @@ atomic_t irq_err_count;
35asmlinkage void do_IRQ(int irq, struct pt_regs *regs) 35asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
36{ 36{
37 struct pt_regs *old_regs = set_irq_regs(regs); 37 struct pt_regs *old_regs = set_irq_regs(regs);
38 struct irq_desc *desc = irq_desc + irq;
39 38
40 if (irq >= NR_IRQS) { 39 if (irq >= NR_IRQS) {
41 printk(KERN_EMERG "%s: cannot handle IRQ %d\n", 40 printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
@@ -57,104 +56,69 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
57 sp - sizeof(struct thread_info)); 56 sp - sizeof(struct thread_info));
58 } 57 }
59#endif 58#endif
60 desc->handle_irq(irq, desc); 59 generic_handle_irq(irq);
61 60
62 irq_exit(); 61 irq_exit();
63 set_irq_regs(old_regs); 62 set_irq_regs(old_regs);
64} 63}
65 64
66/* 65int arch_show_interrupts(struct seq_file *p, int prec)
67 * Generic, controller-independent functions:
68 */
69
70int show_interrupts(struct seq_file *p, void *v)
71{ 66{
72 int i = *(loff_t *) v, j; 67 int j;
73 struct irqaction * action; 68
74 unsigned long flags; 69 seq_printf(p, "%*s: ", prec, "NMI");
75 70 for_each_online_cpu(j)
76 if (i == 0) { 71 seq_printf(p, "%10u ", nmi_count(j));
77 seq_printf(p, " "); 72 seq_putc(p, '\n');
78 for_each_online_cpu(j) 73 seq_printf(p, "%*s: ", prec, "ERR");
79 seq_printf(p, "CPU%d ",j); 74 seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
80 seq_putc(p, '\n');
81 }
82
83 if (i < NR_IRQS) {
84 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
85 action = irq_desc[i].action;
86 if (!action)
87 goto skip;
88 seq_printf(p, "%3d: ",i);
89#ifndef CONFIG_SMP
90 seq_printf(p, "%10u ", kstat_irqs(i));
91#else
92 for_each_online_cpu(j)
93 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
94#endif
95 seq_printf(p, " %14s", irq_desc[i].chip->name);
96 seq_printf(p, " %s", action->name);
97
98 for (action=action->next; action; action = action->next)
99 seq_printf(p, ", %s", action->name);
100
101 seq_putc(p, '\n');
102skip:
103 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
104 } else if (i == NR_IRQS) {
105 seq_printf(p, "NMI: ");
106 for_each_online_cpu(j)
107 seq_printf(p, "%10u ", nmi_count(j));
108 seq_putc(p, '\n');
109 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
110 }
111 return 0; 75 return 0;
112} 76}
113 77
114static void xtensa_irq_mask(unsigned int irq) 78static void xtensa_irq_mask(struct irq_chip *d)
115{ 79{
116 cached_irq_mask &= ~(1 << irq); 80 cached_irq_mask &= ~(1 << d->irq);
117 set_sr (cached_irq_mask, INTENABLE); 81 set_sr (cached_irq_mask, INTENABLE);
118} 82}
119 83
120static void xtensa_irq_unmask(unsigned int irq) 84static void xtensa_irq_unmask(struct irq_chip *d)
121{ 85{
122 cached_irq_mask |= 1 << irq; 86 cached_irq_mask |= 1 << d->irq;
123 set_sr (cached_irq_mask, INTENABLE); 87 set_sr (cached_irq_mask, INTENABLE);
124} 88}
125 89
126static void xtensa_irq_enable(unsigned int irq) 90static void xtensa_irq_enable(struct irq_chip *d)
127{ 91{
128 variant_irq_enable(irq); 92 variant_irq_enable(d->irq);
129 xtensa_irq_unmask(irq); 93 xtensa_irq_unmask(d->irq);
130} 94}
131 95
132static void xtensa_irq_disable(unsigned int irq) 96static void xtensa_irq_disable(struct irq_chip *d)
133{ 97{
134 xtensa_irq_mask(irq); 98 xtensa_irq_mask(d->irq);
135 variant_irq_disable(irq); 99 variant_irq_disable(d->irq);
136} 100}
137 101
138static void xtensa_irq_ack(unsigned int irq) 102static void xtensa_irq_ack(struct irq_chip *d)
139{ 103{
140 set_sr(1 << irq, INTCLEAR); 104 set_sr(1 << d->irq, INTCLEAR);
141} 105}
142 106
143static int xtensa_irq_retrigger(unsigned int irq) 107static int xtensa_irq_retrigger(struct irq_chip *d)
144{ 108{
145 set_sr (1 << irq, INTSET); 109 set_sr (1 << d->irq, INTSET);
146 return 1; 110 return 1;
147} 111}
148 112
149 113
150static struct irq_chip xtensa_irq_chip = { 114static struct irq_chip xtensa_irq_chip = {
151 .name = "xtensa", 115 .name = "xtensa",
152 .enable = xtensa_irq_enable, 116 .irq_enable = xtensa_irq_enable,
153 .disable = xtensa_irq_disable, 117 .irq_disable = xtensa_irq_disable,
154 .mask = xtensa_irq_mask, 118 .irq_mask = xtensa_irq_mask,
155 .unmask = xtensa_irq_unmask, 119 .irq_unmask = xtensa_irq_unmask,
156 .ack = xtensa_irq_ack, 120 .irq_ack = xtensa_irq_ack,
157 .retrigger = xtensa_irq_retrigger, 121 .irq_retrigger = xtensa_irq_retrigger,
158}; 122};
159 123
160void __init init_IRQ(void) 124void __init init_IRQ(void)
@@ -165,25 +129,25 @@ void __init init_IRQ(void)
165 int mask = 1 << index; 129 int mask = 1 << index;
166 130
167 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) 131 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
168 set_irq_chip_and_handler(index, &xtensa_irq_chip, 132 irq_set_chip_and_handler(index, &xtensa_irq_chip,
169 handle_simple_irq); 133 handle_simple_irq);
170 134
171 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) 135 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
172 set_irq_chip_and_handler(index, &xtensa_irq_chip, 136 irq_set_chip_and_handler(index, &xtensa_irq_chip,
173 handle_edge_irq); 137 handle_edge_irq);
174 138
175 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) 139 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
176 set_irq_chip_and_handler(index, &xtensa_irq_chip, 140 irq_set_chip_and_handler(index, &xtensa_irq_chip,
177 handle_level_irq); 141 handle_level_irq);
178 142
179 else if (mask & XCHAL_INTTYPE_MASK_TIMER) 143 else if (mask & XCHAL_INTTYPE_MASK_TIMER)
180 set_irq_chip_and_handler(index, &xtensa_irq_chip, 144 irq_set_chip_and_handler(index, &xtensa_irq_chip,
181 handle_edge_irq); 145 handle_edge_irq);
182 146
183 else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */ 147 else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
184 /* XCHAL_INTTYPE_MASK_NMI */ 148 /* XCHAL_INTTYPE_MASK_NMI */
185 149
186 set_irq_chip_and_handler(index, &xtensa_irq_chip, 150 irq_set_chip_and_handler(index, &xtensa_irq_chip,
187 handle_level_irq); 151 handle_level_irq);
188 } 152 }
189 153
diff --git a/arch/xtensa/platforms/s6105/device.c b/arch/xtensa/platforms/s6105/device.c
index 65333ffefb07..4f4fc971042f 100644
--- a/arch/xtensa/platforms/s6105/device.c
+++ b/arch/xtensa/platforms/s6105/device.c
@@ -120,7 +120,7 @@ static int __init prepare_phy_irq(int pin)
120 irq = gpio_to_irq(pin); 120 irq = gpio_to_irq(pin);
121 if (irq < 0) 121 if (irq < 0)
122 goto free; 122 goto free;
123 if (set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0) 123 if (irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0)
124 goto free; 124 goto free;
125 return irq; 125 return irq;
126free: 126free:
diff --git a/arch/xtensa/variants/s6000/gpio.c b/arch/xtensa/variants/s6000/gpio.c
index 380a70fff756..7af0757e001b 100644
--- a/arch/xtensa/variants/s6000/gpio.c
+++ b/arch/xtensa/variants/s6000/gpio.c
@@ -85,30 +85,29 @@ int s6_gpio_init(u32 afsel)
85 return gpiochip_add(&gpiochip); 85 return gpiochip_add(&gpiochip);
86} 86}
87 87
88static void ack(unsigned int irq) 88static void ack(struct irq_data *d)
89{ 89{
90 writeb(1 << (irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC); 90 writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
91} 91}
92 92
93static void mask(unsigned int irq) 93static void mask(struct irq_data *d)
94{ 94{
95 u8 r = readb(S6_REG_GPIO + S6_GPIO_IE); 95 u8 r = readb(S6_REG_GPIO + S6_GPIO_IE);
96 r &= ~(1 << (irq - IRQ_BASE)); 96 r &= ~(1 << (d->irq - IRQ_BASE));
97 writeb(r, S6_REG_GPIO + S6_GPIO_IE); 97 writeb(r, S6_REG_GPIO + S6_GPIO_IE);
98} 98}
99 99
100static void unmask(unsigned int irq) 100static void unmask(struct irq_data *d)
101{ 101{
102 u8 m = readb(S6_REG_GPIO + S6_GPIO_IE); 102 u8 m = readb(S6_REG_GPIO + S6_GPIO_IE);
103 m |= 1 << (irq - IRQ_BASE); 103 m |= 1 << (d->irq - IRQ_BASE);
104 writeb(m, S6_REG_GPIO + S6_GPIO_IE); 104 writeb(m, S6_REG_GPIO + S6_GPIO_IE);
105} 105}
106 106
107static int set_type(unsigned int irq, unsigned int type) 107static int set_type(struct irq_data *d, unsigned int type)
108{ 108{
109 const u8 m = 1 << (irq - IRQ_BASE); 109 const u8 m = 1 << (d->irq - IRQ_BASE);
110 irq_flow_handler_t handler; 110 irq_flow_handler_t handler;
111 struct irq_desc *desc;
112 u8 reg; 111 u8 reg;
113 112
114 if (type == IRQ_TYPE_PROBE) { 113 if (type == IRQ_TYPE_PROBE) {
@@ -129,8 +128,7 @@ static int set_type(unsigned int irq, unsigned int type)
129 handler = handle_edge_irq; 128 handler = handle_edge_irq;
130 } 129 }
131 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS); 130 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
132 desc = irq_to_desc(irq); 131 __irq_set_handler_locked(irq, handler);
133 desc->handle_irq = handler;
134 132
135 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV); 133 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
136 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)) 134 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING))
@@ -150,22 +148,23 @@ static int set_type(unsigned int irq, unsigned int type)
150 148
151static struct irq_chip gpioirqs = { 149static struct irq_chip gpioirqs = {
152 .name = "GPIO", 150 .name = "GPIO",
153 .ack = ack, 151 .irq_ack = ack,
154 .mask = mask, 152 .irq_mask = mask,
155 .unmask = unmask, 153 .irq_unmask = unmask,
156 .set_type = set_type, 154 .irq_set_type = set_type,
157}; 155};
158 156
159static u8 demux_masks[4]; 157static u8 demux_masks[4];
160 158
161static void demux_irqs(unsigned int irq, struct irq_desc *desc) 159static void demux_irqs(unsigned int irq, struct irq_desc *desc)
162{ 160{
163 u8 *mask = get_irq_desc_data(desc); 161 struct irq_chip *chip = irq_desc_get_chip(desc);
162 u8 *mask = irq_desc_get_handler_data(desc);
164 u8 pending; 163 u8 pending;
165 int cirq; 164 int cirq;
166 165
167 desc->chip->mask(irq); 166 chip->irq_mask(&desc->irq_data);
168 desc->chip->ack(irq); 167 chip->irq_ack(&desc->irq_data));
169 pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask; 168 pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask;
170 cirq = IRQ_BASE - 1; 169 cirq = IRQ_BASE - 1;
171 while (pending) { 170 while (pending) {
@@ -174,7 +173,7 @@ static void demux_irqs(unsigned int irq, struct irq_desc *desc)
174 pending >>= n; 173 pending >>= n;
175 generic_handle_irq(cirq); 174 generic_handle_irq(cirq);
176 } 175 }
177 desc->chip->unmask(irq); 176 chip->irq_unmask(&desc->irq_data));
178} 177}
179 178
180extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS]; 179extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS];
@@ -219,11 +218,11 @@ void __init variant_init_irq(void)
219 i = ffs(mask); 218 i = ffs(mask);
220 cirq += i; 219 cirq += i;
221 mask >>= i; 220 mask >>= i;
222 set_irq_chip(cirq, &gpioirqs); 221 irq_set_chip(cirq, &gpioirqs);
223 set_irq_type(irq, IRQ_TYPE_LEVEL_LOW); 222 irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
224 } while (mask); 223 } while (mask);
225 set_irq_data(irq, demux_masks + n); 224 irq_set_handler_data(irq, demux_masks + n);
226 set_irq_chained_handler(irq, demux_irqs); 225 irq_set_chained_handler(irq, demux_irqs);
227 if (++n == ARRAY_SIZE(demux_masks)) 226 if (++n == ARRAY_SIZE(demux_masks))
228 break; 227 break;
229 } 228 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-22 00:09:10 -0500