diff options
author | Andrew Victor <andrew@sanpeople.com> | 2006-06-19 10:26:50 -0400 |
---|---|---|
committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-06-19 10:26:50 -0400 |
commit | 2a6f9902c6a799a9c0218b37e39b75690c3b9a70 (patch) | |
tree | ef35c9fd90421e0e667be719489422cb52c629c1 /arch | |
parent | 963151f2471d0e6475d8b2d3a005417aec1766f7 (diff) |
[ARM] 3580/1: AT91RM9200 Timer suspend/resume support
Patch from Andrew Victor
Added suspend/resume support for the AT91RM9200 timer.
Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-at91rm9200/time.c | 44 |
1 files changed, 30 insertions, 14 deletions
diff --git a/arch/arm/mach-at91rm9200/time.c b/arch/arm/mach-at91rm9200/time.c index 36798a8d532a..fc2d7d5e4637 100644 --- a/arch/arm/mach-at91rm9200/time.c +++ b/arch/arm/mach-at91rm9200/time.c | |||
@@ -90,6 +90,20 @@ static struct irqaction at91rm9200_timer_irq = { | |||
90 | .handler = at91rm9200_timer_interrupt | 90 | .handler = at91rm9200_timer_interrupt |
91 | }; | 91 | }; |
92 | 92 | ||
93 | void at91rm9200_timer_reset(void) | ||
94 | { | ||
95 | last_crtr = 0; | ||
96 | |||
97 | /* Real time counter incremented every 30.51758 microseconds */ | ||
98 | at91_sys_write(AT91_ST_RTMR, 1); | ||
99 | |||
100 | /* Set Period Interval timer */ | ||
101 | at91_sys_write(AT91_ST_PIMR, LATCH); | ||
102 | |||
103 | /* Enable Period Interval Timer interrupt */ | ||
104 | at91_sys_write(AT91_ST_IER, AT91_ST_PITS); | ||
105 | } | ||
106 | |||
93 | /* | 107 | /* |
94 | * Set up timer interrupt. | 108 | * Set up timer interrupt. |
95 | */ | 109 | */ |
@@ -99,28 +113,30 @@ void __init at91rm9200_timer_init(void) | |||
99 | at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); | 113 | at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS); |
100 | (void) at91_sys_read(AT91_ST_SR); /* Clear any pending interrupts */ | 114 | (void) at91_sys_read(AT91_ST_SR); /* Clear any pending interrupts */ |
101 | 115 | ||
102 | /* | 116 | /* Make IRQs happen for the system timer */ |
103 | * Make IRQs happen for the system timer. | ||
104 | */ | ||
105 | setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); | 117 | setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq); |
106 | 118 | ||
107 | /* Set initial alarm to 0 */ | ||
108 | at91_sys_write(AT91_ST_RTAR, 0); | ||
109 | |||
110 | /* Real time counter incremented every 30.51758 microseconds */ | ||
111 | at91_sys_write(AT91_ST_RTMR, 1); | ||
112 | |||
113 | /* Set Period Interval timer */ | ||
114 | at91_sys_write(AT91_ST_PIMR, LATCH); | ||
115 | |||
116 | /* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */ | 119 | /* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */ |
117 | tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE; | 120 | tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE; |
118 | 121 | ||
119 | /* Enable Period Interval Timer interrupt */ | 122 | /* Initialize and enable the timer interrupt */ |
120 | at91_sys_write(AT91_ST_IER, AT91_ST_PITS); | 123 | at91rm9200_timer_reset(); |
124 | } | ||
125 | |||
126 | #ifdef CONFIG_PM | ||
127 | static void at91rm9200_timer_suspend(void) | ||
128 | { | ||
129 | /* disable Period Interval Timer interrupt */ | ||
130 | at91_sys_write(AT91_ST_IDR, AT91_ST_PITS); | ||
121 | } | 131 | } |
132 | #else | ||
133 | #define at91rm9200_timer_suspend NULL | ||
134 | #endif | ||
122 | 135 | ||
123 | struct sys_timer at91rm9200_timer = { | 136 | struct sys_timer at91rm9200_timer = { |
124 | .init = at91rm9200_timer_init, | 137 | .init = at91rm9200_timer_init, |
125 | .offset = at91rm9200_gettimeoffset, | 138 | .offset = at91rm9200_gettimeoffset, |
139 | .suspend = at91rm9200_timer_suspend, | ||
140 | .resume = at91rm9200_timer_reset, | ||
126 | }; | 141 | }; |
142 | |||