x86/PCI: Clean up pci_cache_line_size

Separate out x86 cache_line_size initialisation code into its own
function (so it can be shared by Xen later in this patch series)

[ Impact: cleanup ]

Signed-off-by: Alex Nixon <alex.nixon@citrix.com>
Signed-off-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: "H. Peter Anvin" <hpa@zytor.com>
Reviewed-by: Matthew Wilcox <willy@linux.intel.com>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: x86@kernel.org

2 files changed, 11 insertions, 7 deletions

diff --git a/arch/x86/include/asm/pci_x86.h b/arch/x86/include/asm/pci_x86.h
index 49c7219826f9..704526734bef 100644
--- a/arch/x86/include/asm/pci_x86.h
+++ b/arch/x86/include/asm/pci_x86.h
@@ -47,6 +47,7 @@ enum pci_bf_sort_state {
 extern unsigned int pcibios_max_latency;
 
 void pcibios_resource_survey(void);
+void pcibios_set_cache_line_size(void);
 
 /* pci-pc.c */
 
diff --git a/arch/x86/pci/common.c b/arch/x86/pci/common.c
index a0772af64efb..f7c8a399978c 100644
--- a/arch/x86/pci/common.c
+++ b/arch/x86/pci/common.c
@@ -421,16 +421,10 @@ struct pci_bus * __devinit pcibios_scan_root(int busnum)
 
         return bus;
 }
-
-int __init pcibios_init(void)
+void __init pcibios_set_cache_line_size(void)
 {
         struct cpuinfo_x86 *c = &boot_cpu_data;
 
-        if (!raw_pci_ops) {
-                printk(KERN_WARNING "PCI: System does not support PCI\n");
-                return 0;
-        }
-
         /*
          * Set PCI cacheline size to that of the CPU if the CPU has reported it.
          * (For older CPUs that don't support cpuid, we se it to 32 bytes
@@ -445,7 +439,16 @@ int __init pcibios_init(void)
                 pci_dfl_cache_line_size = 32 >> 2;
                 printk(KERN_DEBUG "PCI: Unknown cacheline size. Setting to 32 bytes\n");
         }
+}
+
+int __init pcibios_init(void)
+{
+        if (!raw_pci_ops) {
+                printk(KERN_WARNING "PCI: System does not support PCI\n");
+                return 0;
+        }
 
+        pcibios_set_cache_line_size();
         pcibios_resource_survey();
 
         if (pci_bf_sort >= pci_force_bf)