diff options
author | Tony Lindgren <tony@atomide.com> | 2010-02-15 12:26:51 -0500 |
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committer | Tony Lindgren <tony@atomide.com> | 2010-02-15 12:26:51 -0500 |
commit | 9556175183ddf19e9a7afa449c259a0a5081fa29 (patch) | |
tree | 523efe187c98241d7575f2b4b12ce686a388c176 /arch | |
parent | be26a3df0b80307bf8f73cea535c112210151bb9 (diff) |
omap2/3: Make get_irqnr_and_base common for mach-omap2 multiboot
Make get_irqnr_and_base common for mach-omap2 multiboot
Thanks to a tip from Russell King <rmk+kernel@arm.linux.org.uk>,
this also optimizes the code for non-multiboot configurations by
using get_irqnr_preamble.
Note that this will only work currently for 24xx and 34xx.
Support for 44xx can be added later on for basic multiboot,
and similar patch should be done for mach-omap1/entry-macro.S.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/arm/mach-omap2/include/mach/entry-macro.S | 77 |
1 files changed, 57 insertions, 20 deletions
diff --git a/arch/arm/mach-omap2/include/mach/entry-macro.S b/arch/arm/mach-omap2/include/mach/entry-macro.S index c7f1720bf282..4fd6b1bdcb2b 100644 --- a/arch/arm/mach-omap2/include/mach/entry-macro.S +++ b/arch/arm/mach-omap2/include/mach/entry-macro.S | |||
@@ -17,47 +17,84 @@ | |||
17 | 17 | ||
18 | #include <plat/omap24xx.h> | 18 | #include <plat/omap24xx.h> |
19 | #include <plat/omap34xx.h> | 19 | #include <plat/omap34xx.h> |
20 | |||
21 | /* REVISIT: This should be set dynamically if CONFIG_MULTI_OMAP2 is selected */ | ||
22 | #if defined(CONFIG_ARCH_OMAP2420) || defined(CONFIG_ARCH_OMAP2430) | ||
23 | #define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) | ||
24 | #elif defined(CONFIG_ARCH_OMAP34XX) | ||
25 | #define OMAP2_VA_IC_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) | ||
26 | #endif | ||
27 | #if defined(CONFIG_ARCH_OMAP4) | ||
28 | #include <plat/omap44xx.h> | 20 | #include <plat/omap44xx.h> |
29 | #endif | ||
30 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ | ||
31 | #define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ | ||
32 | 21 | ||
33 | .macro disable_fiq | 22 | .macro disable_fiq |
34 | .endm | 23 | .endm |
35 | 24 | ||
36 | .macro get_irqnr_preamble, base, tmp | ||
37 | .endm | ||
38 | |||
39 | .macro arch_ret_to_user, tmp1, tmp2 | 25 | .macro arch_ret_to_user, tmp1, tmp2 |
40 | .endm | 26 | .endm |
41 | 27 | ||
42 | #ifndef CONFIG_ARCH_OMAP4 | 28 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
29 | |||
30 | #define OMAP2_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP24XX_IC_BASE) | ||
31 | #define OMAP3_IRQ_BASE OMAP2_L4_IO_ADDRESS(OMAP34XX_IC_BASE) | ||
32 | #define INTCPS_SIR_IRQ_OFFSET 0x0040 /* Active interrupt offset */ | ||
33 | #define ACTIVEIRQ_MASK 0x7f /* Active interrupt bits */ | ||
34 | |||
35 | .pushsection .data | ||
36 | omap_irq_base: .word 0 | ||
37 | .popsection | ||
38 | |||
39 | #if defined(CONFIG_ARCH_OMAP2) && defined(CONFIG_ARCH_OMAP3) | ||
40 | /* Configure the interrupt base on the first interrupt */ | ||
41 | .macro get_irqnr_preamble, base, tmp | ||
42 | 9: | ||
43 | ldr \base, =omap_irq_base @ irq base address | ||
44 | ldr \base, [\base, #0] @ irq base value | ||
45 | cmp \base, #0 @ already configured? | ||
46 | bne 9998f @ nothing to do | ||
47 | |||
48 | mrc p15, 0, \tmp, c0, c0, 0 @ get processor revision | ||
49 | and \tmp, \tmp, #0x000f0000 @ only check architecture | ||
50 | cmp \tmp, #0x00060000 @ is v6? | ||
51 | beq 2400f @ found v6 so it's omap24xx | ||
52 | cmp \tmp, #0x000f0000 @ is cortex? | ||
53 | beq 3400f @ found v7 so it's omap34xx | ||
54 | 2400: ldr \base, =OMAP2_IRQ_BASE | ||
55 | ldr \tmp, =omap_irq_base | ||
56 | str \base, [\tmp, #0] | ||
57 | b 9b | ||
58 | 3400: ldr \base, =OMAP3_IRQ_BASE | ||
59 | ldr \tmp, =omap_irq_base | ||
60 | str \base, [\tmp, #0] | ||
61 | b 9b | ||
62 | 9998: | ||
63 | .endm | ||
64 | #else | ||
65 | .macro get_irqnr_preamble, base, tmp | ||
66 | #ifdef CONFIG_ARCH_OMAP2 | ||
67 | ldr \base, =OMAP2_IRQ_BASE | ||
68 | #else | ||
69 | ldr \base, =OMAP3_IRQ_BASE | ||
70 | #endif | ||
71 | .endm | ||
72 | #endif | ||
73 | /* Check the pending interrupts. Note that base already set */ | ||
43 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | 74 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
44 | ldr \base, =OMAP2_VA_IC_BASE | ||
45 | ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ | 75 | ldr \irqnr, [\base, #0x98] /* IRQ pending reg 1 */ |
46 | cmp \irqnr, #0x0 | 76 | cmp \irqnr, #0x0 |
47 | bne 2222f | 77 | bne 9999f |
48 | ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ | 78 | ldr \irqnr, [\base, #0xb8] /* IRQ pending reg 2 */ |
49 | cmp \irqnr, #0x0 | 79 | cmp \irqnr, #0x0 |
50 | bne 2222f | 80 | bne 9999f |
51 | ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ | 81 | ldr \irqnr, [\base, #0xd8] /* IRQ pending reg 3 */ |
52 | cmp \irqnr, #0x0 | 82 | cmp \irqnr, #0x0 |
53 | 2222: | 83 | 9999: |
54 | ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] | 84 | ldrne \irqnr, [\base, #INTCPS_SIR_IRQ_OFFSET] |
55 | and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ | 85 | and \irqnr, \irqnr, #ACTIVEIRQ_MASK /* Clear spurious bits */ |
56 | 86 | ||
57 | .endm | 87 | .endm |
58 | #else | 88 | #endif |
89 | |||
90 | |||
91 | #ifdef CONFIG_ARCH_OMAP4 | ||
92 | |||
59 | #define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) | 93 | #define OMAP44XX_VA_GIC_CPU_BASE OMAP2_L4_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE) |
60 | 94 | ||
95 | .macro get_irqnr_preamble, base, tmp | ||
96 | .endm | ||
97 | |||
61 | /* | 98 | /* |
62 | * The interrupt numbering scheme is defined in the | 99 | * The interrupt numbering scheme is defined in the |
63 | * interrupt controller spec. To wit: | 100 | * interrupt controller spec. To wit: |