diff options
author | Maciej W. Rozycki <macro@linux-mips.org> | 2005-02-01 18:02:12 -0500 |
---|---|---|
committer | Ralf Baechle <ralf@linux-mips.org> | 2005-10-29 14:30:21 -0400 |
commit | 304429915dad26ccf212d63ea1f18be36e3188e2 (patch) | |
tree | f9f2637dee4d1480356c8fb41f5b6515093043b0 /arch | |
parent | 6b123979543a37d109b74a359b147b38ee8166dd (diff) |
Formatting fixes.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
-rw-r--r-- | arch/mips/mm/tlb-r4k.c | 19 |
1 files changed, 10 insertions, 9 deletions
diff --git a/arch/mips/mm/tlb-r4k.c b/arch/mips/mm/tlb-r4k.c index 59d38bc05b69..09249a756016 100644 --- a/arch/mips/mm/tlb-r4k.c +++ b/arch/mips/mm/tlb-r4k.c | |||
@@ -100,7 +100,7 @@ void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, | |||
100 | continue; | 100 | continue; |
101 | /* Make sure all entries differ. */ | 101 | /* Make sure all entries differ. */ |
102 | write_c0_entryhi(CKSEG0 + | 102 | write_c0_entryhi(CKSEG0 + |
103 | (idx << (PAGE_SHIFT + 1))); | 103 | (idx << (PAGE_SHIFT + 1))); |
104 | mtc0_tlbw_hazard(); | 104 | mtc0_tlbw_hazard(); |
105 | tlb_write_indexed(); | 105 | tlb_write_indexed(); |
106 | } | 106 | } |
@@ -250,13 +250,13 @@ void __update_tlb(struct vm_area_struct * vma, unsigned long address, pte_t pte) | |||
250 | idx = read_c0_index(); | 250 | idx = read_c0_index(); |
251 | ptep = pte_offset_map(pmdp, address); | 251 | ptep = pte_offset_map(pmdp, address); |
252 | 252 | ||
253 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) | 253 | #if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) |
254 | write_c0_entrylo0(ptep->pte_high); | 254 | write_c0_entrylo0(ptep->pte_high); |
255 | ptep++; | 255 | ptep++; |
256 | write_c0_entrylo1(ptep->pte_high); | 256 | write_c0_entrylo1(ptep->pte_high); |
257 | #else | 257 | #else |
258 | write_c0_entrylo0(pte_val(*ptep++) >> 6); | 258 | write_c0_entrylo0(pte_val(*ptep++) >> 6); |
259 | write_c0_entrylo1(pte_val(*ptep) >> 6); | 259 | write_c0_entrylo1(pte_val(*ptep) >> 6); |
260 | #endif | 260 | #endif |
261 | write_c0_entryhi(address | pid); | 261 | write_c0_entryhi(address | pid); |
262 | mtc0_tlbw_hazard(); | 262 | mtc0_tlbw_hazard(); |
@@ -357,7 +357,8 @@ __init int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, | |||
357 | old_pagemask = read_c0_pagemask(); | 357 | old_pagemask = read_c0_pagemask(); |
358 | wired = read_c0_wired(); | 358 | wired = read_c0_wired(); |
359 | if (--temp_tlb_entry < wired) { | 359 | if (--temp_tlb_entry < wired) { |
360 | printk(KERN_WARNING "No TLB space left for add_temporary_entry\n"); | 360 | printk(KERN_WARNING |
361 | "No TLB space left for add_temporary_entry\n"); | ||
361 | ret = -ENOSPC; | 362 | ret = -ENOSPC; |
362 | goto out; | 363 | goto out; |
363 | } | 364 | } |
@@ -388,7 +389,7 @@ static void __init probe_tlb(unsigned long config) | |||
388 | * is not supported, we assume R4k style. Cpu probing already figured | 389 | * is not supported, we assume R4k style. Cpu probing already figured |
389 | * out the number of tlb entries. | 390 | * out the number of tlb entries. |
390 | */ | 391 | */ |
391 | if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY) | 392 | if ((c->processor_id & 0xff0000) == PRID_COMP_LEGACY) |
392 | return; | 393 | return; |
393 | 394 | ||
394 | reg = read_c0_config1(); | 395 | reg = read_c0_config1(); |