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authorTony Lindgren <tony@atomide.com>2008-01-25 03:42:48 -0500
committerTony Lindgren <tony@atomide.com>2008-04-14 12:57:11 -0400
commit225dfda1d676b70acf1e696ace68c23297926ce0 (patch)
tree4390425ac95cb0f4c62a2e042296df9e0b8c4eb6 /arch
parent7d7f665d5dac8d19f2fcb56baea09c59a3f861be (diff)
ARM: OMAP: Split omap_cfg_reg() into omap processor specific functions
Use omap processor specific function depending on system type. Based on an earlier patch by Klaus Pedersen <klaus.k.pedersen@nokia.com>. Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch')
-rw-r--r--arch/arm/mach-omap1/mux.c103
-rw-r--r--arch/arm/mach-omap2/mux.c31
-rw-r--r--arch/arm/plat-omap/mux.c142
3 files changed, 139 insertions, 137 deletions
diff --git a/arch/arm/mach-omap1/mux.c b/arch/arm/mach-omap1/mux.c
index d74f6798d081..cf3bdc00cfdb 100644
--- a/arch/arm/mach-omap1/mux.c
+++ b/arch/arm/mach-omap1/mux.c
@@ -314,7 +314,110 @@ MUX_CFG("Y14_1610_CCP_DATAM", 9, 21, 6, 2, 3, 1, 2, 0, 0)
314 314
315int __init_or_module omap1_cfg_reg(const struct pin_config *cfg) 315int __init_or_module omap1_cfg_reg(const struct pin_config *cfg)
316{ 316{
317 static DEFINE_SPINLOCK(mux_spin_lock);
318 unsigned long flags;
319 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
320 pull_orig = 0, pull = 0;
321 unsigned int mask, warn = 0;
322
323 /* Check the mux register in question */
324 if (cfg->mux_reg) {
325 unsigned tmp1, tmp2;
326
327 spin_lock_irqsave(&mux_spin_lock, flags);
328 reg_orig = omap_readl(cfg->mux_reg);
329
330 /* The mux registers always seem to be 3 bits long */
331 mask = (0x7 << cfg->mask_offset);
332 tmp1 = reg_orig & mask;
333 reg = reg_orig & ~mask;
334
335 tmp2 = (cfg->mask << cfg->mask_offset);
336 reg |= tmp2;
337
338 if (tmp1 != tmp2)
339 warn = 1;
340
341 omap_writel(reg, cfg->mux_reg);
342 spin_unlock_irqrestore(&mux_spin_lock, flags);
343 }
344
345 /* Check for pull up or pull down selection on 1610 */
346 if (!cpu_is_omap15xx()) {
347 if (cfg->pu_pd_reg && cfg->pull_val) {
348 spin_lock_irqsave(&mux_spin_lock, flags);
349 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
350 mask = 1 << cfg->pull_bit;
351
352 if (cfg->pu_pd_val) {
353 if (!(pu_pd_orig & mask))
354 warn = 1;
355 /* Use pull up */
356 pu_pd = pu_pd_orig | mask;
357 } else {
358 if (pu_pd_orig & mask)
359 warn = 1;
360 /* Use pull down */
361 pu_pd = pu_pd_orig & ~mask;
362 }
363 omap_writel(pu_pd, cfg->pu_pd_reg);
364 spin_unlock_irqrestore(&mux_spin_lock, flags);
365 }
366 }
367
368 /* Check for an associated pull down register */
369 if (cfg->pull_reg) {
370 spin_lock_irqsave(&mux_spin_lock, flags);
371 pull_orig = omap_readl(cfg->pull_reg);
372 mask = 1 << cfg->pull_bit;
373
374 if (cfg->pull_val) {
375 if (pull_orig & mask)
376 warn = 1;
377 /* Low bit = pull enabled */
378 pull = pull_orig & ~mask;
379 } else {
380 if (!(pull_orig & mask))
381 warn = 1;
382 /* High bit = pull disabled */
383 pull = pull_orig | mask;
384 }
385
386 omap_writel(pull, cfg->pull_reg);
387 spin_unlock_irqrestore(&mux_spin_lock, flags);
388 }
389
390 if (warn) {
391#ifdef CONFIG_OMAP_MUX_WARNINGS
392 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
393#endif
394 }
395
396#ifdef CONFIG_OMAP_MUX_DEBUG
397 if (cfg->debug || warn) {
398 printk("MUX: Setting register %s\n", cfg->name);
399 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
400 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
401
402 if (!cpu_is_omap15xx()) {
403 if (cfg->pu_pd_reg && cfg->pull_val) {
404 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
405 cfg->pu_pd_name, cfg->pu_pd_reg,
406 pu_pd_orig, pu_pd);
407 }
408 }
409
410 if (cfg->pull_reg)
411 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
412 cfg->pull_name, cfg->pull_reg, pull_orig, pull);
413 }
414#endif
415
416#ifdef CONFIG_OMAP_MUX_ERRORS
417 return warn ? -ETXTBSY : 0;
418#else
317 return 0; 419 return 0;
420#endif
318} 421}
319 422
320int __init omap1_mux_init(void) 423int __init omap1_mux_init(void)
diff --git a/arch/arm/mach-omap2/mux.c b/arch/arm/mach-omap2/mux.c
index 351baab0503a..71cff46a8b71 100644
--- a/arch/arm/mach-omap2/mux.c
+++ b/arch/arm/mach-omap2/mux.c
@@ -172,8 +172,39 @@ MUX_CFG_24XX("B13_24XX_KBC6", 0x110, 3, 0, 0, 1)
172}; 172};
173 173
174#ifdef CONFIG_ARCH_OMAP24XX 174#ifdef CONFIG_ARCH_OMAP24XX
175
176#define OMAP24XX_L4_BASE 0x48000000
177#define OMAP24XX_PULL_ENA (1 << 3)
178#define OMAP24XX_PULL_UP (1 << 4)
179
180/* REVISIT: Convert this code to use ctrl_{read,write}_reg */
175int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg) 181int __init_or_module omap24xx_cfg_reg(const struct pin_config *cfg)
176{ 182{
183 u8 reg = 0;
184 unsigned int warn = 0;
185
186 reg |= cfg->mask & 0x7;
187 if (cfg->pull_val)
188 reg |= OMAP24XX_PULL_ENA;
189 if(cfg->pu_pd_val)
190 reg |= OMAP24XX_PULL_UP;
191#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
192 {
193 u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
194 u8 debug = 0;
195
196#ifdef CONFIG_OMAP_MUX_DEBUG
197 debug = cfg->debug;
198#endif
199 warn = (orig != reg);
200 if (debug || warn)
201 printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
202 cfg->name, OMAP24XX_L4_BASE + cfg->mux_reg,
203 orig, reg);
204 }
205#endif
206 omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
207
177 return 0; 208 return 0;
178} 209}
179#endif 210#endif
diff --git a/arch/arm/plat-omap/mux.c b/arch/arm/plat-omap/mux.c
index d881379111e1..4de18b9ffb16 100644
--- a/arch/arm/plat-omap/mux.c
+++ b/arch/arm/plat-omap/mux.c
@@ -32,10 +32,6 @@
32 32
33#ifdef CONFIG_OMAP_MUX 33#ifdef CONFIG_OMAP_MUX
34 34
35#define OMAP24XX_L4_BASE 0x48000000
36#define OMAP24XX_PULL_ENA (1 << 3)
37#define OMAP24XX_PULL_UP (1 << 4)
38
39static struct omap_mux_cfg *mux_cfg; 35static struct omap_mux_cfg *mux_cfg;
40 36
41int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg) 37int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
@@ -56,13 +52,7 @@ int __init omap_mux_register(struct omap_mux_cfg *arch_mux_cfg)
56 */ 52 */
57int __init_or_module omap_cfg_reg(const unsigned long index) 53int __init_or_module omap_cfg_reg(const unsigned long index)
58{ 54{
59 static DEFINE_SPINLOCK(mux_spin_lock); 55 struct pin_config *reg;
60
61 unsigned long flags;
62 struct pin_config *cfg;
63 unsigned int reg_orig = 0, reg = 0, pu_pd_orig = 0, pu_pd = 0,
64 pull_orig = 0, pull = 0;
65 unsigned int mask, warn = 0;
66 56
67 if (mux_cfg == NULL) { 57 if (mux_cfg == NULL) {
68 printk(KERN_ERR "Pin mux table not initialized\n"); 58 printk(KERN_ERR "Pin mux table not initialized\n");
@@ -76,134 +66,12 @@ int __init_or_module omap_cfg_reg(const unsigned long index)
76 return -ENODEV; 66 return -ENODEV;
77 } 67 }
78 68
79 cfg = (struct pin_config *)&mux_cfg->pins[index]; 69 reg = (struct pin_config *)&mux_cfg->pins[index];
80 if (cpu_is_omap24xx()) {
81 u8 reg = 0;
82
83 reg |= cfg->mask & 0x7;
84 if (cfg->pull_val)
85 reg |= OMAP24XX_PULL_ENA;
86 if(cfg->pu_pd_val)
87 reg |= OMAP24XX_PULL_UP;
88#if defined(CONFIG_OMAP_MUX_DEBUG) || defined(CONFIG_OMAP_MUX_WARNINGS)
89 {
90 u8 orig = omap_readb(OMAP24XX_L4_BASE + cfg->mux_reg);
91 u8 debug = 0;
92
93#ifdef CONFIG_OMAP_MUX_DEBUG
94 debug = cfg->debug;
95#endif
96 warn = (orig != reg);
97 if (debug || warn)
98 printk("MUX: setup %s (0x%08x): 0x%02x -> 0x%02x\n",
99 cfg->name,
100 OMAP24XX_L4_BASE + cfg->mux_reg,
101 orig, reg);
102 }
103#endif
104 omap_writeb(reg, OMAP24XX_L4_BASE + cfg->mux_reg);
105
106 return 0;
107 }
108
109 /* Check the mux register in question */
110 if (cfg->mux_reg) {
111 unsigned tmp1, tmp2;
112
113 spin_lock_irqsave(&mux_spin_lock, flags);
114 reg_orig = omap_readl(cfg->mux_reg);
115
116 /* The mux registers always seem to be 3 bits long */
117 mask = (0x7 << cfg->mask_offset);
118 tmp1 = reg_orig & mask;
119 reg = reg_orig & ~mask;
120
121 tmp2 = (cfg->mask << cfg->mask_offset);
122 reg |= tmp2;
123
124 if (tmp1 != tmp2)
125 warn = 1;
126
127 omap_writel(reg, cfg->mux_reg);
128 spin_unlock_irqrestore(&mux_spin_lock, flags);
129 }
130
131 /* Check for pull up or pull down selection on 1610 */
132 if (!cpu_is_omap15xx()) {
133 if (cfg->pu_pd_reg && cfg->pull_val) {
134 spin_lock_irqsave(&mux_spin_lock, flags);
135 pu_pd_orig = omap_readl(cfg->pu_pd_reg);
136 mask = 1 << cfg->pull_bit;
137 70
138 if (cfg->pu_pd_val) { 71 if (!mux_cfg->cfg_reg)
139 if (!(pu_pd_orig & mask)) 72 return -ENODEV;
140 warn = 1;
141 /* Use pull up */
142 pu_pd = pu_pd_orig | mask;
143 } else {
144 if (pu_pd_orig & mask)
145 warn = 1;
146 /* Use pull down */
147 pu_pd = pu_pd_orig & ~mask;
148 }
149 omap_writel(pu_pd, cfg->pu_pd_reg);
150 spin_unlock_irqrestore(&mux_spin_lock, flags);
151 }
152 }
153
154 /* Check for an associated pull down register */
155 if (cfg->pull_reg) {
156 spin_lock_irqsave(&mux_spin_lock, flags);
157 pull_orig = omap_readl(cfg->pull_reg);
158 mask = 1 << cfg->pull_bit;
159
160 if (cfg->pull_val) {
161 if (pull_orig & mask)
162 warn = 1;
163 /* Low bit = pull enabled */
164 pull = pull_orig & ~mask;
165 } else {
166 if (!(pull_orig & mask))
167 warn = 1;
168 /* High bit = pull disabled */
169 pull = pull_orig | mask;
170 }
171
172 omap_writel(pull, cfg->pull_reg);
173 spin_unlock_irqrestore(&mux_spin_lock, flags);
174 }
175
176 if (warn) {
177#ifdef CONFIG_OMAP_MUX_WARNINGS
178 printk(KERN_WARNING "MUX: initialized %s\n", cfg->name);
179#endif
180 }
181
182#ifdef CONFIG_OMAP_MUX_DEBUG
183 if (cfg->debug || warn) {
184 printk("MUX: Setting register %s\n", cfg->name);
185 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
186 cfg->mux_reg_name, cfg->mux_reg, reg_orig, reg);
187
188 if (!cpu_is_omap15xx()) {
189 if (cfg->pu_pd_reg && cfg->pull_val) {
190 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
191 cfg->pu_pd_name, cfg->pu_pd_reg,
192 pu_pd_orig, pu_pd);
193 }
194 }
195
196 if (cfg->pull_reg)
197 printk(" %s (0x%08x) = 0x%08x -> 0x%08x\n",
198 cfg->pull_name, cfg->pull_reg, pull_orig, pull);
199 }
200#endif
201 73
202#ifdef CONFIG_OMAP_MUX_ERRORS 74 return mux_cfg->cfg_reg(reg);
203 return warn ? -ETXTBSY : 0;
204#else
205 return 0;
206#endif
207} 75}
208EXPORT_SYMBOL(omap_cfg_reg); 76EXPORT_SYMBOL(omap_cfg_reg);
209#else 77#else
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