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authorTejun Heo <tj@kernel.org>2011-05-24 03:59:36 -0400
committerTejun Heo <tj@kernel.org>2011-05-24 03:59:36 -0400
commit6988f20fe04e9ef3aea488cb8ab57fbeb78e12f0 (patch)
treec9d7fc50a2e2147a5ca07e3096e7eeb916ad2da9 /arch/xtensa
parent0415b00d175e0d8945e6785aad21b5f157976ce0 (diff)
parent6ea0c34dac89611126455537552cffe6c7e832ad (diff)
Merge branch 'fixes-2.6.39' into for-2.6.40
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/Kconfig6
-rw-r--r--arch/xtensa/kernel/irq.c106
-rw-r--r--arch/xtensa/platforms/s6105/device.c2
-rw-r--r--arch/xtensa/variants/s6000/gpio.c45
4 files changed, 61 insertions, 98 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 72839190f503..1d730b5579a0 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -7,6 +7,9 @@ config ZONE_DMA
7config XTENSA 7config XTENSA
8 def_bool y 8 def_bool y
9 select HAVE_IDE 9 select HAVE_IDE
10 select HAVE_GENERIC_HARDIRQS
11 select GENERIC_IRQ_SHOW
12 select GENERIC_HARDIRQS_NO_DEPRECATED
10 help 13 help
11 Xtensa processors are 32-bit RISC machines designed by Tensilica 14 Xtensa processors are 32-bit RISC machines designed by Tensilica
12 primarily for embedded systems. These processors are both 15 primarily for embedded systems. These processors are both
@@ -27,9 +30,6 @@ config GENERIC_FIND_BIT_LE
27config GENERIC_HWEIGHT 30config GENERIC_HWEIGHT
28 def_bool y 31 def_bool y
29 32
30config GENERIC_HARDIRQS
31 def_bool y
32
33config GENERIC_GPIO 33config GENERIC_GPIO
34 def_bool y 34 def_bool y
35 35
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c
index 87508886cbbd..d77089df412e 100644
--- a/arch/xtensa/kernel/irq.c
+++ b/arch/xtensa/kernel/irq.c
@@ -35,7 +35,6 @@ atomic_t irq_err_count;
35asmlinkage void do_IRQ(int irq, struct pt_regs *regs) 35asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
36{ 36{
37 struct pt_regs *old_regs = set_irq_regs(regs); 37 struct pt_regs *old_regs = set_irq_regs(regs);
38 struct irq_desc *desc = irq_desc + irq;
39 38
40 if (irq >= NR_IRQS) { 39 if (irq >= NR_IRQS) {
41 printk(KERN_EMERG "%s: cannot handle IRQ %d\n", 40 printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
@@ -57,104 +56,69 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
57 sp - sizeof(struct thread_info)); 56 sp - sizeof(struct thread_info));
58 } 57 }
59#endif 58#endif
60 desc->handle_irq(irq, desc); 59 generic_handle_irq(irq);
61 60
62 irq_exit(); 61 irq_exit();
63 set_irq_regs(old_regs); 62 set_irq_regs(old_regs);
64} 63}
65 64
66/* 65int arch_show_interrupts(struct seq_file *p, int prec)
67 * Generic, controller-independent functions:
68 */
69
70int show_interrupts(struct seq_file *p, void *v)
71{ 66{
72 int i = *(loff_t *) v, j; 67 int j;
73 struct irqaction * action; 68
74 unsigned long flags; 69 seq_printf(p, "%*s: ", prec, "NMI");
75 70 for_each_online_cpu(j)
76 if (i == 0) { 71 seq_printf(p, "%10u ", nmi_count(j));
77 seq_printf(p, " "); 72 seq_putc(p, '\n');
78 for_each_online_cpu(j) 73 seq_printf(p, "%*s: ", prec, "ERR");
79 seq_printf(p, "CPU%d ",j); 74 seq_printf(p, "%10u\n", atomic_read(&irq_err_count));
80 seq_putc(p, '\n');
81 }
82
83 if (i < NR_IRQS) {
84 raw_spin_lock_irqsave(&irq_desc[i].lock, flags);
85 action = irq_desc[i].action;
86 if (!action)
87 goto skip;
88 seq_printf(p, "%3d: ",i);
89#ifndef CONFIG_SMP
90 seq_printf(p, "%10u ", kstat_irqs(i));
91#else
92 for_each_online_cpu(j)
93 seq_printf(p, "%10u ", kstat_irqs_cpu(i, j));
94#endif
95 seq_printf(p, " %14s", irq_desc[i].chip->name);
96 seq_printf(p, " %s", action->name);
97
98 for (action=action->next; action; action = action->next)
99 seq_printf(p, ", %s", action->name);
100
101 seq_putc(p, '\n');
102skip:
103 raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags);
104 } else if (i == NR_IRQS) {
105 seq_printf(p, "NMI: ");
106 for_each_online_cpu(j)
107 seq_printf(p, "%10u ", nmi_count(j));
108 seq_putc(p, '\n');
109 seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count));
110 }
111 return 0; 75 return 0;
112} 76}
113 77
114static void xtensa_irq_mask(unsigned int irq) 78static void xtensa_irq_mask(struct irq_chip *d)
115{ 79{
116 cached_irq_mask &= ~(1 << irq); 80 cached_irq_mask &= ~(1 << d->irq);
117 set_sr (cached_irq_mask, INTENABLE); 81 set_sr (cached_irq_mask, INTENABLE);
118} 82}
119 83
120static void xtensa_irq_unmask(unsigned int irq) 84static void xtensa_irq_unmask(struct irq_chip *d)
121{ 85{
122 cached_irq_mask |= 1 << irq; 86 cached_irq_mask |= 1 << d->irq;
123 set_sr (cached_irq_mask, INTENABLE); 87 set_sr (cached_irq_mask, INTENABLE);
124} 88}
125 89
126static void xtensa_irq_enable(unsigned int irq) 90static void xtensa_irq_enable(struct irq_chip *d)
127{ 91{
128 variant_irq_enable(irq); 92 variant_irq_enable(d->irq);
129 xtensa_irq_unmask(irq); 93 xtensa_irq_unmask(d->irq);
130} 94}
131 95
132static void xtensa_irq_disable(unsigned int irq) 96static void xtensa_irq_disable(struct irq_chip *d)
133{ 97{
134 xtensa_irq_mask(irq); 98 xtensa_irq_mask(d->irq);
135 variant_irq_disable(irq); 99 variant_irq_disable(d->irq);
136} 100}
137 101
138static void xtensa_irq_ack(unsigned int irq) 102static void xtensa_irq_ack(struct irq_chip *d)
139{ 103{
140 set_sr(1 << irq, INTCLEAR); 104 set_sr(1 << d->irq, INTCLEAR);
141} 105}
142 106
143static int xtensa_irq_retrigger(unsigned int irq) 107static int xtensa_irq_retrigger(struct irq_chip *d)
144{ 108{
145 set_sr (1 << irq, INTSET); 109 set_sr (1 << d->irq, INTSET);
146 return 1; 110 return 1;
147} 111}
148 112
149 113
150static struct irq_chip xtensa_irq_chip = { 114static struct irq_chip xtensa_irq_chip = {
151 .name = "xtensa", 115 .name = "xtensa",
152 .enable = xtensa_irq_enable, 116 .irq_enable = xtensa_irq_enable,
153 .disable = xtensa_irq_disable, 117 .irq_disable = xtensa_irq_disable,
154 .mask = xtensa_irq_mask, 118 .irq_mask = xtensa_irq_mask,
155 .unmask = xtensa_irq_unmask, 119 .irq_unmask = xtensa_irq_unmask,
156 .ack = xtensa_irq_ack, 120 .irq_ack = xtensa_irq_ack,
157 .retrigger = xtensa_irq_retrigger, 121 .irq_retrigger = xtensa_irq_retrigger,
158}; 122};
159 123
160void __init init_IRQ(void) 124void __init init_IRQ(void)
@@ -165,25 +129,25 @@ void __init init_IRQ(void)
165 int mask = 1 << index; 129 int mask = 1 << index;
166 130
167 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) 131 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
168 set_irq_chip_and_handler(index, &xtensa_irq_chip, 132 irq_set_chip_and_handler(index, &xtensa_irq_chip,
169 handle_simple_irq); 133 handle_simple_irq);
170 134
171 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) 135 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
172 set_irq_chip_and_handler(index, &xtensa_irq_chip, 136 irq_set_chip_and_handler(index, &xtensa_irq_chip,
173 handle_edge_irq); 137 handle_edge_irq);
174 138
175 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) 139 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
176 set_irq_chip_and_handler(index, &xtensa_irq_chip, 140 irq_set_chip_and_handler(index, &xtensa_irq_chip,
177 handle_level_irq); 141 handle_level_irq);
178 142
179 else if (mask & XCHAL_INTTYPE_MASK_TIMER) 143 else if (mask & XCHAL_INTTYPE_MASK_TIMER)
180 set_irq_chip_and_handler(index, &xtensa_irq_chip, 144 irq_set_chip_and_handler(index, &xtensa_irq_chip,
181 handle_edge_irq); 145 handle_edge_irq);
182 146
183 else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */ 147 else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
184 /* XCHAL_INTTYPE_MASK_NMI */ 148 /* XCHAL_INTTYPE_MASK_NMI */
185 149
186 set_irq_chip_and_handler(index, &xtensa_irq_chip, 150 irq_set_chip_and_handler(index, &xtensa_irq_chip,
187 handle_level_irq); 151 handle_level_irq);
188 } 152 }
189 153
diff --git a/arch/xtensa/platforms/s6105/device.c b/arch/xtensa/platforms/s6105/device.c
index 65333ffefb07..4f4fc971042f 100644
--- a/arch/xtensa/platforms/s6105/device.c
+++ b/arch/xtensa/platforms/s6105/device.c
@@ -120,7 +120,7 @@ static int __init prepare_phy_irq(int pin)
120 irq = gpio_to_irq(pin); 120 irq = gpio_to_irq(pin);
121 if (irq < 0) 121 if (irq < 0)
122 goto free; 122 goto free;
123 if (set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0) 123 if (irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0)
124 goto free; 124 goto free;
125 return irq; 125 return irq;
126free: 126free:
diff --git a/arch/xtensa/variants/s6000/gpio.c b/arch/xtensa/variants/s6000/gpio.c
index 380a70fff756..7af0757e001b 100644
--- a/arch/xtensa/variants/s6000/gpio.c
+++ b/arch/xtensa/variants/s6000/gpio.c
@@ -85,30 +85,29 @@ int s6_gpio_init(u32 afsel)
85 return gpiochip_add(&gpiochip); 85 return gpiochip_add(&gpiochip);
86} 86}
87 87
88static void ack(unsigned int irq) 88static void ack(struct irq_data *d)
89{ 89{
90 writeb(1 << (irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC); 90 writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
91} 91}
92 92
93static void mask(unsigned int irq) 93static void mask(struct irq_data *d)
94{ 94{
95 u8 r = readb(S6_REG_GPIO + S6_GPIO_IE); 95 u8 r = readb(S6_REG_GPIO + S6_GPIO_IE);
96 r &= ~(1 << (irq - IRQ_BASE)); 96 r &= ~(1 << (d->irq - IRQ_BASE));
97 writeb(r, S6_REG_GPIO + S6_GPIO_IE); 97 writeb(r, S6_REG_GPIO + S6_GPIO_IE);
98} 98}
99 99
100static void unmask(unsigned int irq) 100static void unmask(struct irq_data *d)
101{ 101{
102 u8 m = readb(S6_REG_GPIO + S6_GPIO_IE); 102 u8 m = readb(S6_REG_GPIO + S6_GPIO_IE);
103 m |= 1 << (irq - IRQ_BASE); 103 m |= 1 << (d->irq - IRQ_BASE);
104 writeb(m, S6_REG_GPIO + S6_GPIO_IE); 104 writeb(m, S6_REG_GPIO + S6_GPIO_IE);
105} 105}
106 106
107static int set_type(unsigned int irq, unsigned int type) 107static int set_type(struct irq_data *d, unsigned int type)
108{ 108{
109 const u8 m = 1 << (irq - IRQ_BASE); 109 const u8 m = 1 << (d->irq - IRQ_BASE);
110 irq_flow_handler_t handler; 110 irq_flow_handler_t handler;
111 struct irq_desc *desc;
112 u8 reg; 111 u8 reg;
113 112
114 if (type == IRQ_TYPE_PROBE) { 113 if (type == IRQ_TYPE_PROBE) {
@@ -129,8 +128,7 @@ static int set_type(unsigned int irq, unsigned int type)
129 handler = handle_edge_irq; 128 handler = handle_edge_irq;
130 } 129 }
131 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS); 130 writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
132 desc = irq_to_desc(irq); 131 __irq_set_handler_locked(irq, handler);
133 desc->handle_irq = handler;
134 132
135 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV); 133 reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
136 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING)) 134 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING))
@@ -150,22 +148,23 @@ static int set_type(unsigned int irq, unsigned int type)
150 148
151static struct irq_chip gpioirqs = { 149static struct irq_chip gpioirqs = {
152 .name = "GPIO", 150 .name = "GPIO",
153 .ack = ack, 151 .irq_ack = ack,
154 .mask = mask, 152 .irq_mask = mask,
155 .unmask = unmask, 153 .irq_unmask = unmask,
156 .set_type = set_type, 154 .irq_set_type = set_type,
157}; 155};
158 156
159static u8 demux_masks[4]; 157static u8 demux_masks[4];
160 158
161static void demux_irqs(unsigned int irq, struct irq_desc *desc) 159static void demux_irqs(unsigned int irq, struct irq_desc *desc)
162{ 160{
163 u8 *mask = get_irq_desc_data(desc); 161 struct irq_chip *chip = irq_desc_get_chip(desc);
162 u8 *mask = irq_desc_get_handler_data(desc);
164 u8 pending; 163 u8 pending;
165 int cirq; 164 int cirq;
166 165
167 desc->chip->mask(irq); 166 chip->irq_mask(&desc->irq_data);
168 desc->chip->ack(irq); 167 chip->irq_ack(&desc->irq_data));
169 pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask; 168 pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask;
170 cirq = IRQ_BASE - 1; 169 cirq = IRQ_BASE - 1;
171 while (pending) { 170 while (pending) {
@@ -174,7 +173,7 @@ static void demux_irqs(unsigned int irq, struct irq_desc *desc)
174 pending >>= n; 173 pending >>= n;
175 generic_handle_irq(cirq); 174 generic_handle_irq(cirq);
176 } 175 }
177 desc->chip->unmask(irq); 176 chip->irq_unmask(&desc->irq_data));
178} 177}
179 178
180extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS]; 179extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS];
@@ -219,11 +218,11 @@ void __init variant_init_irq(void)
219 i = ffs(mask); 218 i = ffs(mask);
220 cirq += i; 219 cirq += i;
221 mask >>= i; 220 mask >>= i;
222 set_irq_chip(cirq, &gpioirqs); 221 irq_set_chip(cirq, &gpioirqs);
223 set_irq_type(irq, IRQ_TYPE_LEVEL_LOW); 222 irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
224 } while (mask); 223 } while (mask);
225 set_irq_data(irq, demux_masks + n); 224 irq_set_handler_data(irq, demux_masks + n);
226 set_irq_chained_handler(irq, demux_irqs); 225 irq_set_chained_handler(irq, demux_irqs);
227 if (++n == ARRAY_SIZE(demux_masks)) 226 if (++n == ARRAY_SIZE(demux_masks))
228 break; 227 break;
229 } 228 }