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authorJohannes Weiner <jw@emlix.com>2009-03-04 10:21:32 -0500
committerChris Zankel <chris@zankel.net>2009-04-03 02:43:16 -0400
commiteff35af9c0c83a24376a67ff88c65679c25c7a51 (patch)
treebbda29e090be680550cf4779c63499e1f8ecea73 /arch/xtensa
parent4c0d214144bcedc0b3582c88d6313055949755b5 (diff)
xtensa: s6000 variant core definitions
S6000 core configuration files from Tensilica. Signed-off-by: Johannes Weiner <jw@emlix.com> Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/variants/s6000/include/variant/core.h431
-rw-r--r--arch/xtensa/variants/s6000/include/variant/tie-asm.h304
-rw-r--r--arch/xtensa/variants/s6000/include/variant/tie.h191
3 files changed, 926 insertions, 0 deletions
diff --git a/arch/xtensa/variants/s6000/include/variant/core.h b/arch/xtensa/variants/s6000/include/variant/core.h
new file mode 100644
index 000000000000..af007953027e
--- /dev/null
+++ b/arch/xtensa/variants/s6000/include/variant/core.h
@@ -0,0 +1,431 @@
1/*
2 * Xtensa processor core configuration information.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (c) 1999-2008 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CORE_CONFIGURATION_H
12#define _XTENSA_CORE_CONFIGURATION_H
13
14
15/****************************************************************************
16 Parameters Useful for Any Code, USER or PRIVILEGED
17 ****************************************************************************/
18
19/*
20 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
21 * configured, and a value of 0 otherwise. These macros are always defined.
22 */
23
24
25/*----------------------------------------------------------------------
26 ISA
27 ----------------------------------------------------------------------*/
28
29#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
30#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
31#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
32#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
33#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
34#define XCHAL_HAVE_DEBUG 1 /* debug option */
35#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
37#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
38#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
39#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
40#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
41#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
42#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
43#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
44#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
45#define XCHAL_HAVE_L32R 1 /* L32R instruction */
46#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
47#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
48#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
49#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
50#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
51#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
52#define XCHAL_HAVE_ABS 1 /* ABS instruction */
53/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
54/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
55#define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */
56#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */
57#define XCHAL_HAVE_SPECULATION 0 /* speculation */
58#define XCHAL_HAVE_FULL_RESET 0 /* all regs/state reset */
59#define XCHAL_NUM_CONTEXTS 1 /* */
60#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
61#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
62#define XCHAL_HAVE_PRID 0 /* processor ID register */
63#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
64#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
65#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
66#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
67#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
68#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
69#define XCHAL_HAVE_FP 1 /* floating point pkg */
70#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
71#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
72#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
73
74
75/*----------------------------------------------------------------------
76 MISC
77 ----------------------------------------------------------------------*/
78
79#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
80#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
81#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
82/* In T1050, applies to selected core load and store instructions (see ISA): */
83#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
84#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
85
86#define XCHAL_SW_VERSION 701001 /* sw version of this header */
87
88#define XCHAL_CORE_ID "stretch_bali" /* alphanum core name
89 (CoreID) set in the Xtensa
90 Processor Generator */
91
92#define XCHAL_BUILD_UNIQUE_ID 0x000104B9 /* 22-bit sw build ID */
93
94/*
95 * These definitions describe the hardware targeted by this software.
96 */
97#define XCHAL_HW_CONFIGID0 0xC2F3F9FE /* ConfigID hi 32 bits*/
98#define XCHAL_HW_CONFIGID1 0x054104B9 /* ConfigID lo 32 bits*/
99#define XCHAL_HW_VERSION_NAME "LX1.0.2" /* full version name */
100#define XCHAL_HW_VERSION_MAJOR 2100 /* major ver# of targeted hw */
101#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
102#define XCHAL_HW_VERSION 210002 /* major*100+minor */
103#define XCHAL_HW_REL_LX1 1
104#define XCHAL_HW_REL_LX1_0 1
105#define XCHAL_HW_REL_LX1_0_2 1
106#define XCHAL_HW_CONFIGID_RELIABLE 1
107/* If software targets a *range* of hardware versions, these are the bounds: */
108#define XCHAL_HW_MIN_VERSION_MAJOR 2100 /* major v of earliest tgt hw */
109#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
110#define XCHAL_HW_MIN_VERSION 210002 /* earliest targeted hw */
111#define XCHAL_HW_MAX_VERSION_MAJOR 2100 /* major v of latest tgt hw */
112#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
113#define XCHAL_HW_MAX_VERSION 210002 /* latest targeted hw */
114
115
116/*----------------------------------------------------------------------
117 CACHE
118 ----------------------------------------------------------------------*/
119
120#define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */
121#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
122#define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */
123#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
124
125#define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */
126#define XCHAL_DCACHE_SIZE 32768 /* D-cache size in bytes or 0 */
127
128#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
129
130
131
132
133/****************************************************************************
134 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
135 ****************************************************************************/
136
137
138#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
139
140/*----------------------------------------------------------------------
141 CACHE
142 ----------------------------------------------------------------------*/
143
144#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
145
146/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
147
148/* Number of cache sets in log2(lines per way): */
149#define XCHAL_ICACHE_SETWIDTH 9
150#define XCHAL_DCACHE_SETWIDTH 10
151
152/* Cache set associativity (number of ways): */
153#define XCHAL_ICACHE_WAYS 4
154#define XCHAL_DCACHE_WAYS 2
155
156/* Cache features: */
157#define XCHAL_ICACHE_LINE_LOCKABLE 1
158#define XCHAL_DCACHE_LINE_LOCKABLE 0
159#define XCHAL_ICACHE_ECC_PARITY 0
160#define XCHAL_DCACHE_ECC_PARITY 0
161
162/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
163#define XCHAL_CA_BITS 4
164
165
166/*----------------------------------------------------------------------
167 INTERNAL I/D RAM/ROMs and XLMI
168 ----------------------------------------------------------------------*/
169
170#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
171#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
172#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
173#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
174#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
175#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
176
177/* Data RAM 0: */
178#define XCHAL_DATARAM0_VADDR 0x3FFF0000
179#define XCHAL_DATARAM0_PADDR 0x3FFF0000
180#define XCHAL_DATARAM0_SIZE 65536
181#define XCHAL_DATARAM0_ECC_PARITY 0
182
183/* XLMI Port 0: */
184#define XCHAL_XLMI0_VADDR 0x37F80000
185#define XCHAL_XLMI0_PADDR 0x37F80000
186#define XCHAL_XLMI0_SIZE 262144
187#define XCHAL_XLMI0_ECC_PARITY 0
188
189
190/*----------------------------------------------------------------------
191 INTERRUPTS and TIMERS
192 ----------------------------------------------------------------------*/
193
194#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
195#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
196#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
197#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
198#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
199#define XCHAL_NUM_INTERRUPTS 27 /* number of interrupts */
200#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
201#define XCHAL_NUM_EXTINTERRUPTS 20 /* num of external interrupts */
202#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
203 (not including level zero) */
204#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
205 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
206
207/* Masks of interrupts at each interrupt level: */
208#define XCHAL_INTLEVEL1_MASK 0x01F07FFF
209#define XCHAL_INTLEVEL2_MASK 0x02018000
210#define XCHAL_INTLEVEL3_MASK 0x04060000
211#define XCHAL_INTLEVEL4_MASK 0x00000000
212#define XCHAL_INTLEVEL5_MASK 0x00080000
213#define XCHAL_INTLEVEL6_MASK 0x00000000
214#define XCHAL_INTLEVEL7_MASK 0x00000000
215
216/* Masks of interrupts at each range 1..n of interrupt levels: */
217#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x01F07FFF
218#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x03F1FFFF
219#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x07F7FFFF
220#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x07F7FFFF
221#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x07FFFFFF
222#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x07FFFFFF
223#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x07FFFFFF
224
225/* Level of each interrupt: */
226#define XCHAL_INT0_LEVEL 1
227#define XCHAL_INT1_LEVEL 1
228#define XCHAL_INT2_LEVEL 1
229#define XCHAL_INT3_LEVEL 1
230#define XCHAL_INT4_LEVEL 1
231#define XCHAL_INT5_LEVEL 1
232#define XCHAL_INT6_LEVEL 1
233#define XCHAL_INT7_LEVEL 1
234#define XCHAL_INT8_LEVEL 1
235#define XCHAL_INT9_LEVEL 1
236#define XCHAL_INT10_LEVEL 1
237#define XCHAL_INT11_LEVEL 1
238#define XCHAL_INT12_LEVEL 1
239#define XCHAL_INT13_LEVEL 1
240#define XCHAL_INT14_LEVEL 1
241#define XCHAL_INT15_LEVEL 2
242#define XCHAL_INT16_LEVEL 2
243#define XCHAL_INT17_LEVEL 3
244#define XCHAL_INT18_LEVEL 3
245#define XCHAL_INT19_LEVEL 5
246#define XCHAL_INT20_LEVEL 1
247#define XCHAL_INT21_LEVEL 1
248#define XCHAL_INT22_LEVEL 1
249#define XCHAL_INT23_LEVEL 1
250#define XCHAL_INT24_LEVEL 1
251#define XCHAL_INT25_LEVEL 2
252#define XCHAL_INT26_LEVEL 3
253#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
254#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
255#define XCHAL_NMILEVEL 5 /* NMI "level" (for use with
256 EXCSAVE/EPS/EPC_n, RFI n) */
257
258/* Type of each interrupt: */
259#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
260#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
261#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
262#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
263#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
264#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
265#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
266#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
267#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
268#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
269#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
270#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
271#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
272#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
273#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
274#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
275#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
276#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
277#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
278#define XCHAL_INT19_TYPE XTHAL_INTTYPE_NMI
279#define XCHAL_INT20_TYPE XTHAL_INTTYPE_SOFTWARE
280#define XCHAL_INT21_TYPE XTHAL_INTTYPE_SOFTWARE
281#define XCHAL_INT22_TYPE XTHAL_INTTYPE_SOFTWARE
282#define XCHAL_INT23_TYPE XTHAL_INTTYPE_SOFTWARE
283#define XCHAL_INT24_TYPE XTHAL_INTTYPE_TIMER
284#define XCHAL_INT25_TYPE XTHAL_INTTYPE_TIMER
285#define XCHAL_INT26_TYPE XTHAL_INTTYPE_TIMER
286
287/* Masks of interrupts for each type of interrupt: */
288#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xF8000000
289#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00F00000
290#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
291#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0007FFFF
292#define XCHAL_INTTYPE_MASK_TIMER 0x07000000
293#define XCHAL_INTTYPE_MASK_NMI 0x00080000
294#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
295
296/* Interrupt numbers assigned to specific interrupt sources: */
297#define XCHAL_TIMER0_INTERRUPT 24 /* CCOMPARE0 */
298#define XCHAL_TIMER1_INTERRUPT 25 /* CCOMPARE1 */
299#define XCHAL_TIMER2_INTERRUPT 26 /* CCOMPARE2 */
300#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
301#define XCHAL_NMI_INTERRUPT 19 /* non-maskable interrupt */
302
303/* Interrupt numbers for levels at which only one interrupt is configured: */
304#define XCHAL_INTLEVEL5_NUM 19
305/* (There are many interrupts each at level(s) 1, 2, 3.) */
306
307
308/*
309 * External interrupt vectors/levels.
310 * These macros describe how Xtensa processor interrupt numbers
311 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
312 * map to external BInterrupt<n> pins, for those interrupts
313 * configured as external (level-triggered, edge-triggered, or NMI).
314 * See the Xtensa processor databook for more details.
315 */
316
317/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
318#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
319#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
320#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
321#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
322#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
323#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
324#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
325#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
326#define XCHAL_EXTINT8_NUM 8 /* (intlevel 1) */
327#define XCHAL_EXTINT9_NUM 9 /* (intlevel 1) */
328#define XCHAL_EXTINT10_NUM 10 /* (intlevel 1) */
329#define XCHAL_EXTINT11_NUM 11 /* (intlevel 1) */
330#define XCHAL_EXTINT12_NUM 12 /* (intlevel 1) */
331#define XCHAL_EXTINT13_NUM 13 /* (intlevel 1) */
332#define XCHAL_EXTINT14_NUM 14 /* (intlevel 1) */
333#define XCHAL_EXTINT15_NUM 15 /* (intlevel 2) */
334#define XCHAL_EXTINT16_NUM 16 /* (intlevel 2) */
335#define XCHAL_EXTINT17_NUM 17 /* (intlevel 3) */
336#define XCHAL_EXTINT18_NUM 18 /* (intlevel 3) */
337#define XCHAL_EXTINT19_NUM 19 /* (intlevel 5) */
338
339
340/*----------------------------------------------------------------------
341 EXCEPTIONS and VECTORS
342 ----------------------------------------------------------------------*/
343
344#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
345 number: 1 == XEA1 (old)
346 2 == XEA2 (new)
347 0 == XEAX (extern) */
348#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
349#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
350#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
351#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
352#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
353#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */
354#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */
355
356#define XCHAL_RESET_VECOFS 0x00000000
357#define XCHAL_RESET_VECTOR_VADDR 0x3FFE03D0
358#define XCHAL_RESET_VECTOR_PADDR 0x3FFE03D0
359#define XCHAL_USER_VECOFS 0x00000000
360#define XCHAL_USER_VECTOR_VADDR 0x40000220
361#define XCHAL_USER_VECTOR_PADDR 0x40000220
362#define XCHAL_KERNEL_VECOFS 0x00000000
363#define XCHAL_KERNEL_VECTOR_VADDR 0x40000200
364#define XCHAL_KERNEL_VECTOR_PADDR 0x40000200
365#define XCHAL_DOUBLEEXC_VECOFS 0x00000000
366#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400002A0
367#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400002A0
368#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
369#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
370#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
371#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
372#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
373#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
374#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
375#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
376#define XCHAL_INTLEVEL2_VECOFS 0x00000000
377#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000240
378#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000240
379#define XCHAL_INTLEVEL3_VECOFS 0x00000000
380#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x40000260
381#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x40000260
382#define XCHAL_INTLEVEL4_VECOFS 0x00000000
383#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000390
384#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000390
385#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS
386#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
387#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
388#define XCHAL_NMI_VECOFS 0x00000000
389#define XCHAL_NMI_VECTOR_VADDR 0x400003B0
390#define XCHAL_NMI_VECTOR_PADDR 0x400003B0
391#define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS
392#define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
393#define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
394
395
396/*----------------------------------------------------------------------
397 DEBUG
398 ----------------------------------------------------------------------*/
399
400#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
401#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
402#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
403#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
404
405
406/*----------------------------------------------------------------------
407 MMU
408 ----------------------------------------------------------------------*/
409
410/* See core-matmap.h header file for more details. */
411
412#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
413#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
414#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
415#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
416#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
417#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
418#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
419 [autorefill] and protection)
420 usable for an MMU-based OS */
421/* If none of the above last 4 are set, it's a custom TLB configuration. */
422
423#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
424#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
425#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
426
427#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
428
429
430#endif /* _XTENSA_CORE_CONFIGURATION_H */
431
diff --git a/arch/xtensa/variants/s6000/include/variant/tie-asm.h b/arch/xtensa/variants/s6000/include/variant/tie-asm.h
new file mode 100644
index 000000000000..f02d0a3a2e20
--- /dev/null
+++ b/arch/xtensa/variants/s6000/include/variant/tie-asm.h
@@ -0,0 +1,304 @@
1/*
2 * This header file contains assembly-language definitions (assembly
3 * macros, etc.) for this specific Xtensa processor's TIE extensions
4 * and options. It is customized to this Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2008 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_ASM_H
14#define _XTENSA_CORE_TIE_ASM_H
15
16/* Selection parameter values for save-area save/restore macros: */
17/* Option vs. TIE: */
18#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
19#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
20/* Whether used automatically by compiler: */
21#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
22#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
23/* ABI handling across function calls: */
24#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27/* Misc */
28#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
29
30
31
32/* Macro to save all non-coprocessor (extra) custom TIE and optional state
33 * (not including zero-overhead loop registers).
34 * Save area ptr (clobbered): ptr (16 byte aligned)
35 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
36 */
37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
38 xchal_sa_start \continue, \ofs
39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
40 xchal_sa_align \ptr, 0, 1024-4, 4, 4
41 rsr \at1, BR // boolean option
42 s32i \at1, \ptr, .Lxchal_ofs_ + 0
43 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
44 .endif
45 .endm // xchal_ncp_store
46
47/* Macro to save all non-coprocessor (extra) custom TIE and optional state
48 * (not including zero-overhead loop registers).
49 * Save area ptr (clobbered): ptr (16 byte aligned)
50 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
51 */
52 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
53 xchal_sa_start \continue, \ofs
54 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
55 xchal_sa_align \ptr, 0, 1024-4, 4, 4
56 l32i \at1, \ptr, .Lxchal_ofs_ + 0
57 wsr \at1, BR // boolean option
58 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
59 .endif
60 .endm // xchal_ncp_load
61
62
63
64#define XCHAL_NCP_NUM_ATMPS 1
65
66
67
68/* Macro to save the state of TIE coprocessor FPU.
69 * Save area ptr (clobbered): ptr (16 byte aligned)
70 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
71 */
72#define xchal_cp_FPU_store xchal_cp0_store
73/* #define xchal_cp_FPU_store_a2 xchal_cp0_store a2 a3 a4 a5 a6 */
74 .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
75 xchal_sa_start \continue, \ofs
76 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
77 xchal_sa_align \ptr, 0, 0, 1, 16
78 rur232 \at1 // FCR
79 s32i \at1, \ptr, 0
80 rur233 \at1 // FSR
81 s32i \at1, \ptr, 4
82 SSI f0, \ptr, 8
83 SSI f1, \ptr, 12
84 SSI f2, \ptr, 16
85 SSI f3, \ptr, 20
86 SSI f4, \ptr, 24
87 SSI f5, \ptr, 28
88 SSI f6, \ptr, 32
89 SSI f7, \ptr, 36
90 SSI f8, \ptr, 40
91 SSI f9, \ptr, 44
92 SSI f10, \ptr, 48
93 SSI f11, \ptr, 52
94 SSI f12, \ptr, 56
95 SSI f13, \ptr, 60
96 SSI f14, \ptr, 64
97 SSI f15, \ptr, 68
98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
99 .endif
100 .endm // xchal_cp0_store
101
102/* Macro to restore the state of TIE coprocessor FPU.
103 * Save area ptr (clobbered): ptr (16 byte aligned)
104 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
105 */
106#define xchal_cp_FPU_load xchal_cp0_load
107/* #define xchal_cp_FPU_load_a2 xchal_cp0_load a2 a3 a4 a5 a6 */
108 .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
109 xchal_sa_start \continue, \ofs
110 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
111 xchal_sa_align \ptr, 0, 0, 1, 16
112 l32i \at1, \ptr, 0
113 wur232 \at1 // FCR
114 l32i \at1, \ptr, 4
115 wur233 \at1 // FSR
116 LSI f0, \ptr, 8
117 LSI f1, \ptr, 12
118 LSI f2, \ptr, 16
119 LSI f3, \ptr, 20
120 LSI f4, \ptr, 24
121 LSI f5, \ptr, 28
122 LSI f6, \ptr, 32
123 LSI f7, \ptr, 36
124 LSI f8, \ptr, 40
125 LSI f9, \ptr, 44
126 LSI f10, \ptr, 48
127 LSI f11, \ptr, 52
128 LSI f12, \ptr, 56
129 LSI f13, \ptr, 60
130 LSI f14, \ptr, 64
131 LSI f15, \ptr, 68
132 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
133 .endif
134 .endm // xchal_cp0_load
135
136#define XCHAL_CP0_NUM_ATMPS 1
137
138/* Macro to save the state of TIE coprocessor XAD.
139 * Save area ptr (clobbered): ptr (16 byte aligned)
140 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
141 */
142#define xchal_cp_XAD_store xchal_cp6_store
143/* #define xchal_cp_XAD_store_a2 xchal_cp6_store a2 a3 a4 a5 a6 */
144 .macro xchal_cp6_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
145 xchal_sa_start \continue, \ofs
146 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
147 xchal_sa_align \ptr, 0, 0, 1, 16
148 rur0 \at1 // LDCBHI
149 s32i \at1, \ptr, 0
150 rur1 \at1 // LDCBLO
151 s32i \at1, \ptr, 4
152 rur2 \at1 // STCBHI
153 s32i \at1, \ptr, 8
154 rur3 \at1 // STCBLO
155 s32i \at1, \ptr, 12
156 rur8 \at1 // LDBRBASE
157 s32i \at1, \ptr, 16
158 rur9 \at1 // LDBROFF
159 s32i \at1, \ptr, 20
160 rur10 \at1 // LDBRINC
161 s32i \at1, \ptr, 24
162 rur11 \at1 // STBRBASE
163 s32i \at1, \ptr, 28
164 rur12 \at1 // STBROFF
165 s32i \at1, \ptr, 32
166 rur13 \at1 // STBRINC
167 s32i \at1, \ptr, 36
168 rur24 \at1 // SCRATCH0
169 s32i \at1, \ptr, 40
170 rur25 \at1 // SCRATCH1
171 s32i \at1, \ptr, 44
172 rur26 \at1 // SCRATCH2
173 s32i \at1, \ptr, 48
174 rur27 \at1 // SCRATCH3
175 s32i \at1, \ptr, 52
176 WRAS128I wra0, \ptr, 64
177 WRAS128I wra1, \ptr, 80
178 WRAS128I wra2, \ptr, 96
179 WRAS128I wra3, \ptr, 112
180 WRAS128I wra4, \ptr, 128
181 WRAS128I wra5, \ptr, 144
182 WRAS128I wra6, \ptr, 160
183 WRAS128I wra7, \ptr, 176
184 WRAS128I wra8, \ptr, 192
185 WRAS128I wra9, \ptr, 208
186 WRAS128I wra10, \ptr, 224
187 WRAS128I wra11, \ptr, 240
188 WRAS128I wra12, \ptr, 256
189 WRAS128I wra13, \ptr, 272
190 WRAS128I wra14, \ptr, 288
191 WRAS128I wra15, \ptr, 304
192 WRBS128I wrb0, \ptr, 320
193 WRBS128I wrb1, \ptr, 336
194 WRBS128I wrb2, \ptr, 352
195 WRBS128I wrb3, \ptr, 368
196 WRBS128I wrb4, \ptr, 384
197 WRBS128I wrb5, \ptr, 400
198 WRBS128I wrb6, \ptr, 416
199 WRBS128I wrb7, \ptr, 432
200 WRBS128I wrb8, \ptr, 448
201 WRBS128I wrb9, \ptr, 464
202 WRBS128I wrb10, \ptr, 480
203 WRBS128I wrb11, \ptr, 496
204 WRBS128I wrb12, \ptr, 512
205 WRBS128I wrb13, \ptr, 528
206 WRBS128I wrb14, \ptr, 544
207 WRBS128I wrb15, \ptr, 560
208 .set .Lxchal_ofs_, .Lxchal_ofs_ + 576
209 .endif
210 .endm // xchal_cp6_store
211
212/* Macro to restore the state of TIE coprocessor XAD.
213 * Save area ptr (clobbered): ptr (16 byte aligned)
214 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
215 */
216#define xchal_cp_XAD_load xchal_cp6_load
217/* #define xchal_cp_XAD_load_a2 xchal_cp6_load a2 a3 a4 a5 a6 */
218 .macro xchal_cp6_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
219 xchal_sa_start \continue, \ofs
220 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
221 xchal_sa_align \ptr, 0, 0, 1, 16
222 l32i \at1, \ptr, 0
223 wur0 \at1 // LDCBHI
224 l32i \at1, \ptr, 4
225 wur1 \at1 // LDCBLO
226 l32i \at1, \ptr, 8
227 wur2 \at1 // STCBHI
228 l32i \at1, \ptr, 12
229 wur3 \at1 // STCBLO
230 l32i \at1, \ptr, 16
231 wur8 \at1 // LDBRBASE
232 l32i \at1, \ptr, 20
233 wur9 \at1 // LDBROFF
234 l32i \at1, \ptr, 24
235 wur10 \at1 // LDBRINC
236 l32i \at1, \ptr, 28
237 wur11 \at1 // STBRBASE
238 l32i \at1, \ptr, 32
239 wur12 \at1 // STBROFF
240 l32i \at1, \ptr, 36
241 wur13 \at1 // STBRINC
242 l32i \at1, \ptr, 40
243 wur24 \at1 // SCRATCH0
244 l32i \at1, \ptr, 44
245 wur25 \at1 // SCRATCH1
246 l32i \at1, \ptr, 48
247 wur26 \at1 // SCRATCH2
248 l32i \at1, \ptr, 52
249 wur27 \at1 // SCRATCH3
250 WRBL128I wrb0, \ptr, 320
251 WRBL128I wrb1, \ptr, 336
252 WRBL128I wrb2, \ptr, 352
253 WRBL128I wrb3, \ptr, 368
254 WRBL128I wrb4, \ptr, 384
255 WRBL128I wrb5, \ptr, 400
256 WRBL128I wrb6, \ptr, 416
257 WRBL128I wrb7, \ptr, 432
258 WRBL128I wrb8, \ptr, 448
259 WRBL128I wrb9, \ptr, 464
260 WRBL128I wrb10, \ptr, 480
261 WRBL128I wrb11, \ptr, 496
262 WRBL128I wrb12, \ptr, 512
263 WRBL128I wrb13, \ptr, 528
264 WRBL128I wrb14, \ptr, 544
265 WRBL128I wrb15, \ptr, 560
266 WRAL128I wra0, \ptr, 64
267 WRAL128I wra1, \ptr, 80
268 WRAL128I wra2, \ptr, 96
269 WRAL128I wra3, \ptr, 112
270 WRAL128I wra4, \ptr, 128
271 WRAL128I wra5, \ptr, 144
272 WRAL128I wra6, \ptr, 160
273 WRAL128I wra7, \ptr, 176
274 WRAL128I wra8, \ptr, 192
275 WRAL128I wra9, \ptr, 208
276 WRAL128I wra10, \ptr, 224
277 WRAL128I wra11, \ptr, 240
278 WRAL128I wra12, \ptr, 256
279 WRAL128I wra13, \ptr, 272
280 WRAL128I wra14, \ptr, 288
281 WRAL128I wra15, \ptr, 304
282 .set .Lxchal_ofs_, .Lxchal_ofs_ + 576
283 .endif
284 .endm // xchal_cp6_load
285
286#define XCHAL_CP6_NUM_ATMPS 1
287#define XCHAL_SA_NUM_ATMPS 1
288
289 /* Empty macros for unconfigured coprocessors: */
290 .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
291 .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
292 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
293 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
294 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
295 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
296 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
297 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
298 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
299 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
300 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
301 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
302
303#endif /*_XTENSA_CORE_TIE_ASM_H*/
304
diff --git a/arch/xtensa/variants/s6000/include/variant/tie.h b/arch/xtensa/variants/s6000/include/variant/tie.h
new file mode 100644
index 000000000000..be7ea843d5df
--- /dev/null
+++ b/arch/xtensa/variants/s6000/include/variant/tie.h
@@ -0,0 +1,191 @@
1/*
2 * This header file describes this specific Xtensa processor's TIE extensions
3 * that extend basic Xtensa core functionality. It is customized to this
4 * Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2008 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_H
14#define _XTENSA_CORE_TIE_H
15
16#define XCHAL_CP_NUM 2 /* number of coprocessors */
17#define XCHAL_CP_MAX 7 /* max CP ID + 1 (0 if none) */
18#define XCHAL_CP_MASK 0x41 /* bitmask of all CPs by ID */
19#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
20
21/* Basic parameters of each coprocessor: */
22#define XCHAL_CP0_NAME "FPU"
23#define XCHAL_CP0_IDENT FPU
24#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
25#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
26#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
27#define XCHAL_CP6_NAME "XAD"
28#define XCHAL_CP6_IDENT XAD
29#define XCHAL_CP6_SA_SIZE 576 /* size of state save area */
30#define XCHAL_CP6_SA_ALIGN 16 /* min alignment of save area */
31#define XCHAL_CP_ID_XAD 6 /* coprocessor ID (0..7) */
32
33/* Filler info for unassigned coprocessors, to simplify arrays etc: */
34#define XCHAL_CP1_SA_SIZE 0
35#define XCHAL_CP1_SA_ALIGN 1
36#define XCHAL_CP2_SA_SIZE 0
37#define XCHAL_CP2_SA_ALIGN 1
38#define XCHAL_CP3_SA_SIZE 0
39#define XCHAL_CP3_SA_ALIGN 1
40#define XCHAL_CP4_SA_SIZE 0
41#define XCHAL_CP4_SA_ALIGN 1
42#define XCHAL_CP5_SA_SIZE 0
43#define XCHAL_CP5_SA_ALIGN 1
44#define XCHAL_CP7_SA_SIZE 0
45#define XCHAL_CP7_SA_ALIGN 1
46
47/* Save area for non-coprocessor optional and custom (TIE) state: */
48#define XCHAL_NCP_SA_SIZE 4
49#define XCHAL_NCP_SA_ALIGN 4
50
51/* Total save area for optional and custom state (NCP + CPn): */
52#define XCHAL_TOTAL_SA_SIZE 672 /* with 16-byte align padding */
53#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
54
55/*
56 * Detailed contents of save areas.
57 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
58 * before expanding the XCHAL_xxx_SA_LIST() macros.
59 *
60 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
61 * dbnum,base,regnum,bitsz,gapsz,reset,x...)
62 *
63 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
64 * ccused = set if used by compiler without special options or code
65 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
66 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
67 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
68 * name = lowercase reg name (no quotes)
69 * galign = group byte alignment (power of 2) (galign >= align)
70 * align = register byte alignment (power of 2)
71 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
72 * (not including any pad bytes required to galign this or next reg)
73 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
74 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
75 * regnum = reg index in regfile, or special/TIE-user reg number
76 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
77 * gapsz = intervening bits, if bitsz bits not stored contiguously
78 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
79 * reset = register reset value (or 0 if undefined at reset)
80 * x = reserved for future use (0 until then)
81 *
82 * To filter out certain registers, e.g. to expand only the non-global
83 * registers used by the compiler, you can do something like this:
84 *
85 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
86 * #define SELCC0(p...)
87 * #define SELCC1(abikind,p...) SELAK##abikind(p)
88 * #define SELAK0(p...) REG(p)
89 * #define SELAK1(p...) REG(p)
90 * #define SELAK2(p...)
91 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
92 * ...what you want to expand...
93 */
94
95#define XCHAL_NCP_SA_NUM 1
96#define XCHAL_NCP_SA_LIST(s) \
97 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0)
98
99#define XCHAL_CP0_SA_NUM 18
100#define XCHAL_CP0_SA_LIST(s) \
101 XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
102 XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
103 XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
104 XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
105 XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
106 XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
107 XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
108 XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
109 XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
110 XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
111 XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
112 XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
113 XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
114 XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
115 XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
116 XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
117 XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
119
120#define XCHAL_CP1_SA_NUM 0
121#define XCHAL_CP1_SA_LIST(s) /* empty */
122
123#define XCHAL_CP2_SA_NUM 0
124#define XCHAL_CP2_SA_LIST(s) /* empty */
125
126#define XCHAL_CP3_SA_NUM 0
127#define XCHAL_CP3_SA_LIST(s) /* empty */
128
129#define XCHAL_CP4_SA_NUM 0
130#define XCHAL_CP4_SA_LIST(s) /* empty */
131
132#define XCHAL_CP5_SA_NUM 0
133#define XCHAL_CP5_SA_LIST(s) /* empty */
134
135#define XCHAL_CP6_SA_NUM 46
136#define XCHAL_CP6_SA_LIST(s) \
137 XCHAL_SA_REG(s,0,0,1,0, ldcbhi,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
138 XCHAL_SA_REG(s,0,0,1,0, ldcblo, 4, 4, 4,0x0301, ur,1 , 32,0,0,0) \
139 XCHAL_SA_REG(s,0,0,1,0, stcbhi, 4, 4, 4,0x0302, ur,2 , 32,0,0,0) \
140 XCHAL_SA_REG(s,0,0,1,0, stcblo, 4, 4, 4,0x0303, ur,3 , 32,0,0,0) \
141 XCHAL_SA_REG(s,0,0,1,0, ldbrbase, 4, 4, 4,0x0308, ur,8 , 32,0,0,0) \
142 XCHAL_SA_REG(s,0,0,1,0, ldbroff, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
143 XCHAL_SA_REG(s,0,0,1,0, ldbrinc, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
144 XCHAL_SA_REG(s,0,0,1,0, stbrbase, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
145 XCHAL_SA_REG(s,0,0,1,0, stbroff, 4, 4, 4,0x030C, ur,12 , 32,0,0,0) \
146 XCHAL_SA_REG(s,0,0,1,0, stbrinc, 4, 4, 4,0x030D, ur,13 , 32,0,0,0) \
147 XCHAL_SA_REG(s,0,0,1,0, scratch0, 4, 4, 4,0x0318, ur,24 , 32,0,0,0) \
148 XCHAL_SA_REG(s,0,0,1,0, scratch1, 4, 4, 4,0x0319, ur,25 , 32,0,0,0) \
149 XCHAL_SA_REG(s,0,0,1,0, scratch2, 4, 4, 4,0x031A, ur,26 , 32,0,0,0) \
150 XCHAL_SA_REG(s,0,0,1,0, scratch3, 4, 4, 4,0x031B, ur,27 , 32,0,0,0) \
151 XCHAL_SA_REG(s,0,0,2,0, wra0,16,16,16,0x1010, wra,0 ,128,0,0,0) \
152 XCHAL_SA_REG(s,0,0,2,0, wra1,16,16,16,0x1011, wra,1 ,128,0,0,0) \
153 XCHAL_SA_REG(s,0,0,2,0, wra2,16,16,16,0x1012, wra,2 ,128,0,0,0) \
154 XCHAL_SA_REG(s,0,0,2,0, wra3,16,16,16,0x1013, wra,3 ,128,0,0,0) \
155 XCHAL_SA_REG(s,0,0,2,0, wra4,16,16,16,0x1014, wra,4 ,128,0,0,0) \
156 XCHAL_SA_REG(s,0,0,2,0, wra5,16,16,16,0x1015, wra,5 ,128,0,0,0) \
157 XCHAL_SA_REG(s,0,0,2,0, wra6,16,16,16,0x1016, wra,6 ,128,0,0,0) \
158 XCHAL_SA_REG(s,0,0,2,0, wra7,16,16,16,0x1017, wra,7 ,128,0,0,0) \
159 XCHAL_SA_REG(s,0,0,2,0, wra8,16,16,16,0x1018, wra,8 ,128,0,0,0) \
160 XCHAL_SA_REG(s,0,0,2,0, wra9,16,16,16,0x1019, wra,9 ,128,0,0,0) \
161 XCHAL_SA_REG(s,0,0,2,0, wra10,16,16,16,0x101A, wra,10 ,128,0,0,0) \
162 XCHAL_SA_REG(s,0,0,2,0, wra11,16,16,16,0x101B, wra,11 ,128,0,0,0) \
163 XCHAL_SA_REG(s,0,0,2,0, wra12,16,16,16,0x101C, wra,12 ,128,0,0,0) \
164 XCHAL_SA_REG(s,0,0,2,0, wra13,16,16,16,0x101D, wra,13 ,128,0,0,0) \
165 XCHAL_SA_REG(s,0,0,2,0, wra14,16,16,16,0x101E, wra,14 ,128,0,0,0) \
166 XCHAL_SA_REG(s,0,0,2,0, wra15,16,16,16,0x101F, wra,15 ,128,0,0,0) \
167 XCHAL_SA_REG(s,0,0,2,0, wrb0,16,16,16,0x1020, wrb,0 ,128,0,0,0) \
168 XCHAL_SA_REG(s,0,0,2,0, wrb1,16,16,16,0x1021, wrb,1 ,128,0,0,0) \
169 XCHAL_SA_REG(s,0,0,2,0, wrb2,16,16,16,0x1022, wrb,2 ,128,0,0,0) \
170 XCHAL_SA_REG(s,0,0,2,0, wrb3,16,16,16,0x1023, wrb,3 ,128,0,0,0) \
171 XCHAL_SA_REG(s,0,0,2,0, wrb4,16,16,16,0x1024, wrb,4 ,128,0,0,0) \
172 XCHAL_SA_REG(s,0,0,2,0, wrb5,16,16,16,0x1025, wrb,5 ,128,0,0,0) \
173 XCHAL_SA_REG(s,0,0,2,0, wrb6,16,16,16,0x1026, wrb,6 ,128,0,0,0) \
174 XCHAL_SA_REG(s,0,0,2,0, wrb7,16,16,16,0x1027, wrb,7 ,128,0,0,0) \
175 XCHAL_SA_REG(s,0,0,2,0, wrb8,16,16,16,0x1028, wrb,8 ,128,0,0,0) \
176 XCHAL_SA_REG(s,0,0,2,0, wrb9,16,16,16,0x1029, wrb,9 ,128,0,0,0) \
177 XCHAL_SA_REG(s,0,0,2,0, wrb10,16,16,16,0x102A, wrb,10 ,128,0,0,0) \
178 XCHAL_SA_REG(s,0,0,2,0, wrb11,16,16,16,0x102B, wrb,11 ,128,0,0,0) \
179 XCHAL_SA_REG(s,0,0,2,0, wrb12,16,16,16,0x102C, wrb,12 ,128,0,0,0) \
180 XCHAL_SA_REG(s,0,0,2,0, wrb13,16,16,16,0x102D, wrb,13 ,128,0,0,0) \
181 XCHAL_SA_REG(s,0,0,2,0, wrb14,16,16,16,0x102E, wrb,14 ,128,0,0,0) \
182 XCHAL_SA_REG(s,0,0,2,0, wrb15,16,16,16,0x102F, wrb,15 ,128,0,0,0)
183
184#define XCHAL_CP7_SA_NUM 0
185#define XCHAL_CP7_SA_LIST(s) /* empty */
186
187/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
188#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
189
190#endif /*_XTENSA_CORE_TIE_H*/
191