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authorDavid Woodhouse <dwmw2@infradead.org>2007-01-17 18:34:51 -0500
committerDavid Woodhouse <dwmw2@infradead.org>2007-01-17 18:34:51 -0500
commit9cdf083f981b8d37b3212400a359368661385099 (patch)
treeaa15a6a08ad87e650dea40fb59b3180bef0d345b /arch/xtensa
parente499e01d234a31d59679b7b1e1cf628d917ba49a (diff)
parenta8b3485287731978899ced11f24628c927890e78 (diff)
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/Kconfig29
-rw-r--r--arch/xtensa/Makefile25
-rw-r--r--arch/xtensa/boot/boot-elf/bootstrap.S3
-rw-r--r--arch/xtensa/boot/boot-redboot/bootstrap.S37
-rw-r--r--arch/xtensa/configs/iss_defconfig6
-rw-r--r--arch/xtensa/kernel/Makefile2
-rw-r--r--arch/xtensa/kernel/align.S42
-rw-r--r--arch/xtensa/kernel/asm-offsets.c5
-rw-r--r--arch/xtensa/kernel/coprocessor.S2
-rw-r--r--arch/xtensa/kernel/entry.S256
-rw-r--r--arch/xtensa/kernel/head.S53
-rw-r--r--arch/xtensa/kernel/irq.c107
-rw-r--r--arch/xtensa/kernel/pci-dma.c44
-rw-r--r--arch/xtensa/kernel/process.c108
-rw-r--r--arch/xtensa/kernel/ptrace.c28
-rw-r--r--arch/xtensa/kernel/setup.c41
-rw-r--r--arch/xtensa/kernel/signal.c28
-rw-r--r--arch/xtensa/kernel/syscall.c95
-rw-r--r--arch/xtensa/kernel/syscalls.c288
-rw-r--r--arch/xtensa/kernel/syscalls.h247
-rw-r--r--arch/xtensa/kernel/time.c8
-rw-r--r--arch/xtensa/kernel/traps.c56
-rw-r--r--arch/xtensa/kernel/vectors.S12
-rw-r--r--arch/xtensa/kernel/vmlinux.lds.S26
-rw-r--r--arch/xtensa/lib/checksum.S3
-rw-r--r--arch/xtensa/lib/memcopy.S2
-rw-r--r--arch/xtensa/lib/memset.S2
-rw-r--r--arch/xtensa/lib/strncpy_user.S2
-rw-r--r--arch/xtensa/lib/strnlen_user.S2
-rw-r--r--arch/xtensa/lib/usercopy.S2
-rw-r--r--arch/xtensa/mm/fault.c10
-rw-r--r--arch/xtensa/mm/init.c6
-rw-r--r--arch/xtensa/mm/misc.S265
-rw-r--r--arch/xtensa/mm/tlb.c445
-rw-r--r--arch/xtensa/platform-iss/console.c8
-rw-r--r--arch/xtensa/platform-iss/network.c2
36 files changed, 670 insertions, 1627 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index c1e69a1f92a4..2e74cb0b7807 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -34,31 +34,24 @@ config GENERIC_HARDIRQS
34 bool 34 bool
35 default y 35 default y
36 36
37config ARCH_HAS_ILOG2_U32
38 bool
39 default n
40
41config ARCH_HAS_ILOG2_U64
42 bool
43 default n
44
37source "init/Kconfig" 45source "init/Kconfig"
38 46
39menu "Processor type and features" 47menu "Processor type and features"
40 48
41choice 49choice
42 prompt "Xtensa Processor Configuration" 50 prompt "Xtensa Processor Configuration"
43 default XTENSA_CPU_LINUX_BE 51 default XTENSA_VARIANT_FSF
44 52
45config XTENSA_CPU_LINUX_BE 53config XTENSA_VARIANT_FSF
46 bool "linux_be" 54 bool "fsf"
47 ---help---
48 The linux_be processor configuration is the baseline Xtensa
49 configurations included in this kernel and also used by
50 binutils, gcc, and gdb. It contains no TIE, no coprocessors,
51 and the following configuration options:
52
53 Code Density Option 2 Misc Special Registers
54 NSA/NSAU Instructions 128-bit Data Bus Width
55 Processor ID 8K, 2-way I and D Caches
56 Zero-Overhead Loops 2 Inst Address Break Registers
57 Big Endian 2 Data Address Break Registers
58 64 General-Purpose Registers JTAG Interface and Trace Port
59 17 Interrupts MMU w/ TLBs and Autorefill
60 3 Interrupt Levels 8 Autorefill Ways (I/D TLBs)
61 3 Timers Unaligned Exceptions
62endchoice 55endchoice
63 56
64config MMU 57config MMU
diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile
index 3a3a4c66ef87..95f836db38fa 100644
--- a/arch/xtensa/Makefile
+++ b/arch/xtensa/Makefile
@@ -11,13 +11,13 @@
11# this architecture 11# this architecture
12 12
13# Core configuration. 13# Core configuration.
14# (Use CPU=<xtensa_config> to use another default compiler.) 14# (Use VAR=<xtensa_config> to use another default compiler.)
15 15
16cpu-$(CONFIG_XTENSA_CPU_LINUX_BE) := linux_be 16variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf
17cpu-$(CONFIG_XTENSA_CPU_LINUX_CUSTOM) := linux_custom 17variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom
18 18
19CPU = $(cpu-y) 19VARIANT = $(variant-y)
20export CPU 20export VARIANT
21 21
22# Platform configuration 22# Platform configuration
23 23
@@ -27,8 +27,6 @@ platform-$(CONFIG_XTENSA_PLATFORM_ISS) := iss
27PLATFORM = $(platform-y) 27PLATFORM = $(platform-y)
28export PLATFORM 28export PLATFORM
29 29
30CPPFLAGS += $(if $(KBUILD_SRC),-I$(srctree)/include/asm-xtensa/)
31CPPFLAGS += -Iinclude/asm
32CFLAGS += -pipe -mlongcalls 30CFLAGS += -pipe -mlongcalls
33 31
34KBUILD_DEFCONFIG := iss_defconfig 32KBUILD_DEFCONFIG := iss_defconfig
@@ -41,12 +39,12 @@ core-$(CONFIG_EMBEDDED_RAMDISK) += arch/xtensa/boot/ramdisk/
41 39
42# Test for cross compiling 40# Test for cross compiling
43 41
44ifneq ($(CPU),) 42ifneq ($(VARIANT),)
45 COMPILE_ARCH = $(shell uname -m) 43 COMPILE_ARCH = $(shell uname -m)
46 44
47 ifneq ($(COMPILE_ARCH), xtensa) 45 ifneq ($(COMPILE_ARCH), xtensa)
48 ifndef CROSS_COMPILE 46 ifndef CROSS_COMPILE
49 CROSS_COMPILE = xtensa_$(CPU)- 47 CROSS_COMPILE = xtensa_$(VARIANT)-
50 endif 48 endif
51 endif 49 endif
52endif 50endif
@@ -68,14 +66,13 @@ archinc := include/asm-xtensa
68 66
69archprepare: $(archinc)/.platform 67archprepare: $(archinc)/.platform
70 68
71# Update machine cpu and platform symlinks if something which affects 69# Update processor variant and platform symlinks if something which affects
72# them changed. 70# them changed.
73 71
74$(archinc)/.platform: $(wildcard include/config/arch/*.h) include/config/auto.conf 72$(archinc)/.platform: $(wildcard include/config/arch/*.h) include/config/auto.conf
75 @echo ' SYMLINK $(archinc)/xtensa/config -> $(archinc)/xtensa/config-$(CPU)' 73 @echo ' SYMLINK $(archinc)/variant -> $(archinc)/variant-$(VARIANT)'
76 $(Q)mkdir -p $(archinc) 74 $(Q)mkdir -p $(archinc)
77 $(Q)mkdir -p $(archinc)/xtensa 75 $(Q)ln -fsn $(srctree)/$(archinc)/variant-$(VARIANT) $(archinc)/variant
78 $(Q)ln -fsn $(srctree)/$(archinc)/xtensa/config-$(CPU) $(archinc)/xtensa/config
79 @echo ' SYMLINK $(archinc)/platform -> $(archinc)/platform-$(PLATFORM)' 76 @echo ' SYMLINK $(archinc)/platform -> $(archinc)/platform-$(PLATFORM)'
80 $(Q)ln -fsn $(srctree)/$(archinc)/platform-$(PLATFORM) $(archinc)/platform 77 $(Q)ln -fsn $(srctree)/$(archinc)/platform-$(PLATFORM) $(archinc)/platform
81 @touch $@ 78 @touch $@
@@ -89,7 +86,7 @@ zImage zImage.initrd: vmlinux
89 $(Q)$(MAKE) $(build)=$(boot) $@ 86 $(Q)$(MAKE) $(build)=$(boot) $@
90 87
91CLEAN_FILES += arch/xtensa/vmlinux.lds \ 88CLEAN_FILES += arch/xtensa/vmlinux.lds \
92 $(archinc)/platform $(archinc)/xtensa/config \ 89 $(archinc)/platform $(archinc)/variant \
93 $(archinc)/.platform 90 $(archinc)/.platform
94 91
95define archhelp 92define archhelp
diff --git a/arch/xtensa/boot/boot-elf/bootstrap.S b/arch/xtensa/boot/boot-elf/bootstrap.S
index f857fc760aa8..464298bc348b 100644
--- a/arch/xtensa/boot/boot-elf/bootstrap.S
+++ b/arch/xtensa/boot/boot-elf/bootstrap.S
@@ -1,7 +1,4 @@
1 1
2#include <xtensa/config/specreg.h>
3#include <xtensa/config/core.h>
4
5#include <asm/bootparam.h> 2#include <asm/bootparam.h>
6 3
7 4
diff --git a/arch/xtensa/boot/boot-redboot/bootstrap.S b/arch/xtensa/boot/boot-redboot/bootstrap.S
index ee636b0da81c..84848123e2a8 100644
--- a/arch/xtensa/boot/boot-redboot/bootstrap.S
+++ b/arch/xtensa/boot/boot-redboot/bootstrap.S
@@ -1,9 +1,7 @@
1 1#include <asm/variant/core.h>
2#define _ASMLANGUAGE 2#include <asm/regs.h>
3#include <xtensa/config/specreg.h> 3#include <asm/asmmacro.h>
4#include <xtensa/config/core.h> 4#include <asm/cacheasm.h>
5#include <xtensa/cacheasm.h>
6
7 /* 5 /*
8 * RB-Data: RedBoot data/bss 6 * RB-Data: RedBoot data/bss
9 * P: Boot-Parameters 7 * P: Boot-Parameters
@@ -77,8 +75,14 @@ _start:
77 /* Note: The assembler cannot relax "addi a0, a0, ..." to an 75 /* Note: The assembler cannot relax "addi a0, a0, ..." to an
78 l32r, so we load to a4 first. */ 76 l32r, so we load to a4 first. */
79 77
80 addi a4, a0, __start - __start_a0 78 # addi a4, a0, __start - __start_a0
81 mov a0, a4 79 # mov a0, a4
80
81 movi a4, __start
82 movi a5, __start_a0
83 add a4, a0, a4
84 sub a0, a4, a5
85
82 movi a4, __start 86 movi a4, __start
83 movi a5, __reloc_end 87 movi a5, __reloc_end
84 88
@@ -106,9 +110,13 @@ _start:
106 /* We have to flush and invalidate the caches here before we jump. */ 110 /* We have to flush and invalidate the caches here before we jump. */
107 111
108#if XCHAL_DCACHE_IS_WRITEBACK 112#if XCHAL_DCACHE_IS_WRITEBACK
109 dcache_writeback_all a5, a6 113
114 ___flush_dcache_all a5 a6
115
110#endif 116#endif
111 icache_invalidate_all a5, a6 117
118 ___invalidate_icache_all a5 a6
119 isync
112 120
113 movi a11, _reloc 121 movi a11, _reloc
114 jx a11 122 jx a11
@@ -209,9 +217,14 @@ _reloc:
209 /* jump to the kernel */ 217 /* jump to the kernel */
2102: 2182:
211#if XCHAL_DCACHE_IS_WRITEBACK 219#if XCHAL_DCACHE_IS_WRITEBACK
212 dcache_writeback_all a5, a6 220
221 ___flush_dcache_all a5 a6
222
213#endif 223#endif
214 icache_invalidate_all a5, a6 224
225 ___invalidate_icache_all a5 a6
226
227 isync
215 228
216 movi a5, __start 229 movi a5, __start
217 movi a3, boot_initrd_start 230 movi a3, boot_initrd_start
diff --git a/arch/xtensa/configs/iss_defconfig b/arch/xtensa/configs/iss_defconfig
index 802621dd4867..f19854035e61 100644
--- a/arch/xtensa/configs/iss_defconfig
+++ b/arch/xtensa/configs/iss_defconfig
@@ -53,11 +53,7 @@ CONFIG_CC_ALIGN_JUMPS=0
53# 53#
54# Processor type and features 54# Processor type and features
55# 55#
56CONFIG_XTENSA_ARCH_LINUX_BE=y 56CONFIG_XTENSA_VARIANT_FSF=y
57# CONFIG_XTENSA_ARCH_LINUX_LE is not set
58# CONFIG_XTENSA_ARCH_LINUX_TEST is not set
59# CONFIG_XTENSA_ARCH_S5 is not set
60# CONFIG_XTENSA_CUSTOM is not set
61CONFIG_MMU=y 57CONFIG_MMU=y
62# CONFIG_XTENSA_UNALIGNED_USER is not set 58# CONFIG_XTENSA_UNALIGNED_USER is not set
63# CONFIG_PREEMPT is not set 59# CONFIG_PREEMPT is not set
diff --git a/arch/xtensa/kernel/Makefile b/arch/xtensa/kernel/Makefile
index d573017a5dde..71f733c4f66d 100644
--- a/arch/xtensa/kernel/Makefile
+++ b/arch/xtensa/kernel/Makefile
@@ -6,7 +6,7 @@ extra-y := head.o vmlinux.lds
6 6
7 7
8obj-y := align.o entry.o irq.o coprocessor.o process.o ptrace.o semaphore.o \ 8obj-y := align.o entry.o irq.o coprocessor.o process.o ptrace.o semaphore.o \
9 setup.o signal.o syscalls.o time.o traps.o vectors.o platform.o \ 9 setup.o signal.o syscall.o time.o traps.o vectors.o platform.o \
10 pci-dma.o 10 pci-dma.o
11 11
12## windowspill.o 12## windowspill.o
diff --git a/arch/xtensa/kernel/align.S b/arch/xtensa/kernel/align.S
index a4956578a24d..33d6e9d2e83c 100644
--- a/arch/xtensa/kernel/align.S
+++ b/arch/xtensa/kernel/align.S
@@ -16,14 +16,9 @@
16 */ 16 */
17 17
18#include <linux/linkage.h> 18#include <linux/linkage.h>
19#include <asm/ptrace.h>
20#include <asm/ptrace.h>
21#include <asm/current.h> 19#include <asm/current.h>
22#include <asm/asm-offsets.h> 20#include <asm/asm-offsets.h>
23#include <asm/pgtable.h>
24#include <asm/processor.h> 21#include <asm/processor.h>
25#include <asm/page.h>
26#include <asm/thread_info.h>
27 22
28#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION 23#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
29 24
@@ -216,7 +211,7 @@ ENTRY(fast_unaligned)
216 211
217 extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble 212 extui a5, a4, INSN_OP0, 4 # get insn.op0 nibble
218 213
219#if XCHAL_HAVE_NARROW 214#if XCHAL_HAVE_DENSITY
220 _beqi a5, OP0_L32I_N, .Lload # L32I.N, jump 215 _beqi a5, OP0_L32I_N, .Lload # L32I.N, jump
221 addi a6, a5, -OP0_S32I_N 216 addi a6, a5, -OP0_S32I_N
222 _beqz a6, .Lstore # S32I.N, do a store 217 _beqz a6, .Lstore # S32I.N, do a store
@@ -251,7 +246,7 @@ ENTRY(fast_unaligned)
251#endif 246#endif
252 __src_b a3, a5, a6 # a3 has the data word 247 __src_b a3, a5, a6 # a3 has the data word
253 248
254#if XCHAL_HAVE_NARROW 249#if XCHAL_HAVE_DENSITY
255 addi a7, a7, 2 # increment PC (assume 16-bit insn) 250 addi a7, a7, 2 # increment PC (assume 16-bit insn)
256 251
257 extui a5, a4, INSN_OP0, 4 252 extui a5, a4, INSN_OP0, 4
@@ -279,14 +274,14 @@ ENTRY(fast_unaligned)
279 274
2801: 2751:
281 276
282#if XCHAL_HAVE_LOOP 277#if XCHAL_HAVE_LOOPS
283 rsr a3, LEND # check if we reached LEND 278 rsr a5, LEND # check if we reached LEND
284 bne a7, a3, 1f 279 bne a7, a5, 1f
285 rsr a3, LCOUNT # and LCOUNT != 0 280 rsr a5, LCOUNT # and LCOUNT != 0
286 beqz a3, 1f 281 beqz a5, 1f
287 addi a3, a3, -1 # decrement LCOUNT and set 282 addi a5, a5, -1 # decrement LCOUNT and set
288 rsr a7, LBEG # set PC to LBEGIN 283 rsr a7, LBEG # set PC to LBEGIN
289 wsr a3, LCOUNT 284 wsr a5, LCOUNT
290#endif 285#endif
291 286
2921: wsr a7, EPC_1 # skip load instruction 2871: wsr a7, EPC_1 # skip load instruction
@@ -336,7 +331,7 @@ ENTRY(fast_unaligned)
336 331
337 movi a6, 0 # mask: ffffffff:00000000 332 movi a6, 0 # mask: ffffffff:00000000
338 333
339#if XCHAL_HAVE_NARROW 334#if XCHAL_HAVE_DENSITY
340 addi a7, a7, 2 # incr. PC,assume 16-bit instruction 335 addi a7, a7, 2 # incr. PC,assume 16-bit instruction
341 336
342 extui a5, a4, INSN_OP0, 4 # extract OP0 337 extui a5, a4, INSN_OP0, 4 # extract OP0
@@ -359,14 +354,14 @@ ENTRY(fast_unaligned)
359 /* Get memory address */ 354 /* Get memory address */
360 355
3611: 3561:
362#if XCHAL_HAVE_LOOP 357#if XCHAL_HAVE_LOOPS
363 rsr a3, LEND # check if we reached LEND 358 rsr a4, LEND # check if we reached LEND
364 bne a7, a3, 1f 359 bne a7, a4, 1f
365 rsr a3, LCOUNT # and LCOUNT != 0 360 rsr a4, LCOUNT # and LCOUNT != 0
366 beqz a3, 1f 361 beqz a4, 1f
367 addi a3, a3, -1 # decrement LCOUNT and set 362 addi a4, a4, -1 # decrement LCOUNT and set
368 rsr a7, LBEG # set PC to LBEGIN 363 rsr a7, LBEG # set PC to LBEGIN
369 wsr a3, LCOUNT 364 wsr a4, LCOUNT
370#endif 365#endif
371 366
3721: wsr a7, EPC_1 # skip store instruction 3671: wsr a7, EPC_1 # skip store instruction
@@ -416,6 +411,7 @@ ENTRY(fast_unaligned)
416 411
417 /* Restore working register */ 412 /* Restore working register */
418 413
414 l32i a8, a2, PT_AREG8
419 l32i a7, a2, PT_AREG7 415 l32i a7, a2, PT_AREG7
420 l32i a6, a2, PT_AREG6 416 l32i a6, a2, PT_AREG6
421 l32i a5, a2, PT_AREG5 417 l32i a5, a2, PT_AREG5
@@ -446,7 +442,7 @@ ENTRY(fast_unaligned)
446 mov a1, a2 442 mov a1, a2
447 443
448 rsr a0, PS 444 rsr a0, PS
449 bbsi.l a2, PS_UM_SHIFT, 1f # jump if user mode 445 bbsi.l a2, PS_UM_BIT, 1f # jump if user mode
450 446
451 movi a0, _kernel_exception 447 movi a0, _kernel_exception
452 jx a0 448 jx a0
diff --git a/arch/xtensa/kernel/asm-offsets.c b/arch/xtensa/kernel/asm-offsets.c
index 7cd1d7f8f608..b256cfbef344 100644
--- a/arch/xtensa/kernel/asm-offsets.c
+++ b/arch/xtensa/kernel/asm-offsets.c
@@ -87,6 +87,11 @@ int main(void)
87 DEFINE(MM_CONTEXT, offsetof (struct mm_struct, context)); 87 DEFINE(MM_CONTEXT, offsetof (struct mm_struct, context));
88 BLANK(); 88 BLANK();
89 DEFINE(PT_SINGLESTEP_BIT, PT_SINGLESTEP_BIT); 89 DEFINE(PT_SINGLESTEP_BIT, PT_SINGLESTEP_BIT);
90
91 /* constants */
92 DEFINE(_CLONE_VM, CLONE_VM);
93 DEFINE(_CLONE_UNTRACED, CLONE_UNTRACED);
94
90 return 0; 95 return 0;
91} 96}
92 97
diff --git a/arch/xtensa/kernel/coprocessor.S b/arch/xtensa/kernel/coprocessor.S
index cf5a93fb6a2e..01bcb9fcfcbd 100644
--- a/arch/xtensa/kernel/coprocessor.S
+++ b/arch/xtensa/kernel/coprocessor.S
@@ -90,7 +90,6 @@ ENTRY(enable_coprocessor)
90 rsync 90 rsync
91 retw 91 retw
92 92
93#endif
94 93
95ENTRY(save_coprocessor_extra) 94ENTRY(save_coprocessor_extra)
96 entry sp, 16 95 entry sp, 16
@@ -197,4 +196,5 @@ _xtensa_reginfo_tables:
197 XCHAL_CP7_SA_CONTENTS_LIBDB 196 XCHAL_CP7_SA_CONTENTS_LIBDB
198 .word 0xFC000000 /* invalid register number,marks end of table*/ 197 .word 0xFC000000 /* invalid register number,marks end of table*/
199_xtensa_reginfo_table_end: 198_xtensa_reginfo_table_end:
199#endif
200 200
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index 89e409e9e0de..9e271ba009bf 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -24,7 +24,7 @@
24#include <asm/pgtable.h> 24#include <asm/pgtable.h>
25#include <asm/page.h> 25#include <asm/page.h>
26#include <asm/signal.h> 26#include <asm/signal.h>
27#include <xtensa/coreasm.h> 27#include <asm/tlbflush.h>
28 28
29/* Unimplemented features. */ 29/* Unimplemented features. */
30 30
@@ -364,7 +364,7 @@ common_exception:
364 movi a2, 1 364 movi a2, 1
365 extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0] 365 extui a3, a3, 0, 1 # a3 = PS.INTLEVEL[0]
366 moveqz a3, a2, a0 # a3 = 1 iff interrupt exception 366 moveqz a3, a2, a0 # a3 = 1 iff interrupt exception
367 movi a2, PS_WOE_MASK 367 movi a2, 1 << PS_WOE_BIT
368 or a3, a3, a2 368 or a3, a3, a2
369 rsr a0, EXCCAUSE 369 rsr a0, EXCCAUSE
370 xsr a3, PS 370 xsr a3, PS
@@ -399,7 +399,7 @@ common_exception_return:
399 /* Jump if we are returning from kernel exceptions. */ 399 /* Jump if we are returning from kernel exceptions. */
400 400
4011: l32i a3, a1, PT_PS 4011: l32i a3, a1, PT_PS
402 _bbsi.l a3, PS_UM_SHIFT, 2f 402 _bbsi.l a3, PS_UM_BIT, 2f
403 j kernel_exception_exit 403 j kernel_exception_exit
404 404
405 /* Specific to a user exception exit: 405 /* Specific to a user exception exit:
@@ -422,7 +422,7 @@ common_exception_return:
422 * (Hint: There is only one user exception frame on stack) 422 * (Hint: There is only one user exception frame on stack)
423 */ 423 */
424 424
425 movi a3, PS_WOE_MASK 425 movi a3, 1 << PS_WOE_BIT
426 426
427 _bbsi.l a4, TIF_NEED_RESCHED, 3f 427 _bbsi.l a4, TIF_NEED_RESCHED, 3f
428 _bbci.l a4, TIF_SIGPENDING, 4f 428 _bbci.l a4, TIF_SIGPENDING, 4f
@@ -694,7 +694,7 @@ common_exception_exit:
694ENTRY(debug_exception) 694ENTRY(debug_exception)
695 695
696 rsr a0, EPS + XCHAL_DEBUGLEVEL 696 rsr a0, EPS + XCHAL_DEBUGLEVEL
697 bbsi.l a0, PS_EXCM_SHIFT, 1f # exception mode 697 bbsi.l a0, PS_EXCM_BIT, 1f # exception mode
698 698
699 /* Set EPC_1 and EXCCAUSE */ 699 /* Set EPC_1 and EXCCAUSE */
700 700
@@ -707,7 +707,7 @@ ENTRY(debug_exception)
707 707
708 /* Restore PS to the value before the debug exc but with PS.EXCM set.*/ 708 /* Restore PS to the value before the debug exc but with PS.EXCM set.*/
709 709
710 movi a2, 1 << PS_EXCM_SHIFT 710 movi a2, 1 << PS_EXCM_BIT
711 or a2, a0, a2 711 or a2, a0, a2
712 movi a0, debug_exception # restore a3, debug jump vector 712 movi a0, debug_exception # restore a3, debug jump vector
713 wsr a2, PS 713 wsr a2, PS
@@ -715,7 +715,7 @@ ENTRY(debug_exception)
715 715
716 /* Switch to kernel/user stack, restore jump vector, and save a0 */ 716 /* Switch to kernel/user stack, restore jump vector, and save a0 */
717 717
718 bbsi.l a2, PS_UM_SHIFT, 2f # jump if user mode 718 bbsi.l a2, PS_UM_BIT, 2f # jump if user mode
719 719
720 addi a2, a1, -16-PT_SIZE # assume kernel stack 720 addi a2, a1, -16-PT_SIZE # assume kernel stack
721 s32i a0, a2, PT_AREG0 721 s32i a0, a2, PT_AREG0
@@ -778,7 +778,7 @@ ENTRY(unrecoverable_exception)
778 wsr a1, WINDOWBASE 778 wsr a1, WINDOWBASE
779 rsync 779 rsync
780 780
781 movi a1, PS_WOE_MASK | 1 781 movi a1, (1 << PS_WOE_BIT) | 1
782 wsr a1, PS 782 wsr a1, PS
783 rsync 783 rsync
784 784
@@ -1004,13 +1004,10 @@ ENTRY(fast_syscall_kernel)
1004 1004
1005 rsr a0, DEPC # get syscall-nr 1005 rsr a0, DEPC # get syscall-nr
1006 _beqz a0, fast_syscall_spill_registers 1006 _beqz a0, fast_syscall_spill_registers
1007 1007 _beqi a0, __NR_xtensa, fast_syscall_xtensa
1008 addi a0, a0, -__NR_sysxtensa
1009 _beqz a0, fast_syscall_sysxtensa
1010 1008
1011 j kernel_exception 1009 j kernel_exception
1012 1010
1013
1014ENTRY(fast_syscall_user) 1011ENTRY(fast_syscall_user)
1015 1012
1016 /* Skip syscall. */ 1013 /* Skip syscall. */
@@ -1024,9 +1021,7 @@ ENTRY(fast_syscall_user)
1024 1021
1025 rsr a0, DEPC # get syscall-nr 1022 rsr a0, DEPC # get syscall-nr
1026 _beqz a0, fast_syscall_spill_registers 1023 _beqz a0, fast_syscall_spill_registers
1027 1024 _beqi a0, __NR_xtensa, fast_syscall_xtensa
1028 addi a0, a0, -__NR_sysxtensa
1029 _beqz a0, fast_syscall_sysxtensa
1030 1025
1031 j user_exception 1026 j user_exception
1032 1027
@@ -1047,18 +1042,19 @@ ENTRY(fast_syscall_unrecoverable)
1047/* 1042/*
1048 * sysxtensa syscall handler 1043 * sysxtensa syscall handler
1049 * 1044 *
1050 * int sysxtensa (XTENSA_ATOMIC_SET, ptr, val, unused); 1045 * int sysxtensa (SYS_XTENSA_ATOMIC_SET, ptr, val, unused);
1051 * int sysxtensa (XTENSA_ATOMIC_ADD, ptr, val, unused); 1046 * int sysxtensa (SYS_XTENSA_ATOMIC_ADD, ptr, val, unused);
1052 * int sysxtensa (XTENSA_ATOMIC_EXG_ADD, ptr, val, unused); 1047 * int sysxtensa (SYS_XTENSA_ATOMIC_EXG_ADD, ptr, val, unused);
1053 * int sysxtensa (XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval); 1048 * int sysxtensa (SYS_XTENSA_ATOMIC_CMP_SWP, ptr, oldval, newval);
1054 * a2 a6 a3 a4 a5 1049 * a2 a6 a3 a4 a5
1055 * 1050 *
1056 * Entry condition: 1051 * Entry condition:
1057 * 1052 *
1058 * a0: trashed, original value saved on stack (PT_AREG0) 1053 * a0: a2 (syscall-nr), original value saved on stack (PT_AREG0)
1059 * a1: a1 1054 * a1: a1
1060 * a2: new stack pointer, original in DEPC 1055 * a2: new stack pointer, original in a0 and DEPC
1061 * a3: dispatch table 1056 * a3: dispatch table, original in excsave_1
1057 * a4..a15: unchanged
1062 * depc: a2, original value saved on stack (PT_DEPC) 1058 * depc: a2, original value saved on stack (PT_DEPC)
1063 * excsave_1: a3 1059 * excsave_1: a3
1064 * 1060 *
@@ -1091,59 +1087,62 @@ ENTRY(fast_syscall_unrecoverable)
1091#define CATCH \ 1087#define CATCH \
109267: 108867:
1093 1089
1094ENTRY(fast_syscall_sysxtensa) 1090ENTRY(fast_syscall_xtensa)
1095
1096 _beqz a6, 1f
1097 _blti a6, SYSXTENSA_COUNT, 2f
1098 1091
10991: j user_exception 1092 xsr a3, EXCSAVE_1 # restore a3, excsave1
1100
11012: xsr a3, EXCSAVE_1 # restore a3, excsave1
1102 s32i a7, a2, PT_AREG7
1103 1093
1094 s32i a7, a2, PT_AREG7 # we need an additional register
1104 movi a7, 4 # sizeof(unsigned int) 1095 movi a7, 4 # sizeof(unsigned int)
1105 access_ok a0, a3, a7, a2, .Leac 1096 access_ok a3, a7, a0, a2, .Leac # a0: scratch reg, a2: sp
1106 1097
1107 _beqi a6, SYSXTENSA_ATOMIC_SET, .Lset 1098 addi a6, a6, -1 # assuming SYS_XTENSA_ATOMIC_SET = 1
1108 _beqi a6, SYSXTENSA_ATOMIC_EXG_ADD, .Lexg 1099 _bgeui a6, SYS_XTENSA_COUNT - 1, .Lill
1109 _beqi a6, SYSXTENSA_ATOMIC_ADD, .Ladd 1100 _bnei a6, SYS_XTENSA_ATOMIC_CMP_SWP - 1, .Lnswp
1110 1101
1111 /* Fall through for SYSXTENSA_ATOMIC_CMP_SWP */ 1102 /* Fall through for ATOMIC_CMP_SWP. */
1112 1103
1113.Lswp: /* Atomic compare and swap */ 1104.Lswp: /* Atomic compare and swap */
1114 1105
1115TRY l32i a7, a3, 0 # read old value 1106TRY l32i a0, a3, 0 # read old value
1116 bne a7, a4, 1f # same as old value? jump 1107 bne a0, a4, 1f # same as old value? jump
1117 s32i a5, a3, 0 # different, modify value 1108TRY s32i a5, a3, 0 # different, modify value
1118 movi a7, 1 # and return 1 1109 l32i a7, a2, PT_AREG7 # restore a7
1119 j .Lret 1110 l32i a0, a2, PT_AREG0 # restore a0
1120 1111 movi a2, 1 # and return 1
11211: movi a7, 0 # same values: return 0 1112 addi a6, a6, 1 # restore a6 (really necessary?)
1122 j .Lret 1113 rfe
1123
1124.Ladd: /* Atomic add */
1125.Lexg: /* Atomic (exchange) add */
1126 1114
1127TRY l32i a7, a3, 0 11151: l32i a7, a2, PT_AREG7 # restore a7
1128 add a4, a4, a7 1116 l32i a0, a2, PT_AREG0 # restore a0
1129 s32i a4, a3, 0 1117 movi a2, 0 # return 0 (note that we cannot set
1130 j .Lret 1118 addi a6, a6, 1 # restore a6 (really necessary?)
1119 rfe
1131 1120
1132.Lset: /* Atomic set */ 1121.Lnswp: /* Atomic set, add, and exg_add. */
1133 1122
1134TRY l32i a7, a3, 0 # read old value as return value 1123TRY l32i a7, a3, 0 # orig
1135 s32i a4, a3, 0 # write new value 1124 add a0, a4, a7 # + arg
1125 moveqz a0, a4, a6 # set
1126TRY s32i a0, a3, 0 # write new value
1136 1127
1137.Lret: mov a0, a2 1128 mov a0, a2
1138 mov a2, a7 1129 mov a2, a7
1139 l32i a7, a0, PT_AREG7 1130 l32i a7, a0, PT_AREG7 # restore a7
1140 l32i a3, a0, PT_AREG3 1131 l32i a0, a0, PT_AREG0 # restore a0
1141 l32i a0, a0, PT_AREG0 1132 addi a6, a6, 1 # restore a6 (really necessary?)
1142 rfe 1133 rfe
1143 1134
1144CATCH 1135CATCH
1145.Leac: movi a7, -EFAULT 1136.Leac: l32i a7, a2, PT_AREG7 # restore a7
1146 j .Lret 1137 l32i a0, a2, PT_AREG0 # restore a0
1138 movi a2, -EFAULT
1139 rfe
1140
1141.Lill: l32i a7, a2, PT_AREG0 # restore a7
1142 l32i a0, a2, PT_AREG0 # restore a0
1143 movi a2, -EINVAL
1144 rfe
1145
1147 1146
1148 1147
1149 1148
@@ -1491,7 +1490,7 @@ ENTRY(_spill_registers)
1491 */ 1490 */
1492 1491
1493 rsr a0, PS 1492 rsr a0, PS
1494 _bbci.l a0, PS_UM_SHIFT, 1f 1493 _bbci.l a0, PS_UM_BIT, 1f
1495 1494
1496 /* User space: Setup a dummy frame and kill application. 1495 /* User space: Setup a dummy frame and kill application.
1497 * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer. 1496 * Note: We assume EXC_TABLE_KSTK contains a valid stack pointer.
@@ -1510,7 +1509,7 @@ ENTRY(_spill_registers)
1510 l32i a1, a3, EXC_TABLE_KSTK 1509 l32i a1, a3, EXC_TABLE_KSTK
1511 wsr a3, EXCSAVE_1 1510 wsr a3, EXCSAVE_1
1512 1511
1513 movi a4, PS_WOE_MASK | 1 1512 movi a4, (1 << PS_WOE_BIT) | 1
1514 wsr a4, PS 1513 wsr a4, PS
1515 rsync 1514 rsync
1516 1515
@@ -1612,7 +1611,7 @@ ENTRY(fast_second_level_miss)
1612 rsr a1, PTEVADDR 1611 rsr a1, PTEVADDR
1613 srli a1, a1, PAGE_SHIFT 1612 srli a1, a1, PAGE_SHIFT
1614 slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK 1613 slli a1, a1, PAGE_SHIFT # ptevaddr & PAGE_MASK
1615 addi a1, a1, DTLB_WAY_PGTABLE # ... + way_number 1614 addi a1, a1, DTLB_WAY_PGD # ... + way_number
1616 1615
1617 wdtlb a0, a1 1616 wdtlb a0, a1
1618 dsync 1617 dsync
@@ -1654,7 +1653,7 @@ ENTRY(fast_second_level_miss)
1654 mov a1, a2 1653 mov a1, a2
1655 1654
1656 rsr a2, PS 1655 rsr a2, PS
1657 bbsi.l a2, PS_UM_SHIFT, 1f 1656 bbsi.l a2, PS_UM_BIT, 1f
1658 j _kernel_exception 1657 j _kernel_exception
16591: j _user_exception 16581: j _user_exception
1660 1659
@@ -1753,7 +1752,7 @@ ENTRY(fast_store_prohibited)
1753 mov a1, a2 1752 mov a1, a2
1754 1753
1755 rsr a2, PS 1754 rsr a2, PS
1756 bbsi.l a2, PS_UM_SHIFT, 1f 1755 bbsi.l a2, PS_UM_BIT, 1f
1757 j _kernel_exception 1756 j _kernel_exception
17581: j _user_exception 17571: j _user_exception
1759 1758
@@ -1907,6 +1906,103 @@ ENTRY(fast_coprocessor)
1907#endif /* XCHAL_EXTRA_SA_SIZE */ 1906#endif /* XCHAL_EXTRA_SA_SIZE */
1908 1907
1909/* 1908/*
1909 * System Calls.
1910 *
1911 * void system_call (struct pt_regs* regs, int exccause)
1912 * a2 a3
1913 */
1914
1915ENTRY(system_call)
1916 entry a1, 32
1917
1918 /* regs->syscall = regs->areg[2] */
1919
1920 l32i a3, a2, PT_AREG2
1921 mov a6, a2
1922 movi a4, do_syscall_trace_enter
1923 s32i a3, a2, PT_SYSCALL
1924 callx4 a4
1925
1926 /* syscall = sys_call_table[syscall_nr] */
1927
1928 movi a4, sys_call_table;
1929 movi a5, __NR_syscall_count
1930 movi a6, -ENOSYS
1931 bgeu a3, a5, 1f
1932
1933 addx4 a4, a3, a4
1934 l32i a4, a4, 0
1935 movi a5, sys_ni_syscall;
1936 beq a4, a5, 1f
1937
1938 /* Load args: arg0 - arg5 are passed via regs. */
1939
1940 l32i a6, a2, PT_AREG6
1941 l32i a7, a2, PT_AREG3
1942 l32i a8, a2, PT_AREG4
1943 l32i a9, a2, PT_AREG5
1944 l32i a10, a2, PT_AREG8
1945 l32i a11, a2, PT_AREG9
1946
1947 /* Pass one additional argument to the syscall: pt_regs (on stack) */
1948 s32i a2, a1, 0
1949
1950 callx4 a4
1951
19521: /* regs->areg[2] = return_value */
1953
1954 s32i a6, a2, PT_AREG2
1955 movi a4, do_syscall_trace_leave
1956 mov a6, a2
1957 callx4 a4
1958 retw
1959
1960
1961/*
1962 * Create a kernel thread
1963 *
1964 * int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags)
1965 * a2 a2 a3 a4
1966 */
1967
1968ENTRY(kernel_thread)
1969 entry a1, 16
1970
1971 mov a5, a2 # preserve fn over syscall
1972 mov a7, a3 # preserve args over syscall
1973
1974 movi a3, _CLONE_VM | _CLONE_UNTRACED
1975 movi a2, __NR_clone
1976 or a6, a4, a3 # arg0: flags
1977 mov a3, a1 # arg1: sp
1978 syscall
1979
1980 beq a3, a1, 1f # branch if parent
1981 mov a6, a7 # args
1982 callx4 a5 # fn(args)
1983
1984 movi a2, __NR_exit
1985 syscall # return value of fn(args) still in a6
1986
19871: retw
1988
1989/*
1990 * Do a system call from kernel instead of calling sys_execve, so we end up
1991 * with proper pt_regs.
1992 *
1993 * int kernel_execve(const char *fname, char *const argv[], charg *const envp[])
1994 * a2 a2 a3 a4
1995 */
1996
1997ENTRY(kernel_execve)
1998 entry a1, 16
1999 mov a6, a2 # arg0 is in a6
2000 movi a2, __NR_execve
2001 syscall
2002
2003 retw
2004
2005/*
1910 * Task switch. 2006 * Task switch.
1911 * 2007 *
1912 * struct task* _switch_to (struct task* prev, struct task* next) 2008 * struct task* _switch_to (struct task* prev, struct task* next)
@@ -1924,7 +2020,7 @@ ENTRY(_switch_to)
1924 2020
1925 /* Disable ints while we manipulate the stack pointer; spill regs. */ 2021 /* Disable ints while we manipulate the stack pointer; spill regs. */
1926 2022
1927 movi a5, PS_EXCM_MASK | LOCKLEVEL 2023 movi a5, (1 << PS_EXCM_BIT) | LOCKLEVEL
1928 xsr a5, PS 2024 xsr a5, PS
1929 rsr a3, EXCSAVE_1 2025 rsr a3, EXCSAVE_1
1930 rsync 2026 rsync
@@ -1964,33 +2060,9 @@ ENTRY(ret_from_fork)
1964 movi a4, schedule_tail 2060 movi a4, schedule_tail
1965 callx4 a4 2061 callx4 a4
1966 2062
1967 movi a4, do_syscall_trace 2063 movi a4, do_syscall_trace_leave
2064 mov a6, a1
1968 callx4 a4 2065 callx4 a4
1969 2066
1970 j common_exception_return 2067 j common_exception_return
1971 2068
1972
1973
1974/*
1975 * Table of syscalls
1976 */
1977
1978.data
1979.align 4
1980.global sys_call_table
1981sys_call_table:
1982
1983#define SYSCALL(call, narg) .word call
1984#include "syscalls.h"
1985
1986/*
1987 * Number of arguments of each syscall
1988 */
1989
1990.global sys_narg_table
1991sys_narg_table:
1992
1993#undef SYSCALL
1994#define SYSCALL(call, narg) .byte narg
1995#include "syscalls.h"
1996
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index c07cb2522993..ea89910efa44 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -15,9 +15,9 @@
15 * Kevin Chea 15 * Kevin Chea
16 */ 16 */
17 17
18#include <xtensa/cacheasm.h>
19#include <asm/processor.h> 18#include <asm/processor.h>
20#include <asm/page.h> 19#include <asm/page.h>
20#include <asm/cacheasm.h>
21 21
22/* 22/*
23 * This module contains the entry code for kernel images. It performs the 23 * This module contains the entry code for kernel images. It performs the
@@ -32,13 +32,6 @@
32 * 32 *
33 */ 33 */
34 34
35 .macro iterate from, to , cmd
36 .ifeq ((\to - \from) & ~0xfff)
37 \cmd \from
38 iterate "(\from+1)", \to, \cmd
39 .endif
40 .endm
41
42/* 35/*
43 * _start 36 * _start
44 * 37 *
@@ -64,7 +57,7 @@ _startup:
64 57
65 /* Disable interrupts and exceptions. */ 58 /* Disable interrupts and exceptions. */
66 59
67 movi a0, XCHAL_PS_EXCM_MASK 60 movi a0, LOCKLEVEL
68 wsr a0, PS 61 wsr a0, PS
69 62
70 /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */ 63 /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */
@@ -91,11 +84,11 @@ _startup:
91 movi a1, 15 84 movi a1, 15
92 wsr a0, ICOUNTLEVEL 85 wsr a0, ICOUNTLEVEL
93 86
94 .macro reset_dbreak num 87 .set _index, 0
95 wsr a0, DBREAKC + \num 88 .rept XCHAL_NUM_DBREAK - 1
96 .endm 89 wsr a0, DBREAKC + _index
97 90 .set _index, _index + 1
98 iterate 0, XCHAL_NUM_IBREAK-1, reset_dbreak 91 .endr
99#endif 92#endif
100 93
101 /* Clear CCOUNT (not really necessary, but nice) */ 94 /* Clear CCOUNT (not really necessary, but nice) */
@@ -110,10 +103,11 @@ _startup:
110 103
111 /* Disable all timers. */ 104 /* Disable all timers. */
112 105
113 .macro reset_timer num 106 .set _index, 0
114 wsr a0, CCOMPARE_0 + \num 107 .rept XCHAL_NUM_TIMERS - 1
115 .endm 108 wsr a0, CCOMPARE + _index
116 iterate 0, XCHAL_NUM_TIMERS-1, reset_timer 109 .set _index, _index + 1
110 .endr
117 111
118 /* Interrupt initialization. */ 112 /* Interrupt initialization. */
119 113
@@ -139,12 +133,21 @@ _startup:
139 rsync 133 rsync
140 134
141 /* Initialize the caches. 135 /* Initialize the caches.
142 * Does not include flushing writeback d-cache. 136 * a2, a3 are just working registers (clobbered).
143 * a6, a7 are just working registers (clobbered).
144 */ 137 */
145 138
146 icache_reset a2, a3 139#if XCHAL_DCACHE_LINE_LOCKABLE
147 dcache_reset a2, a3 140 ___unlock_dcache_all a2 a3
141#endif
142
143#if XCHAL_ICACHE_LINE_LOCKABLE
144 ___unlock_icache_all a2 a3
145#endif
146
147 ___invalidate_dcache_all a2 a3
148 ___invalidate_icache_all a2 a3
149
150 isync
148 151
149 /* Unpack data sections 152 /* Unpack data sections
150 * 153 *
@@ -181,9 +184,9 @@ _startup:
181 movi a2, _bss_start # start of BSS 184 movi a2, _bss_start # start of BSS
182 movi a3, _bss_end # end of BSS 185 movi a3, _bss_end # end of BSS
183 186
1841: addi a2, a2, 4 187 __loopt a2, a3, a4, 2
185 s32i a0, a2, 0 188 s32i a0, a2, 0
186 blt a2, a3, 1b 189 __endla a2, a4, 4
187 190
188#if XCHAL_DCACHE_IS_WRITEBACK 191#if XCHAL_DCACHE_IS_WRITEBACK
189 192
@@ -191,7 +194,7 @@ _startup:
191 * instructions/data are available. 194 * instructions/data are available.
192 */ 195 */
193 196
194 dcache_writeback_all a2, a3 197 ___flush_dcache_all a2 a3
195#endif 198#endif
196 199
197 /* Setup stack and enable window exceptions (keep irqs disabled) */ 200 /* Setup stack and enable window exceptions (keep irqs disabled) */
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c
index 1cf744ee0959..c9ea73b7031b 100644
--- a/arch/xtensa/kernel/irq.c
+++ b/arch/xtensa/kernel/irq.c
@@ -4,7 +4,7 @@
4 * Xtensa built-in interrupt controller and some generic functions copied 4 * Xtensa built-in interrupt controller and some generic functions copied
5 * from i386. 5 * from i386.
6 * 6 *
7 * Copyright (C) 2002 - 2005 Tensilica, Inc. 7 * Copyright (C) 2002 - 2006 Tensilica, Inc.
8 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar 8 * Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar
9 * 9 *
10 * 10 *
@@ -22,11 +22,6 @@
22#include <asm/uaccess.h> 22#include <asm/uaccess.h>
23#include <asm/platform.h> 23#include <asm/platform.h>
24 24
25static void enable_xtensa_irq(unsigned int irq);
26static void disable_xtensa_irq(unsigned int irq);
27static void mask_and_ack_xtensa(unsigned int irq);
28static void end_xtensa_irq(unsigned int irq);
29
30static unsigned int cached_irq_mask; 25static unsigned int cached_irq_mask;
31 26
32atomic_t irq_err_count; 27atomic_t irq_err_count;
@@ -46,8 +41,16 @@ void ack_bad_irq(unsigned int irq)
46 * handlers). 41 * handlers).
47 */ 42 */
48 43
49unsigned int do_IRQ(int irq, struct pt_regs *regs) 44asmlinkage void do_IRQ(int irq, struct pt_regs *regs)
50{ 45{
46 struct pt_regs *old_regs = set_irq_regs(regs);
47 struct irq_desc *desc = irq_desc + irq;
48
49 if (irq >= NR_IRQS) {
50 printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
51 __FUNCTION__, irq);
52 }
53
51 irq_enter(); 54 irq_enter();
52 55
53#ifdef CONFIG_DEBUG_STACKOVERFLOW 56#ifdef CONFIG_DEBUG_STACKOVERFLOW
@@ -63,12 +66,10 @@ unsigned int do_IRQ(int irq, struct pt_regs *regs)
63 sp - sizeof(struct thread_info)); 66 sp - sizeof(struct thread_info));
64 } 67 }
65#endif 68#endif
66 69 desc->handle_irq(irq, desc);
67 __do_IRQ(irq, regs);
68 70
69 irq_exit(); 71 irq_exit();
70 72 set_irq_regs(old_regs);
71 return 1;
72} 73}
73 74
74/* 75/*
@@ -118,72 +119,68 @@ skip:
118 } 119 }
119 return 0; 120 return 0;
120} 121}
121/* shutdown is same as "disable" */
122#define shutdown_xtensa_irq disable_xtensa_irq
123 122
124static unsigned int startup_xtensa_irq(unsigned int irq) 123static void xtensa_irq_mask(unsigned int irq)
125{
126 enable_xtensa_irq(irq);
127 return 0; /* never anything pending */
128}
129
130static struct hw_interrupt_type xtensa_irq_type = {
131 "Xtensa-IRQ",
132 startup_xtensa_irq,
133 shutdown_xtensa_irq,
134 enable_xtensa_irq,
135 disable_xtensa_irq,
136 mask_and_ack_xtensa,
137 end_xtensa_irq
138};
139
140static inline void mask_irq(unsigned int irq)
141{ 124{
142 cached_irq_mask &= ~(1 << irq); 125 cached_irq_mask &= ~(1 << irq);
143 set_sr (cached_irq_mask, INTENABLE); 126 set_sr (cached_irq_mask, INTENABLE);
144} 127}
145 128
146static inline void unmask_irq(unsigned int irq) 129static void xtensa_irq_unmask(unsigned int irq)
147{ 130{
148 cached_irq_mask |= 1 << irq; 131 cached_irq_mask |= 1 << irq;
149 set_sr (cached_irq_mask, INTENABLE); 132 set_sr (cached_irq_mask, INTENABLE);
150} 133}
151 134
152static void disable_xtensa_irq(unsigned int irq) 135static void xtensa_irq_ack(unsigned int irq)
153{ 136{
154 unsigned long flags; 137 set_sr(1 << irq, INTCLEAR);
155 local_save_flags(flags);
156 mask_irq(irq);
157 local_irq_restore(flags);
158} 138}
159 139
160static void enable_xtensa_irq(unsigned int irq) 140static int xtensa_irq_retrigger(unsigned int irq)
161{ 141{
162 unsigned long flags; 142 set_sr (1 << irq, INTSET);
163 local_save_flags(flags); 143 return 1;
164 unmask_irq(irq);
165 local_irq_restore(flags);
166}
167
168static void mask_and_ack_xtensa(unsigned int irq)
169{
170 disable_xtensa_irq(irq);
171} 144}
172 145
173static void end_xtensa_irq(unsigned int irq)
174{
175 enable_xtensa_irq(irq);
176}
177 146
147static struct irq_chip xtensa_irq_chip = {
148 .name = "xtensa",
149 .mask = xtensa_irq_mask,
150 .unmask = xtensa_irq_unmask,
151 .ack = xtensa_irq_ack,
152 .retrigger = xtensa_irq_retrigger,
153};
178 154
179void __init init_IRQ(void) 155void __init init_IRQ(void)
180{ 156{
181 int i; 157 int index;
182 158
183 for (i=0; i < XTENSA_NR_IRQS; i++) 159 for (index = 0; index < XTENSA_NR_IRQS; index++) {
184 irq_desc[i].chip = &xtensa_irq_type; 160 int mask = 1 << index;
185 161
186 cached_irq_mask = 0; 162 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE)
163 set_irq_chip_and_handler(index, &xtensa_irq_chip,
164 handle_simple_irq);
187 165
188 platform_init_irq(); 166 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE)
167 set_irq_chip_and_handler(index, &xtensa_irq_chip,
168 handle_edge_irq);
169
170 else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL)
171 set_irq_chip_and_handler(index, &xtensa_irq_chip,
172 handle_level_irq);
173
174 else if (mask & XCHAL_INTTYPE_MASK_TIMER)
175 set_irq_chip_and_handler(index, &xtensa_irq_chip,
176 handle_edge_irq);
177
178 else /* XCHAL_INTTYPE_MASK_WRITE_ERROR */
179 /* XCHAL_INTTYPE_MASK_NMI */
180
181 set_irq_chip_and_handler(index, &xtensa_irq_chip,
182 handle_level_irq);
183 }
184
185 cached_irq_mask = 0;
189} 186}
diff --git a/arch/xtensa/kernel/pci-dma.c b/arch/xtensa/kernel/pci-dma.c
index 6648fa9d9192..ca76f071666e 100644
--- a/arch/xtensa/kernel/pci-dma.c
+++ b/arch/xtensa/kernel/pci-dma.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * arch/xtensa/kernel/pci-dma.c 2 * arch/xtensa/pci-dma.c
3 * 3 *
4 * DMA coherent memory allocation. 4 * DMA coherent memory allocation.
5 * 5 *
@@ -29,28 +29,48 @@
29 */ 29 */
30 30
31void * 31void *
32dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) 32dma_alloc_coherent(struct device *dev,size_t size,dma_addr_t *handle,gfp_t flag)
33{ 33{
34 void *ret; 34 unsigned long ret;
35 unsigned long uncached = 0;
35 36
36 /* ignore region speicifiers */ 37 /* ignore region speicifiers */
37 gfp &= ~(__GFP_DMA | __GFP_HIGHMEM);
38 38
39 if (dev == NULL || (*dev->dma_mask < 0xffffffff)) 39 flag &= ~(__GFP_DMA | __GFP_HIGHMEM);
40 gfp |= GFP_DMA;
41 ret = (void *)__get_free_pages(gfp, get_order(size));
42 40
43 if (ret != NULL) { 41 if (dev == NULL || (dev->coherent_dma_mask < 0xffffffff))
44 memset(ret, 0, size); 42 flag |= GFP_DMA;
45 *handle = virt_to_bus(ret); 43 ret = (unsigned long)__get_free_pages(flag, get_order(size));
44
45 if (ret == 0)
46 return NULL;
47
48 /* We currently don't support coherent memory outside KSEG */
49
50 if (ret < XCHAL_KSEG_CACHED_VADDR
51 || ret >= XCHAL_KSEG_CACHED_VADDR + XCHAL_KSEG_SIZE)
52 BUG();
53
54
55 if (ret != 0) {
56 memset((void*) ret, 0, size);
57 uncached = ret+XCHAL_KSEG_BYPASS_VADDR-XCHAL_KSEG_CACHED_VADDR;
58 *handle = virt_to_bus((void*)ret);
59 __flush_invalidate_dcache_range(ret, size);
46 } 60 }
47 return (void*) BYPASS_ADDR((unsigned long)ret); 61
62 return (void*)uncached;
48} 63}
49 64
50void dma_free_coherent(struct device *hwdev, size_t size, 65void dma_free_coherent(struct device *hwdev, size_t size,
51 void *vaddr, dma_addr_t dma_handle) 66 void *vaddr, dma_addr_t dma_handle)
52{ 67{
53 free_pages(CACHED_ADDR((unsigned long)vaddr), get_order(size)); 68 long addr=(long)vaddr+XCHAL_KSEG_CACHED_VADDR-XCHAL_KSEG_BYPASS_VADDR;
69
70 if (addr < 0 || addr >= XCHAL_KSEG_SIZE)
71 BUG();
72
73 free_pages(addr, get_order(size));
54} 74}
55 75
56 76
diff --git a/arch/xtensa/kernel/process.c b/arch/xtensa/kernel/process.c
index a7c4178c2a8c..795bd5ac6f4c 100644
--- a/arch/xtensa/kernel/process.c
+++ b/arch/xtensa/kernel/process.c
@@ -1,4 +1,3 @@
1// TODO verify coprocessor handling
2/* 1/*
3 * arch/xtensa/kernel/process.c 2 * arch/xtensa/kernel/process.c
4 * 3 *
@@ -43,7 +42,7 @@
43#include <asm/irq.h> 42#include <asm/irq.h>
44#include <asm/atomic.h> 43#include <asm/atomic.h>
45#include <asm/asm-offsets.h> 44#include <asm/asm-offsets.h>
46#include <asm/coprocessor.h> 45#include <asm/regs.h>
47 46
48extern void ret_from_fork(void); 47extern void ret_from_fork(void);
49 48
@@ -67,25 +66,6 @@ void (*pm_power_off)(void) = NULL;
67EXPORT_SYMBOL(pm_power_off); 66EXPORT_SYMBOL(pm_power_off);
68 67
69 68
70#if XCHAL_CP_NUM > 0
71
72/*
73 * Coprocessor ownership.
74 */
75
76coprocessor_info_t coprocessor_info[] = {
77 { 0, XTENSA_CPE_CP0_OFFSET },
78 { 0, XTENSA_CPE_CP1_OFFSET },
79 { 0, XTENSA_CPE_CP2_OFFSET },
80 { 0, XTENSA_CPE_CP3_OFFSET },
81 { 0, XTENSA_CPE_CP4_OFFSET },
82 { 0, XTENSA_CPE_CP5_OFFSET },
83 { 0, XTENSA_CPE_CP6_OFFSET },
84 { 0, XTENSA_CPE_CP7_OFFSET },
85};
86
87#endif
88
89/* 69/*
90 * Powermanagement idle function, if any is provided by the platform. 70 * Powermanagement idle function, if any is provided by the platform.
91 */ 71 */
@@ -110,12 +90,10 @@ void cpu_idle(void)
110 90
111void exit_thread(void) 91void exit_thread(void)
112{ 92{
113 release_coprocessors(current); /* Empty macro if no CPs are defined */
114} 93}
115 94
116void flush_thread(void) 95void flush_thread(void)
117{ 96{
118 release_coprocessors(current); /* Empty macro if no CPs are defined */
119} 97}
120 98
121/* 99/*
@@ -183,36 +161,6 @@ int copy_thread(int nr, unsigned long clone_flags, unsigned long usp,
183 161
184 162
185/* 163/*
186 * Create a kernel thread
187 */
188
189int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags)
190{
191 long retval;
192 __asm__ __volatile__
193 ("mov a5, %4\n\t" /* preserve fn in a5 */
194 "mov a6, %3\n\t" /* preserve and setup arg in a6 */
195 "movi a2, %1\n\t" /* load __NR_clone for syscall*/
196 "mov a3, sp\n\t" /* sp check and sys_clone */
197 "mov a4, %5\n\t" /* load flags for syscall */
198 "syscall\n\t"
199 "beq a3, sp, 1f\n\t" /* branch if parent */
200 "callx4 a5\n\t" /* call fn */
201 "movi a2, %2\n\t" /* load __NR_exit for syscall */
202 "mov a3, a6\n\t" /* load fn return value */
203 "syscall\n"
204 "1:\n\t"
205 "mov %0, a2\n\t" /* parent returns zero */
206 :"=r" (retval)
207 :"i" (__NR_clone), "i" (__NR_exit),
208 "r" (arg), "r" (fn),
209 "r" (flags | CLONE_VM)
210 : "a2", "a3", "a4", "a5", "a6" );
211 return retval;
212}
213
214
215/*
216 * These bracket the sleeping functions.. 164 * These bracket the sleeping functions..
217 */ 165 */
218 166
@@ -275,7 +223,7 @@ void do_copy_regs (xtensa_gregset_t *elfregs, struct pt_regs *regs,
275 */ 223 */
276 224
277 elfregs->pc = regs->pc; 225 elfregs->pc = regs->pc;
278 elfregs->ps = (regs->ps & ~XCHAL_PS_EXCM_MASK); 226 elfregs->ps = (regs->ps & ~(1 << PS_EXCM_BIT));
279 elfregs->exccause = regs->exccause; 227 elfregs->exccause = regs->exccause;
280 elfregs->excvaddr = regs->excvaddr; 228 elfregs->excvaddr = regs->excvaddr;
281 elfregs->windowbase = regs->windowbase; 229 elfregs->windowbase = regs->windowbase;
@@ -325,7 +273,7 @@ void do_restore_regs (xtensa_gregset_t *elfregs, struct pt_regs *regs,
325 */ 273 */
326 274
327 regs->pc = elfregs->pc; 275 regs->pc = elfregs->pc;
328 regs->ps = (elfregs->ps | XCHAL_PS_EXCM_MASK); 276 regs->ps = (elfregs->ps | (1 << PS_EXCM_BIT));
329 regs->exccause = elfregs->exccause; 277 regs->exccause = elfregs->exccause;
330 regs->excvaddr = elfregs->excvaddr; 278 regs->excvaddr = elfregs->excvaddr;
331 regs->windowbase = elfregs->windowbase; 279 regs->windowbase = elfregs->windowbase;
@@ -459,16 +407,7 @@ int do_restore_fpregs (elf_fpregset_t *fpregs, struct pt_regs *regs,
459int 407int
460dump_task_fpu(struct pt_regs *regs, struct task_struct *task, elf_fpregset_t *r) 408dump_task_fpu(struct pt_regs *regs, struct task_struct *task, elf_fpregset_t *r)
461{ 409{
462/* see asm/coprocessor.h for this magic number 16 */
463#if XTENSA_CP_EXTRA_SIZE > 16
464 do_save_fpregs (r, regs, task);
465
466 /* For now, bit 16 means some extra state may be present: */
467// FIXME!! need to track to return more accurate mask
468 return 0x10000 | XCHAL_CP_MASK;
469#else
470 return 0; /* no coprocessors active on this processor */ 410 return 0; /* no coprocessors active on this processor */
471#endif
472} 411}
473 412
474/* 413/*
@@ -483,3 +422,44 @@ int dump_fpu(struct pt_regs *regs, elf_fpregset_t *r)
483{ 422{
484 return dump_task_fpu(regs, current, r); 423 return dump_task_fpu(regs, current, r);
485} 424}
425
426asmlinkage
427long xtensa_clone(unsigned long clone_flags, unsigned long newsp,
428 void __user *parent_tid, void *child_tls,
429 void __user *child_tid, long a5,
430 struct pt_regs *regs)
431{
432 if (!newsp)
433 newsp = regs->areg[1];
434 return do_fork(clone_flags, newsp, regs, 0, parent_tid, child_tid);
435}
436
437/*
438 * * xtensa_execve() executes a new program.
439 * */
440
441asmlinkage
442long xtensa_execve(char __user *name, char __user * __user *argv,
443 char __user * __user *envp,
444 long a3, long a4, long a5,
445 struct pt_regs *regs)
446{
447 long error;
448 char * filename;
449
450 filename = getname(name);
451 error = PTR_ERR(filename);
452 if (IS_ERR(filename))
453 goto out;
454 // FIXME: release coprocessor??
455 error = do_execve(filename, argv, envp, regs);
456 if (error == 0) {
457 task_lock(current);
458 current->ptrace &= ~PT_DTRACE;
459 task_unlock(current);
460 }
461 putname(filename);
462out:
463 return error;
464}
465
diff --git a/arch/xtensa/kernel/ptrace.c b/arch/xtensa/kernel/ptrace.c
index 9aea23cc0dc5..8b6d3d0623b6 100644
--- a/arch/xtensa/kernel/ptrace.c
+++ b/arch/xtensa/kernel/ptrace.c
@@ -96,7 +96,7 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
96 /* Note: PS.EXCM is not set while user task is running; 96 /* Note: PS.EXCM is not set while user task is running;
97 * its being set in regs is for exception handling 97 * its being set in regs is for exception handling
98 * convenience. */ 98 * convenience. */
99 tmp = (regs->ps & ~XCHAL_PS_EXCM_MASK); 99 tmp = (regs->ps & ~(1 << PS_EXCM_BIT));
100 break; 100 break;
101 case REG_WB: 101 case REG_WB:
102 tmp = regs->windowbase; 102 tmp = regs->windowbase;
@@ -332,12 +332,6 @@ long arch_ptrace(struct task_struct *child, long request, long addr, long data)
332 332
333void do_syscall_trace(void) 333void do_syscall_trace(void)
334{ 334{
335 if (!test_thread_flag(TIF_SYSCALL_TRACE))
336 return;
337
338 if (!(current->ptrace & PT_PTRACED))
339 return;
340
341 /* 335 /*
342 * The 0x80 provides a way for the tracing parent to distinguish 336 * The 0x80 provides a way for the tracing parent to distinguish
343 * between a syscall stop and SIGTRAP delivery 337 * between a syscall stop and SIGTRAP delivery
@@ -354,3 +348,23 @@ void do_syscall_trace(void)
354 current->exit_code = 0; 348 current->exit_code = 0;
355 } 349 }
356} 350}
351
352void do_syscall_trace_enter(struct pt_regs *regs)
353{
354 if (test_thread_flag(TIF_SYSCALL_TRACE)
355 && (current->ptrace & PT_PTRACED))
356 do_syscall_trace();
357
358#if 0
359 if (unlikely(current->audit_context))
360 audit_syscall_entry(current, AUDIT_ARCH_XTENSA..);
361#endif
362}
363
364void do_syscall_trace_leave(struct pt_regs *regs)
365{
366 if ((test_thread_flag(TIF_SYSCALL_TRACE))
367 && (current->ptrace & PT_PTRACED))
368 do_syscall_trace();
369}
370
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index c99ab72b41b6..b6374c09de20 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -42,8 +42,6 @@
42#include <asm/page.h> 42#include <asm/page.h>
43#include <asm/setup.h> 43#include <asm/setup.h>
44 44
45#include <xtensa/config/system.h>
46
47#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE) 45#if defined(CONFIG_VGA_CONSOLE) || defined(CONFIG_DUMMY_CONSOLE)
48struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16}; 46struct screen_info screen_info = { 0, 24, 0, 0, 0, 80, 0, 0, 0, 24, 1, 16};
49#endif 47#endif
@@ -336,7 +334,7 @@ c_show(struct seq_file *f, void *slot)
336 /* high-level stuff */ 334 /* high-level stuff */
337 seq_printf(f,"processor\t: 0\n" 335 seq_printf(f,"processor\t: 0\n"
338 "vendor_id\t: Tensilica\n" 336 "vendor_id\t: Tensilica\n"
339 "model\t\t: Xtensa " XCHAL_HW_RELEASE_NAME "\n" 337 "model\t\t: Xtensa " XCHAL_HW_VERSION_NAME "\n"
340 "core ID\t\t: " XCHAL_CORE_ID "\n" 338 "core ID\t\t: " XCHAL_CORE_ID "\n"
341 "build ID\t: 0x%x\n" 339 "build ID\t: 0x%x\n"
342 "byte order\t: %s\n" 340 "byte order\t: %s\n"
@@ -420,25 +418,6 @@ c_show(struct seq_file *f, void *slot)
420 XCHAL_NUM_TIMERS, 418 XCHAL_NUM_TIMERS,
421 XCHAL_DEBUGLEVEL); 419 XCHAL_DEBUGLEVEL);
422 420
423 /* Coprocessors */
424#if XCHAL_HAVE_CP
425 seq_printf(f, "coprocessors\t: %d\n", XCHAL_CP_NUM);
426#else
427 seq_printf(f, "coprocessors\t: none\n");
428#endif
429
430 /* {I,D}{RAM,ROM} and XLMI */
431 seq_printf(f,"inst ROMs\t: %d\n"
432 "inst RAMs\t: %d\n"
433 "data ROMs\t: %d\n"
434 "data RAMs\t: %d\n"
435 "XLMI ports\t: %d\n",
436 XCHAL_NUM_IROM,
437 XCHAL_NUM_IRAM,
438 XCHAL_NUM_DROM,
439 XCHAL_NUM_DRAM,
440 XCHAL_NUM_XLMI);
441
442 /* Cache */ 421 /* Cache */
443 seq_printf(f,"icache line size: %d\n" 422 seq_printf(f,"icache line size: %d\n"
444 "icache ways\t: %d\n" 423 "icache ways\t: %d\n"
@@ -466,24 +445,6 @@ c_show(struct seq_file *f, void *slot)
466 XCHAL_DCACHE_WAYS, 445 XCHAL_DCACHE_WAYS,
467 XCHAL_DCACHE_SIZE); 446 XCHAL_DCACHE_SIZE);
468 447
469 /* MMU */
470 seq_printf(f,"ASID bits\t: %d\n"
471 "ASID invalid\t: %d\n"
472 "ASID kernel\t: %d\n"
473 "rings\t\t: %d\n"
474 "itlb ways\t: %d\n"
475 "itlb AR ways\t: %d\n"
476 "dtlb ways\t: %d\n"
477 "dtlb AR ways\t: %d\n",
478 XCHAL_MMU_ASID_BITS,
479 XCHAL_MMU_ASID_INVALID,
480 XCHAL_MMU_ASID_KERNEL,
481 XCHAL_MMU_RINGS,
482 XCHAL_ITLB_WAYS,
483 XCHAL_ITLB_ARF_WAYS,
484 XCHAL_DTLB_WAYS,
485 XCHAL_DTLB_ARF_WAYS);
486
487 return 0; 448 return 0;
488} 449}
489 450
diff --git a/arch/xtensa/kernel/signal.c b/arch/xtensa/kernel/signal.c
index c494f0826fc5..c6d9880a4cdb 100644
--- a/arch/xtensa/kernel/signal.c
+++ b/arch/xtensa/kernel/signal.c
@@ -12,8 +12,8 @@
12 * 12 *
13 */ 13 */
14 14
15#include <xtensa/config/core.h> 15#include <asm/variant/core.h>
16#include <xtensa/hal.h> 16#include <asm/coprocessor.h>
17#include <linux/sched.h> 17#include <linux/sched.h>
18#include <linux/mm.h> 18#include <linux/mm.h>
19#include <linux/smp.h> 19#include <linux/smp.h>
@@ -46,7 +46,7 @@ extern struct task_struct *coproc_owners[];
46 * Atomically swap in the new signal mask, and wait for a signal. 46 * Atomically swap in the new signal mask, and wait for a signal.
47 */ 47 */
48 48
49int sys_sigsuspend(struct pt_regs *regs) 49int xtensa_sigsuspend(struct pt_regs *regs)
50{ 50{
51 old_sigset_t mask = (old_sigset_t) regs->areg[3]; 51 old_sigset_t mask = (old_sigset_t) regs->areg[3];
52 sigset_t saveset; 52 sigset_t saveset;
@@ -68,7 +68,7 @@ int sys_sigsuspend(struct pt_regs *regs)
68} 68}
69 69
70asmlinkage int 70asmlinkage int
71sys_rt_sigsuspend(struct pt_regs *regs) 71xtensa_rt_sigsuspend(struct pt_regs *regs)
72{ 72{
73 sigset_t *unewset = (sigset_t *) regs->areg[4]; 73 sigset_t *unewset = (sigset_t *) regs->areg[4];
74 size_t sigsetsize = (size_t) regs->areg[3]; 74 size_t sigsetsize = (size_t) regs->areg[3];
@@ -96,7 +96,7 @@ sys_rt_sigsuspend(struct pt_regs *regs)
96} 96}
97 97
98asmlinkage int 98asmlinkage int
99sys_sigaction(int sig, const struct old_sigaction *act, 99xtensa_sigaction(int sig, const struct old_sigaction *act,
100 struct old_sigaction *oact) 100 struct old_sigaction *oact)
101{ 101{
102 struct k_sigaction new_ka, old_ka; 102 struct k_sigaction new_ka, old_ka;
@@ -128,7 +128,7 @@ sys_sigaction(int sig, const struct old_sigaction *act,
128} 128}
129 129
130asmlinkage int 130asmlinkage int
131sys_sigaltstack(struct pt_regs *regs) 131xtensa_sigaltstack(struct pt_regs *regs)
132{ 132{
133 const stack_t *uss = (stack_t *) regs->areg[4]; 133 const stack_t *uss = (stack_t *) regs->areg[4];
134 stack_t *uoss = (stack_t *) regs->areg[3]; 134 stack_t *uoss = (stack_t *) regs->areg[3];
@@ -216,8 +216,8 @@ restore_sigcontext(struct pt_regs *regs, struct sigcontext *sc)
216 * handler, or the user mode value doesn't matter (e.g. PS.OWB). 216 * handler, or the user mode value doesn't matter (e.g. PS.OWB).
217 */ 217 */
218 err |= __get_user(ps, &sc->sc_ps); 218 err |= __get_user(ps, &sc->sc_ps);
219 regs->ps = (regs->ps & ~XCHAL_PS_CALLINC_MASK) 219 regs->ps = (regs->ps & ~PS_CALLINC_MASK)
220 | (ps & XCHAL_PS_CALLINC_MASK); 220 | (ps & PS_CALLINC_MASK);
221 221
222 /* Additional corruption checks */ 222 /* Additional corruption checks */
223 223
@@ -280,7 +280,7 @@ flush_my_cpstate(struct task_struct *tsk)
280static int 280static int
281save_cpextra (struct _cpstate *buf) 281save_cpextra (struct _cpstate *buf)
282{ 282{
283#if (XCHAL_EXTRA_SA_SIZE == 0) && (XCHAL_CP_NUM == 0) 283#if XCHAL_CP_NUM == 0
284 return 0; 284 return 0;
285#else 285#else
286 286
@@ -350,7 +350,7 @@ setup_sigcontext(struct sigcontext *sc, struct _cpstate *cpstate,
350 return err; 350 return err;
351} 351}
352 352
353asmlinkage int sys_sigreturn(struct pt_regs *regs) 353asmlinkage int xtensa_sigreturn(struct pt_regs *regs)
354{ 354{
355 struct sigframe *frame = (struct sigframe *)regs->areg[1]; 355 struct sigframe *frame = (struct sigframe *)regs->areg[1];
356 sigset_t set; 356 sigset_t set;
@@ -382,7 +382,7 @@ badframe:
382 return 0; 382 return 0;
383} 383}
384 384
385asmlinkage int sys_rt_sigreturn(struct pt_regs *regs) 385asmlinkage int xtensa_rt_sigreturn(struct pt_regs *regs)
386{ 386{
387 struct rt_sigframe *frame = (struct rt_sigframe *)regs->areg[1]; 387 struct rt_sigframe *frame = (struct rt_sigframe *)regs->areg[1];
388 sigset_t set; 388 sigset_t set;
@@ -497,8 +497,10 @@ gen_return_code(unsigned char *codemem, unsigned int use_rt_sigreturn)
497 497
498 /* Flush generated code out of the data cache */ 498 /* Flush generated code out of the data cache */
499 499
500 if (err == 0) 500 if (err == 0) {
501 __flush_invalidate_cache_range((unsigned long)codemem, 6UL); 501 __invalidate_icache_range((unsigned long)codemem, 6UL);
502 __flush_invalidate_dcache_range((unsigned long)codemem, 6UL);
503 }
502 504
503 return err; 505 return err;
504} 506}
diff --git a/arch/xtensa/kernel/syscall.c b/arch/xtensa/kernel/syscall.c
new file mode 100644
index 000000000000..fe3834bc1dbf
--- /dev/null
+++ b/arch/xtensa/kernel/syscall.c
@@ -0,0 +1,95 @@
1/*
2 * arch/xtensa/kernel/syscall.c
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 * Copyright (C) 2000 Silicon Graphics, Inc.
10 * Copyright (C) 1995 - 2000 by Ralf Baechle
11 *
12 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
13 * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
14 * Chris Zankel <chris@zankel.net>
15 * Kevin Chea
16 *
17 */
18#include <asm/uaccess.h>
19#include <asm/syscall.h>
20#include <asm/unistd.h>
21#include <linux/linkage.h>
22#include <linux/stringify.h>
23#include <linux/errno.h>
24#include <linux/syscalls.h>
25#include <linux/file.h>
26#include <linux/fs.h>
27#include <linux/mman.h>
28#include <linux/shm.h>
29
30typedef void (*syscall_t)(void);
31
32syscall_t sys_call_table[__NR_syscall_count] /* FIXME __cacheline_aligned */= {
33 [0 ... __NR_syscall_count - 1] = (syscall_t)&sys_ni_syscall,
34
35#undef __SYSCALL
36#define __SYSCALL(nr,symbol,nargs) [ nr ] = (syscall_t)symbol,
37#undef _XTENSA_UNISTD_H
38#undef __KERNEL_SYSCALLS__
39#include <asm/unistd.h>
40};
41
42/*
43 * xtensa_pipe() is the normal C calling standard for creating a pipe. It's not
44 * the way unix traditional does this, though.
45 */
46
47asmlinkage long xtensa_pipe(int __user *userfds)
48{
49 int fd[2];
50 int error;
51
52 error = do_pipe(fd);
53 if (!error) {
54 if (copy_to_user(userfds, fd, 2 * sizeof(int)))
55 error = -EFAULT;
56 }
57 return error;
58}
59
60
61asmlinkage long xtensa_mmap2(unsigned long addr, unsigned long len,
62 unsigned long prot, unsigned long flags,
63 unsigned long fd, unsigned long pgoff)
64{
65 int error = -EBADF;
66 struct file * file = NULL;
67
68 flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
69 if (!(flags & MAP_ANONYMOUS)) {
70 file = fget(fd);
71 if (!file)
72 goto out;
73 }
74
75 down_write(&current->mm->mmap_sem);
76 error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
77 up_write(&current->mm->mmap_sem);
78
79 if (file)
80 fput(file);
81out:
82 return error;
83}
84
85asmlinkage long xtensa_shmat(int shmid, char __user *shmaddr, int shmflg)
86{
87 unsigned long ret;
88 long err;
89
90 err = do_shmat(shmid, shmaddr, shmflg, &ret);
91 if (err)
92 return err;
93 return (long)ret;
94}
95
diff --git a/arch/xtensa/kernel/syscalls.c b/arch/xtensa/kernel/syscalls.c
deleted file mode 100644
index f49cb239e603..000000000000
--- a/arch/xtensa/kernel/syscalls.c
+++ /dev/null
@@ -1,288 +0,0 @@
1/*
2 * arch/xtensa/kernel/syscalls.c
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 * Copyright (C) 2000 Silicon Graphics, Inc.
10 * Copyright (C) 1995 - 2000 by Ralf Baechle
11 *
12 * Joe Taylor <joe@tensilica.com, joetylr@yahoo.com>
13 * Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
14 * Chris Zankel <chris@zankel.net>
15 * Kevin Chea
16 *
17 */
18
19#define DEBUG 0
20
21#include <linux/linkage.h>
22#include <linux/mm.h>
23#include <linux/smp.h>
24#include <linux/smp_lock.h>
25#include <linux/mman.h>
26#include <linux/sched.h>
27#include <linux/file.h>
28#include <linux/slab.h>
29#include <linux/utsname.h>
30#include <linux/unistd.h>
31#include <linux/stringify.h>
32#include <linux/syscalls.h>
33#include <linux/sem.h>
34#include <linux/msg.h>
35#include <linux/shm.h>
36#include <linux/errno.h>
37#include <asm/ptrace.h>
38#include <asm/signal.h>
39#include <asm/uaccess.h>
40#include <asm/hardirq.h>
41#include <asm/mman.h>
42#include <asm/shmparam.h>
43#include <asm/page.h>
44
45extern void do_syscall_trace(void);
46typedef int (*syscall_t)(void *a0,...);
47extern syscall_t sys_call_table[];
48extern unsigned char sys_narg_table[];
49
50/*
51 * sys_pipe() is the normal C calling standard for creating a pipe. It's not
52 * the way unix traditional does this, though.
53 */
54
55int sys_pipe(int __user *userfds)
56{
57 int fd[2];
58 int error;
59
60 error = do_pipe(fd);
61 if (!error) {
62 if (copy_to_user(userfds, fd, 2 * sizeof(int)))
63 error = -EFAULT;
64 }
65 return error;
66}
67
68/*
69 * Common code for old and new mmaps.
70 */
71long sys_mmap(unsigned long addr, unsigned long len, unsigned long prot,
72 unsigned long flags, unsigned long fd, unsigned long pgoff)
73{
74 int error = -EBADF;
75 struct file * file = NULL;
76
77 flags &= ~(MAP_EXECUTABLE | MAP_DENYWRITE);
78 if (!(flags & MAP_ANONYMOUS)) {
79 file = fget(fd);
80 if (!file)
81 goto out;
82 }
83
84 down_write(&current->mm->mmap_sem);
85 error = do_mmap_pgoff(file, addr, len, prot, flags, pgoff);
86 up_write(&current->mm->mmap_sem);
87
88 if (file)
89 fput(file);
90out:
91 return error;
92}
93
94int sys_clone(struct pt_regs *regs)
95{
96 unsigned long clone_flags;
97 unsigned long newsp;
98 int __user *parent_tidptr, *child_tidptr;
99 clone_flags = regs->areg[4];
100 newsp = regs->areg[3];
101 parent_tidptr = (int __user *)regs->areg[5];
102 child_tidptr = (int __user *)regs->areg[6];
103 if (!newsp)
104 newsp = regs->areg[1];
105 return do_fork(clone_flags,newsp,regs,0,parent_tidptr,child_tidptr);
106}
107
108/*
109 * sys_execve() executes a new program.
110 */
111
112int sys_execve(struct pt_regs *regs)
113{
114 int error;
115 char * filename;
116
117 filename = getname((char *) (long)regs->areg[5]);
118 error = PTR_ERR(filename);
119 if (IS_ERR(filename))
120 goto out;
121 error = do_execve(filename, (char **) (long)regs->areg[3],
122 (char **) (long)regs->areg[4], regs);
123 putname(filename);
124
125out:
126 return error;
127}
128
129int sys_uname(struct old_utsname * name)
130{
131 if (name && !copy_to_user(name, utsname(), sizeof (*name)))
132 return 0;
133 return -EFAULT;
134}
135
136/*
137 * Build the string table for the builtin "poor man's strace".
138 */
139
140#if DEBUG
141#define SYSCALL(fun, narg) #fun,
142static char *sfnames[] = {
143#include "syscalls.h"
144};
145#undef SYS
146#endif
147
148void system_call (struct pt_regs *regs)
149{
150 syscall_t syscall;
151 unsigned long parm0, parm1, parm2, parm3, parm4, parm5;
152 int nargs, res;
153 unsigned int syscallnr;
154 int ps;
155
156#if DEBUG
157 int i;
158 unsigned long parms[6];
159 char *sysname;
160#endif
161
162 regs->syscall = regs->areg[2];
163
164 do_syscall_trace();
165
166 /* Have to load after syscall_trace because strace
167 * sometimes changes regs->syscall.
168 */
169 syscallnr = regs->syscall;
170
171 parm0 = parm1 = parm2 = parm3 = parm4 = parm5 = 0;
172
173 /* Restore interrupt level to syscall invoker's.
174 * If this were in assembly, we wouldn't disable
175 * interrupts in the first place:
176 */
177 local_save_flags (ps);
178 local_irq_restore((ps & ~XCHAL_PS_INTLEVEL_MASK) |
179 (regs->ps & XCHAL_PS_INTLEVEL_MASK) );
180
181 if (syscallnr > __NR_Linux_syscalls) {
182 regs->areg[2] = -ENOSYS;
183 return;
184 }
185
186 syscall = sys_call_table[syscallnr];
187 nargs = sys_narg_table[syscallnr];
188
189 if (syscall == NULL) {
190 regs->areg[2] = -ENOSYS;
191 return;
192 }
193
194 /* There shouldn't be more than six arguments in the table! */
195
196 if (nargs > 6)
197 panic("Internal error - too many syscall arguments (%d)!\n",
198 nargs);
199
200 /* Linux takes system-call arguments in registers. The ABI
201 * and Xtensa software conventions require the system-call
202 * number in a2. If an argument exists in a2, we move it to
203 * the next available register. Note that for improved
204 * efficiency, we do NOT shift all parameters down one
205 * register to maintain the original order.
206 *
207 * At best case (zero arguments), we just write the syscall
208 * number to a2. At worst case (1 to 6 arguments), we move
209 * the argument in a2 to the next available register, then
210 * write the syscall number to a2.
211 *
212 * For clarity, the following truth table enumerates all
213 * possibilities.
214 *
215 * arguments syscall number arg0, arg1, arg2, arg3, arg4, arg5
216 * --------- -------------- ----------------------------------
217 * 0 a2
218 * 1 a2 a3
219 * 2 a2 a4, a3
220 * 3 a2 a5, a3, a4
221 * 4 a2 a6, a3, a4, a5
222 * 5 a2 a7, a3, a4, a5, a6
223 * 6 a2 a8, a3, a4, a5, a6, a7
224 */
225 if (nargs) {
226 parm0 = regs->areg[nargs+2];
227 parm1 = regs->areg[3];
228 parm2 = regs->areg[4];
229 parm3 = regs->areg[5];
230 parm4 = regs->areg[6];
231 parm5 = regs->areg[7];
232 } else /* nargs == 0 */
233 parm0 = (unsigned long) regs;
234
235#if DEBUG
236 parms[0] = parm0;
237 parms[1] = parm1;
238 parms[2] = parm2;
239 parms[3] = parm3;
240 parms[4] = parm4;
241 parms[5] = parm5;
242
243 sysname = sfnames[syscallnr];
244 if (strncmp(sysname, "sys_", 4) == 0)
245 sysname = sysname + 4;
246
247 printk("\017SYSCALL:I:%x:%d:%s %s(", regs->pc, current->pid,
248 current->comm, sysname);
249 for (i = 0; i < nargs; i++)
250 printk((i>0) ? ", %#lx" : "%#lx", parms[i]);
251 printk(")\n");
252#endif
253
254 res = syscall((void *)parm0, parm1, parm2, parm3, parm4, parm5);
255
256#if DEBUG
257 printk("\017SYSCALL:O:%d:%s %s(",current->pid, current->comm, sysname);
258 for (i = 0; i < nargs; i++)
259 printk((i>0) ? ", %#lx" : "%#lx", parms[i]);
260 if (res < 4096)
261 printk(") = %d\n", res);
262 else
263 printk(") = %#x\n", res);
264#endif /* DEBUG */
265
266 regs->areg[2] = res;
267 do_syscall_trace();
268}
269
270/*
271 * Do a system call from kernel instead of calling sys_execve so we
272 * end up with proper pt_regs.
273 */
274int kernel_execve(const char *filename, char *const argv[], char *const envp[])
275{
276 long __res;
277 asm volatile (
278 " mov a5, %2 \n"
279 " mov a4, %4 \n"
280 " mov a3, %3 \n"
281 " movi a2, %1 \n"
282 " syscall \n"
283 " mov %0, a2 \n"
284 : "=a" (__res)
285 : "i" (__NR_execve), "a" (filename), "a" (argv), "a" (envp)
286 : "a2", "a3", "a4", "a5");
287 return __res;
288}
diff --git a/arch/xtensa/kernel/syscalls.h b/arch/xtensa/kernel/syscalls.h
deleted file mode 100644
index 216c10a31501..000000000000
--- a/arch/xtensa/kernel/syscalls.h
+++ /dev/null
@@ -1,247 +0,0 @@
1/*
2 * arch/xtensa/kernel/syscalls.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1995, 1996, 1997, 1998 by Ralf Baechle
9 * Copyright (C) 2001 - 2005 Tensilica Inc.
10 *
11 * Changes by Joe Taylor <joe@tensilica.com>
12 */
13
14/*
15 * This file is being included twice - once to build a list of all
16 * syscalls and once to build a table of how many arguments each syscall
17 * accepts. Syscalls that receive a pointer to the saved registers are
18 * marked as having zero arguments.
19 *
20 * The binary compatibility calls are in a separate list.
21 *
22 * Entry '0' used to be system_call. It's removed to disable indirect
23 * system calls for now so user tasks can't recurse. See mips'
24 * sys_syscall for a comparable example.
25 */
26
27SYSCALL(0, 0) /* 00 */
28SYSCALL(sys_exit, 1)
29SYSCALL(sys_ni_syscall, 0)
30SYSCALL(sys_read, 3)
31SYSCALL(sys_write, 3)
32SYSCALL(sys_open, 3) /* 05 */
33SYSCALL(sys_close, 1)
34SYSCALL(sys_ni_syscall, 3)
35SYSCALL(sys_creat, 2)
36SYSCALL(sys_link, 2)
37SYSCALL(sys_unlink, 1) /* 10 */
38SYSCALL(sys_execve, 0)
39SYSCALL(sys_chdir, 1)
40SYSCALL(sys_ni_syscall, 1)
41SYSCALL(sys_mknod, 3)
42SYSCALL(sys_chmod, 2) /* 15 */
43SYSCALL(sys_lchown, 3)
44SYSCALL(sys_ni_syscall, 0)
45SYSCALL(sys_newstat, 2)
46SYSCALL(sys_lseek, 3)
47SYSCALL(sys_getpid, 0) /* 20 */
48SYSCALL(sys_mount, 5)
49SYSCALL(sys_ni_syscall, 1)
50SYSCALL(sys_setuid, 1)
51SYSCALL(sys_getuid, 0)
52SYSCALL(sys_ni_syscall, 1) /* 25 */
53SYSCALL(sys_ptrace, 4)
54SYSCALL(sys_ni_syscall, 1)
55SYSCALL(sys_newfstat, 2)
56SYSCALL(sys_ni_syscall, 0)
57SYSCALL(sys_utime, 2) /* 30 */
58SYSCALL(sys_ni_syscall, 0)
59SYSCALL(sys_ni_syscall, 0)
60SYSCALL(sys_access, 2)
61SYSCALL(sys_ni_syscall, 1)
62SYSCALL(sys_ni_syscall, 0) /* 35 */
63SYSCALL(sys_sync, 0)
64SYSCALL(sys_kill, 2)
65SYSCALL(sys_rename, 2)
66SYSCALL(sys_mkdir, 2)
67SYSCALL(sys_rmdir, 1) /* 40 */
68SYSCALL(sys_dup, 1)
69SYSCALL(sys_pipe, 1)
70SYSCALL(sys_times, 1)
71SYSCALL(sys_ni_syscall, 0)
72SYSCALL(sys_brk, 1) /* 45 */
73SYSCALL(sys_setgid, 1)
74SYSCALL(sys_getgid, 0)
75SYSCALL(sys_ni_syscall, 0)
76SYSCALL(sys_geteuid, 0)
77SYSCALL(sys_getegid, 0) /* 50 */
78SYSCALL(sys_acct, 1)
79SYSCALL(sys_umount, 2)
80SYSCALL(sys_ni_syscall, 0)
81SYSCALL(sys_ioctl, 3)
82SYSCALL(sys_fcntl, 3) /* 55 */
83SYSCALL(sys_ni_syscall, 2)
84SYSCALL(sys_setpgid, 2)
85SYSCALL(sys_ni_syscall, 0)
86SYSCALL(sys_ni_syscall, 0)
87SYSCALL(sys_umask, 1) /* 60 */
88SYSCALL(sys_chroot, 1)
89SYSCALL(sys_ustat, 2)
90SYSCALL(sys_dup2, 2)
91SYSCALL(sys_getppid, 0)
92SYSCALL(sys_ni_syscall, 0) /* 65 */
93SYSCALL(sys_setsid, 0)
94SYSCALL(sys_sigaction, 3)
95SYSCALL(sys_ni_syscall, 0)
96SYSCALL(sys_ni_syscall, 1)
97SYSCALL(sys_setreuid, 2) /* 70 */
98SYSCALL(sys_setregid, 2)
99SYSCALL(sys_sigsuspend, 0)
100SYSCALL(sys_ni_syscall, 1)
101SYSCALL(sys_sethostname, 2)
102SYSCALL(sys_setrlimit, 2) /* 75 */
103SYSCALL(sys_getrlimit, 2)
104SYSCALL(sys_getrusage, 2)
105SYSCALL(sys_gettimeofday, 2)
106SYSCALL(sys_settimeofday, 2)
107SYSCALL(sys_getgroups, 2) /* 80 */
108SYSCALL(sys_setgroups, 2)
109SYSCALL(sys_ni_syscall, 0)
110SYSCALL(sys_symlink, 2)
111SYSCALL(sys_newlstat, 2)
112SYSCALL(sys_readlink, 3) /* 85 */
113SYSCALL(sys_uselib, 1)
114SYSCALL(sys_swapon, 2)
115SYSCALL(sys_reboot, 3)
116SYSCALL(sys_ni_syscall, 3)
117SYSCALL(sys_ni_syscall, 6) /* 90 */
118SYSCALL(sys_munmap, 2)
119SYSCALL(sys_truncate, 2)
120SYSCALL(sys_ftruncate, 2)
121SYSCALL(sys_fchmod, 2)
122SYSCALL(sys_fchown, 3) /* 95 */
123SYSCALL(sys_getpriority, 2)
124SYSCALL(sys_setpriority, 3)
125SYSCALL(sys_ni_syscall, 0)
126SYSCALL(sys_statfs, 2)
127SYSCALL(sys_fstatfs, 2) /* 100 */
128SYSCALL(sys_ni_syscall, 3)
129SYSCALL(sys_ni_syscall, 2)
130SYSCALL(sys_syslog, 3)
131SYSCALL(sys_setitimer, 3)
132SYSCALL(sys_getitimer, 2) /* 105 */
133SYSCALL(sys_newstat, 2)
134SYSCALL(sys_newlstat, 2)
135SYSCALL(sys_newfstat, 2)
136SYSCALL(sys_uname, 1)
137SYSCALL(sys_ni_syscall, 0) /* 110 */
138SYSCALL(sys_vhangup, 0)
139SYSCALL(sys_ni_syscall, 0)
140SYSCALL(sys_ni_syscall, 0)
141SYSCALL(sys_wait4, 4)
142SYSCALL(sys_swapoff, 1) /* 115 */
143SYSCALL(sys_sysinfo, 1)
144SYSCALL(sys_ni_syscall, 0)
145SYSCALL(sys_fsync, 1)
146SYSCALL(sys_sigreturn, 0)
147SYSCALL(sys_clone, 0) /* 120 */
148SYSCALL(sys_setdomainname, 2)
149SYSCALL(sys_newuname, 1)
150SYSCALL(sys_ni_syscall, 0)
151SYSCALL(sys_adjtimex, 1)
152SYSCALL(sys_mprotect, 3) /* 125 */
153SYSCALL(sys_ni_syscall, 3)
154SYSCALL(sys_ni_syscall, 2)
155SYSCALL(sys_init_module, 2)
156SYSCALL(sys_delete_module, 1)
157SYSCALL(sys_ni_syscall, 1) /* 130 */
158SYSCALL(sys_quotactl, 0)
159SYSCALL(sys_getpgid, 1)
160SYSCALL(sys_fchdir, 1)
161SYSCALL(sys_bdflush, 2)
162SYSCALL(sys_sysfs, 3) /* 135 */
163SYSCALL(sys_personality, 1)
164SYSCALL(sys_ni_syscall, 0)
165SYSCALL(sys_setfsuid, 1)
166SYSCALL(sys_setfsgid, 1)
167SYSCALL(sys_llseek, 5) /* 140 */
168SYSCALL(sys_getdents, 3)
169SYSCALL(sys_select, 5)
170SYSCALL(sys_flock, 2)
171SYSCALL(sys_msync, 3)
172SYSCALL(sys_readv, 3) /* 145 */
173SYSCALL(sys_writev, 3)
174SYSCALL(sys_ni_syscall, 3)
175SYSCALL(sys_ni_syscall, 3)
176SYSCALL(sys_ni_syscall, 4) /* handled in fast syscall handler. */
177SYSCALL(sys_ni_syscall, 0) /* 150 */
178SYSCALL(sys_getsid, 1)
179SYSCALL(sys_fdatasync, 1)
180SYSCALL(sys_sysctl, 1)
181SYSCALL(sys_mlock, 2)
182SYSCALL(sys_munlock, 2) /* 155 */
183SYSCALL(sys_mlockall, 1)
184SYSCALL(sys_munlockall, 0)
185SYSCALL(sys_sched_setparam,2)
186SYSCALL(sys_sched_getparam,2)
187SYSCALL(sys_sched_setscheduler,3) /* 160 */
188SYSCALL(sys_sched_getscheduler,1)
189SYSCALL(sys_sched_yield,0)
190SYSCALL(sys_sched_get_priority_max,1)
191SYSCALL(sys_sched_get_priority_min,1)
192SYSCALL(sys_sched_rr_get_interval,2) /* 165 */
193SYSCALL(sys_nanosleep,2)
194SYSCALL(sys_mremap,4)
195SYSCALL(sys_accept, 3)
196SYSCALL(sys_bind, 3)
197SYSCALL(sys_connect, 3) /* 170 */
198SYSCALL(sys_getpeername, 3)
199SYSCALL(sys_getsockname, 3)
200SYSCALL(sys_getsockopt, 5)
201SYSCALL(sys_listen, 2)
202SYSCALL(sys_recv, 4) /* 175 */
203SYSCALL(sys_recvfrom, 6)
204SYSCALL(sys_recvmsg, 3)
205SYSCALL(sys_send, 4)
206SYSCALL(sys_sendmsg, 3)
207SYSCALL(sys_sendto, 6) /* 180 */
208SYSCALL(sys_setsockopt, 5)
209SYSCALL(sys_shutdown, 2)
210SYSCALL(sys_socket, 3)
211SYSCALL(sys_socketpair, 4)
212SYSCALL(sys_setresuid, 3) /* 185 */
213SYSCALL(sys_getresuid, 3)
214SYSCALL(sys_ni_syscall, 5)
215SYSCALL(sys_poll, 3)
216SYSCALL(sys_nfsservctl, 3)
217SYSCALL(sys_setresgid, 3) /* 190 */
218SYSCALL(sys_getresgid, 3)
219SYSCALL(sys_prctl, 5)
220SYSCALL(sys_rt_sigreturn, 0)
221SYSCALL(sys_rt_sigaction, 4)
222SYSCALL(sys_rt_sigprocmask, 4) /* 195 */
223SYSCALL(sys_rt_sigpending, 2)
224SYSCALL(sys_rt_sigtimedwait, 4)
225SYSCALL(sys_rt_sigqueueinfo, 3)
226SYSCALL(sys_rt_sigsuspend, 0)
227SYSCALL(sys_pread64, 5) /* 200 */
228SYSCALL(sys_pwrite64, 5)
229SYSCALL(sys_chown, 3)
230SYSCALL(sys_getcwd, 2)
231SYSCALL(sys_capget, 2)
232SYSCALL(sys_capset, 2) /* 205 */
233SYSCALL(sys_sigaltstack, 0)
234SYSCALL(sys_sendfile, 4)
235SYSCALL(sys_ni_syscall, 0)
236SYSCALL(sys_ni_syscall, 0)
237SYSCALL(sys_mmap, 6) /* 210 */
238SYSCALL(sys_truncate64, 2)
239SYSCALL(sys_ftruncate64, 2)
240SYSCALL(sys_stat64, 2)
241SYSCALL(sys_lstat64, 2)
242SYSCALL(sys_fstat64, 2) /* 215 */
243SYSCALL(sys_pivot_root, 2)
244SYSCALL(sys_mincore, 3)
245SYSCALL(sys_madvise, 3)
246SYSCALL(sys_getdents64, 3)
247SYSCALL(sys_ni_syscall, 0) /* 220 */
diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c
index 37347e369987..a350431363a0 100644
--- a/arch/xtensa/kernel/time.c
+++ b/arch/xtensa/kernel/time.c
@@ -47,7 +47,7 @@ unsigned long long sched_clock(void)
47 return (unsigned long long)jiffies * (1000000000 / HZ); 47 return (unsigned long long)jiffies * (1000000000 / HZ);
48} 48}
49 49
50static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs); 50static irqreturn_t timer_interrupt(int irq, void *dev_id);
51static struct irqaction timer_irqaction = { 51static struct irqaction timer_irqaction = {
52 .handler = timer_interrupt, 52 .handler = timer_interrupt,
53 .flags = IRQF_DISABLED, 53 .flags = IRQF_DISABLED,
@@ -150,7 +150,7 @@ EXPORT_SYMBOL(do_gettimeofday);
150 * The timer interrupt is called HZ times per second. 150 * The timer interrupt is called HZ times per second.
151 */ 151 */
152 152
153irqreturn_t timer_interrupt (int irq, void *dev_id, struct pt_regs *regs) 153irqreturn_t timer_interrupt (int irq, void *dev_id)
154{ 154{
155 155
156 unsigned long next; 156 unsigned long next;
@@ -160,9 +160,9 @@ irqreturn_t timer_interrupt (int irq, void *dev_id, struct pt_regs *regs)
160again: 160again:
161 while ((signed long)(get_ccount() - next) > 0) { 161 while ((signed long)(get_ccount() - next) > 0) {
162 162
163 profile_tick(CPU_PROFILING, regs); 163 profile_tick(CPU_PROFILING);
164#ifndef CONFIG_SMP 164#ifndef CONFIG_SMP
165 update_process_times(user_mode(regs)); 165 update_process_times(user_mode(get_irq_regs()));
166#endif 166#endif
167 167
168 write_seqlock(&xtime_lock); 168 write_seqlock(&xtime_lock);
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c
index ce077d6bf3a0..693ab268485e 100644
--- a/arch/xtensa/kernel/traps.c
+++ b/arch/xtensa/kernel/traps.c
@@ -75,7 +75,7 @@ extern void system_call (struct pt_regs*);
75#define USER 0x02 75#define USER 0x02
76 76
77#define COPROCESSOR(x) \ 77#define COPROCESSOR(x) \
78{ XCHAL_EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor } 78{ EXCCAUSE_COPROCESSOR ## x ## _DISABLED, USER, fast_coprocessor }
79 79
80typedef struct { 80typedef struct {
81 int cause; 81 int cause;
@@ -85,38 +85,38 @@ typedef struct {
85 85
86dispatch_init_table_t __init dispatch_init_table[] = { 86dispatch_init_table_t __init dispatch_init_table[] = {
87 87
88{ XCHAL_EXCCAUSE_ILLEGAL_INSTRUCTION, 0, do_illegal_instruction}, 88{ EXCCAUSE_ILLEGAL_INSTRUCTION, 0, do_illegal_instruction},
89{ XCHAL_EXCCAUSE_SYSTEM_CALL, KRNL, fast_syscall_kernel }, 89{ EXCCAUSE_SYSTEM_CALL, KRNL, fast_syscall_kernel },
90{ XCHAL_EXCCAUSE_SYSTEM_CALL, USER, fast_syscall_user }, 90{ EXCCAUSE_SYSTEM_CALL, USER, fast_syscall_user },
91{ XCHAL_EXCCAUSE_SYSTEM_CALL, 0, system_call }, 91{ EXCCAUSE_SYSTEM_CALL, 0, system_call },
92/* XCHAL_EXCCAUSE_INSTRUCTION_FETCH unhandled */ 92/* EXCCAUSE_INSTRUCTION_FETCH unhandled */
93/* XCHAL_EXCCAUSE_LOAD_STORE_ERROR unhandled*/ 93/* EXCCAUSE_LOAD_STORE_ERROR unhandled*/
94{ XCHAL_EXCCAUSE_LEVEL1_INTERRUPT, 0, do_interrupt }, 94{ EXCCAUSE_LEVEL1_INTERRUPT, 0, do_interrupt },
95{ XCHAL_EXCCAUSE_ALLOCA, USER|KRNL, fast_alloca }, 95{ EXCCAUSE_ALLOCA, USER|KRNL, fast_alloca },
96/* XCHAL_EXCCAUSE_INTEGER_DIVIDE_BY_ZERO unhandled */ 96/* EXCCAUSE_INTEGER_DIVIDE_BY_ZERO unhandled */
97/* XCHAL_EXCCAUSE_PRIVILEGED unhandled */ 97/* EXCCAUSE_PRIVILEGED unhandled */
98#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION 98#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
99#ifdef CONFIG_UNALIGNED_USER 99#ifdef CONFIG_UNALIGNED_USER
100{ XCHAL_EXCCAUSE_UNALIGNED, USER, fast_unaligned }, 100{ EXCCAUSE_UNALIGNED, USER, fast_unaligned },
101#else 101#else
102{ XCHAL_EXCCAUSE_UNALIGNED, 0, do_unaligned_user }, 102{ EXCCAUSE_UNALIGNED, 0, do_unaligned_user },
103#endif 103#endif
104{ XCHAL_EXCCAUSE_UNALIGNED, KRNL, fast_unaligned }, 104{ EXCCAUSE_UNALIGNED, KRNL, fast_unaligned },
105#endif 105#endif
106{ XCHAL_EXCCAUSE_ITLB_MISS, 0, do_page_fault }, 106{ EXCCAUSE_ITLB_MISS, 0, do_page_fault },
107{ XCHAL_EXCCAUSE_ITLB_MISS, USER|KRNL, fast_second_level_miss}, 107{ EXCCAUSE_ITLB_MISS, USER|KRNL, fast_second_level_miss},
108{ XCHAL_EXCCAUSE_ITLB_MULTIHIT, 0, do_multihit }, 108{ EXCCAUSE_ITLB_MULTIHIT, 0, do_multihit },
109{ XCHAL_EXCCAUSE_ITLB_PRIVILEGE, 0, do_page_fault }, 109{ EXCCAUSE_ITLB_PRIVILEGE, 0, do_page_fault },
110/* XCHAL_EXCCAUSE_SIZE_RESTRICTION unhandled */ 110/* EXCCAUSE_SIZE_RESTRICTION unhandled */
111{ XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE, 0, do_page_fault }, 111{ EXCCAUSE_FETCH_CACHE_ATTRIBUTE, 0, do_page_fault },
112{ XCHAL_EXCCAUSE_DTLB_MISS, USER|KRNL, fast_second_level_miss}, 112{ EXCCAUSE_DTLB_MISS, USER|KRNL, fast_second_level_miss},
113{ XCHAL_EXCCAUSE_DTLB_MISS, 0, do_page_fault }, 113{ EXCCAUSE_DTLB_MISS, 0, do_page_fault },
114{ XCHAL_EXCCAUSE_DTLB_MULTIHIT, 0, do_multihit }, 114{ EXCCAUSE_DTLB_MULTIHIT, 0, do_multihit },
115{ XCHAL_EXCCAUSE_DTLB_PRIVILEGE, 0, do_page_fault }, 115{ EXCCAUSE_DTLB_PRIVILEGE, 0, do_page_fault },
116/* XCHAL_EXCCAUSE_DTLB_SIZE_RESTRICTION unhandled */ 116/* EXCCAUSE_DTLB_SIZE_RESTRICTION unhandled */
117{ XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE, USER|KRNL, fast_store_prohibited }, 117{ EXCCAUSE_STORE_CACHE_ATTRIBUTE, USER|KRNL, fast_store_prohibited },
118{ XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault }, 118{ EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault },
119{ XCHAL_EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault }, 119{ EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault },
120/* XCCHAL_EXCCAUSE_FLOATING_POINT unhandled */ 120/* XCCHAL_EXCCAUSE_FLOATING_POINT unhandled */
121#if (XCHAL_CP_MASK & 1) 121#if (XCHAL_CP_MASK & 1)
122COPROCESSOR(0), 122COPROCESSOR(0),
diff --git a/arch/xtensa/kernel/vectors.S b/arch/xtensa/kernel/vectors.S
index 0e74397bfa2b..eb2d7bb69ee0 100644
--- a/arch/xtensa/kernel/vectors.S
+++ b/arch/xtensa/kernel/vectors.S
@@ -53,6 +53,8 @@
53#include <asm/thread_info.h> 53#include <asm/thread_info.h>
54#include <asm/processor.h> 54#include <asm/processor.h>
55 55
56#define WINDOW_VECTORS_SIZE 0x180
57
56 58
57/* 59/*
58 * User exception vector. (Exceptions with PS.UM == 1, PS.EXCM == 0) 60 * User exception vector. (Exceptions with PS.UM == 1, PS.EXCM == 0)
@@ -210,7 +212,7 @@ ENTRY(_DoubleExceptionVector)
210 /* Check for kernel double exception (usually fatal). */ 212 /* Check for kernel double exception (usually fatal). */
211 213
212 rsr a3, PS 214 rsr a3, PS
213 _bbci.l a3, PS_UM_SHIFT, .Lksp 215 _bbci.l a3, PS_UM_BIT, .Lksp
214 216
215 /* Check if we are currently handling a window exception. */ 217 /* Check if we are currently handling a window exception. */
216 /* Note: We don't need to indicate that we enter a critical section. */ 218 /* Note: We don't need to indicate that we enter a critical section. */
@@ -219,7 +221,7 @@ ENTRY(_DoubleExceptionVector)
219 221
220 movi a3, XCHAL_WINDOW_VECTORS_VADDR 222 movi a3, XCHAL_WINDOW_VECTORS_VADDR
221 _bltu a0, a3, .Lfixup 223 _bltu a0, a3, .Lfixup
222 addi a3, a3, XSHAL_WINDOW_VECTORS_SIZE 224 addi a3, a3, WINDOW_VECTORS_SIZE
223 _bgeu a0, a3, .Lfixup 225 _bgeu a0, a3, .Lfixup
224 226
225 /* Window overflow/underflow exception. Get stack pointer. */ 227 /* Window overflow/underflow exception. Get stack pointer. */
@@ -245,7 +247,7 @@ ENTRY(_DoubleExceptionVector)
245 247
246 wsr a2, DEPC # save stack pointer temporarily 248 wsr a2, DEPC # save stack pointer temporarily
247 rsr a0, PS 249 rsr a0, PS
248 extui a0, a0, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS 250 extui a0, a0, PS_OWB_SHIFT, 4
249 wsr a0, WINDOWBASE 251 wsr a0, WINDOWBASE
250 rsync 252 rsync
251 253
@@ -312,8 +314,8 @@ ENTRY(_DoubleExceptionVector)
312.Lksp: /* a0: a0, a1: a1, a2: a2, a3: trashed, depc: depc, excsave: a3 */ 314.Lksp: /* a0: a0, a1: a1, a2: a2, a3: trashed, depc: depc, excsave: a3 */
313 315
314 rsr a3, EXCCAUSE 316 rsr a3, EXCCAUSE
315 beqi a3, XCHAL_EXCCAUSE_ITLB_MISS, 1f 317 beqi a3, EXCCAUSE_ITLB_MISS, 1f
316 addi a3, a3, -XCHAL_EXCCAUSE_DTLB_MISS 318 addi a3, a3, -EXCCAUSE_DTLB_MISS
317 bnez a3, .Lunrecoverable 319 bnez a3, .Lunrecoverable
3181: movi a3, fast_second_level_miss_double_kernel 3201: movi a3, fast_second_level_miss_double_kernel
319 jx a3 321 jx a3
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S
index cfe75f528725..a36c104c3a52 100644
--- a/arch/xtensa/kernel/vmlinux.lds.S
+++ b/arch/xtensa/kernel/vmlinux.lds.S
@@ -16,19 +16,17 @@
16 16
17#include <asm-generic/vmlinux.lds.h> 17#include <asm-generic/vmlinux.lds.h>
18 18
19#define _NOCLANGUAGE 19#include <asm/variant/core.h>
20#include <xtensa/config/core.h>
21#include <xtensa/config/system.h>
22OUTPUT_ARCH(xtensa) 20OUTPUT_ARCH(xtensa)
23ENTRY(_start) 21ENTRY(_start)
24 22
25#if XCHAL_MEMORY_ORDER == XTHAL_BIGENDIAN 23#ifdef __XTENSA_EB__
26jiffies = jiffies_64 + 4; 24jiffies = jiffies_64 + 4;
27#else 25#else
28jiffies = jiffies_64; 26jiffies = jiffies_64;
29#endif 27#endif
30 28
31#define KERNELOFFSET 0x1000 29#define KERNELOFFSET 0xd0001000
32 30
33/* Note: In the following macros, it would be nice to specify only the 31/* Note: In the following macros, it would be nice to specify only the
34 vector name and section kind and construct "sym" and "section" using 32 vector name and section kind and construct "sym" and "section" using
@@ -75,7 +73,7 @@ jiffies = jiffies_64;
75 73
76SECTIONS 74SECTIONS
77{ 75{
78 . = XCHAL_KSEG_CACHED_VADDR + KERNELOFFSET; 76 . = KERNELOFFSET;
79 /* .text section */ 77 /* .text section */
80 78
81 _text = .; 79 _text = .;
@@ -159,7 +157,7 @@ SECTIONS
159 157
160 /* Initialization code and data: */ 158 /* Initialization code and data: */
161 159
162 . = ALIGN(1<<XCHAL_MMU_MIN_PTE_PAGE_SIZE); 160 . = ALIGN(1 << 12);
163 __init_begin = .; 161 __init_begin = .;
164 .init.text : { 162 .init.text : {
165 _sinittext = .; 163 _sinittext = .;
@@ -223,32 +221,32 @@ SECTIONS
223 .dummy) 221 .dummy)
224 SECTION_VECTOR (_DebugInterruptVector_literal, 222 SECTION_VECTOR (_DebugInterruptVector_literal,
225 .DebugInterruptVector.literal, 223 .DebugInterruptVector.literal,
226 XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL) - 4, 224 XCHAL_DEBUG_VECTOR_VADDR - 4,
227 SIZEOF(.WindowVectors.text), 225 SIZEOF(.WindowVectors.text),
228 .WindowVectors.text) 226 .WindowVectors.text)
229 SECTION_VECTOR (_DebugInterruptVector_text, 227 SECTION_VECTOR (_DebugInterruptVector_text,
230 .DebugInterruptVector.text, 228 .DebugInterruptVector.text,
231 XCHAL_INTLEVEL_VECTOR_VADDR(XCHAL_DEBUGLEVEL), 229 XCHAL_DEBUG_VECTOR_VADDR,
232 4, 230 4,
233 .DebugInterruptVector.literal) 231 .DebugInterruptVector.literal)
234 SECTION_VECTOR (_KernelExceptionVector_literal, 232 SECTION_VECTOR (_KernelExceptionVector_literal,
235 .KernelExceptionVector.literal, 233 .KernelExceptionVector.literal,
236 XCHAL_KERNELEXC_VECTOR_VADDR - 4, 234 XCHAL_KERNEL_VECTOR_VADDR - 4,
237 SIZEOF(.DebugInterruptVector.text), 235 SIZEOF(.DebugInterruptVector.text),
238 .DebugInterruptVector.text) 236 .DebugInterruptVector.text)
239 SECTION_VECTOR (_KernelExceptionVector_text, 237 SECTION_VECTOR (_KernelExceptionVector_text,
240 .KernelExceptionVector.text, 238 .KernelExceptionVector.text,
241 XCHAL_KERNELEXC_VECTOR_VADDR, 239 XCHAL_KERNEL_VECTOR_VADDR,
242 4, 240 4,
243 .KernelExceptionVector.literal) 241 .KernelExceptionVector.literal)
244 SECTION_VECTOR (_UserExceptionVector_literal, 242 SECTION_VECTOR (_UserExceptionVector_literal,
245 .UserExceptionVector.literal, 243 .UserExceptionVector.literal,
246 XCHAL_USEREXC_VECTOR_VADDR - 4, 244 XCHAL_USER_VECTOR_VADDR - 4,
247 SIZEOF(.KernelExceptionVector.text), 245 SIZEOF(.KernelExceptionVector.text),
248 .KernelExceptionVector.text) 246 .KernelExceptionVector.text)
249 SECTION_VECTOR (_UserExceptionVector_text, 247 SECTION_VECTOR (_UserExceptionVector_text,
250 .UserExceptionVector.text, 248 .UserExceptionVector.text,
251 XCHAL_USEREXC_VECTOR_VADDR, 249 XCHAL_USER_VECTOR_VADDR,
252 4, 250 4,
253 .UserExceptionVector.literal) 251 .UserExceptionVector.literal)
254 SECTION_VECTOR (_DoubleExceptionVector_literal, 252 SECTION_VECTOR (_DoubleExceptionVector_literal,
@@ -263,7 +261,7 @@ SECTIONS
263 .DoubleExceptionVector.literal) 261 .DoubleExceptionVector.literal)
264 262
265 . = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3; 263 . = (LOADADDR( .DoubleExceptionVector.text ) + SIZEOF( .DoubleExceptionVector.text ) + 3) & ~ 3;
266 . = ALIGN(1<<XCHAL_MMU_MIN_PTE_PAGE_SIZE); 264 . = ALIGN(1 << 12);
267 265
268 __init_end = .; 266 __init_end = .;
269 267
diff --git a/arch/xtensa/lib/checksum.S b/arch/xtensa/lib/checksum.S
index e2d64dfd530c..9d9cd990afa6 100644
--- a/arch/xtensa/lib/checksum.S
+++ b/arch/xtensa/lib/checksum.S
@@ -16,8 +16,7 @@
16 16
17#include <asm/errno.h> 17#include <asm/errno.h>
18#include <linux/linkage.h> 18#include <linux/linkage.h>
19#define _ASMLANGUAGE 19#include <asm/variant/core.h>
20#include <xtensa/config/core.h>
21 20
22/* 21/*
23 * computes a partial checksum, e.g. for TCP/UDP fragments 22 * computes a partial checksum, e.g. for TCP/UDP fragments
diff --git a/arch/xtensa/lib/memcopy.S b/arch/xtensa/lib/memcopy.S
index e8f6d7eb7222..ddda8f4bc862 100644
--- a/arch/xtensa/lib/memcopy.S
+++ b/arch/xtensa/lib/memcopy.S
@@ -9,7 +9,7 @@
9 * Copyright (C) 2002 - 2005 Tensilica Inc. 9 * Copyright (C) 2002 - 2005 Tensilica Inc.
10 */ 10 */
11 11
12#include <xtensa/coreasm.h> 12#include <asm/variant/core.h>
13 13
14 .macro src_b r, w0, w1 14 .macro src_b r, w0, w1
15#ifdef __XTENSA_EB__ 15#ifdef __XTENSA_EB__
diff --git a/arch/xtensa/lib/memset.S b/arch/xtensa/lib/memset.S
index 4de25134bc62..56a17495b2db 100644
--- a/arch/xtensa/lib/memset.S
+++ b/arch/xtensa/lib/memset.S
@@ -11,7 +11,7 @@
11 * Copyright (C) 2002 Tensilica Inc. 11 * Copyright (C) 2002 Tensilica Inc.
12 */ 12 */
13 13
14#include <xtensa/coreasm.h> 14#include <asm/variant/core.h>
15 15
16/* 16/*
17 * void *memset(void *dst, int c, size_t length) 17 * void *memset(void *dst, int c, size_t length)
diff --git a/arch/xtensa/lib/strncpy_user.S b/arch/xtensa/lib/strncpy_user.S
index 71d55df43893..a834057bda6b 100644
--- a/arch/xtensa/lib/strncpy_user.S
+++ b/arch/xtensa/lib/strncpy_user.S
@@ -11,7 +11,7 @@
11 * Copyright (C) 2002 Tensilica Inc. 11 * Copyright (C) 2002 Tensilica Inc.
12 */ 12 */
13 13
14#include <xtensa/coreasm.h> 14#include <asm/variant/core.h>
15#include <linux/errno.h> 15#include <linux/errno.h>
16 16
17/* Load or store instructions that may cause exceptions use the EX macro. */ 17/* Load or store instructions that may cause exceptions use the EX macro. */
diff --git a/arch/xtensa/lib/strnlen_user.S b/arch/xtensa/lib/strnlen_user.S
index cdff4d670f3b..5e9c1e709b2e 100644
--- a/arch/xtensa/lib/strnlen_user.S
+++ b/arch/xtensa/lib/strnlen_user.S
@@ -11,7 +11,7 @@
11 * Copyright (C) 2002 Tensilica Inc. 11 * Copyright (C) 2002 Tensilica Inc.
12 */ 12 */
13 13
14#include <xtensa/coreasm.h> 14#include <asm/variant/core.h>
15 15
16/* Load or store instructions that may cause exceptions use the EX macro. */ 16/* Load or store instructions that may cause exceptions use the EX macro. */
17 17
diff --git a/arch/xtensa/lib/usercopy.S b/arch/xtensa/lib/usercopy.S
index 4641ef510f0e..a8ab1d4fe0ae 100644
--- a/arch/xtensa/lib/usercopy.S
+++ b/arch/xtensa/lib/usercopy.S
@@ -53,7 +53,7 @@
53 * a11/ original length 53 * a11/ original length
54 */ 54 */
55 55
56#include <xtensa/coreasm.h> 56#include <asm/variant/core.h>
57 57
58#ifdef __XTENSA_EB__ 58#ifdef __XTENSA_EB__
59#define ALIGN(R, W0, W1) src R, W0, W1 59#define ALIGN(R, W0, W1) src R, W0, W1
diff --git a/arch/xtensa/mm/fault.c b/arch/xtensa/mm/fault.c
index dd0dbec2e57e..3dc6f2f07bbe 100644
--- a/arch/xtensa/mm/fault.c
+++ b/arch/xtensa/mm/fault.c
@@ -21,7 +21,7 @@
21#include <asm/system.h> 21#include <asm/system.h>
22#include <asm/pgalloc.h> 22#include <asm/pgalloc.h>
23 23
24unsigned long asid_cache = ASID_FIRST_VERSION; 24unsigned long asid_cache = ASID_USER_FIRST;
25void bad_page_fault(struct pt_regs*, unsigned long, int); 25void bad_page_fault(struct pt_regs*, unsigned long, int);
26 26
27/* 27/*
@@ -58,10 +58,10 @@ void do_page_fault(struct pt_regs *regs)
58 return; 58 return;
59 } 59 }
60 60
61 is_write = (exccause == XCHAL_EXCCAUSE_STORE_CACHE_ATTRIBUTE) ? 1 : 0; 61 is_write = (exccause == EXCCAUSE_STORE_CACHE_ATTRIBUTE) ? 1 : 0;
62 is_exec = (exccause == XCHAL_EXCCAUSE_ITLB_PRIVILEGE || 62 is_exec = (exccause == EXCCAUSE_ITLB_PRIVILEGE ||
63 exccause == XCHAL_EXCCAUSE_ITLB_MISS || 63 exccause == EXCCAUSE_ITLB_MISS ||
64 exccause == XCHAL_EXCCAUSE_FETCH_CACHE_ATTRIBUTE) ? 1 : 0; 64 exccause == EXCCAUSE_FETCH_CACHE_ATTRIBUTE) ? 1 : 0;
65 65
66#if 0 66#if 0
67 printk("[%s:%d:%08x:%d:%08x:%s%s]\n", current->comm, current->pid, 67 printk("[%s:%d:%08x:%d:%08x:%s%s]\n", current->comm, current->pid,
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index 660ef058c149..e1ec2d1e8189 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -141,8 +141,8 @@ void __init bootmem_init(void)
141 if (min_low_pfn > max_pfn) 141 if (min_low_pfn > max_pfn)
142 panic("No memory found!\n"); 142 panic("No memory found!\n");
143 143
144 max_low_pfn = max_pfn < MAX_LOW_MEMORY >> PAGE_SHIFT ? 144 max_low_pfn = max_pfn < MAX_MEM_PFN >> PAGE_SHIFT ?
145 max_pfn : MAX_LOW_MEMORY >> PAGE_SHIFT; 145 max_pfn : MAX_MEM_PFN >> PAGE_SHIFT;
146 146
147 /* Find an area to use for the bootmem bitmap. */ 147 /* Find an area to use for the bootmem bitmap. */
148 148
@@ -215,7 +215,7 @@ void __init init_mmu (void)
215 215
216 /* Set rasid register to a known value. */ 216 /* Set rasid register to a known value. */
217 217
218 set_rasid_register (ASID_ALL_RESERVED); 218 set_rasid_register (ASID_USER_FIRST);
219 219
220 /* Set PTEVADDR special register to the start of the page 220 /* Set PTEVADDR special register to the start of the page
221 * table, which is in kernel mappable space (ie. not 221 * table, which is in kernel mappable space (ie. not
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S
index 327c0f17187c..ae085332c607 100644
--- a/arch/xtensa/mm/misc.S
+++ b/arch/xtensa/mm/misc.S
@@ -19,9 +19,8 @@
19#include <linux/linkage.h> 19#include <linux/linkage.h>
20#include <asm/page.h> 20#include <asm/page.h>
21#include <asm/pgtable.h> 21#include <asm/pgtable.h>
22 22#include <asm/asmmacro.h>
23#include <xtensa/cacheasm.h> 23#include <asm/cacheasm.h>
24#include <xtensa/cacheattrasm.h>
25 24
26/* clear_page (page) */ 25/* clear_page (page) */
27 26
@@ -74,104 +73,66 @@ ENTRY(copy_page)
74 73
75 retw 74 retw
76 75
77
78/* 76/*
79 * void __flush_invalidate_cache_all(void) 77 * void __invalidate_icache_page(ulong start)
80 */ 78 */
81 79
82ENTRY(__flush_invalidate_cache_all) 80ENTRY(__invalidate_icache_page)
83 entry sp, 16 81 entry sp, 16
84 dcache_writeback_inv_all a2, a3
85 icache_invalidate_all a2, a3
86 retw
87 82
88/* 83 ___invalidate_icache_page a2 a3
89 * void __invalidate_icache_all(void) 84 isync
90 */
91 85
92ENTRY(__invalidate_icache_all)
93 entry sp, 16
94 icache_invalidate_all a2, a3
95 retw 86 retw
96 87
97/* 88/*
98 * void __flush_invalidate_dcache_all(void) 89 * void __invalidate_dcache_page(ulong start)
99 */ 90 */
100 91
101ENTRY(__flush_invalidate_dcache_all) 92ENTRY(__invalidate_dcache_page)
102 entry sp, 16 93 entry sp, 16
103 dcache_writeback_inv_all a2, a3
104 retw
105
106 94
107/* 95 ___invalidate_dcache_page a2 a3
108 * void __flush_invalidate_cache_range(ulong start, ulong size) 96 dsync
109 */
110 97
111ENTRY(__flush_invalidate_cache_range)
112 entry sp, 16
113 mov a4, a2
114 mov a5, a3
115 dcache_writeback_inv_region a4, a5, a6
116 icache_invalidate_region a2, a3, a4
117 retw 98 retw
118 99
119/* 100/*
120 * void __invalidate_icache_page(ulong start) 101 * void __flush_invalidate_dcache_page(ulong start)
121 */ 102 */
122 103
123ENTRY(__invalidate_icache_page) 104ENTRY(__flush_invalidate_dcache_page)
124 entry sp, 16 105 entry sp, 16
125 movi a3, PAGE_SIZE
126 icache_invalidate_region a2, a3, a4
127 retw
128 106
129/* 107 ___flush_invalidate_dcache_page a2 a3
130 * void __invalidate_dcache_page(ulong start)
131 */
132 108
133ENTRY(__invalidate_dcache_page) 109 dsync
134 entry sp, 16
135 movi a3, PAGE_SIZE
136 dcache_invalidate_region a2, a3, a4
137 retw 110 retw
138 111
139/* 112/*
140 * void __invalidate_icache_range(ulong start, ulong size) 113 * void __flush_dcache_page(ulong start)
141 */ 114 */
142 115
143ENTRY(__invalidate_icache_range) 116ENTRY(__flush_dcache_page)
144 entry sp, 16 117 entry sp, 16
145 icache_invalidate_region a2, a3, a4
146 retw
147 118
148/* 119 ___flush_dcache_page a2 a3
149 * void __invalidate_dcache_range(ulong start, ulong size)
150 */
151 120
152ENTRY(__invalidate_dcache_range) 121 dsync
153 entry sp, 16
154 dcache_invalidate_region a2, a3, a4
155 retw 122 retw
156 123
157/*
158 * void __flush_dcache_page(ulong start)
159 */
160 124
161ENTRY(__flush_dcache_page)
162 entry sp, 16
163 movi a3, PAGE_SIZE
164 dcache_writeback_region a2, a3, a4
165 retw
166 125
167/* 126/*
168 * void __flush_invalidate_dcache_page(ulong start) 127 * void __invalidate_icache_range(ulong start, ulong size)
169 */ 128 */
170 129
171ENTRY(__flush_invalidate_dcache_page) 130ENTRY(__invalidate_icache_range)
172 entry sp, 16 131 entry sp, 16
173 movi a3, PAGE_SIZE 132
174 dcache_writeback_inv_region a2, a3, a4 133 ___invalidate_icache_range a2 a3 a4
134 isync
135
175 retw 136 retw
176 137
177/* 138/*
@@ -180,195 +141,69 @@ ENTRY(__flush_invalidate_dcache_page)
180 141
181ENTRY(__flush_invalidate_dcache_range) 142ENTRY(__flush_invalidate_dcache_range)
182 entry sp, 16 143 entry sp, 16
183 dcache_writeback_inv_region a2, a3, a4
184 retw
185 144
186/* 145 ___flush_invalidate_dcache_range a2 a3 a4
187 * void __invalidate_dcache_all(void) 146 dsync
188 */
189 147
190ENTRY(__invalidate_dcache_all)
191 entry sp, 16
192 dcache_invalidate_all a2, a3
193 retw 148 retw
194 149
195/* 150/*
196 * void __flush_invalidate_dcache_page_phys(ulong start) 151 * void _flush_dcache_range(ulong start, ulong size)
197 */ 152 */
198 153
199ENTRY(__flush_invalidate_dcache_page_phys) 154ENTRY(__flush_dcache_range)
200 entry sp, 16 155 entry sp, 16
201 156
202 movi a3, XCHAL_DCACHE_SIZE 157 ___flush_dcache_range a2 a3 a4
203 movi a4, PAGE_MASK | 1
204 addi a2, a2, 1
205
2061: addi a3, a3, -XCHAL_DCACHE_LINESIZE
207
208 ldct a6, a3
209 dsync 158 dsync
210 and a6, a6, a4
211 beq a6, a2, 2f
212 bgeui a3, 2, 1b
213 retw
214 159
2152: diwbi a3, 0
216 bgeui a3, 2, 1b
217 retw 160 retw
218 161
219ENTRY(check_dcache_low0) 162/*
220 entry sp, 16 163 * void _invalidate_dcache_range(ulong start, ulong size)
221 164 */
222 movi a3, XCHAL_DCACHE_SIZE / 4
223 movi a4, PAGE_MASK | 1
224 addi a2, a2, 1
225
2261: addi a3, a3, -XCHAL_DCACHE_LINESIZE
227
228 ldct a6, a3
229 dsync
230 and a6, a6, a4
231 beq a6, a2, 2f
232 bgeui a3, 2, 1b
233 retw
234
2352: j 2b
236
237ENTRY(check_dcache_high0)
238 entry sp, 16
239
240 movi a5, XCHAL_DCACHE_SIZE / 4
241 movi a3, XCHAL_DCACHE_SIZE / 2
242 movi a4, PAGE_MASK | 1
243 addi a2, a2, 1
244
2451: addi a3, a3, -XCHAL_DCACHE_LINESIZE
246 addi a5, a5, -XCHAL_DCACHE_LINESIZE
247
248 ldct a6, a3
249 dsync
250 and a6, a6, a4
251 beq a6, a2, 2f
252 bgeui a5, 2, 1b
253 retw
254
2552: j 2b
256 165
257ENTRY(check_dcache_low1) 166ENTRY(__invalidate_dcache_range)
258 entry sp, 16 167 entry sp, 16
259 168
260 movi a5, XCHAL_DCACHE_SIZE / 4 169 ___invalidate_dcache_range a2 a3 a4
261 movi a3, XCHAL_DCACHE_SIZE * 3 / 4
262 movi a4, PAGE_MASK | 1
263 addi a2, a2, 1
264 170
2651: addi a3, a3, -XCHAL_DCACHE_LINESIZE
266 addi a5, a5, -XCHAL_DCACHE_LINESIZE
267 171
268 ldct a6, a3
269 dsync
270 and a6, a6, a4
271 beq a6, a2, 2f
272 bgeui a5, 2, 1b
273 retw 172 retw
274 173
2752: j 2b 174/*
175 * void _invalidate_icache_all(void)
176 */
276 177
277ENTRY(check_dcache_high1) 178ENTRY(__invalidate_icache_all)
278 entry sp, 16 179 entry sp, 16
279 180
280 movi a5, XCHAL_DCACHE_SIZE / 4 181 ___invalidate_icache_all a2 a3
281 movi a3, XCHAL_DCACHE_SIZE 182 isync
282 movi a4, PAGE_MASK | 1
283 addi a2, a2, 1
284
2851: addi a3, a3, -XCHAL_DCACHE_LINESIZE
286 addi a5, a5, -XCHAL_DCACHE_LINESIZE
287 183
288 ldct a6, a3
289 dsync
290 and a6, a6, a4
291 beq a6, a2, 2f
292 bgeui a5, 2, 1b
293 retw 184 retw
294 185
2952: j 2b
296
297
298/* 186/*
299 * void __invalidate_icache_page_phys(ulong start) 187 * void _flush_invalidate_dcache_all(void)
300 */ 188 */
301 189
302ENTRY(__invalidate_icache_page_phys) 190ENTRY(__flush_invalidate_dcache_all)
303 entry sp, 16 191 entry sp, 16
304 192
305 movi a3, XCHAL_ICACHE_SIZE 193 ___flush_invalidate_dcache_all a2 a3
306 movi a4, PAGE_MASK | 1 194 dsync
307 addi a2, a2, 1
308
3091: addi a3, a3, -XCHAL_ICACHE_LINESIZE
310
311 lict a6, a3
312 isync
313 and a6, a6, a4
314 beq a6, a2, 2f
315 bgeui a3, 2, 1b
316 retw
317 195
3182: iii a3, 0
319 bgeui a3, 2, 1b
320 retw 196 retw
321 197
198/*
199 * void _invalidate_dcache_all(void)
200 */
322 201
323#if 0 202ENTRY(__invalidate_dcache_all)
324
325 movi a3, XCHAL_DCACHE_WAYS - 1
326 movi a4, PAGE_SIZE
327
3281: mov a5, a2
329 add a6, a2, a4
330
3312: diwbi a5, 0
332 diwbi a5, XCHAL_DCACHE_LINESIZE
333 diwbi a5, XCHAL_DCACHE_LINESIZE * 2
334 diwbi a5, XCHAL_DCACHE_LINESIZE * 3
335
336 addi a5, a5, XCHAL_DCACHE_LINESIZE * 4
337 blt a5, a6, 2b
338
339 addi a3, a3, -1
340 addi a2, a2, XCHAL_DCACHE_SIZE / XCHAL_DCACHE_WAYS
341 bgez a3, 1b
342
343 retw
344
345ENTRY(__invalidate_icache_page_index)
346 entry sp, 16 203 entry sp, 16
347 204
348 movi a3, XCHAL_ICACHE_WAYS - 1 205 ___invalidate_dcache_all a2 a3
349 movi a4, PAGE_SIZE 206 dsync
350
3511: mov a5, a2
352 add a6, a2, a4
353
3542: iii a5, 0
355 iii a5, XCHAL_ICACHE_LINESIZE
356 iii a5, XCHAL_ICACHE_LINESIZE * 2
357 iii a5, XCHAL_ICACHE_LINESIZE * 3
358
359 addi a5, a5, XCHAL_ICACHE_LINESIZE * 4
360 blt a5, a6, 2b
361
362 addi a3, a3, -1
363 addi a2, a2, XCHAL_ICACHE_SIZE / XCHAL_ICACHE_WAYS
364 bgez a3, 2b
365 207
366 retw 208 retw
367 209
368#endif
369
370
371
372
373
374
diff --git a/arch/xtensa/mm/tlb.c b/arch/xtensa/mm/tlb.c
index 0fefb8666874..239461d8ea88 100644
--- a/arch/xtensa/mm/tlb.c
+++ b/arch/xtensa/mm/tlb.c
@@ -24,12 +24,12 @@
24 24
25static inline void __flush_itlb_all (void) 25static inline void __flush_itlb_all (void)
26{ 26{
27 int way, index; 27 int w, i;
28 28
29 for (way = 0; way < XCHAL_ITLB_ARF_WAYS; way++) { 29 for (w = 0; w < ITLB_ARF_WAYS; w++) {
30 for (index = 0; index < ITLB_ENTRIES_PER_ARF_WAY; index++) { 30 for (i = 0; i < (1 << XCHAL_ITLB_ARF_ENTRIES_LOG2); i++) {
31 int entry = way + (index << PAGE_SHIFT); 31 int e = w + (i << PAGE_SHIFT);
32 invalidate_itlb_entry_no_isync (entry); 32 invalidate_itlb_entry_no_isync(e);
33 } 33 }
34 } 34 }
35 asm volatile ("isync\n"); 35 asm volatile ("isync\n");
@@ -37,12 +37,12 @@ static inline void __flush_itlb_all (void)
37 37
38static inline void __flush_dtlb_all (void) 38static inline void __flush_dtlb_all (void)
39{ 39{
40 int way, index; 40 int w, i;
41 41
42 for (way = 0; way < XCHAL_DTLB_ARF_WAYS; way++) { 42 for (w = 0; w < DTLB_ARF_WAYS; w++) {
43 for (index = 0; index < DTLB_ENTRIES_PER_ARF_WAY; index++) { 43 for (i = 0; i < (1 << XCHAL_DTLB_ARF_ENTRIES_LOG2); i++) {
44 int entry = way + (index << PAGE_SHIFT); 44 int e = w + (i << PAGE_SHIFT);
45 invalidate_dtlb_entry_no_isync (entry); 45 invalidate_dtlb_entry_no_isync(e);
46 } 46 }
47 } 47 }
48 asm volatile ("isync\n"); 48 asm volatile ("isync\n");
@@ -63,21 +63,25 @@ void flush_tlb_all (void)
63 63
64void flush_tlb_mm(struct mm_struct *mm) 64void flush_tlb_mm(struct mm_struct *mm)
65{ 65{
66#if 0
67 printk("[tlbmm<%lx>]\n", (unsigned long)mm->context);
68#endif
69
70 if (mm == current->active_mm) { 66 if (mm == current->active_mm) {
71 int flags; 67 int flags;
72 local_save_flags(flags); 68 local_save_flags(flags);
73 get_new_mmu_context(mm, asid_cache); 69 __get_new_mmu_context(mm);
74 set_rasid_register(ASID_INSERT(mm->context)); 70 __load_mmu_context(mm);
75 local_irq_restore(flags); 71 local_irq_restore(flags);
76 } 72 }
77 else 73 else
78 mm->context = 0; 74 mm->context = 0;
79} 75}
80 76
77#define _ITLB_ENTRIES (ITLB_ARF_WAYS << XCHAL_ITLB_ARF_ENTRIES_LOG2)
78#define _DTLB_ENTRIES (DTLB_ARF_WAYS << XCHAL_DTLB_ARF_ENTRIES_LOG2)
79#if _ITLB_ENTRIES > _DTLB_ENTRIES
80# define _TLB_ENTRIES _ITLB_ENTRIES
81#else
82# define _TLB_ENTRIES _DTLB_ENTRIES
83#endif
84
81void flush_tlb_range (struct vm_area_struct *vma, 85void flush_tlb_range (struct vm_area_struct *vma,
82 unsigned long start, unsigned long end) 86 unsigned long start, unsigned long end)
83{ 87{
@@ -93,7 +97,7 @@ void flush_tlb_range (struct vm_area_struct *vma,
93#endif 97#endif
94 local_save_flags(flags); 98 local_save_flags(flags);
95 99
96 if (end-start + (PAGE_SIZE-1) <= SMALLEST_NTLB_ENTRIES << PAGE_SHIFT) { 100 if (end-start + (PAGE_SIZE-1) <= _TLB_ENTRIES << PAGE_SHIFT) {
97 int oldpid = get_rasid_register(); 101 int oldpid = get_rasid_register();
98 set_rasid_register (ASID_INSERT(mm->context)); 102 set_rasid_register (ASID_INSERT(mm->context));
99 start &= PAGE_MASK; 103 start &= PAGE_MASK;
@@ -111,9 +115,7 @@ void flush_tlb_range (struct vm_area_struct *vma,
111 115
112 set_rasid_register(oldpid); 116 set_rasid_register(oldpid);
113 } else { 117 } else {
114 get_new_mmu_context(mm, asid_cache); 118 flush_tlb_mm(mm);
115 if (mm == current->active_mm)
116 set_rasid_register(ASID_INSERT(mm->context));
117 } 119 }
118 local_irq_restore(flags); 120 local_irq_restore(flags);
119} 121}
@@ -123,10 +125,6 @@ void flush_tlb_page (struct vm_area_struct *vma, unsigned long page)
123 struct mm_struct* mm = vma->vm_mm; 125 struct mm_struct* mm = vma->vm_mm;
124 unsigned long flags; 126 unsigned long flags;
125 int oldpid; 127 int oldpid;
126#if 0
127 printk("[tlbpage<%02lx,%08lx>]\n",
128 (unsigned long)mm->context, page);
129#endif
130 128
131 if(mm->context == NO_CONTEXT) 129 if(mm->context == NO_CONTEXT)
132 return; 130 return;
@@ -142,404 +140,5 @@ void flush_tlb_page (struct vm_area_struct *vma, unsigned long page)
142 set_rasid_register(oldpid); 140 set_rasid_register(oldpid);
143 141
144 local_irq_restore(flags); 142 local_irq_restore(flags);
145
146#if 0
147 flush_tlb_all();
148 return;
149#endif
150}
151
152
153#ifdef DEBUG_TLB
154
155#define USE_ITLB 0
156#define USE_DTLB 1
157
158struct way_config_t {
159 int indicies;
160 int indicies_log2;
161 int pgsz_log2;
162 int arf;
163};
164
165static struct way_config_t itlb[XCHAL_ITLB_WAYS] =
166{
167 { XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES),
168 XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES_LOG2),
169 XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, PAGESZ_LOG2_MIN),
170 XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ARF)
171 },
172 { XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES),
173 XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES_LOG2),
174 XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, PAGESZ_LOG2_MIN),
175 XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ARF)
176 },
177 { XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES),
178 XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES_LOG2),
179 XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, PAGESZ_LOG2_MIN),
180 XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ARF)
181 },
182 { XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES),
183 XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES_LOG2),
184 XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, PAGESZ_LOG2_MIN),
185 XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ARF)
186 },
187 { XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES),
188 XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES_LOG2),
189 XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, PAGESZ_LOG2_MIN),
190 XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ARF)
191 },
192 { XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES),
193 XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES_LOG2),
194 XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, PAGESZ_LOG2_MIN),
195 XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ARF)
196 },
197 { XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES),
198 XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES_LOG2),
199 XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, PAGESZ_LOG2_MIN),
200 XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ARF)
201 }
202};
203
204static struct way_config_t dtlb[XCHAL_DTLB_WAYS] =
205{
206 { XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES),
207 XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES_LOG2),
208 XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, PAGESZ_LOG2_MIN),
209 XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ARF)
210 },
211 { XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES),
212 XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES_LOG2),
213 XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, PAGESZ_LOG2_MIN),
214 XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ARF)
215 },
216 { XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES),
217 XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES_LOG2),
218 XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, PAGESZ_LOG2_MIN),
219 XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ARF)
220 },
221 { XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES),
222 XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES_LOG2),
223 XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, PAGESZ_LOG2_MIN),
224 XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ARF)
225 },
226 { XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES),
227 XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES_LOG2),
228 XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, PAGESZ_LOG2_MIN),
229 XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ARF)
230 },
231 { XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES),
232 XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES_LOG2),
233 XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, PAGESZ_LOG2_MIN),
234 XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ARF)
235 },
236 { XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES),
237 XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES_LOG2),
238 XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, PAGESZ_LOG2_MIN),
239 XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ARF)
240 },
241 { XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES),
242 XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES_LOG2),
243 XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, PAGESZ_LOG2_MIN),
244 XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ARF)
245 },
246 { XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES),
247 XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES_LOG2),
248 XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, PAGESZ_LOG2_MIN),
249 XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ARF)
250 },
251 { XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES),
252 XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES_LOG2),
253 XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, PAGESZ_LOG2_MIN),
254 XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ARF)
255 }
256};
257
258/* Total number of entries: */
259#define ITLB_TOTAL_ENTRIES \
260 XCHAL_ITLB_SET(XCHAL_ITLB_WAY0_SET, ENTRIES) + \
261 XCHAL_ITLB_SET(XCHAL_ITLB_WAY1_SET, ENTRIES) + \
262 XCHAL_ITLB_SET(XCHAL_ITLB_WAY2_SET, ENTRIES) + \
263 XCHAL_ITLB_SET(XCHAL_ITLB_WAY3_SET, ENTRIES) + \
264 XCHAL_ITLB_SET(XCHAL_ITLB_WAY4_SET, ENTRIES) + \
265 XCHAL_ITLB_SET(XCHAL_ITLB_WAY5_SET, ENTRIES) + \
266 XCHAL_ITLB_SET(XCHAL_ITLB_WAY6_SET, ENTRIES)
267#define DTLB_TOTAL_ENTRIES \
268 XCHAL_DTLB_SET(XCHAL_DTLB_WAY0_SET, ENTRIES) + \
269 XCHAL_DTLB_SET(XCHAL_DTLB_WAY1_SET, ENTRIES) + \
270 XCHAL_DTLB_SET(XCHAL_DTLB_WAY2_SET, ENTRIES) + \
271 XCHAL_DTLB_SET(XCHAL_DTLB_WAY3_SET, ENTRIES) + \
272 XCHAL_DTLB_SET(XCHAL_DTLB_WAY4_SET, ENTRIES) + \
273 XCHAL_DTLB_SET(XCHAL_DTLB_WAY5_SET, ENTRIES) + \
274 XCHAL_DTLB_SET(XCHAL_DTLB_WAY6_SET, ENTRIES) + \
275 XCHAL_DTLB_SET(XCHAL_DTLB_WAY7_SET, ENTRIES) + \
276 XCHAL_DTLB_SET(XCHAL_DTLB_WAY8_SET, ENTRIES) + \
277 XCHAL_DTLB_SET(XCHAL_DTLB_WAY9_SET, ENTRIES)
278
279
280typedef struct {
281 unsigned va;
282 unsigned pa;
283 unsigned char asid;
284 unsigned char ca;
285 unsigned char way;
286 unsigned char index;
287 unsigned char pgsz_log2; /* 0 .. 32 */
288 unsigned char type; /* 0=ITLB 1=DTLB */
289} tlb_dump_entry_t;
290
291/* Return -1 if a precedes b, +1 if a follows b, 0 if same: */
292int cmp_tlb_dump_info( tlb_dump_entry_t *a, tlb_dump_entry_t *b )
293{
294 if (a->asid < b->asid) return -1;
295 if (a->asid > b->asid) return 1;
296 if (a->va < b->va) return -1;
297 if (a->va > b->va) return 1;
298 if (a->pa < b->pa) return -1;
299 if (a->pa > b->pa) return 1;
300 if (a->ca < b->ca) return -1;
301 if (a->ca > b->ca) return 1;
302 if (a->way < b->way) return -1;
303 if (a->way > b->way) return 1;
304 if (a->index < b->index) return -1;
305 if (a->index > b->index) return 1;
306 return 0;
307}
308
309void sort_tlb_dump_info( tlb_dump_entry_t *t, int n )
310{
311 int i, j;
312 /* Simple O(n*n) sort: */
313 for (i = 0; i < n-1; i++)
314 for (j = i+1; j < n; j++)
315 if (cmp_tlb_dump_info(t+i, t+j) > 0) {
316 tlb_dump_entry_t tmp = t[i];
317 t[i] = t[j];
318 t[j] = tmp;
319 }
320}
321
322
323static tlb_dump_entry_t itlb_dump_info[ITLB_TOTAL_ENTRIES];
324static tlb_dump_entry_t dtlb_dump_info[DTLB_TOTAL_ENTRIES];
325
326
327static inline char *way_type (int type)
328{
329 return type ? "autorefill" : "non-autorefill";
330}
331
332void print_entry (struct way_config_t *way_info,
333 unsigned int way,
334 unsigned int index,
335 unsigned int virtual,
336 unsigned int translation)
337{
338 char valid_chr;
339 unsigned int va, pa, asid, ca;
340
341 va = virtual &
342 ~((1 << (way_info->pgsz_log2 + way_info->indicies_log2)) - 1);
343 asid = virtual & ((1 << XCHAL_MMU_ASID_BITS) - 1);
344 pa = translation & ~((1 << way_info->pgsz_log2) - 1);
345 ca = translation & ((1 << XCHAL_MMU_CA_BITS) - 1);
346 valid_chr = asid ? 'V' : 'I';
347
348 /* Compute and incorporate the effect of the index bits on the
349 * va. It's more useful for kernel debugging, since we always
350 * want to know the effective va anyway. */
351
352 va += index << way_info->pgsz_log2;
353
354 printk ("\t[%d,%d] (%c) vpn 0x%.8x ppn 0x%.8x asid 0x%.2x am 0x%x\n",
355 way, index, valid_chr, va, pa, asid, ca);
356}
357
358void print_itlb_entry (struct way_config_t *way_info, int way, int index)
359{
360 print_entry (way_info, way, index,
361 read_itlb_virtual (way + (index << way_info->pgsz_log2)),
362 read_itlb_translation (way + (index << way_info->pgsz_log2)));
363}
364
365void print_dtlb_entry (struct way_config_t *way_info, int way, int index)
366{
367 print_entry (way_info, way, index,
368 read_dtlb_virtual (way + (index << way_info->pgsz_log2)),
369 read_dtlb_translation (way + (index << way_info->pgsz_log2)));
370}
371
372void dump_itlb (void)
373{
374 int way, index;
375
376 printk ("\nITLB: ways = %d\n", XCHAL_ITLB_WAYS);
377
378 for (way = 0; way < XCHAL_ITLB_WAYS; way++) {
379 printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
380 way, itlb[way].indicies,
381 itlb[way].pgsz_log2, way_type(itlb[way].arf));
382 for (index = 0; index < itlb[way].indicies; index++) {
383 print_itlb_entry(&itlb[way], way, index);
384 }
385 }
386}
387
388void dump_dtlb (void)
389{
390 int way, index;
391
392 printk ("\nDTLB: ways = %d\n", XCHAL_DTLB_WAYS);
393
394 for (way = 0; way < XCHAL_DTLB_WAYS; way++) {
395 printk ("\nWay: %d, Entries: %d, MinPageSize: %d, Type: %s\n",
396 way, dtlb[way].indicies,
397 dtlb[way].pgsz_log2, way_type(dtlb[way].arf));
398 for (index = 0; index < dtlb[way].indicies; index++) {
399 print_dtlb_entry(&dtlb[way], way, index);
400 }
401 }
402}
403
404void dump_tlb (tlb_dump_entry_t *tinfo, struct way_config_t *config,
405 int entries, int ways, int type, int show_invalid)
406{
407 tlb_dump_entry_t *e = tinfo;
408 int way, i;
409
410 /* Gather all info: */
411 for (way = 0; way < ways; way++) {
412 struct way_config_t *cfg = config + way;
413 for (i = 0; i < cfg->indicies; i++) {
414 unsigned wayindex = way + (i << cfg->pgsz_log2);
415 unsigned vv = (type ? read_dtlb_virtual (wayindex)
416 : read_itlb_virtual (wayindex));
417 unsigned pp = (type ? read_dtlb_translation (wayindex)
418 : read_itlb_translation (wayindex));
419
420 /* Compute and incorporate the effect of the index bits on the
421 * va. It's more useful for kernel debugging, since we always
422 * want to know the effective va anyway. */
423
424 e->va = (vv & ~((1 << (cfg->pgsz_log2 + cfg->indicies_log2)) - 1));
425 e->va += (i << cfg->pgsz_log2);
426 e->pa = (pp & ~((1 << cfg->pgsz_log2) - 1));
427 e->asid = (vv & ((1 << XCHAL_MMU_ASID_BITS) - 1));
428 e->ca = (pp & ((1 << XCHAL_MMU_CA_BITS) - 1));
429 e->way = way;
430 e->index = i;
431 e->pgsz_log2 = cfg->pgsz_log2;
432 e->type = type;
433 e++;
434 }
435 }
436#if 1
437 /* Sort by ASID and VADDR: */
438 sort_tlb_dump_info (tinfo, entries);
439#endif
440
441 /* Display all sorted info: */
442 printk ("\n%cTLB dump:\n", (type ? 'D' : 'I'));
443 for (e = tinfo, i = 0; i < entries; i++, e++) {
444#if 0
445 if (e->asid == 0 && !show_invalid)
446 continue;
447#endif
448 printk ("%c way=%d i=%d ASID=%02X V=%08X -> P=%08X CA=%X (%d %cB)\n",
449 (e->type ? 'D' : 'I'), e->way, e->index,
450 e->asid, e->va, e->pa, e->ca,
451 (1 << (e->pgsz_log2 % 10)),
452 " kMG"[e->pgsz_log2 / 10]
453 );
454 }
455}
456
457void dump_tlbs2 (int showinv)
458{
459 dump_tlb (itlb_dump_info, itlb, ITLB_TOTAL_ENTRIES, XCHAL_ITLB_WAYS, 0, showinv);
460 dump_tlb (dtlb_dump_info, dtlb, DTLB_TOTAL_ENTRIES, XCHAL_DTLB_WAYS, 1, showinv);
461}
462
463void dump_all_tlbs (void)
464{
465 dump_tlbs2 (1);
466}
467
468void dump_valid_tlbs (void)
469{
470 dump_tlbs2 (0);
471} 143}
472 144
473
474void dump_tlbs (void)
475{
476 dump_itlb();
477 dump_dtlb();
478}
479
480void dump_cache_tag(int dcache, int idx)
481{
482 int w, i, s, e;
483 unsigned long tag, index;
484 unsigned long num_lines, num_ways, cache_size, line_size;
485
486 num_ways = dcache ? XCHAL_DCACHE_WAYS : XCHAL_ICACHE_WAYS;
487 cache_size = dcache ? XCHAL_DCACHE_SIZE : XCHAL_ICACHE_SIZE;
488 line_size = dcache ? XCHAL_DCACHE_LINESIZE : XCHAL_ICACHE_LINESIZE;
489
490 num_lines = cache_size / num_ways;
491
492 s = 0; e = num_lines;
493
494 if (idx >= 0)
495 e = (s = idx * line_size) + 1;
496
497 for (i = s; i < e; i+= line_size) {
498 printk("\nline %#08x:", i);
499 for (w = 0; w < num_ways; w++) {
500 index = w * num_lines + i;
501 if (dcache)
502 __asm__ __volatile__("ldct %0, %1\n\t"
503 : "=a"(tag) : "a"(index));
504 else
505 __asm__ __volatile__("lict %0, %1\n\t"
506 : "=a"(tag) : "a"(index));
507
508 printk(" %#010lx", tag);
509 }
510 }
511 printk ("\n");
512}
513
514void dump_icache(int index)
515{
516 unsigned long data, addr;
517 int w, i;
518
519 const unsigned long num_ways = XCHAL_ICACHE_WAYS;
520 const unsigned long cache_size = XCHAL_ICACHE_SIZE;
521 const unsigned long line_size = XCHAL_ICACHE_LINESIZE;
522 const unsigned long num_lines = cache_size / num_ways / line_size;
523
524 for (w = 0; w < num_ways; w++) {
525 printk ("\nWay %d", w);
526
527 for (i = 0; i < line_size; i+= 4) {
528 addr = w * num_lines + index * line_size + i;
529 __asm__ __volatile__("licw %0, %1\n\t"
530 : "=a"(data) : "a"(addr));
531 printk(" %#010lx", data);
532 }
533 }
534 printk ("\n");
535}
536
537void dump_cache_tags(void)
538{
539 printk("Instruction cache\n");
540 dump_cache_tag(0, -1);
541 printk("Data cache\n");
542 dump_cache_tag(1, -1);
543}
544
545#endif
diff --git a/arch/xtensa/platform-iss/console.c b/arch/xtensa/platform-iss/console.c
index 5c947cae7520..2f4f20ffe666 100644
--- a/arch/xtensa/platform-iss/console.c
+++ b/arch/xtensa/platform-iss/console.c
@@ -25,11 +25,15 @@
25#include <asm/uaccess.h> 25#include <asm/uaccess.h>
26#include <asm/irq.h> 26#include <asm/irq.h>
27 27
28#include <xtensa/simcall.h> 28#include <asm/platform/simcall.h>
29 29
30#include <linux/tty.h> 30#include <linux/tty.h>
31#include <linux/tty_flip.h> 31#include <linux/tty_flip.h>
32 32
33#ifdef SERIAL_INLINE
34#define _INLINE_ inline
35#endif
36
33#define SERIAL_MAX_NUM_LINES 1 37#define SERIAL_MAX_NUM_LINES 1
34#define SERIAL_TIMER_VALUE (20 * HZ) 38#define SERIAL_TIMER_VALUE (20 * HZ)
35 39
@@ -191,7 +195,7 @@ static int rs_read_proc(char *page, char **start, off_t off, int count,
191} 195}
192 196
193 197
194static const struct tty_operations serial_ops = { 198static struct tty_operations serial_ops = {
195 .open = rs_open, 199 .open = rs_open,
196 .close = rs_close, 200 .close = rs_close,
197 .write = rs_write, 201 .write = rs_write,
diff --git a/arch/xtensa/platform-iss/network.c b/arch/xtensa/platform-iss/network.c
index 15d64414bd60..8ebfc8761229 100644
--- a/arch/xtensa/platform-iss/network.c
+++ b/arch/xtensa/platform-iss/network.c
@@ -34,7 +34,7 @@
34#include <linux/timer.h> 34#include <linux/timer.h>
35#include <linux/platform_device.h> 35#include <linux/platform_device.h>
36 36
37#include <xtensa/simcall.h> 37#include <asm/platform/simcall.h>
38 38
39#define DRIVER_NAME "iss-netdev" 39#define DRIVER_NAME "iss-netdev"
40#define ETH_MAX_PACKET 1500 40#define ETH_MAX_PACKET 1500
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 14:46:45 -0500