diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2011-03-24 13:28:40 -0400 |
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committer | Thomas Gleixner <tglx@linutronix.de> | 2011-03-24 15:35:59 -0400 |
commit | 47a5d9dcbb595b1bef54f59ba3846170e13be32a (patch) | |
tree | bfb8b9b2321970723b145db8d363c79bfaf2bca4 /arch/xtensa | |
parent | 610e1756eafdeca15cc24ade6dae23d8129225f9 (diff) |
xtensa: Use generic show_interrupts()
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/xtensa')
-rw-r--r-- | arch/xtensa/Kconfig | 1 | ||||
-rw-r--r-- | arch/xtensa/kernel/irq.c | 53 |
2 files changed, 10 insertions, 44 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index a1c7482ad0ec..d0ecf7e2a9b6 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig | |||
@@ -8,6 +8,7 @@ config XTENSA | |||
8 | def_bool y | 8 | def_bool y |
9 | select HAVE_IDE | 9 | select HAVE_IDE |
10 | select HAVE_GENERIC_HARDIRQS | 10 | select HAVE_GENERIC_HARDIRQS |
11 | select GENERIC_IRQ_SHOW | ||
11 | select GENERIC_HARDIRQS_NO_DEPRECATED | 12 | select GENERIC_HARDIRQS_NO_DEPRECATED |
12 | help | 13 | help |
13 | Xtensa processors are 32-bit RISC machines designed by Tensilica | 14 | Xtensa processors are 32-bit RISC machines designed by Tensilica |
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c index 98c0d6bafdf2..d77089df412e 100644 --- a/arch/xtensa/kernel/irq.c +++ b/arch/xtensa/kernel/irq.c | |||
@@ -62,51 +62,16 @@ asmlinkage void do_IRQ(int irq, struct pt_regs *regs) | |||
62 | set_irq_regs(old_regs); | 62 | set_irq_regs(old_regs); |
63 | } | 63 | } |
64 | 64 | ||
65 | /* | 65 | int arch_show_interrupts(struct seq_file *p, int prec) |
66 | * Generic, controller-independent functions: | ||
67 | */ | ||
68 | |||
69 | int show_interrupts(struct seq_file *p, void *v) | ||
70 | { | 66 | { |
71 | int i = *(loff_t *) v, j; | 67 | int j; |
72 | struct irqaction * action; | 68 | |
73 | unsigned long flags; | 69 | seq_printf(p, "%*s: ", prec, "NMI"); |
74 | 70 | for_each_online_cpu(j) | |
75 | if (i == 0) { | 71 | seq_printf(p, "%10u ", nmi_count(j)); |
76 | seq_printf(p, " "); | 72 | seq_putc(p, '\n'); |
77 | for_each_online_cpu(j) | 73 | seq_printf(p, "%*s: ", prec, "ERR"); |
78 | seq_printf(p, "CPU%d ",j); | 74 | seq_printf(p, "%10u\n", atomic_read(&irq_err_count)); |
79 | seq_putc(p, '\n'); | ||
80 | } | ||
81 | |||
82 | if (i < NR_IRQS) { | ||
83 | raw_spin_lock_irqsave(&irq_desc[i].lock, flags); | ||
84 | action = irq_desc[i].action; | ||
85 | if (!action) | ||
86 | goto skip; | ||
87 | seq_printf(p, "%3d: ",i); | ||
88 | #ifndef CONFIG_SMP | ||
89 | seq_printf(p, "%10u ", kstat_irqs(i)); | ||
90 | #else | ||
91 | for_each_online_cpu(j) | ||
92 | seq_printf(p, "%10u ", kstat_irqs_cpu(i, j)); | ||
93 | #endif | ||
94 | seq_printf(p, " %14s", irq_desc[i].chip->name); | ||
95 | seq_printf(p, " %s", action->name); | ||
96 | |||
97 | for (action=action->next; action; action = action->next) | ||
98 | seq_printf(p, ", %s", action->name); | ||
99 | |||
100 | seq_putc(p, '\n'); | ||
101 | skip: | ||
102 | raw_spin_unlock_irqrestore(&irq_desc[i].lock, flags); | ||
103 | } else if (i == NR_IRQS) { | ||
104 | seq_printf(p, "NMI: "); | ||
105 | for_each_online_cpu(j) | ||
106 | seq_printf(p, "%10u ", nmi_count(j)); | ||
107 | seq_putc(p, '\n'); | ||
108 | seq_printf(p, "ERR: %10u\n", atomic_read(&irq_err_count)); | ||
109 | } | ||
110 | return 0; | 75 | return 0; |
111 | } | 76 | } |
112 | 77 | ||