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authorLinus Torvalds <torvalds@linux-foundation.org>2009-04-03 18:15:25 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2009-04-03 18:15:25 -0400
commit4e76c5ccd5ac9bd003467d3bb0f49b18572dd4cd (patch)
tree1c1b58b1964fec04ae7f830b53a47f1693993135 /arch/xtensa
parentb983471794e568fd71fa767da77a62ba517c3e63 (diff)
parent65127d28e312bb6b38ce84a7bb71d762ef63ad4c (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/czankel/xtensa-2.6: (21 commits) xtensa: we don't need to include asm/io.h xtensa: only build platform or variant if they contain a Makefile xtensa: make startup code discardable xtensa: ccount clocksource xtensa: remove platform rtc hooks xtensa: use generic sched_clock() xtensa: platform: s6105 xtensa: let platform override KERNELOFFSET xtensa: s6000 variant xtensa: s6000 variant core definitions xtensa: variant irq set callbacks xtensa: variant-specific code xtensa: nommu support xtensa: add flat support xtensa: enforce slab alignment to maximum register width xtensa: cope with ram beginning at higher addresses xtensa: don't make bootmem bitmap larger than required xtensa: fix init_bootmem_node() argument order xtensa: use correct stack pointer for stack traces xtensa: beat Kconfig into shape ...
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/Kconfig184
-rw-r--r--arch/xtensa/Makefile15
-rw-r--r--arch/xtensa/configs/s6105_defconfig530
-rw-r--r--arch/xtensa/include/asm/cacheflush.h10
-rw-r--r--arch/xtensa/include/asm/dma.h3
-rw-r--r--arch/xtensa/include/asm/flat.h12
-rw-r--r--arch/xtensa/include/asm/gpio.h56
-rw-r--r--arch/xtensa/include/asm/io.h9
-rw-r--r--arch/xtensa/include/asm/irq.h7
-rw-r--r--arch/xtensa/include/asm/mmu.h5
-rw-r--r--arch/xtensa/include/asm/mmu_context.h9
-rw-r--r--arch/xtensa/include/asm/nommu.h3
-rw-r--r--arch/xtensa/include/asm/nommu_context.h25
-rw-r--r--arch/xtensa/include/asm/page.h14
-rw-r--r--arch/xtensa/include/asm/pgtable.h13
-rw-r--r--arch/xtensa/include/asm/platform.h11
-rw-r--r--arch/xtensa/include/asm/processor.h8
-rw-r--r--arch/xtensa/kernel/entry.S3
-rw-r--r--arch/xtensa/kernel/head.S5
-rw-r--r--arch/xtensa/kernel/irq.c14
-rw-r--r--arch/xtensa/kernel/platform.c2
-rw-r--r--arch/xtensa/kernel/setup.c7
-rw-r--r--arch/xtensa/kernel/time.c131
-rw-r--r--arch/xtensa/kernel/traps.c16
-rw-r--r--arch/xtensa/kernel/vectors.S4
-rw-r--r--arch/xtensa/kernel/vmlinux.lds.S3
-rw-r--r--arch/xtensa/mm/Makefile3
-rw-r--r--arch/xtensa/mm/init.c78
-rw-r--r--arch/xtensa/mm/misc.S2
-rw-r--r--arch/xtensa/mm/mmu.c70
-rw-r--r--arch/xtensa/platforms/s6105/Makefile3
-rw-r--r--arch/xtensa/platforms/s6105/device.c67
-rw-r--r--arch/xtensa/platforms/s6105/include/platform/gpio.h27
-rw-r--r--arch/xtensa/platforms/s6105/include/platform/hardware.h11
-rw-r--r--arch/xtensa/platforms/s6105/include/platform/serial.h8
-rw-r--r--arch/xtensa/platforms/s6105/setup.c61
-rw-r--r--arch/xtensa/platforms/xt2000/include/platform/hardware.h1
-rw-r--r--arch/xtensa/variants/s6000/Makefile3
-rw-r--r--arch/xtensa/variants/s6000/gpio.c71
-rw-r--r--arch/xtensa/variants/s6000/include/variant/core.h431
-rw-r--r--arch/xtensa/variants/s6000/include/variant/hardware.h259
-rw-r--r--arch/xtensa/variants/s6000/include/variant/irq.h9
-rw-r--r--arch/xtensa/variants/s6000/include/variant/tie-asm.h304
-rw-r--r--arch/xtensa/variants/s6000/include/variant/tie.h191
-rw-r--r--arch/xtensa/variants/s6000/irq.c74
45 files changed, 2466 insertions, 306 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index 981200830432..fa6dc4dd3b19 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -4,16 +4,13 @@
4mainmenu "Linux/Xtensa Kernel Configuration" 4mainmenu "Linux/Xtensa Kernel Configuration"
5 5
6config FRAME_POINTER 6config FRAME_POINTER
7 bool 7 def_bool n
8 default n
9 8
10config ZONE_DMA 9config ZONE_DMA
11 bool 10 def_bool y
12 default y
13 11
14config XTENSA 12config XTENSA
15 bool 13 def_bool y
16 default y
17 select HAVE_IDE 14 select HAVE_IDE
18 help 15 help
19 Xtensa processors are 32-bit RISC machines designed by Tensilica 16 Xtensa processors are 32-bit RISC machines designed by Tensilica
@@ -24,28 +21,25 @@ config XTENSA
24 a home page at <http://xtensa.sourceforge.net/>. 21 a home page at <http://xtensa.sourceforge.net/>.
25 22
26config RWSEM_XCHGADD_ALGORITHM 23config RWSEM_XCHGADD_ALGORITHM
27 bool 24 def_bool y
28 default y
29 25
30config GENERIC_FIND_NEXT_BIT 26config GENERIC_FIND_NEXT_BIT
31 bool 27 def_bool y
32 default y
33 28
34config GENERIC_HWEIGHT 29config GENERIC_HWEIGHT
35 bool 30 def_bool y
36 default y
37 31
38config GENERIC_HARDIRQS 32config GENERIC_HARDIRQS
39 bool 33 def_bool y
40 default y 34
35config GENERIC_GPIO
36 def_bool y
41 37
42config ARCH_HAS_ILOG2_U32 38config ARCH_HAS_ILOG2_U32
43 bool 39 def_bool n
44 default n
45 40
46config ARCH_HAS_ILOG2_U64 41config ARCH_HAS_ILOG2_U64
47 bool 42 def_bool n
48 default n
49 43
50config NO_IOPORT 44config NO_IOPORT
51 def_bool y 45 def_bool y
@@ -54,9 +48,18 @@ config HZ
54 int 48 int
55 default 100 49 default 100
56 50
51config GENERIC_TIME
52 def_bool y
53
57source "init/Kconfig" 54source "init/Kconfig"
58source "kernel/Kconfig.freezer" 55source "kernel/Kconfig.freezer"
59 56
57config MMU
58 def_bool n
59
60config VARIANT_IRQ_SWITCH
61 def_bool n
62
60menu "Processor type and features" 63menu "Processor type and features"
61 64
62choice 65choice
@@ -65,38 +68,41 @@ choice
65 68
66config XTENSA_VARIANT_FSF 69config XTENSA_VARIANT_FSF
67 bool "fsf - default (not generic) configuration" 70 bool "fsf - default (not generic) configuration"
71 select MMU
68 72
69config XTENSA_VARIANT_DC232B 73config XTENSA_VARIANT_DC232B
70 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 74 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)"
75 select MMU
71 help 76 help
72 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 77 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE).
73endchoice
74 78
75config MMU 79config XTENSA_VARIANT_S6000
76 bool 80 bool "s6000 - Stretch software configurable processor"
77 default y 81 select VARIANT_IRQ_SWITCH
82 select ARCH_REQUIRE_GPIOLIB
83endchoice
78 84
79config XTENSA_UNALIGNED_USER 85config XTENSA_UNALIGNED_USER
80 bool "Unaligned memory access in use space" 86 bool "Unaligned memory access in use space"
81 ---help--- 87 help
82 The Xtensa architecture currently does not handle unaligned 88 The Xtensa architecture currently does not handle unaligned
83 memory accesses in hardware but through an exception handler. 89 memory accesses in hardware but through an exception handler.
84 Per default, unaligned memory accesses are disabled in user space. 90 Per default, unaligned memory accesses are disabled in user space.
85 91
86 Say Y here to enable unaligned memory access in user space. 92 Say Y here to enable unaligned memory access in user space.
87 93
88config PREEMPT 94config PREEMPT
89 bool "Preemptible Kernel" 95 bool "Preemptible Kernel"
90 ---help--- 96 help
91 This option reduces the latency of the kernel when reacting to 97 This option reduces the latency of the kernel when reacting to
92 real-time or interactive events by allowing a low priority process to 98 real-time or interactive events by allowing a low priority process to
93 be preempted even if it is in kernel mode executing a system call. 99 be preempted even if it is in kernel mode executing a system call.
94 Unfortunately the kernel code has some race conditions if both 100 Unfortunately the kernel code has some race conditions if both
95 CONFIG_SMP and CONFIG_PREEMPT are enabled, so this option is 101 CONFIG_SMP and CONFIG_PREEMPT are enabled, so this option is
96 currently disabled if you are building an SMP kernel. 102 currently disabled if you are building an SMP kernel.
97 103
98 Say Y here if you are building a kernel for a desktop, embedded 104 Say Y here if you are building a kernel for a desktop, embedded
99 or real-time system. Say N if you are unsure. 105 or real-time system. Say N if you are unsure.
100 106
101config MATH_EMULATION 107config MATH_EMULATION
102 bool "Math emulation" 108 bool "Math emulation"
@@ -105,6 +111,32 @@ config MATH_EMULATION
105 111
106endmenu 112endmenu
107 113
114config XTENSA_CALIBRATE_CCOUNT
115 def_bool n
116 help
117 On some platforms (XT2000, for example), the CPU clock rate can
118 vary. The frequency can be determined, however, by measuring
119 against a well known, fixed frequency, such as an UART oscillator.
120
121config SERIAL_CONSOLE
122 def_bool n
123
124config XTENSA_ISS_NETWORK
125 def_bool n
126
127menu "Bus options"
128
129config PCI
130 bool "PCI support"
131 default y
132 help
133 Find out whether you have a PCI motherboard. PCI is the name of a
134 bus system, i.e. the way the CPU talks to the other stuff inside
135 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
136 VESA. If you have PCI, say Y, otherwise N.
137
138source "drivers/pci/Kconfig"
139
108menu "Platform options" 140menu "Platform options"
109 141
110choice 142choice
@@ -113,33 +145,35 @@ choice
113 145
114config XTENSA_PLATFORM_ISS 146config XTENSA_PLATFORM_ISS
115 bool "ISS" 147 bool "ISS"
148 select XTENSA_CALIBRATE_CCOUNT
149 select SERIAL_CONSOLE
150 select XTENSA_ISS_NETWORK
116 help 151 help
117 ISS is an acronym for Tensilica's Instruction Set Simulator. 152 ISS is an acronym for Tensilica's Instruction Set Simulator.
118 153
119config XTENSA_PLATFORM_XT2000 154config XTENSA_PLATFORM_XT2000
120 bool "XT2000" 155 bool "XT2000"
156 select XTENSA_CALIBRATE_CCOUNT
157 select PCI
121 help 158 help
122 XT2000 is the name of Tensilica's feature-rich emulation platform. 159 XT2000 is the name of Tensilica's feature-rich emulation platform.
123 This hardware is capable of running a full Linux distribution. 160 This hardware is capable of running a full Linux distribution.
124 161
125endchoice 162config XTENSA_PLATFORM_S6105
163 bool "S6105"
164 select SERIAL_CONSOLE
126 165
166endchoice
127 167
128config XTENSA_CALIBRATE_CCOUNT
129 bool "Auto calibration of the CPU clock rate"
130 ---help---
131 On some platforms (XT2000, for example), the CPU clock rate can
132 vary. The frequency can be determined, however, by measuring
133 against a well known, fixed frequency, such as an UART oscillator.
134 168
135config XTENSA_CPU_CLOCK 169config XTENSA_CPU_CLOCK
136 int "CPU clock rate [MHz]" 170 int "CPU clock rate [MHz]"
137 depends on !XTENSA_CALIBRATE_CCOUNT 171 depends on !XTENSA_CALIBRATE_CCOUNT
138 default "16" 172 default 16
139 173
140config GENERIC_CALIBRATE_DELAY 174config GENERIC_CALIBRATE_DELAY
141 bool "Auto calibration of the BogoMIPS value" 175 bool "Auto calibration of the BogoMIPS value"
142 ---help--- 176 help
143 The BogoMIPS value can easily be derived from the CPU frequency. 177 The BogoMIPS value can easily be derived from the CPU frequency.
144 178
145config CMDLINE_BOOL 179config CMDLINE_BOOL
@@ -156,52 +190,27 @@ config CMDLINE
156 time by entering them here. As a minimum, you should specify the 190 time by entering them here. As a minimum, you should specify the
157 memory size and the root device (e.g., mem=64M root=/dev/nfs). 191 memory size and the root device (e.g., mem=64M root=/dev/nfs).
158 192
159config SERIAL_CONSOLE
160 bool
161 depends on XTENSA_PLATFORM_ISS
162 default y
163
164config XTENSA_ISS_NETWORK
165 bool
166 depends on XTENSA_PLATFORM_ISS
167 default y
168
169source "mm/Kconfig" 193source "mm/Kconfig"
170 194
171endmenu 195endmenu
172 196
173menu "Bus options" 197config HOTPLUG
174 198 bool "Support for hot-pluggable devices"
175config PCI
176 bool "PCI support" if !XTENSA_PLATFORM_ISS
177 depends on !XTENSA_PLATFORM_ISS
178 default y
179 help 199 help
180 Find out whether you have a PCI motherboard. PCI is the name of a 200 Say Y here if you want to plug devices into your computer while
181 bus system, i.e. the way the CPU talks to the other stuff inside 201 the system is running, and be able to use them quickly. In many
182 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or 202 cases, the devices can likewise be unplugged at any time too.
183 VESA. If you have PCI, say Y, otherwise N.
184 203
185source "drivers/pci/Kconfig" 204 One well known example of this is PCMCIA- or PC-cards, credit-card
205 size devices such as network cards, modems or hard drives which are
206 plugged into slots found on all modern laptop computers. Another
207 example, used on modern desktops as well as laptops, is USB.
186 208
187config HOTPLUG 209 Enable HOTPLUG and build a modular kernel. Get agent software
188 210 (from <http://linux-hotplug.sourceforge.net/>) and install it.
189 bool "Support for hot-pluggable devices" 211 Then your kernel will automatically call out to a user mode "policy
190 ---help--- 212 agent" (/sbin/hotplug) to load modules and set up software needed
191 Say Y here if you want to plug devices into your computer while 213 to use devices as you hotplug them.
192 the system is running, and be able to use them quickly. In many
193 cases, the devices can likewise be unplugged at any time too.
194
195 One well known example of this is PCMCIA- or PC-cards, credit-card
196 size devices such as network cards, modems or hard drives which are
197 plugged into slots found on all modern laptop computers. Another
198 example, used on modern desktops as well as laptops, is USB.
199
200 Enable HOTPLUG and build a modular kernel. Get agent software
201 (from <http://linux-hotplug.sourceforge.net/>) and install it.
202 Then your kernel will automatically call out to a user mode "policy
203 agent" (/sbin/hotplug) to load modules and set up software needed
204 to use devices as you hotplug them.
205 214
206source "drivers/pcmcia/Kconfig" 215source "drivers/pcmcia/Kconfig"
207 216
@@ -213,9 +222,8 @@ menu "Executable file formats"
213 222
214# only elf supported 223# only elf supported
215config KCORE_ELF 224config KCORE_ELF
216 bool 225 def_bool y
217 depends on PROC_FS 226 depends on PROC_FS
218 default y
219 help 227 help
220 If you enabled support for /proc file system then the file 228 If you enabled support for /proc file system then the file
221 /proc/kcore will contain the kernel core image in ELF format. This 229 /proc/kcore will contain the kernel core image in ELF format. This
@@ -240,7 +248,7 @@ source "fs/Kconfig"
240menu "Xtensa initrd options" 248menu "Xtensa initrd options"
241 depends on BLK_DEV_INITRD 249 depends on BLK_DEV_INITRD
242 250
243 config EMBEDDED_RAMDISK 251config EMBEDDED_RAMDISK
244 bool "Embed root filesystem ramdisk into the kernel" 252 bool "Embed root filesystem ramdisk into the kernel"
245 253
246config EMBEDDED_RAMDISK_IMAGE 254config EMBEDDED_RAMDISK_IMAGE
diff --git a/arch/xtensa/Makefile b/arch/xtensa/Makefile
index 1da55fe4beff..4caffac3ca2e 100644
--- a/arch/xtensa/Makefile
+++ b/arch/xtensa/Makefile
@@ -15,6 +15,7 @@
15 15
16variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf 16variant-$(CONFIG_XTENSA_VARIANT_FSF) := fsf
17variant-$(CONFIG_XTENSA_VARIANT_DC232B) := dc232b 17variant-$(CONFIG_XTENSA_VARIANT_DC232B) := dc232b
18variant-$(CONFIG_XTENSA_VARIANT_S6000) := s6000
18variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom 19variant-$(CONFIG_XTENSA_VARIANT_LINUX_CUSTOM) := custom
19 20
20VARIANT = $(variant-y) 21VARIANT = $(variant-y)
@@ -24,6 +25,7 @@ export VARIANT
24 25
25platform-$(CONFIG_XTENSA_PLATFORM_XT2000) := xt2000 26platform-$(CONFIG_XTENSA_PLATFORM_XT2000) := xt2000
26platform-$(CONFIG_XTENSA_PLATFORM_ISS) := iss 27platform-$(CONFIG_XTENSA_PLATFORM_ISS) := iss
28platform-$(CONFIG_XTENSA_PLATFORM_S6105) := s6105
27 29
28PLATFORM = $(platform-y) 30PLATFORM = $(platform-y)
29export PLATFORM 31export PLATFORM
@@ -62,20 +64,23 @@ ifneq ($(VARIANT),)
62 endif 64 endif
63endif 65endif
64 66
65# 67# Only build variant and/or platform if it includes a Makefile
68
69buildvar := $(shell test -a $(srctree)/arch/xtensa/variants/$(VARIANT)/Makefile && echo arch/xtensa/variants/$(VARIANT)/)
70buildplf := $(shell test -a $(srctree)/arch/xtensa/platforms/$(PLATFORM)/Makefile && echo arch/xtensa/platforms/$(PLATFORM)/)
71
72# Find libgcc.a
66 73
67LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name) 74LIBGCC := $(shell $(CC) $(KBUILD_CFLAGS) -print-libgcc-file-name)
68 75
69head-y := arch/xtensa/kernel/head.o 76head-y := arch/xtensa/kernel/head.o
70core-y += arch/xtensa/kernel/ arch/xtensa/mm/ 77core-y += arch/xtensa/kernel/ arch/xtensa/mm/
71ifneq ($(PLATFORM),) 78core-y += $(buildvar) $(buildplf)
72core-y += arch/xtensa/platforms/$(PLATFORM)/ 79
73endif
74libs-y += arch/xtensa/lib/ $(LIBGCC) 80libs-y += arch/xtensa/lib/ $(LIBGCC)
75 81
76boot := arch/xtensa/boot 82boot := arch/xtensa/boot
77 83
78
79all: zImage 84all: zImage
80 85
81bzImage : zImage 86bzImage : zImage
diff --git a/arch/xtensa/configs/s6105_defconfig b/arch/xtensa/configs/s6105_defconfig
new file mode 100644
index 000000000000..6e1deff41590
--- /dev/null
+++ b/arch/xtensa/configs/s6105_defconfig
@@ -0,0 +1,530 @@
1#
2# Automatically generated make config: don't edit
3# Linux kernel version: 2.6.29-rc7-s6
4# Tue Mar 10 11:09:26 2009
5#
6# CONFIG_FRAME_POINTER is not set
7CONFIG_ZONE_DMA=y
8CONFIG_XTENSA=y
9CONFIG_RWSEM_XCHGADD_ALGORITHM=y
10CONFIG_GENERIC_FIND_NEXT_BIT=y
11CONFIG_GENERIC_HWEIGHT=y
12CONFIG_GENERIC_HARDIRQS=y
13CONFIG_GENERIC_GPIO=y
14# CONFIG_ARCH_HAS_ILOG2_U32 is not set
15# CONFIG_ARCH_HAS_ILOG2_U64 is not set
16CONFIG_NO_IOPORT=y
17CONFIG_HZ=100
18CONFIG_GENERIC_TIME=y
19CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
20
21#
22# General setup
23#
24CONFIG_EXPERIMENTAL=y
25CONFIG_BROKEN_ON_SMP=y
26CONFIG_LOCK_KERNEL=y
27CONFIG_INIT_ENV_ARG_LIMIT=32
28CONFIG_LOCALVERSION=""
29CONFIG_LOCALVERSION_AUTO=y
30CONFIG_SYSVIPC=y
31CONFIG_SYSVIPC_SYSCTL=y
32# CONFIG_POSIX_MQUEUE is not set
33# CONFIG_BSD_PROCESS_ACCT is not set
34# CONFIG_TASKSTATS is not set
35# CONFIG_AUDIT is not set
36
37#
38# RCU Subsystem
39#
40# CONFIG_CLASSIC_RCU is not set
41# CONFIG_TREE_RCU is not set
42CONFIG_PREEMPT_RCU=y
43# CONFIG_RCU_TRACE is not set
44# CONFIG_TREE_RCU_TRACE is not set
45# CONFIG_PREEMPT_RCU_TRACE is not set
46CONFIG_IKCONFIG=y
47CONFIG_IKCONFIG_PROC=y
48CONFIG_LOG_BUF_SHIFT=16
49# CONFIG_GROUP_SCHED is not set
50# CONFIG_CGROUPS is not set
51# CONFIG_SYSFS_DEPRECATED_V2 is not set
52# CONFIG_RELAY is not set
53# CONFIG_NAMESPACES is not set
54CONFIG_BLK_DEV_INITRD=y
55CONFIG_INITRAMFS_SOURCE=""
56CONFIG_CC_OPTIMIZE_FOR_SIZE=y
57CONFIG_SYSCTL=y
58CONFIG_EMBEDDED=y
59CONFIG_SYSCTL_SYSCALL=y
60CONFIG_KALLSYMS=y
61# CONFIG_KALLSYMS_ALL is not set
62# CONFIG_KALLSYMS_EXTRA_PASS is not set
63# CONFIG_HOTPLUG is not set
64CONFIG_PRINTK=y
65CONFIG_BUG=y
66CONFIG_ELF_CORE=y
67# CONFIG_COMPAT_BRK is not set
68CONFIG_BASE_FULL=y
69CONFIG_FUTEX=y
70CONFIG_ANON_INODES=y
71CONFIG_EPOLL=y
72CONFIG_SIGNALFD=y
73CONFIG_TIMERFD=y
74CONFIG_EVENTFD=y
75CONFIG_AIO=y
76CONFIG_VM_EVENT_COUNTERS=y
77CONFIG_SLAB=y
78# CONFIG_SLUB is not set
79# CONFIG_SLOB is not set
80# CONFIG_PROFILING is not set
81# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
82CONFIG_SLABINFO=y
83CONFIG_RT_MUTEXES=y
84CONFIG_BASE_SMALL=0
85# CONFIG_MODULES is not set
86CONFIG_BLOCK=y
87# CONFIG_LBD is not set
88# CONFIG_BLK_DEV_IO_TRACE is not set
89# CONFIG_BLK_DEV_BSG is not set
90# CONFIG_BLK_DEV_INTEGRITY is not set
91
92#
93# IO Schedulers
94#
95CONFIG_IOSCHED_NOOP=y
96# CONFIG_IOSCHED_AS is not set
97# CONFIG_IOSCHED_DEADLINE is not set
98CONFIG_IOSCHED_CFQ=y
99# CONFIG_DEFAULT_AS is not set
100# CONFIG_DEFAULT_DEADLINE is not set
101CONFIG_DEFAULT_CFQ=y
102# CONFIG_DEFAULT_NOOP is not set
103CONFIG_DEFAULT_IOSCHED="cfq"
104# CONFIG_FREEZER is not set
105# CONFIG_MMU is not set
106CONFIG_VARIANT_IRQ_SWITCH=y
107
108#
109# Processor type and features
110#
111# CONFIG_XTENSA_VARIANT_FSF is not set
112# CONFIG_XTENSA_VARIANT_DC232B is not set
113CONFIG_XTENSA_VARIANT_S6000=y
114# CONFIG_XTENSA_UNALIGNED_USER is not set
115CONFIG_PREEMPT=y
116# CONFIG_MATH_EMULATION is not set
117# CONFIG_HIGHMEM is not set
118# CONFIG_XTENSA_CALIBRATE_CCOUNT is not set
119CONFIG_SERIAL_CONSOLE=y
120# CONFIG_XTENSA_ISS_NETWORK is not set
121
122#
123# Bus options
124#
125# CONFIG_PCI is not set
126# CONFIG_ARCH_SUPPORTS_MSI is not set
127
128#
129# Platform options
130#
131# CONFIG_XTENSA_PLATFORM_ISS is not set
132# CONFIG_XTENSA_PLATFORM_XT2000 is not set
133CONFIG_XTENSA_PLATFORM_S6105=y
134CONFIG_XTENSA_CPU_CLOCK=300
135CONFIG_GENERIC_CALIBRATE_DELAY=y
136CONFIG_CMDLINE_BOOL=y
137CONFIG_CMDLINE="console=ttyS1,38400 debug bootmem_debug loglevel=7"
138CONFIG_SELECT_MEMORY_MODEL=y
139CONFIG_FLATMEM_MANUAL=y
140# CONFIG_DISCONTIGMEM_MANUAL is not set
141# CONFIG_SPARSEMEM_MANUAL is not set
142CONFIG_FLATMEM=y
143CONFIG_FLAT_NODE_MEM_MAP=y
144CONFIG_PAGEFLAGS_EXTENDED=y
145CONFIG_SPLIT_PTLOCK_CPUS=4
146# CONFIG_PHYS_ADDR_T_64BIT is not set
147CONFIG_ZONE_DMA_FLAG=1
148CONFIG_VIRT_TO_BUS=y
149
150#
151# Executable file formats
152#
153CONFIG_KCORE_ELF=y
154CONFIG_BINFMT_FLAT=y
155# CONFIG_BINFMT_ZFLAT is not set
156# CONFIG_BINFMT_SHARED_FLAT is not set
157# CONFIG_HAVE_AOUT is not set
158# CONFIG_BINFMT_MISC is not set
159CONFIG_NET=y
160
161#
162# Networking options
163#
164CONFIG_COMPAT_NET_DEV_OPS=y
165CONFIG_PACKET=y
166# CONFIG_PACKET_MMAP is not set
167CONFIG_UNIX=y
168# CONFIG_NET_KEY is not set
169CONFIG_INET=y
170# CONFIG_IP_MULTICAST is not set
171# CONFIG_IP_ADVANCED_ROUTER is not set
172CONFIG_IP_FIB_HASH=y
173# CONFIG_IP_PNP is not set
174# CONFIG_NET_IPIP is not set
175# CONFIG_NET_IPGRE is not set
176# CONFIG_ARPD is not set
177# CONFIG_SYN_COOKIES is not set
178# CONFIG_INET_AH is not set
179# CONFIG_INET_ESP is not set
180# CONFIG_INET_IPCOMP is not set
181# CONFIG_INET_XFRM_TUNNEL is not set
182# CONFIG_INET_TUNNEL is not set
183# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
184# CONFIG_INET_XFRM_MODE_TUNNEL is not set
185# CONFIG_INET_XFRM_MODE_BEET is not set
186# CONFIG_INET_LRO is not set
187# CONFIG_INET_DIAG is not set
188# CONFIG_TCP_CONG_ADVANCED is not set
189CONFIG_TCP_CONG_CUBIC=y
190CONFIG_DEFAULT_TCP_CONG="cubic"
191# CONFIG_TCP_MD5SIG is not set
192# CONFIG_IPV6 is not set
193# CONFIG_NETWORK_SECMARK is not set
194# CONFIG_NETFILTER is not set
195# CONFIG_IP_DCCP is not set
196# CONFIG_IP_SCTP is not set
197# CONFIG_TIPC is not set
198# CONFIG_ATM is not set
199# CONFIG_BRIDGE is not set
200# CONFIG_NET_DSA is not set
201# CONFIG_VLAN_8021Q is not set
202# CONFIG_DECNET is not set
203# CONFIG_LLC2 is not set
204# CONFIG_IPX is not set
205# CONFIG_ATALK is not set
206# CONFIG_X25 is not set
207# CONFIG_LAPB is not set
208# CONFIG_ECONET is not set
209# CONFIG_WAN_ROUTER is not set
210# CONFIG_NET_SCHED is not set
211# CONFIG_DCB is not set
212
213#
214# Network testing
215#
216# CONFIG_NET_PKTGEN is not set
217# CONFIG_HAMRADIO is not set
218# CONFIG_CAN is not set
219# CONFIG_IRDA is not set
220# CONFIG_BT is not set
221# CONFIG_AF_RXRPC is not set
222# CONFIG_PHONET is not set
223# CONFIG_WIRELESS is not set
224# CONFIG_WIMAX is not set
225# CONFIG_RFKILL is not set
226# CONFIG_NET_9P is not set
227
228#
229# Device Drivers
230#
231
232#
233# Generic Driver Options
234#
235CONFIG_STANDALONE=y
236CONFIG_PREVENT_FIRMWARE_BUILD=y
237# CONFIG_DEBUG_DRIVER is not set
238# CONFIG_DEBUG_DEVRES is not set
239# CONFIG_SYS_HYPERVISOR is not set
240# CONFIG_CONNECTOR is not set
241# CONFIG_MTD is not set
242# CONFIG_PARPORT is not set
243CONFIG_BLK_DEV=y
244# CONFIG_BLK_DEV_COW_COMMON is not set
245# CONFIG_BLK_DEV_LOOP is not set
246# CONFIG_BLK_DEV_NBD is not set
247CONFIG_BLK_DEV_RAM=y
248CONFIG_BLK_DEV_RAM_COUNT=16
249CONFIG_BLK_DEV_RAM_SIZE=4096
250# CONFIG_BLK_DEV_XIP is not set
251# CONFIG_CDROM_PKTCDVD is not set
252# CONFIG_ATA_OVER_ETH is not set
253# CONFIG_BLK_DEV_HD is not set
254# CONFIG_MISC_DEVICES is not set
255CONFIG_HAVE_IDE=y
256# CONFIG_IDE is not set
257
258#
259# SCSI device support
260#
261# CONFIG_RAID_ATTRS is not set
262# CONFIG_SCSI is not set
263# CONFIG_SCSI_DMA is not set
264# CONFIG_SCSI_NETLINK is not set
265# CONFIG_ATA is not set
266# CONFIG_MD is not set
267# CONFIG_NETDEVICES is not set
268# CONFIG_ISDN is not set
269# CONFIG_PHONE is not set
270
271#
272# Input device support
273#
274# CONFIG_INPUT is not set
275
276#
277# Hardware I/O ports
278#
279# CONFIG_SERIO is not set
280# CONFIG_GAMEPORT is not set
281
282#
283# Character devices
284#
285# CONFIG_VT is not set
286# CONFIG_DEVKMEM is not set
287# CONFIG_SERIAL_NONSTANDARD is not set
288
289#
290# Serial drivers
291#
292CONFIG_SERIAL_8250=y
293CONFIG_SERIAL_8250_CONSOLE=y
294CONFIG_SERIAL_8250_NR_UARTS=2
295CONFIG_SERIAL_8250_RUNTIME_UARTS=2
296# CONFIG_SERIAL_8250_EXTENDED is not set
297
298#
299# Non-8250 serial port support
300#
301CONFIG_SERIAL_CORE=y
302CONFIG_SERIAL_CORE_CONSOLE=y
303CONFIG_UNIX98_PTYS=y
304# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
305# CONFIG_LEGACY_PTYS is not set
306# CONFIG_IPMI_HANDLER is not set
307# CONFIG_HW_RANDOM is not set
308# CONFIG_RTC is not set
309# CONFIG_GEN_RTC is not set
310# CONFIG_R3964 is not set
311# CONFIG_RAW_DRIVER is not set
312# CONFIG_TCG_TPM is not set
313# CONFIG_I2C is not set
314# CONFIG_SPI is not set
315CONFIG_ARCH_REQUIRE_GPIOLIB=y
316CONFIG_GPIOLIB=y
317# CONFIG_DEBUG_GPIO is not set
318# CONFIG_GPIO_SYSFS is not set
319
320#
321# Memory mapped GPIO expanders:
322#
323
324#
325# I2C GPIO expanders:
326#
327
328#
329# PCI GPIO expanders:
330#
331
332#
333# SPI GPIO expanders:
334#
335# CONFIG_W1 is not set
336# CONFIG_POWER_SUPPLY is not set
337# CONFIG_HWMON is not set
338# CONFIG_THERMAL is not set
339# CONFIG_THERMAL_HWMON is not set
340# CONFIG_WATCHDOG is not set
341CONFIG_SSB_POSSIBLE=y
342
343#
344# Sonics Silicon Backplane
345#
346# CONFIG_SSB is not set
347
348#
349# Multifunction device drivers
350#
351# CONFIG_MFD_CORE is not set
352# CONFIG_MFD_SM501 is not set
353# CONFIG_HTC_PASIC3 is not set
354# CONFIG_MFD_TMIO is not set
355# CONFIG_REGULATOR is not set
356
357#
358# Multimedia devices
359#
360
361#
362# Multimedia core support
363#
364# CONFIG_VIDEO_DEV is not set
365# CONFIG_DVB_CORE is not set
366# CONFIG_VIDEO_MEDIA is not set
367
368#
369# Multimedia drivers
370#
371# CONFIG_DAB is not set
372
373#
374# Graphics support
375#
376# CONFIG_VGASTATE is not set
377# CONFIG_VIDEO_OUTPUT_CONTROL is not set
378# CONFIG_FB is not set
379# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
380
381#
382# Display device support
383#
384# CONFIG_DISPLAY_SUPPORT is not set
385# CONFIG_SOUND is not set
386# CONFIG_USB_SUPPORT is not set
387# CONFIG_MMC is not set
388# CONFIG_MEMSTICK is not set
389# CONFIG_NEW_LEDS is not set
390# CONFIG_ACCESSIBILITY is not set
391# CONFIG_RTC_CLASS is not set
392# CONFIG_DMADEVICES is not set
393# CONFIG_UIO is not set
394# CONFIG_STAGING is not set
395
396#
397# File systems
398#
399# CONFIG_EXT2_FS is not set
400# CONFIG_EXT3_FS is not set
401# CONFIG_EXT4_FS is not set
402# CONFIG_REISERFS_FS is not set
403# CONFIG_JFS_FS is not set
404# CONFIG_FS_POSIX_ACL is not set
405CONFIG_FILE_LOCKING=y
406# CONFIG_XFS_FS is not set
407# CONFIG_OCFS2_FS is not set
408# CONFIG_BTRFS_FS is not set
409# CONFIG_DNOTIFY is not set
410# CONFIG_INOTIFY is not set
411# CONFIG_QUOTA is not set
412# CONFIG_AUTOFS_FS is not set
413# CONFIG_AUTOFS4_FS is not set
414# CONFIG_FUSE_FS is not set
415
416#
417# CD-ROM/DVD Filesystems
418#
419# CONFIG_ISO9660_FS is not set
420# CONFIG_UDF_FS is not set
421
422#
423# DOS/FAT/NT Filesystems
424#
425# CONFIG_MSDOS_FS is not set
426# CONFIG_VFAT_FS is not set
427# CONFIG_NTFS_FS is not set
428
429#
430# Pseudo filesystems
431#
432CONFIG_PROC_FS=y
433CONFIG_PROC_SYSCTL=y
434CONFIG_SYSFS=y
435# CONFIG_TMPFS is not set
436# CONFIG_HUGETLB_PAGE is not set
437# CONFIG_CONFIGFS_FS is not set
438# CONFIG_MISC_FILESYSTEMS is not set
439# CONFIG_NETWORK_FILESYSTEMS is not set
440
441#
442# Partition Types
443#
444# CONFIG_PARTITION_ADVANCED is not set
445CONFIG_MSDOS_PARTITION=y
446# CONFIG_NLS is not set
447# CONFIG_DLM is not set
448
449#
450# Xtensa initrd options
451#
452# CONFIG_EMBEDDED_RAMDISK is not set
453
454#
455# Kernel hacking
456#
457CONFIG_PRINTK_TIME=y
458# CONFIG_ENABLE_WARN_DEPRECATED is not set
459# CONFIG_ENABLE_MUST_CHECK is not set
460CONFIG_FRAME_WARN=1024
461# CONFIG_MAGIC_SYSRQ is not set
462# CONFIG_UNUSED_SYMBOLS is not set
463# CONFIG_DEBUG_FS is not set
464# CONFIG_HEADERS_CHECK is not set
465CONFIG_DEBUG_KERNEL=y
466CONFIG_DEBUG_SHIRQ=y
467CONFIG_DETECT_SOFTLOCKUP=y
468# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
469CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
470# CONFIG_SCHED_DEBUG is not set
471# CONFIG_SCHEDSTATS is not set
472# CONFIG_TIMER_STATS is not set
473# CONFIG_DEBUG_OBJECTS is not set
474# CONFIG_DEBUG_SLAB is not set
475# CONFIG_DEBUG_RT_MUTEXES is not set
476# CONFIG_RT_MUTEX_TESTER is not set
477CONFIG_DEBUG_SPINLOCK=y
478CONFIG_DEBUG_MUTEXES=y
479CONFIG_DEBUG_SPINLOCK_SLEEP=y
480# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
481# CONFIG_DEBUG_KOBJECT is not set
482# CONFIG_DEBUG_INFO is not set
483# CONFIG_DEBUG_VM is not set
484CONFIG_DEBUG_NOMMU_REGIONS=y
485# CONFIG_DEBUG_WRITECOUNT is not set
486# CONFIG_DEBUG_MEMORY_INIT is not set
487# CONFIG_DEBUG_LIST is not set
488# CONFIG_DEBUG_SG is not set
489# CONFIG_DEBUG_NOTIFIERS is not set
490# CONFIG_BOOT_PRINTK_DELAY is not set
491# CONFIG_RCU_TORTURE_TEST is not set
492# CONFIG_BACKTRACE_SELF_TEST is not set
493# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
494# CONFIG_FAULT_INJECTION is not set
495# CONFIG_SYSCTL_SYSCALL_CHECK is not set
496
497#
498# Tracers
499#
500# CONFIG_PREEMPT_TRACER is not set
501# CONFIG_SCHED_TRACER is not set
502# CONFIG_CONTEXT_SWITCH_TRACER is not set
503# CONFIG_BOOT_TRACER is not set
504# CONFIG_TRACE_BRANCH_PROFILING is not set
505# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
506# CONFIG_SAMPLES is not set
507
508#
509# Security options
510#
511# CONFIG_KEYS is not set
512# CONFIG_SECURITY is not set
513# CONFIG_SECURITYFS is not set
514# CONFIG_SECURITY_FILE_CAPABILITIES is not set
515# CONFIG_CRYPTO is not set
516
517#
518# Library routines
519#
520CONFIG_GENERIC_FIND_LAST_BIT=y
521# CONFIG_CRC_CCITT is not set
522# CONFIG_CRC16 is not set
523# CONFIG_CRC_T10DIF is not set
524# CONFIG_CRC_ITU_T is not set
525# CONFIG_CRC32 is not set
526# CONFIG_CRC7 is not set
527# CONFIG_LIBCRC32C is not set
528CONFIG_PLIST=y
529CONFIG_HAS_IOMEM=y
530CONFIG_HAS_DMA=y
diff --git a/arch/xtensa/include/asm/cacheflush.h b/arch/xtensa/include/asm/cacheflush.h
index 94c4c53a099e..8fc1c0c8de07 100644
--- a/arch/xtensa/include/asm/cacheflush.h
+++ b/arch/xtensa/include/asm/cacheflush.h
@@ -65,13 +65,17 @@ extern void __flush_invalidate_dcache_range(unsigned long, unsigned long);
65# define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s) 65# define __flush_invalidate_dcache_range(p,s) __invalidate_dcache_range(p,s)
66#endif 66#endif
67 67
68#if (DCACHE_WAY_SIZE > PAGE_SIZE) 68#if defined(CONFIG_MMU) && (DCACHE_WAY_SIZE > PAGE_SIZE)
69extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long); 69extern void __flush_invalidate_dcache_page_alias(unsigned long, unsigned long);
70#else
71static inline void __flush_invalidate_dcache_page_alias(unsigned long virt,
72 unsigned long phys) { }
70#endif 73#endif
71#if (ICACHE_WAY_SIZE > PAGE_SIZE) 74#if defined(CONFIG_MMU) && (ICACHE_WAY_SIZE > PAGE_SIZE)
72extern void __invalidate_icache_page_alias(unsigned long, unsigned long); 75extern void __invalidate_icache_page_alias(unsigned long, unsigned long);
73#else 76#else
74# define __invalidate_icache_page_alias(v,p) do { } while(0) 77static inline void __invalidate_icache_page_alias(unsigned long virt,
78 unsigned long phys) { }
75#endif 79#endif
76 80
77/* 81/*
diff --git a/arch/xtensa/include/asm/dma.h b/arch/xtensa/include/asm/dma.h
index e30f3abf48f0..137ca3945b07 100644
--- a/arch/xtensa/include/asm/dma.h
+++ b/arch/xtensa/include/asm/dma.h
@@ -44,8 +44,9 @@
44 * the value desired). 44 * the value desired).
45 */ 45 */
46 46
47#ifndef MAX_DMA_ADDRESS
47#define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KIO_SIZE - 1) 48#define MAX_DMA_ADDRESS (PAGE_OFFSET + XCHAL_KIO_SIZE - 1)
48 49#endif
49 50
50/* Reserve and release a DMA channel */ 51/* Reserve and release a DMA channel */
51extern int request_dma(unsigned int dmanr, const char * device_id); 52extern int request_dma(unsigned int dmanr, const char * device_id);
diff --git a/arch/xtensa/include/asm/flat.h b/arch/xtensa/include/asm/flat.h
new file mode 100644
index 000000000000..94c44abf15e4
--- /dev/null
+++ b/arch/xtensa/include/asm/flat.h
@@ -0,0 +1,12 @@
1#ifndef __ASM_XTENSA_FLAT_H
2#define __ASM_XTENSA_FLAT_H
3
4#define flat_argvp_envp_on_stack() 0
5#define flat_old_ram_flag(flags) (flags)
6#define flat_reloc_valid(reloc, size) ((reloc) <= (size))
7#define flat_get_addr_from_rp(rp, relval, flags, p) get_unaligned(rp)
8#define flat_put_addr_at_rp(rp, val, relval ) put_unaligned(val, rp)
9#define flat_get_relocate_addr(rel) (rel)
10#define flat_set_persistent(relval, p) 0
11
12#endif /* __ASM_XTENSA_FLAT_H */
diff --git a/arch/xtensa/include/asm/gpio.h b/arch/xtensa/include/asm/gpio.h
new file mode 100644
index 000000000000..0763b0763960
--- /dev/null
+++ b/arch/xtensa/include/asm/gpio.h
@@ -0,0 +1,56 @@
1/*
2 * Generic GPIO API implementation for xtensa.
3 *
4 * Stolen from x86, which is derived from the generic GPIO API for powerpc:
5 *
6 * Copyright (c) 2007-2008 MontaVista Software, Inc.
7 *
8 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef _ASM_XTENSA_GPIO_H
17#define _ASM_XTENSA_GPIO_H
18
19#include <asm-generic/gpio.h>
20
21#ifdef CONFIG_GPIOLIB
22
23/*
24 * Just call gpiolib.
25 */
26static inline int gpio_get_value(unsigned int gpio)
27{
28 return __gpio_get_value(gpio);
29}
30
31static inline void gpio_set_value(unsigned int gpio, int value)
32{
33 __gpio_set_value(gpio, value);
34}
35
36static inline int gpio_cansleep(unsigned int gpio)
37{
38 return __gpio_cansleep(gpio);
39}
40
41/*
42 * Not implemented, yet.
43 */
44static inline int gpio_to_irq(unsigned int gpio)
45{
46 return -ENOSYS;
47}
48
49static inline int irq_to_gpio(unsigned int irq)
50{
51 return -EINVAL;
52}
53
54#endif /* CONFIG_GPIOLIB */
55
56#endif /* _ASM_XTENSA_GPIO_H */
diff --git a/arch/xtensa/include/asm/io.h b/arch/xtensa/include/asm/io.h
index 07b7299dab20..d04cd3a625fa 100644
--- a/arch/xtensa/include/asm/io.h
+++ b/arch/xtensa/include/asm/io.h
@@ -69,21 +69,28 @@ static inline void * phys_to_virt(unsigned long address)
69 69
70static inline void *ioremap(unsigned long offset, unsigned long size) 70static inline void *ioremap(unsigned long offset, unsigned long size)
71{ 71{
72#ifdef CONFIG_MMU
72 if (offset >= XCHAL_KIO_PADDR 73 if (offset >= XCHAL_KIO_PADDR
73 && offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE) 74 && offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE)
74 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR); 75 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_BYPASS_VADDR);
75
76 else 76 else
77 BUG(); 77 BUG();
78#else
79 return (void *)offset;
80#endif
78} 81}
79 82
80static inline void *ioremap_nocache(unsigned long offset, unsigned long size) 83static inline void *ioremap_nocache(unsigned long offset, unsigned long size)
81{ 84{
85#ifdef CONFIG_MMU
82 if (offset >= XCHAL_KIO_PADDR 86 if (offset >= XCHAL_KIO_PADDR
83 && offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE) 87 && offset < XCHAL_KIO_PADDR + XCHAL_KIO_SIZE)
84 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR); 88 return (void*)(offset-XCHAL_KIO_PADDR+XCHAL_KIO_CACHED_VADDR);
85 else 89 else
86 BUG(); 90 BUG();
91#else
92 return (void *)offset;
93#endif
87} 94}
88 95
89static inline void iounmap(void *addr) 96static inline void iounmap(void *addr)
diff --git a/arch/xtensa/include/asm/irq.h b/arch/xtensa/include/asm/irq.h
index 1620d1e0e695..dfac82dc52ad 100644
--- a/arch/xtensa/include/asm/irq.h
+++ b/arch/xtensa/include/asm/irq.h
@@ -14,6 +14,13 @@
14#include <platform/hardware.h> 14#include <platform/hardware.h>
15#include <variant/core.h> 15#include <variant/core.h>
16 16
17#ifdef CONFIG_VARIANT_IRQ_SWITCH
18#include <variant/irq.h>
19#else
20static inline void variant_irq_enable(unsigned int irq) { }
21static inline void variant_irq_disable(unsigned int irq) { }
22#endif
23
17#ifndef PLATFORM_NR_IRQS 24#ifndef PLATFORM_NR_IRQS
18# define PLATFORM_NR_IRQS 0 25# define PLATFORM_NR_IRQS 0
19#endif 26#endif
diff --git a/arch/xtensa/include/asm/mmu.h b/arch/xtensa/include/asm/mmu.h
index 44c5bb04c55c..04890d6e2335 100644
--- a/arch/xtensa/include/asm/mmu.h
+++ b/arch/xtensa/include/asm/mmu.h
@@ -11,7 +11,12 @@
11#ifndef _XTENSA_MMU_H 11#ifndef _XTENSA_MMU_H
12#define _XTENSA_MMU_H 12#define _XTENSA_MMU_H
13 13
14#ifndef CONFIG_MMU
15#include <asm/nommu.h>
16#else
17
14/* Default "unsigned long" context */ 18/* Default "unsigned long" context */
15typedef unsigned long mm_context_t; 19typedef unsigned long mm_context_t;
16 20
21#endif /* CONFIG_MMU */
17#endif /* _XTENSA_MMU_H */ 22#endif /* _XTENSA_MMU_H */
diff --git a/arch/xtensa/include/asm/mmu_context.h b/arch/xtensa/include/asm/mmu_context.h
index c0fd8e5b4513..dbd8731a876a 100644
--- a/arch/xtensa/include/asm/mmu_context.h
+++ b/arch/xtensa/include/asm/mmu_context.h
@@ -13,16 +13,20 @@
13#ifndef _XTENSA_MMU_CONTEXT_H 13#ifndef _XTENSA_MMU_CONTEXT_H
14#define _XTENSA_MMU_CONTEXT_H 14#define _XTENSA_MMU_CONTEXT_H
15 15
16#ifndef CONFIG_MMU
17#include <asm/nommu_context.h>
18#else
19
16#include <linux/stringify.h> 20#include <linux/stringify.h>
17#include <linux/sched.h> 21#include <linux/sched.h>
18 22
23#include <variant/core.h>
24
19#include <asm/pgtable.h> 25#include <asm/pgtable.h>
20#include <asm/cacheflush.h> 26#include <asm/cacheflush.h>
21#include <asm/tlbflush.h> 27#include <asm/tlbflush.h>
22#include <asm-generic/mm_hooks.h> 28#include <asm-generic/mm_hooks.h>
23 29
24#define XCHAL_MMU_ASID_BITS 8
25
26#if (XCHAL_HAVE_TLBS != 1) 30#if (XCHAL_HAVE_TLBS != 1)
27# error "Linux must have an MMU!" 31# error "Linux must have an MMU!"
28#endif 32#endif
@@ -133,4 +137,5 @@ static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
133 137
134} 138}
135 139
140#endif /* CONFIG_MMU */
136#endif /* _XTENSA_MMU_CONTEXT_H */ 141#endif /* _XTENSA_MMU_CONTEXT_H */
diff --git a/arch/xtensa/include/asm/nommu.h b/arch/xtensa/include/asm/nommu.h
new file mode 100644
index 000000000000..dce2c438c5ba
--- /dev/null
+++ b/arch/xtensa/include/asm/nommu.h
@@ -0,0 +1,3 @@
1typedef struct {
2 unsigned long end_brk;
3} mm_context_t;
diff --git a/arch/xtensa/include/asm/nommu_context.h b/arch/xtensa/include/asm/nommu_context.h
new file mode 100644
index 000000000000..599e7a2e729d
--- /dev/null
+++ b/arch/xtensa/include/asm/nommu_context.h
@@ -0,0 +1,25 @@
1static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
2{
3}
4
5static inline int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
6{
7 return 0;
8}
9
10static inline void destroy_context(struct mm_struct *mm)
11{
12}
13
14static inline void activate_mm(struct mm_struct *prev, struct mm_struct *next)
15{
16}
17
18static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
19 struct task_struct *tsk)
20{
21}
22
23static inline void deactivate_mm(struct task_struct *tsk, struct mm_struct *mm)
24{
25}
diff --git a/arch/xtensa/include/asm/page.h b/arch/xtensa/include/asm/page.h
index 11f7dc2dbec7..17e0c5383b10 100644
--- a/arch/xtensa/include/asm/page.h
+++ b/arch/xtensa/include/asm/page.h
@@ -14,6 +14,7 @@
14#include <asm/processor.h> 14#include <asm/processor.h>
15#include <asm/types.h> 15#include <asm/types.h>
16#include <asm/cache.h> 16#include <asm/cache.h>
17#include <platform/hardware.h>
17 18
18/* 19/*
19 * Fixed TLB translations in the processor. 20 * Fixed TLB translations in the processor.
@@ -32,8 +33,14 @@
32#define PAGE_SIZE (__XTENSA_UL_CONST(1) << PAGE_SHIFT) 33#define PAGE_SIZE (__XTENSA_UL_CONST(1) << PAGE_SHIFT)
33#define PAGE_MASK (~(PAGE_SIZE-1)) 34#define PAGE_MASK (~(PAGE_SIZE-1))
34 35
36#ifdef CONFIG_MMU
35#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR 37#define PAGE_OFFSET XCHAL_KSEG_CACHED_VADDR
36#define MAX_MEM_PFN XCHAL_KSEG_SIZE 38#define MAX_MEM_PFN XCHAL_KSEG_SIZE
39#else
40#define PAGE_OFFSET 0
41#define MAX_MEM_PFN (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE)
42#endif
43
37#define PGTABLE_START 0x80000000 44#define PGTABLE_START 0x80000000
38 45
39/* 46/*
@@ -150,9 +157,11 @@ extern void copy_user_page(void*, void*, unsigned long, struct page*);
150 * addresses. 157 * addresses.
151 */ 158 */
152 159
160#define ARCH_PFN_OFFSET (PLATFORM_DEFAULT_MEM_START >> PAGE_SHIFT)
161
153#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) 162#define __pa(x) ((unsigned long) (x) - PAGE_OFFSET)
154#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) 163#define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET))
155#define pfn_valid(pfn) ((unsigned long)pfn < max_mapnr) 164#define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && ((pfn) - ARCH_PFN_OFFSET) < max_mapnr)
156#ifdef CONFIG_DISCONTIGMEM 165#ifdef CONFIG_DISCONTIGMEM
157# error CONFIG_DISCONTIGMEM not supported 166# error CONFIG_DISCONTIGMEM not supported
158#endif 167#endif
@@ -162,8 +171,9 @@ extern void copy_user_page(void*, void*, unsigned long, struct page*);
162#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT) 171#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
163#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT) 172#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
164 173
174#ifdef CONFIG_MMU
165#define WANT_PAGE_VIRTUAL 175#define WANT_PAGE_VIRTUAL
166 176#endif
167 177
168#endif /* __ASSEMBLY__ */ 178#endif /* __ASSEMBLY__ */
169 179
diff --git a/arch/xtensa/include/asm/pgtable.h b/arch/xtensa/include/asm/pgtable.h
index 8014d96b21f1..a138770c358e 100644
--- a/arch/xtensa/include/asm/pgtable.h
+++ b/arch/xtensa/include/asm/pgtable.h
@@ -183,7 +183,15 @@ extern unsigned long empty_zero_page[1024];
183 183
184#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page)) 184#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
185 185
186#ifdef CONFIG_MMU
186extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)]; 187extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
188extern void paging_init(void);
189extern void pgtable_cache_init(void);
190#else
191# define swapper_pg_dir NULL
192static inline void paging_init(void) { }
193static inline void pgtable_cache_init(void) { }
194#endif
187 195
188/* 196/*
189 * The pmd contains the kernel virtual address of the pte page. 197 * The pmd contains the kernel virtual address of the pte page.
@@ -383,8 +391,6 @@ ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
383 391
384#else 392#else
385 393
386extern void paging_init(void);
387
388#define kern_addr_valid(addr) (1) 394#define kern_addr_valid(addr) (1)
389 395
390extern void update_mmu_cache(struct vm_area_struct * vma, 396extern void update_mmu_cache(struct vm_area_struct * vma,
@@ -398,9 +404,6 @@ extern void update_mmu_cache(struct vm_area_struct * vma,
398#define io_remap_pfn_range(vma,from,pfn,size,prot) \ 404#define io_remap_pfn_range(vma,from,pfn,size,prot) \
399 remap_pfn_range(vma, from, pfn, size, prot) 405 remap_pfn_range(vma, from, pfn, size, prot)
400 406
401
402extern void pgtable_cache_init(void);
403
404typedef pte_t *pte_addr_t; 407typedef pte_t *pte_addr_t;
405 408
406#endif /* !defined (__ASSEMBLY__) */ 409#endif /* !defined (__ASSEMBLY__) */
diff --git a/arch/xtensa/include/asm/platform.h b/arch/xtensa/include/asm/platform.h
index e3d5a48ad495..7d936e58e9be 100644
--- a/arch/xtensa/include/asm/platform.h
+++ b/arch/xtensa/include/asm/platform.h
@@ -74,16 +74,5 @@ extern int platform_pcibios_fixup (void);
74 */ 74 */
75extern void platform_calibrate_ccount (void); 75extern void platform_calibrate_ccount (void);
76 76
77/*
78 * platform_get_rtc_time returns RTC seconds (returns 0 for no error)
79 */
80extern int platform_get_rtc_time(time_t*);
81
82/*
83 * platform_set_rtc_time set RTC seconds (returns 0 for no error)
84 */
85extern int platform_set_rtc_time(time_t);
86
87
88#endif /* _XTENSA_PLATFORM_H */ 77#endif /* _XTENSA_PLATFORM_H */
89 78
diff --git a/arch/xtensa/include/asm/processor.h b/arch/xtensa/include/asm/processor.h
index 07387d3b99f4..0ea4937c0b61 100644
--- a/arch/xtensa/include/asm/processor.h
+++ b/arch/xtensa/include/asm/processor.h
@@ -13,6 +13,7 @@
13 13
14#include <variant/core.h> 14#include <variant/core.h>
15#include <asm/coprocessor.h> 15#include <asm/coprocessor.h>
16#include <platform/hardware.h>
16 17
17#include <linux/compiler.h> 18#include <linux/compiler.h>
18#include <asm/ptrace.h> 19#include <asm/ptrace.h>
@@ -25,6 +26,8 @@
25# error Linux requires the Xtensa Windowed Registers Option. 26# error Linux requires the Xtensa Windowed Registers Option.
26#endif 27#endif
27 28
29#define ARCH_SLAB_MINALIGN XCHAL_DATA_WIDTH
30
28/* 31/*
29 * User space process size: 1 GB. 32 * User space process size: 1 GB.
30 * Windowed call ABI requires caller and callee to be located within the same 33 * Windowed call ABI requires caller and callee to be located within the same
@@ -33,7 +36,12 @@
33 * the 1 GB requirement applies to the stack as well. 36 * the 1 GB requirement applies to the stack as well.
34 */ 37 */
35 38
39#ifdef CONFIG_MMU
36#define TASK_SIZE __XTENSA_UL_CONST(0x40000000) 40#define TASK_SIZE __XTENSA_UL_CONST(0x40000000)
41#else
42#define TASK_SIZE (PLATFORM_DEFAULT_MEM_START + PLATFORM_DEFAULT_MEM_SIZE)
43#endif
44
37#define STACK_TOP TASK_SIZE 45#define STACK_TOP TASK_SIZE
38#define STACK_TOP_MAX STACK_TOP 46#define STACK_TOP_MAX STACK_TOP
39 47
diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index a51d36a27389..80d24c485fd3 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -1463,6 +1463,7 @@ ENTRY(_spill_registers)
1463 callx0 a0 # should not return 1463 callx0 a0 # should not return
14641: j 1b 14641: j 1b
1465 1465
1466#ifdef CONFIG_MMU
1466/* 1467/*
1467 * We should never get here. Bail out! 1468 * We should never get here. Bail out!
1468 */ 1469 */
@@ -1775,7 +1776,7 @@ ENTRY(fast_store_prohibited)
1775 bbsi.l a2, PS_UM_BIT, 1f 1776 bbsi.l a2, PS_UM_BIT, 1f
1776 j _kernel_exception 1777 j _kernel_exception
17771: j _user_exception 17781: j _user_exception
1778 1779#endif /* CONFIG_MMU */
1779 1780
1780/* 1781/*
1781 * System Calls. 1782 * System Calls.
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S
index 67e69139520b..0817f9db836e 100644
--- a/arch/xtensa/kernel/head.S
+++ b/arch/xtensa/kernel/head.S
@@ -53,7 +53,7 @@ _start: _j 2f
532: l32r a0, 1b 532: l32r a0, 1b
54 jx a0 54 jx a0
55 55
56 .text 56 .section .init.text, "ax"
57 .align 4 57 .align 4
58_startup: 58_startup:
59 59
@@ -235,8 +235,9 @@ should_never_return:
235 */ 235 */
236 236
237.section ".bss.page_aligned", "w" 237.section ".bss.page_aligned", "w"
238#ifdef CONFIG_MMU
238ENTRY(swapper_pg_dir) 239ENTRY(swapper_pg_dir)
239 .fill PAGE_SIZE, 1, 0 240 .fill PAGE_SIZE, 1, 0
241#endif
240ENTRY(empty_zero_page) 242ENTRY(empty_zero_page)
241 .fill PAGE_SIZE, 1, 0 243 .fill PAGE_SIZE, 1, 0
242
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c
index f3b66fba5b8f..a36c85edd045 100644
--- a/arch/xtensa/kernel/irq.c
+++ b/arch/xtensa/kernel/irq.c
@@ -132,6 +132,18 @@ static void xtensa_irq_unmask(unsigned int irq)
132 set_sr (cached_irq_mask, INTENABLE); 132 set_sr (cached_irq_mask, INTENABLE);
133} 133}
134 134
135static void xtensa_irq_enable(unsigned int irq)
136{
137 variant_irq_enable(irq);
138 xtensa_irq_unmask(irq);
139}
140
141static void xtensa_irq_disable(unsigned int irq)
142{
143 xtensa_irq_mask(irq);
144 variant_irq_disable(irq);
145}
146
135static void xtensa_irq_ack(unsigned int irq) 147static void xtensa_irq_ack(unsigned int irq)
136{ 148{
137 set_sr(1 << irq, INTCLEAR); 149 set_sr(1 << irq, INTCLEAR);
@@ -146,6 +158,8 @@ static int xtensa_irq_retrigger(unsigned int irq)
146 158
147static struct irq_chip xtensa_irq_chip = { 159static struct irq_chip xtensa_irq_chip = {
148 .name = "xtensa", 160 .name = "xtensa",
161 .enable = xtensa_irq_enable,
162 .disable = xtensa_irq_disable,
149 .mask = xtensa_irq_mask, 163 .mask = xtensa_irq_mask,
150 .unmask = xtensa_irq_unmask, 164 .unmask = xtensa_irq_unmask,
151 .ack = xtensa_irq_ack, 165 .ack = xtensa_irq_ack,
diff --git a/arch/xtensa/kernel/platform.c b/arch/xtensa/kernel/platform.c
index 69675f216062..1b91a97f1d84 100644
--- a/arch/xtensa/kernel/platform.c
+++ b/arch/xtensa/kernel/platform.c
@@ -36,8 +36,6 @@ _F(void, power_off, (void), { while(1); });
36_F(void, idle, (void), { __asm__ __volatile__ ("waiti 0" ::: "memory"); }); 36_F(void, idle, (void), { __asm__ __volatile__ ("waiti 0" ::: "memory"); });
37_F(void, heartbeat, (void), { }); 37_F(void, heartbeat, (void), { });
38_F(int, pcibios_fixup, (void), { return 0; }); 38_F(int, pcibios_fixup, (void), { return 0; });
39_F(int, get_rtc_time, (time_t* t), { return 0; });
40_F(int, set_rtc_time, (time_t t), { return 0; });
41 39
42#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT 40#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
43_F(void, calibrate_ccount, (void), 41_F(void, calibrate_ccount, (void),
diff --git a/arch/xtensa/kernel/setup.c b/arch/xtensa/kernel/setup.c
index 4ec1633c2941..1e5a034fe011 100644
--- a/arch/xtensa/kernel/setup.c
+++ b/arch/xtensa/kernel/setup.c
@@ -84,7 +84,13 @@ sysmem_info_t __initdata sysmem;
84int initrd_is_mapped; 84int initrd_is_mapped;
85#endif 85#endif
86 86
87#ifdef CONFIG_MMU
87extern void init_mmu(void); 88extern void init_mmu(void);
89#else
90static inline void init_mmu(void) { }
91#endif
92
93extern void zones_init(void);
88 94
89/* 95/*
90 * Boot parameter parsing. 96 * Boot parameter parsing.
@@ -286,6 +292,7 @@ void __init setup_arch(char **cmdline_p)
286 292
287 293
288 paging_init(); 294 paging_init();
295 zones_init();
289 296
290#ifdef CONFIG_VT 297#ifdef CONFIG_VT
291# if defined(CONFIG_VGA_CONSOLE) 298# if defined(CONFIG_VGA_CONSOLE)
diff --git a/arch/xtensa/kernel/time.c b/arch/xtensa/kernel/time.c
index 8df1e842f6d4..8848120d291b 100644
--- a/arch/xtensa/kernel/time.c
+++ b/arch/xtensa/kernel/time.c
@@ -14,7 +14,7 @@
14 14
15#include <linux/errno.h> 15#include <linux/errno.h>
16#include <linux/time.h> 16#include <linux/time.h>
17#include <linux/timex.h> 17#include <linux/clocksource.h>
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/module.h> 19#include <linux/module.h>
20#include <linux/init.h> 20#include <linux/init.h>
@@ -25,27 +25,31 @@
25#include <asm/timex.h> 25#include <asm/timex.h>
26#include <asm/platform.h> 26#include <asm/platform.h>
27 27
28
29DEFINE_SPINLOCK(rtc_lock);
30EXPORT_SYMBOL(rtc_lock);
31
32
33#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT 28#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
34unsigned long ccount_per_jiffy; /* per 1/HZ */ 29unsigned long ccount_per_jiffy; /* per 1/HZ */
35unsigned long nsec_per_ccount; /* nsec per ccount increment */ 30unsigned long nsec_per_ccount; /* nsec per ccount increment */
36#endif 31#endif
37 32
38static long last_rtc_update = 0; 33static cycle_t ccount_read(void)
39
40/*
41 * Scheduler clock - returns current tim in nanosec units.
42 */
43
44unsigned long long sched_clock(void)
45{ 34{
46 return (unsigned long long)jiffies * (1000000000 / HZ); 35 return (cycle_t)get_ccount();
47} 36}
48 37
38static struct clocksource ccount_clocksource = {
39 .name = "ccount",
40 .rating = 200,
41 .read = ccount_read,
42 .mask = CLOCKSOURCE_MASK(32),
43 /*
44 * With a shift of 22 the lower limit of the cpu clock is
45 * 1MHz, where NSEC_PER_CCOUNT is 1000 or a bit less than
46 * 2^10: Since we have 32 bits and the multiplicator can
47 * already take up as much as 10 bits, this leaves us with
48 * remaining upper 22 bits.
49 */
50 .shift = 22,
51};
52
49static irqreturn_t timer_interrupt(int irq, void *dev_id); 53static irqreturn_t timer_interrupt(int irq, void *dev_id);
50static struct irqaction timer_irqaction = { 54static struct irqaction timer_irqaction = {
51 .handler = timer_interrupt, 55 .handler = timer_interrupt,
@@ -55,11 +59,11 @@ static struct irqaction timer_irqaction = {
55 59
56void __init time_init(void) 60void __init time_init(void)
57{ 61{
58 time_t sec_o, sec_n = 0; 62 xtime.tv_nsec = 0;
63 xtime.tv_sec = read_persistent_clock();
59 64
60 /* The platform must provide a function to calibrate the processor 65 set_normalized_timespec(&wall_to_monotonic,
61 * speed for the CALIBRATE. 66 -xtime.tv_sec, -xtime.tv_nsec);
62 */
63 67
64#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT 68#ifdef CONFIG_XTENSA_CALIBRATE_CCOUNT
65 printk("Calibrating CPU frequency "); 69 printk("Calibrating CPU frequency ");
@@ -67,19 +71,10 @@ void __init time_init(void)
67 printk("%d.%02d MHz\n", (int)ccount_per_jiffy/(1000000/HZ), 71 printk("%d.%02d MHz\n", (int)ccount_per_jiffy/(1000000/HZ),
68 (int)(ccount_per_jiffy/(10000/HZ))%100); 72 (int)(ccount_per_jiffy/(10000/HZ))%100);
69#endif 73#endif
70 74 ccount_clocksource.mult =
71 /* Set time from RTC (if provided) */ 75 clocksource_hz2mult(CCOUNT_PER_JIFFY * HZ,
72 76 ccount_clocksource.shift);
73 if (platform_get_rtc_time(&sec_o) == 0) 77 clocksource_register(&ccount_clocksource);
74 while (platform_get_rtc_time(&sec_n))
75 if (sec_o != sec_n)
76 break;
77
78 xtime.tv_nsec = 0;
79 last_rtc_update = xtime.tv_sec = sec_n;
80
81 set_normalized_timespec(&wall_to_monotonic,
82 -xtime.tv_sec, -xtime.tv_nsec);
83 78
84 /* Initialize the linux timer interrupt. */ 79 /* Initialize the linux timer interrupt. */
85 80
@@ -87,69 +82,6 @@ void __init time_init(void)
87 set_linux_timer(get_ccount() + CCOUNT_PER_JIFFY); 82 set_linux_timer(get_ccount() + CCOUNT_PER_JIFFY);
88} 83}
89 84
90
91int do_settimeofday(struct timespec *tv)
92{
93 time_t wtm_sec, sec = tv->tv_sec;
94 long wtm_nsec, nsec = tv->tv_nsec;
95 unsigned long delta;
96
97 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
98 return -EINVAL;
99
100 write_seqlock_irq(&xtime_lock);
101
102 /* This is revolting. We need to set "xtime" correctly. However, the
103 * value in this location is the value at the most recent update of
104 * wall time. Discover what correction gettimeofday() would have
105 * made, and then undo it!
106 */
107
108 delta = CCOUNT_PER_JIFFY;
109 delta += get_ccount() - get_linux_timer();
110 nsec -= delta * NSEC_PER_CCOUNT;
111
112 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
113 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
114
115 set_normalized_timespec(&xtime, sec, nsec);
116 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
117
118 ntp_clear();
119 write_sequnlock_irq(&xtime_lock);
120 return 0;
121}
122
123EXPORT_SYMBOL(do_settimeofday);
124
125
126void do_gettimeofday(struct timeval *tv)
127{
128 unsigned long flags;
129 unsigned long volatile sec, usec, delta, seq;
130
131 do {
132 seq = read_seqbegin_irqsave(&xtime_lock, flags);
133
134 sec = xtime.tv_sec;
135 usec = (xtime.tv_nsec / NSEC_PER_USEC);
136
137 delta = get_linux_timer() - get_ccount();
138
139 } while (read_seqretry_irqrestore(&xtime_lock, seq, flags));
140
141 usec += (((unsigned long) CCOUNT_PER_JIFFY - delta)
142 * (unsigned long) NSEC_PER_CCOUNT) / NSEC_PER_USEC;
143
144 for (; usec >= 1000000; sec++, usec -= 1000000)
145 ;
146
147 tv->tv_sec = sec;
148 tv->tv_usec = usec;
149}
150
151EXPORT_SYMBOL(do_gettimeofday);
152
153/* 85/*
154 * The timer interrupt is called HZ times per second. 86 * The timer interrupt is called HZ times per second.
155 */ 87 */
@@ -178,16 +110,6 @@ again:
178 next += CCOUNT_PER_JIFFY; 110 next += CCOUNT_PER_JIFFY;
179 set_linux_timer(next); 111 set_linux_timer(next);
180 112
181 if (ntp_synced() &&
182 xtime.tv_sec - last_rtc_update >= 659 &&
183 abs((xtime.tv_nsec/1000)-(1000000-1000000/HZ))<5000000/HZ) {
184
185 if (platform_set_rtc_time(xtime.tv_sec+1) == 0)
186 last_rtc_update = xtime.tv_sec+1;
187 else
188 /* Do it again in 60 s */
189 last_rtc_update += 60;
190 }
191 write_sequnlock(&xtime_lock); 113 write_sequnlock(&xtime_lock);
192 } 114 }
193 115
@@ -213,4 +135,3 @@ void __cpuinit calibrate_delay(void)
213 (loops_per_jiffy/(10000/HZ)) % 100); 135 (loops_per_jiffy/(10000/HZ)) % 100);
214} 136}
215#endif 137#endif
216
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c
index c44f830b6c7a..9f0b71189e94 100644
--- a/arch/xtensa/kernel/traps.c
+++ b/arch/xtensa/kernel/traps.c
@@ -104,6 +104,7 @@ static dispatch_init_table_t __initdata dispatch_init_table[] = {
104#endif 104#endif
105{ EXCCAUSE_UNALIGNED, KRNL, fast_unaligned }, 105{ EXCCAUSE_UNALIGNED, KRNL, fast_unaligned },
106#endif 106#endif
107#ifdef CONFIG_MMU
107{ EXCCAUSE_ITLB_MISS, 0, do_page_fault }, 108{ EXCCAUSE_ITLB_MISS, 0, do_page_fault },
108{ EXCCAUSE_ITLB_MISS, USER|KRNL, fast_second_level_miss}, 109{ EXCCAUSE_ITLB_MISS, USER|KRNL, fast_second_level_miss},
109{ EXCCAUSE_ITLB_MULTIHIT, 0, do_multihit }, 110{ EXCCAUSE_ITLB_MULTIHIT, 0, do_multihit },
@@ -118,6 +119,7 @@ static dispatch_init_table_t __initdata dispatch_init_table[] = {
118{ EXCCAUSE_STORE_CACHE_ATTRIBUTE, USER|KRNL, fast_store_prohibited }, 119{ EXCCAUSE_STORE_CACHE_ATTRIBUTE, USER|KRNL, fast_store_prohibited },
119{ EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault }, 120{ EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault },
120{ EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault }, 121{ EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault },
122#endif /* CONFIG_MMU */
121/* XCCHAL_EXCCAUSE_FLOATING_POINT unhandled */ 123/* XCCHAL_EXCCAUSE_FLOATING_POINT unhandled */
122#if XTENSA_HAVE_COPROCESSOR(0) 124#if XTENSA_HAVE_COPROCESSOR(0)
123COPROCESSOR(0), 125COPROCESSOR(0),
@@ -372,11 +374,10 @@ void show_trace(struct task_struct *task, unsigned long *sp)
372 unsigned long a0, a1, pc; 374 unsigned long a0, a1, pc;
373 unsigned long sp_start, sp_end; 375 unsigned long sp_start, sp_end;
374 376
375 a1 = (unsigned long)sp; 377 if (sp)
376 378 a1 = (unsigned long)sp;
377 if (a1 == 0) 379 else
378 __asm__ __volatile__ ("mov %0, a1\n" : "=a"(a1)); 380 a1 = task->thread.sp;
379
380 381
381 sp_start = a1 & ~(THREAD_SIZE-1); 382 sp_start = a1 & ~(THREAD_SIZE-1);
382 sp_end = sp_start + THREAD_SIZE; 383 sp_end = sp_start + THREAD_SIZE;
@@ -418,9 +419,8 @@ void show_stack(struct task_struct *task, unsigned long *sp)
418 int i = 0; 419 int i = 0;
419 unsigned long *stack; 420 unsigned long *stack;
420 421
421 if (sp == 0) 422 if (!sp)
422 __asm__ __volatile__ ("mov %0, a1\n" : "=a"(sp)); 423 sp = (unsigned long *)task->thread.sp;
423
424 stack = sp; 424 stack = sp;
425 425
426 printk("\nStack: "); 426 printk("\nStack: ");
diff --git a/arch/xtensa/kernel/vectors.S b/arch/xtensa/kernel/vectors.S
index eb2d7bb69ee0..74a7518faf16 100644
--- a/arch/xtensa/kernel/vectors.S
+++ b/arch/xtensa/kernel/vectors.S
@@ -309,6 +309,7 @@ ENTRY(_DoubleExceptionVector)
309 * All other exceptions are unexpected and thus unrecoverable! 309 * All other exceptions are unexpected and thus unrecoverable!
310 */ 310 */
311 311
312#ifdef CONFIG_MMU
312 .extern fast_second_level_miss_double_kernel 313 .extern fast_second_level_miss_double_kernel
313 314
314.Lksp: /* a0: a0, a1: a1, a2: a2, a3: trashed, depc: depc, excsave: a3 */ 315.Lksp: /* a0: a0, a1: a1, a2: a2, a3: trashed, depc: depc, excsave: a3 */
@@ -319,6 +320,9 @@ ENTRY(_DoubleExceptionVector)
319 bnez a3, .Lunrecoverable 320 bnez a3, .Lunrecoverable
3201: movi a3, fast_second_level_miss_double_kernel 3211: movi a3, fast_second_level_miss_double_kernel
321 jx a3 322 jx a3
323#else
324.equ .Lksp, .Lunrecoverable
325#endif
322 326
323 /* Critical! We can't handle this situation. PANIC! */ 327 /* Critical! We can't handle this situation. PANIC! */
324 328
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S
index d506774f4b05..c1be9a4a740c 100644
--- a/arch/xtensa/kernel/vmlinux.lds.S
+++ b/arch/xtensa/kernel/vmlinux.lds.S
@@ -17,6 +17,7 @@
17#include <asm-generic/vmlinux.lds.h> 17#include <asm-generic/vmlinux.lds.h>
18 18
19#include <variant/core.h> 19#include <variant/core.h>
20#include <platform/hardware.h>
20OUTPUT_ARCH(xtensa) 21OUTPUT_ARCH(xtensa)
21ENTRY(_start) 22ENTRY(_start)
22 23
@@ -26,7 +27,9 @@ jiffies = jiffies_64 + 4;
26jiffies = jiffies_64; 27jiffies = jiffies_64;
27#endif 28#endif
28 29
30#ifndef KERNELOFFSET
29#define KERNELOFFSET 0xd0001000 31#define KERNELOFFSET 0xd0001000
32#endif
30 33
31/* Note: In the following macros, it would be nice to specify only the 34/* Note: In the following macros, it would be nice to specify only the
32 vector name and section kind and construct "sym" and "section" using 35 vector name and section kind and construct "sym" and "section" using
diff --git a/arch/xtensa/mm/Makefile b/arch/xtensa/mm/Makefile
index 64e304a2f884..f0b646d2f843 100644
--- a/arch/xtensa/mm/Makefile
+++ b/arch/xtensa/mm/Makefile
@@ -2,4 +2,5 @@
2# Makefile for the Linux/Xtensa-specific parts of the memory manager. 2# Makefile for the Linux/Xtensa-specific parts of the memory manager.
3# 3#
4 4
5obj-y := init.o fault.o tlb.o misc.o cache.o 5obj-y := init.o cache.o misc.o
6obj-$(CONFIG_MMU) += fault.o mmu.o tlb.o
diff --git a/arch/xtensa/mm/init.c b/arch/xtensa/mm/init.c
index 34163cfaaffc..427e14fa43c5 100644
--- a/arch/xtensa/mm/init.c
+++ b/arch/xtensa/mm/init.c
@@ -24,15 +24,8 @@
24#include <linux/mm.h> 24#include <linux/mm.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26 26
27#include <asm/pgtable.h>
28#include <asm/bootparam.h> 27#include <asm/bootparam.h>
29#include <asm/mmu_context.h>
30#include <asm/tlb.h>
31#include <asm/page.h> 28#include <asm/page.h>
32#include <asm/pgalloc.h>
33
34
35DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
36 29
37/* References to section boundaries */ 30/* References to section boundaries */
38 31
@@ -130,7 +123,8 @@ void __init bootmem_init(void)
130 123
131 /* Find an area to use for the bootmem bitmap. */ 124 /* Find an area to use for the bootmem bitmap. */
132 125
133 bootmap_size = bootmem_bootmap_pages(max_low_pfn) << PAGE_SHIFT; 126 bootmap_size = bootmem_bootmap_pages(max_low_pfn - min_low_pfn);
127 bootmap_size <<= PAGE_SHIFT;
134 bootmap_start = ~0; 128 bootmap_start = ~0;
135 129
136 for (i=0; i<sysmem.nr_banks; i++) 130 for (i=0; i<sysmem.nr_banks; i++)
@@ -145,8 +139,9 @@ void __init bootmem_init(void)
145 /* Reserve the bootmem bitmap area */ 139 /* Reserve the bootmem bitmap area */
146 140
147 mem_reserve(bootmap_start, bootmap_start + bootmap_size, 1); 141 mem_reserve(bootmap_start, bootmap_start + bootmap_size, 1);
148 bootmap_size = init_bootmem_node(NODE_DATA(0), min_low_pfn, 142 bootmap_size = init_bootmem_node(NODE_DATA(0),
149 bootmap_start >> PAGE_SHIFT, 143 bootmap_start >> PAGE_SHIFT,
144 min_low_pfn,
150 max_low_pfn); 145 max_low_pfn);
151 146
152 /* Add all remaining memory pieces into the bootmem map */ 147 /* Add all remaining memory pieces into the bootmem map */
@@ -158,14 +153,14 @@ void __init bootmem_init(void)
158} 153}
159 154
160 155
161void __init paging_init(void) 156void __init zones_init(void)
162{ 157{
163 unsigned long zones_size[MAX_NR_ZONES]; 158 unsigned long zones_size[MAX_NR_ZONES];
164 int i; 159 int i;
165 160
166 /* All pages are DMA-able, so we put them all in the DMA zone. */ 161 /* All pages are DMA-able, so we put them all in the DMA zone. */
167 162
168 zones_size[ZONE_DMA] = max_low_pfn; 163 zones_size[ZONE_DMA] = max_low_pfn - ARCH_PFN_OFFSET;
169 for (i = 1; i < MAX_NR_ZONES; i++) 164 for (i = 1; i < MAX_NR_ZONES; i++)
170 zones_size[i] = 0; 165 zones_size[i] = 0;
171 166
@@ -173,40 +168,7 @@ void __init paging_init(void)
173 zones_size[ZONE_HIGHMEM] = max_pfn - max_low_pfn; 168 zones_size[ZONE_HIGHMEM] = max_pfn - max_low_pfn;
174#endif 169#endif
175 170
176 /* Initialize the kernel's page tables. */ 171 free_area_init_node(0, zones_size, ARCH_PFN_OFFSET, NULL);
177
178 memset(swapper_pg_dir, 0, PAGE_SIZE);
179
180 free_area_init(zones_size);
181}
182
183/*
184 * Flush the mmu and reset associated register to default values.
185 */
186
187void __init init_mmu (void)
188{
189 /* Writing zeros to the <t>TLBCFG special registers ensure
190 * that valid values exist in the register. For existing
191 * PGSZID<w> fields, zero selects the first element of the
192 * page-size array. For nonexistent PGSZID<w> fields, zero is
193 * the best value to write. Also, when changing PGSZID<w>
194 * fields, the corresponding TLB must be flushed.
195 */
196 set_itlbcfg_register (0);
197 set_dtlbcfg_register (0);
198 flush_tlb_all ();
199
200 /* Set rasid register to a known value. */
201
202 set_rasid_register (ASID_USER_FIRST);
203
204 /* Set PTEVADDR special register to the start of the page
205 * table, which is in kernel mappable space (ie. not
206 * statically mapped). This register's value is undefined on
207 * reset.
208 */
209 set_ptevaddr_register (PGTABLE_START);
210} 172}
211 173
212/* 174/*
@@ -218,8 +180,8 @@ void __init mem_init(void)
218 unsigned long codesize, reservedpages, datasize, initsize; 180 unsigned long codesize, reservedpages, datasize, initsize;
219 unsigned long highmemsize, tmp, ram; 181 unsigned long highmemsize, tmp, ram;
220 182
221 max_mapnr = num_physpages = max_low_pfn; 183 max_mapnr = num_physpages = max_low_pfn - ARCH_PFN_OFFSET;
222 high_memory = (void *) __va(max_mapnr << PAGE_SHIFT); 184 high_memory = (void *) __va(max_low_pfn << PAGE_SHIFT);
223 highmemsize = 0; 185 highmemsize = 0;
224 186
225#ifdef CONFIG_HIGHMEM 187#ifdef CONFIG_HIGHMEM
@@ -229,7 +191,7 @@ void __init mem_init(void)
229 totalram_pages += free_all_bootmem(); 191 totalram_pages += free_all_bootmem();
230 192
231 reservedpages = ram = 0; 193 reservedpages = ram = 0;
232 for (tmp = 0; tmp < max_low_pfn; tmp++) { 194 for (tmp = 0; tmp < max_mapnr; tmp++) {
233 ram++; 195 ram++;
234 if (PageReserved(mem_map+tmp)) 196 if (PageReserved(mem_map+tmp))
235 reservedpages++; 197 reservedpages++;
@@ -279,23 +241,3 @@ void free_initmem(void)
279 printk("Freeing unused kernel memory: %dk freed\n", 241 printk("Freeing unused kernel memory: %dk freed\n",
280 (&__init_end - &__init_begin) >> 10); 242 (&__init_end - &__init_begin) >> 10);
281} 243}
282
283struct kmem_cache *pgtable_cache __read_mostly;
284
285static void pgd_ctor(void* addr)
286{
287 pte_t* ptep = (pte_t*)addr;
288 int i;
289
290 for (i = 0; i < 1024; i++, ptep++)
291 pte_clear(NULL, 0, ptep);
292
293}
294
295void __init pgtable_cache_init(void)
296{
297 pgtable_cache = kmem_cache_create("pgd",
298 PAGE_SIZE, PAGE_SIZE,
299 SLAB_HWCACHE_ALIGN,
300 pgd_ctor);
301}
diff --git a/arch/xtensa/mm/misc.S b/arch/xtensa/mm/misc.S
index c885664211d1..b048406d8756 100644
--- a/arch/xtensa/mm/misc.S
+++ b/arch/xtensa/mm/misc.S
@@ -84,6 +84,7 @@ ENTRY(copy_page)
84 84
85 retw 85 retw
86 86
87#ifdef CONFIG_MMU
87/* 88/*
88 * If we have to deal with cache aliasing, we use temporary memory mappings 89 * If we have to deal with cache aliasing, we use temporary memory mappings
89 * to ensure that the source and destination pages have the same color as 90 * to ensure that the source and destination pages have the same color as
@@ -311,6 +312,7 @@ ENTRY(__invalidate_icache_page_alias)
311/* End of special treatment in tlb miss exception */ 312/* End of special treatment in tlb miss exception */
312 313
313ENTRY(__tlbtemp_mapping_end) 314ENTRY(__tlbtemp_mapping_end)
315#endif /* CONFIG_MMU
314 316
315/* 317/*
316 * void __invalidate_icache_page(ulong start) 318 * void __invalidate_icache_page(ulong start)
diff --git a/arch/xtensa/mm/mmu.c b/arch/xtensa/mm/mmu.c
new file mode 100644
index 000000000000..4bb91a970f1f
--- /dev/null
+++ b/arch/xtensa/mm/mmu.c
@@ -0,0 +1,70 @@
1/*
2 * xtensa mmu stuff
3 *
4 * Extracted from init.c
5 */
6#include <linux/percpu.h>
7#include <linux/init.h>
8#include <linux/string.h>
9#include <linux/slab.h>
10#include <linux/cache.h>
11
12#include <asm/tlb.h>
13#include <asm/tlbflush.h>
14#include <asm/mmu_context.h>
15#include <asm/page.h>
16
17DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
18
19void __init paging_init(void)
20{
21 memset(swapper_pg_dir, 0, PAGE_SIZE);
22}
23
24/*
25 * Flush the mmu and reset associated register to default values.
26 */
27void __init init_mmu(void)
28{
29 /* Writing zeros to the <t>TLBCFG special registers ensure
30 * that valid values exist in the register. For existing
31 * PGSZID<w> fields, zero selects the first element of the
32 * page-size array. For nonexistent PGSZID<w> fields, zero is
33 * the best value to write. Also, when changing PGSZID<w>
34 * fields, the corresponding TLB must be flushed.
35 */
36 set_itlbcfg_register(0);
37 set_dtlbcfg_register(0);
38 flush_tlb_all();
39
40 /* Set rasid register to a known value. */
41
42 set_rasid_register(ASID_USER_FIRST);
43
44 /* Set PTEVADDR special register to the start of the page
45 * table, which is in kernel mappable space (ie. not
46 * statically mapped). This register's value is undefined on
47 * reset.
48 */
49 set_ptevaddr_register(PGTABLE_START);
50}
51
52struct kmem_cache *pgtable_cache __read_mostly;
53
54static void pgd_ctor(void *addr)
55{
56 pte_t *ptep = (pte_t *)addr;
57 int i;
58
59 for (i = 0; i < 1024; i++, ptep++)
60 pte_clear(NULL, 0, ptep);
61
62}
63
64void __init pgtable_cache_init(void)
65{
66 pgtable_cache = kmem_cache_create("pgd",
67 PAGE_SIZE, PAGE_SIZE,
68 SLAB_HWCACHE_ALIGN,
69 pgd_ctor);
70}
diff --git a/arch/xtensa/platforms/s6105/Makefile b/arch/xtensa/platforms/s6105/Makefile
new file mode 100644
index 000000000000..0be6194bcb72
--- /dev/null
+++ b/arch/xtensa/platforms/s6105/Makefile
@@ -0,0 +1,3 @@
1# Makefile for the Stretch S6105 eval board
2
3obj-y := setup.o device.o
diff --git a/arch/xtensa/platforms/s6105/device.c b/arch/xtensa/platforms/s6105/device.c
new file mode 100644
index 000000000000..78b08be5a92d
--- /dev/null
+++ b/arch/xtensa/platforms/s6105/device.c
@@ -0,0 +1,67 @@
1/*
2 * s6105 platform devices
3 *
4 * Copyright (c) 2009 emlix GmbH
5 */
6
7#include <linux/kernel.h>
8#include <linux/init.h>
9#include <linux/platform_device.h>
10#include <linux/serial.h>
11#include <linux/serial_8250.h>
12
13#include <variant/hardware.h>
14
15#define UART_INTNUM 4
16
17static const signed char uart_irq_mappings[] = {
18 S6_INTC_UART(0),
19 S6_INTC_UART(1),
20 -1,
21};
22
23const signed char *platform_irq_mappings[NR_IRQS] = {
24 [UART_INTNUM] = uart_irq_mappings,
25};
26
27static struct plat_serial8250_port serial_platform_data[] = {
28 {
29 .membase = (void *)S6_REG_UART + 0x0000,
30 .mapbase = S6_REG_UART + 0x0000,
31 .irq = UART_INTNUM,
32 .uartclk = S6_SCLK,
33 .regshift = 2,
34 .iotype = SERIAL_IO_MEM,
35 .flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST,
36 },
37 {
38 .membase = (void *)S6_REG_UART + 0x1000,
39 .mapbase = S6_REG_UART + 0x1000,
40 .irq = UART_INTNUM,
41 .uartclk = S6_SCLK,
42 .regshift = 2,
43 .iotype = SERIAL_IO_MEM,
44 .flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST,
45 },
46 { },
47};
48
49static struct platform_device platform_devices[] = {
50 {
51 .name = "serial8250",
52 .id = PLAT8250_DEV_PLATFORM,
53 .dev = {
54 .platform_data = serial_platform_data,
55 },
56 },
57};
58
59static int __init device_init(void)
60{
61 int i;
62
63 for (i = 0; i < ARRAY_SIZE(platform_devices); i++)
64 platform_device_register(&platform_devices[i]);
65 return 0;
66}
67arch_initcall_sync(device_init);
diff --git a/arch/xtensa/platforms/s6105/include/platform/gpio.h b/arch/xtensa/platforms/s6105/include/platform/gpio.h
new file mode 100644
index 000000000000..fa11aa4b61e9
--- /dev/null
+++ b/arch/xtensa/platforms/s6105/include/platform/gpio.h
@@ -0,0 +1,27 @@
1#ifndef __ASM_XTENSA_S6105_GPIO_H
2#define __ASM_XTENSA_S6105_GPIO_H
3
4#define GPIO_BP_TEMP_ALARM 0
5#define GPIO_PB_RESET_IN 1
6#define GPIO_EXP_IRQ 2
7#define GPIO_TRIGGER_IRQ 3
8#define GPIO_RTC_IRQ 4
9#define GPIO_PHY_IRQ 5
10#define GPIO_IMAGER_RESET 6
11#define GPIO_SD_IRQ 7
12#define GPIO_MINI_BOOT_INH 8
13#define GPIO_BOARD_RESET 9
14#define GPIO_EXP_PRESENT 10
15#define GPIO_LED1_NGREEN 12
16#define GPIO_LED1_RED 13
17#define GPIO_LED0_NGREEN 14
18#define GPIO_LED0_NRED 15
19#define GPIO_SPI_CS0 16
20#define GPIO_SPI_CS1 17
21#define GPIO_SPI_CS3 19
22#define GPIO_SPI_CS4 20
23#define GPIO_SD_WP 21
24#define GPIO_BP_RESET 22
25#define GPIO_ALARM_OUT 23
26
27#endif /* __ASM_XTENSA_S6105_GPIO_H */
diff --git a/arch/xtensa/platforms/s6105/include/platform/hardware.h b/arch/xtensa/platforms/s6105/include/platform/hardware.h
new file mode 100644
index 000000000000..d628efac7089
--- /dev/null
+++ b/arch/xtensa/platforms/s6105/include/platform/hardware.h
@@ -0,0 +1,11 @@
1#ifndef __XTENSA_S6105_HARDWARE_H
2#define __XTENSA_S6105_HARDWARE_H
3
4#define PLATFORM_DEFAULT_MEM_START 0x40000000
5#define PLATFORM_DEFAULT_MEM_SIZE 0x08000000
6
7#define MAX_DMA_ADDRESS 0
8
9#define KERNELOFFSET (PLATFORM_DEFAULT_MEM_START + 0x1000)
10
11#endif /* __XTENSA_S6105_HARDWARE_H */
diff --git a/arch/xtensa/platforms/s6105/include/platform/serial.h b/arch/xtensa/platforms/s6105/include/platform/serial.h
new file mode 100644
index 000000000000..c8a771e5981b
--- /dev/null
+++ b/arch/xtensa/platforms/s6105/include/platform/serial.h
@@ -0,0 +1,8 @@
1#ifndef __ASM_XTENSA_S6105_SERIAL_H
2#define __ASM_XTENSA_S6105_SERIAL_H
3
4#include <variant/hardware.h>
5
6#define BASE_BAUD (S6_SCLK / 16)
7
8#endif /* __ASM_XTENSA_S6105_SERIAL_H */
diff --git a/arch/xtensa/platforms/s6105/setup.c b/arch/xtensa/platforms/s6105/setup.c
new file mode 100644
index 000000000000..ae041d5027a2
--- /dev/null
+++ b/arch/xtensa/platforms/s6105/setup.c
@@ -0,0 +1,61 @@
1/*
2 * s6105 control routines
3 *
4 * Copyright (c) 2009 emlix GmbH
5 */
6#include <linux/irq.h>
7#include <linux/io.h>
8#include <linux/gpio.h>
9
10#include <asm/bootparam.h>
11
12#include <variant/hardware.h>
13#include <platform/gpio.h>
14
15void platform_halt(void)
16{
17 local_irq_disable();
18 while (1)
19 ;
20}
21
22void platform_power_off(void)
23{
24 platform_halt();
25}
26
27void platform_restart(void)
28{
29 platform_halt();
30}
31
32void __init platform_setup(char **cmdline)
33{
34 unsigned long reg;
35
36 reg = readl(S6_REG_GREG1 + S6_GREG1_CLKGATE);
37 reg &= ~(1 << S6_GREG1_BLOCK_SB);
38 writel(reg, S6_REG_GREG1 + S6_GREG1_CLKGATE);
39
40 reg = readl(S6_REG_GREG1 + S6_GREG1_BLOCKENA);
41 reg |= 1 << S6_GREG1_BLOCK_SB;
42 writel(reg, S6_REG_GREG1 + S6_GREG1_BLOCKENA);
43
44 printk(KERN_NOTICE "S6105 on Stretch S6000 - "
45 "Copyright (C) 2009 emlix GmbH <info@emlix.com>\n");
46}
47
48void __init platform_init(bp_tag_t *first)
49{
50 gpio_request(GPIO_LED1_NGREEN, "led1_green");
51 gpio_request(GPIO_LED1_RED, "led1_red");
52 gpio_direction_output(GPIO_LED1_NGREEN, 1);
53}
54
55void platform_heartbeat(void)
56{
57 static unsigned int c;
58
59 if (!(++c & 0x4F))
60 gpio_direction_output(GPIO_LED1_RED, !(c & 0x10));
61}
diff --git a/arch/xtensa/platforms/xt2000/include/platform/hardware.h b/arch/xtensa/platforms/xt2000/include/platform/hardware.h
index 41459ad07766..886ef156ded3 100644
--- a/arch/xtensa/platforms/xt2000/include/platform/hardware.h
+++ b/arch/xtensa/platforms/xt2000/include/platform/hardware.h
@@ -16,7 +16,6 @@
16#define _XTENSA_XT2000_HARDWARE_H 16#define _XTENSA_XT2000_HARDWARE_H
17 17
18#include <variant/core.h> 18#include <variant/core.h>
19#include <asm/io.h>
20 19
21/* 20/*
22 * Memory configuration. 21 * Memory configuration.
diff --git a/arch/xtensa/variants/s6000/Makefile b/arch/xtensa/variants/s6000/Makefile
new file mode 100644
index 000000000000..03b3975468bd
--- /dev/null
+++ b/arch/xtensa/variants/s6000/Makefile
@@ -0,0 +1,3 @@
1# s6000 Makefile
2
3obj-y += irq.o gpio.o
diff --git a/arch/xtensa/variants/s6000/gpio.c b/arch/xtensa/variants/s6000/gpio.c
new file mode 100644
index 000000000000..33a8d952934c
--- /dev/null
+++ b/arch/xtensa/variants/s6000/gpio.c
@@ -0,0 +1,71 @@
1/*
2 * s6000 gpio driver
3 *
4 * Copyright (c) 2009 emlix GmbH
5 * Authors: Oskar Schirmer <os@emlix.com>
6 * Johannes Weiner <jw@emlix.com>
7 */
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/io.h>
12#include <linux/gpio.h>
13
14#include <variant/hardware.h>
15
16#define S6_GPIO_DATA 0x000
17#define S6_GPIO_IS 0x404
18#define S6_GPIO_IBE 0x408
19#define S6_GPIO_IEV 0x40C
20#define S6_GPIO_IE 0x410
21#define S6_GPIO_RIS 0x414
22#define S6_GPIO_MIS 0x418
23#define S6_GPIO_IC 0x41C
24#define S6_GPIO_AFSEL 0x420
25#define S6_GPIO_DIR 0x800
26#define S6_GPIO_BANK(nr) ((nr) * 0x1000)
27#define S6_GPIO_MASK(nr) (4 << (nr))
28#define S6_GPIO_OFFSET(nr) \
29 (S6_GPIO_BANK((nr) >> 3) + S6_GPIO_MASK((nr) & 7))
30
31static int direction_input(struct gpio_chip *chip, unsigned int off)
32{
33 writeb(0, S6_REG_GPIO + S6_GPIO_DIR + S6_GPIO_OFFSET(off));
34 return 0;
35}
36
37static int get(struct gpio_chip *chip, unsigned int off)
38{
39 return readb(S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
40}
41
42static int direction_output(struct gpio_chip *chip, unsigned int off, int val)
43{
44 unsigned rel = S6_GPIO_OFFSET(off);
45 writeb(~0, S6_REG_GPIO + S6_GPIO_DIR + rel);
46 writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + rel);
47 return 0;
48}
49
50static void set(struct gpio_chip *chip, unsigned int off, int val)
51{
52 writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
53}
54
55static struct gpio_chip gpiochip = {
56 .owner = THIS_MODULE,
57 .direction_input = direction_input,
58 .get = get,
59 .direction_output = direction_output,
60 .set = set,
61 .base = 0,
62 .ngpio = 24,
63 .can_sleep = 0, /* no blocking io needed */
64 .exported = 0, /* no exporting to userspace */
65};
66
67static int gpio_init(void)
68{
69 return gpiochip_add(&gpiochip);
70}
71device_initcall(gpio_init);
diff --git a/arch/xtensa/variants/s6000/include/variant/core.h b/arch/xtensa/variants/s6000/include/variant/core.h
new file mode 100644
index 000000000000..af007953027e
--- /dev/null
+++ b/arch/xtensa/variants/s6000/include/variant/core.h
@@ -0,0 +1,431 @@
1/*
2 * Xtensa processor core configuration information.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (c) 1999-2008 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_CORE_CONFIGURATION_H
12#define _XTENSA_CORE_CONFIGURATION_H
13
14
15/****************************************************************************
16 Parameters Useful for Any Code, USER or PRIVILEGED
17 ****************************************************************************/
18
19/*
20 * Note: Macros of the form XCHAL_HAVE_*** have a value of 1 if the option is
21 * configured, and a value of 0 otherwise. These macros are always defined.
22 */
23
24
25/*----------------------------------------------------------------------
26 ISA
27 ----------------------------------------------------------------------*/
28
29#define XCHAL_HAVE_BE 0 /* big-endian byte ordering */
30#define XCHAL_HAVE_WINDOWED 1 /* windowed registers option */
31#define XCHAL_NUM_AREGS 64 /* num of physical addr regs */
32#define XCHAL_NUM_AREGS_LOG2 6 /* log2(XCHAL_NUM_AREGS) */
33#define XCHAL_MAX_INSTRUCTION_SIZE 8 /* max instr bytes (3..8) */
34#define XCHAL_HAVE_DEBUG 1 /* debug option */
35#define XCHAL_HAVE_DENSITY 1 /* 16-bit instructions */
36#define XCHAL_HAVE_LOOPS 1 /* zero-overhead loops */
37#define XCHAL_HAVE_NSA 1 /* NSA/NSAU instructions */
38#define XCHAL_HAVE_MINMAX 1 /* MIN/MAX instructions */
39#define XCHAL_HAVE_SEXT 1 /* SEXT instruction */
40#define XCHAL_HAVE_CLAMPS 1 /* CLAMPS instruction */
41#define XCHAL_HAVE_MUL16 1 /* MUL16S/MUL16U instructions */
42#define XCHAL_HAVE_MUL32 1 /* MULL instruction */
43#define XCHAL_HAVE_MUL32_HIGH 1 /* MULUH/MULSH instructions */
44#define XCHAL_HAVE_DIV32 0 /* QUOS/QUOU/REMS/REMU instructions */
45#define XCHAL_HAVE_L32R 1 /* L32R instruction */
46#define XCHAL_HAVE_ABSOLUTE_LITERALS 1 /* non-PC-rel (extended) L32R */
47#define XCHAL_HAVE_CONST16 0 /* CONST16 instruction */
48#define XCHAL_HAVE_ADDX 1 /* ADDX#/SUBX# instructions */
49#define XCHAL_HAVE_WIDE_BRANCHES 0 /* B*.W18 or B*.W15 instr's */
50#define XCHAL_HAVE_PREDICTED_BRANCHES 0 /* B[EQ/EQZ/NE/NEZ]T instr's */
51#define XCHAL_HAVE_CALL4AND12 1 /* (obsolete option) */
52#define XCHAL_HAVE_ABS 1 /* ABS instruction */
53/*#define XCHAL_HAVE_POPC 0*/ /* POPC instruction */
54/*#define XCHAL_HAVE_CRC 0*/ /* CRC instruction */
55#define XCHAL_HAVE_RELEASE_SYNC 0 /* L32AI/S32RI instructions */
56#define XCHAL_HAVE_S32C1I 0 /* S32C1I instruction */
57#define XCHAL_HAVE_SPECULATION 0 /* speculation */
58#define XCHAL_HAVE_FULL_RESET 0 /* all regs/state reset */
59#define XCHAL_NUM_CONTEXTS 1 /* */
60#define XCHAL_NUM_MISC_REGS 4 /* num of scratch regs (0..4) */
61#define XCHAL_HAVE_TAP_MASTER 0 /* JTAG TAP control instr's */
62#define XCHAL_HAVE_PRID 0 /* processor ID register */
63#define XCHAL_HAVE_THREADPTR 0 /* THREADPTR register */
64#define XCHAL_HAVE_BOOLEANS 1 /* boolean registers */
65#define XCHAL_HAVE_CP 1 /* CPENABLE reg (coprocessor) */
66#define XCHAL_CP_MAXCFG 8 /* max allowed cp id plus one */
67#define XCHAL_HAVE_MAC16 0 /* MAC16 package */
68#define XCHAL_HAVE_VECTORFPU2005 0 /* vector floating-point pkg */
69#define XCHAL_HAVE_FP 1 /* floating point pkg */
70#define XCHAL_HAVE_VECTRA1 0 /* Vectra I pkg */
71#define XCHAL_HAVE_VECTRALX 0 /* Vectra LX pkg */
72#define XCHAL_HAVE_HIFI2 0 /* HiFi2 Audio Engine pkg */
73
74
75/*----------------------------------------------------------------------
76 MISC
77 ----------------------------------------------------------------------*/
78
79#define XCHAL_NUM_WRITEBUFFER_ENTRIES 8 /* size of write buffer */
80#define XCHAL_INST_FETCH_WIDTH 8 /* instr-fetch width in bytes */
81#define XCHAL_DATA_WIDTH 16 /* data width in bytes */
82/* In T1050, applies to selected core load and store instructions (see ISA): */
83#define XCHAL_UNALIGNED_LOAD_EXCEPTION 1 /* unaligned loads cause exc. */
84#define XCHAL_UNALIGNED_STORE_EXCEPTION 1 /* unaligned stores cause exc.*/
85
86#define XCHAL_SW_VERSION 701001 /* sw version of this header */
87
88#define XCHAL_CORE_ID "stretch_bali" /* alphanum core name
89 (CoreID) set in the Xtensa
90 Processor Generator */
91
92#define XCHAL_BUILD_UNIQUE_ID 0x000104B9 /* 22-bit sw build ID */
93
94/*
95 * These definitions describe the hardware targeted by this software.
96 */
97#define XCHAL_HW_CONFIGID0 0xC2F3F9FE /* ConfigID hi 32 bits*/
98#define XCHAL_HW_CONFIGID1 0x054104B9 /* ConfigID lo 32 bits*/
99#define XCHAL_HW_VERSION_NAME "LX1.0.2" /* full version name */
100#define XCHAL_HW_VERSION_MAJOR 2100 /* major ver# of targeted hw */
101#define XCHAL_HW_VERSION_MINOR 2 /* minor ver# of targeted hw */
102#define XCHAL_HW_VERSION 210002 /* major*100+minor */
103#define XCHAL_HW_REL_LX1 1
104#define XCHAL_HW_REL_LX1_0 1
105#define XCHAL_HW_REL_LX1_0_2 1
106#define XCHAL_HW_CONFIGID_RELIABLE 1
107/* If software targets a *range* of hardware versions, these are the bounds: */
108#define XCHAL_HW_MIN_VERSION_MAJOR 2100 /* major v of earliest tgt hw */
109#define XCHAL_HW_MIN_VERSION_MINOR 2 /* minor v of earliest tgt hw */
110#define XCHAL_HW_MIN_VERSION 210002 /* earliest targeted hw */
111#define XCHAL_HW_MAX_VERSION_MAJOR 2100 /* major v of latest tgt hw */
112#define XCHAL_HW_MAX_VERSION_MINOR 2 /* minor v of latest tgt hw */
113#define XCHAL_HW_MAX_VERSION 210002 /* latest targeted hw */
114
115
116/*----------------------------------------------------------------------
117 CACHE
118 ----------------------------------------------------------------------*/
119
120#define XCHAL_ICACHE_LINESIZE 16 /* I-cache line size in bytes */
121#define XCHAL_DCACHE_LINESIZE 16 /* D-cache line size in bytes */
122#define XCHAL_ICACHE_LINEWIDTH 4 /* log2(I line size in bytes) */
123#define XCHAL_DCACHE_LINEWIDTH 4 /* log2(D line size in bytes) */
124
125#define XCHAL_ICACHE_SIZE 32768 /* I-cache size in bytes or 0 */
126#define XCHAL_DCACHE_SIZE 32768 /* D-cache size in bytes or 0 */
127
128#define XCHAL_DCACHE_IS_WRITEBACK 1 /* writeback feature */
129
130
131
132
133/****************************************************************************
134 Parameters Useful for PRIVILEGED (Supervisory or Non-Virtualized) Code
135 ****************************************************************************/
136
137
138#ifndef XTENSA_HAL_NON_PRIVILEGED_ONLY
139
140/*----------------------------------------------------------------------
141 CACHE
142 ----------------------------------------------------------------------*/
143
144#define XCHAL_HAVE_PIF 1 /* any outbound PIF present */
145
146/* If present, cache size in bytes == (ways * 2^(linewidth + setwidth)). */
147
148/* Number of cache sets in log2(lines per way): */
149#define XCHAL_ICACHE_SETWIDTH 9
150#define XCHAL_DCACHE_SETWIDTH 10
151
152/* Cache set associativity (number of ways): */
153#define XCHAL_ICACHE_WAYS 4
154#define XCHAL_DCACHE_WAYS 2
155
156/* Cache features: */
157#define XCHAL_ICACHE_LINE_LOCKABLE 1
158#define XCHAL_DCACHE_LINE_LOCKABLE 0
159#define XCHAL_ICACHE_ECC_PARITY 0
160#define XCHAL_DCACHE_ECC_PARITY 0
161
162/* Number of encoded cache attr bits (see <xtensa/hal.h> for decoded bits): */
163#define XCHAL_CA_BITS 4
164
165
166/*----------------------------------------------------------------------
167 INTERNAL I/D RAM/ROMs and XLMI
168 ----------------------------------------------------------------------*/
169
170#define XCHAL_NUM_INSTROM 0 /* number of core instr. ROMs */
171#define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
172#define XCHAL_NUM_DATAROM 0 /* number of core data ROMs */
173#define XCHAL_NUM_DATARAM 1 /* number of core data RAMs */
174#define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
175#define XCHAL_NUM_XLMI 1 /* number of core XLMI ports */
176
177/* Data RAM 0: */
178#define XCHAL_DATARAM0_VADDR 0x3FFF0000
179#define XCHAL_DATARAM0_PADDR 0x3FFF0000
180#define XCHAL_DATARAM0_SIZE 65536
181#define XCHAL_DATARAM0_ECC_PARITY 0
182
183/* XLMI Port 0: */
184#define XCHAL_XLMI0_VADDR 0x37F80000
185#define XCHAL_XLMI0_PADDR 0x37F80000
186#define XCHAL_XLMI0_SIZE 262144
187#define XCHAL_XLMI0_ECC_PARITY 0
188
189
190/*----------------------------------------------------------------------
191 INTERRUPTS and TIMERS
192 ----------------------------------------------------------------------*/
193
194#define XCHAL_HAVE_INTERRUPTS 1 /* interrupt option */
195#define XCHAL_HAVE_HIGHPRI_INTERRUPTS 1 /* med/high-pri. interrupts */
196#define XCHAL_HAVE_NMI 1 /* non-maskable interrupt */
197#define XCHAL_HAVE_CCOUNT 1 /* CCOUNT reg. (timer option) */
198#define XCHAL_NUM_TIMERS 3 /* number of CCOMPAREn regs */
199#define XCHAL_NUM_INTERRUPTS 27 /* number of interrupts */
200#define XCHAL_NUM_INTERRUPTS_LOG2 5 /* ceil(log2(NUM_INTERRUPTS)) */
201#define XCHAL_NUM_EXTINTERRUPTS 20 /* num of external interrupts */
202#define XCHAL_NUM_INTLEVELS 4 /* number of interrupt levels
203 (not including level zero) */
204#define XCHAL_EXCM_LEVEL 1 /* level masked by PS.EXCM */
205 /* (always 1 in XEA1; levels 2 .. EXCM_LEVEL are "medium priority") */
206
207/* Masks of interrupts at each interrupt level: */
208#define XCHAL_INTLEVEL1_MASK 0x01F07FFF
209#define XCHAL_INTLEVEL2_MASK 0x02018000
210#define XCHAL_INTLEVEL3_MASK 0x04060000
211#define XCHAL_INTLEVEL4_MASK 0x00000000
212#define XCHAL_INTLEVEL5_MASK 0x00080000
213#define XCHAL_INTLEVEL6_MASK 0x00000000
214#define XCHAL_INTLEVEL7_MASK 0x00000000
215
216/* Masks of interrupts at each range 1..n of interrupt levels: */
217#define XCHAL_INTLEVEL1_ANDBELOW_MASK 0x01F07FFF
218#define XCHAL_INTLEVEL2_ANDBELOW_MASK 0x03F1FFFF
219#define XCHAL_INTLEVEL3_ANDBELOW_MASK 0x07F7FFFF
220#define XCHAL_INTLEVEL4_ANDBELOW_MASK 0x07F7FFFF
221#define XCHAL_INTLEVEL5_ANDBELOW_MASK 0x07FFFFFF
222#define XCHAL_INTLEVEL6_ANDBELOW_MASK 0x07FFFFFF
223#define XCHAL_INTLEVEL7_ANDBELOW_MASK 0x07FFFFFF
224
225/* Level of each interrupt: */
226#define XCHAL_INT0_LEVEL 1
227#define XCHAL_INT1_LEVEL 1
228#define XCHAL_INT2_LEVEL 1
229#define XCHAL_INT3_LEVEL 1
230#define XCHAL_INT4_LEVEL 1
231#define XCHAL_INT5_LEVEL 1
232#define XCHAL_INT6_LEVEL 1
233#define XCHAL_INT7_LEVEL 1
234#define XCHAL_INT8_LEVEL 1
235#define XCHAL_INT9_LEVEL 1
236#define XCHAL_INT10_LEVEL 1
237#define XCHAL_INT11_LEVEL 1
238#define XCHAL_INT12_LEVEL 1
239#define XCHAL_INT13_LEVEL 1
240#define XCHAL_INT14_LEVEL 1
241#define XCHAL_INT15_LEVEL 2
242#define XCHAL_INT16_LEVEL 2
243#define XCHAL_INT17_LEVEL 3
244#define XCHAL_INT18_LEVEL 3
245#define XCHAL_INT19_LEVEL 5
246#define XCHAL_INT20_LEVEL 1
247#define XCHAL_INT21_LEVEL 1
248#define XCHAL_INT22_LEVEL 1
249#define XCHAL_INT23_LEVEL 1
250#define XCHAL_INT24_LEVEL 1
251#define XCHAL_INT25_LEVEL 2
252#define XCHAL_INT26_LEVEL 3
253#define XCHAL_DEBUGLEVEL 4 /* debug interrupt level */
254#define XCHAL_HAVE_DEBUG_EXTERN_INT 1 /* OCD external db interrupt */
255#define XCHAL_NMILEVEL 5 /* NMI "level" (for use with
256 EXCSAVE/EPS/EPC_n, RFI n) */
257
258/* Type of each interrupt: */
259#define XCHAL_INT0_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
260#define XCHAL_INT1_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
261#define XCHAL_INT2_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
262#define XCHAL_INT3_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
263#define XCHAL_INT4_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
264#define XCHAL_INT5_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
265#define XCHAL_INT6_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
266#define XCHAL_INT7_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
267#define XCHAL_INT8_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
268#define XCHAL_INT9_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
269#define XCHAL_INT10_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
270#define XCHAL_INT11_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
271#define XCHAL_INT12_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
272#define XCHAL_INT13_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
273#define XCHAL_INT14_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
274#define XCHAL_INT15_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
275#define XCHAL_INT16_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
276#define XCHAL_INT17_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
277#define XCHAL_INT18_TYPE XTHAL_INTTYPE_EXTERN_LEVEL
278#define XCHAL_INT19_TYPE XTHAL_INTTYPE_NMI
279#define XCHAL_INT20_TYPE XTHAL_INTTYPE_SOFTWARE
280#define XCHAL_INT21_TYPE XTHAL_INTTYPE_SOFTWARE
281#define XCHAL_INT22_TYPE XTHAL_INTTYPE_SOFTWARE
282#define XCHAL_INT23_TYPE XTHAL_INTTYPE_SOFTWARE
283#define XCHAL_INT24_TYPE XTHAL_INTTYPE_TIMER
284#define XCHAL_INT25_TYPE XTHAL_INTTYPE_TIMER
285#define XCHAL_INT26_TYPE XTHAL_INTTYPE_TIMER
286
287/* Masks of interrupts for each type of interrupt: */
288#define XCHAL_INTTYPE_MASK_UNCONFIGURED 0xF8000000
289#define XCHAL_INTTYPE_MASK_SOFTWARE 0x00F00000
290#define XCHAL_INTTYPE_MASK_EXTERN_EDGE 0x00000000
291#define XCHAL_INTTYPE_MASK_EXTERN_LEVEL 0x0007FFFF
292#define XCHAL_INTTYPE_MASK_TIMER 0x07000000
293#define XCHAL_INTTYPE_MASK_NMI 0x00080000
294#define XCHAL_INTTYPE_MASK_WRITE_ERROR 0x00000000
295
296/* Interrupt numbers assigned to specific interrupt sources: */
297#define XCHAL_TIMER0_INTERRUPT 24 /* CCOMPARE0 */
298#define XCHAL_TIMER1_INTERRUPT 25 /* CCOMPARE1 */
299#define XCHAL_TIMER2_INTERRUPT 26 /* CCOMPARE2 */
300#define XCHAL_TIMER3_INTERRUPT XTHAL_TIMER_UNCONFIGURED
301#define XCHAL_NMI_INTERRUPT 19 /* non-maskable interrupt */
302
303/* Interrupt numbers for levels at which only one interrupt is configured: */
304#define XCHAL_INTLEVEL5_NUM 19
305/* (There are many interrupts each at level(s) 1, 2, 3.) */
306
307
308/*
309 * External interrupt vectors/levels.
310 * These macros describe how Xtensa processor interrupt numbers
311 * (as numbered internally, eg. in INTERRUPT and INTENABLE registers)
312 * map to external BInterrupt<n> pins, for those interrupts
313 * configured as external (level-triggered, edge-triggered, or NMI).
314 * See the Xtensa processor databook for more details.
315 */
316
317/* Core interrupt numbers mapped to each EXTERNAL interrupt number: */
318#define XCHAL_EXTINT0_NUM 0 /* (intlevel 1) */
319#define XCHAL_EXTINT1_NUM 1 /* (intlevel 1) */
320#define XCHAL_EXTINT2_NUM 2 /* (intlevel 1) */
321#define XCHAL_EXTINT3_NUM 3 /* (intlevel 1) */
322#define XCHAL_EXTINT4_NUM 4 /* (intlevel 1) */
323#define XCHAL_EXTINT5_NUM 5 /* (intlevel 1) */
324#define XCHAL_EXTINT6_NUM 6 /* (intlevel 1) */
325#define XCHAL_EXTINT7_NUM 7 /* (intlevel 1) */
326#define XCHAL_EXTINT8_NUM 8 /* (intlevel 1) */
327#define XCHAL_EXTINT9_NUM 9 /* (intlevel 1) */
328#define XCHAL_EXTINT10_NUM 10 /* (intlevel 1) */
329#define XCHAL_EXTINT11_NUM 11 /* (intlevel 1) */
330#define XCHAL_EXTINT12_NUM 12 /* (intlevel 1) */
331#define XCHAL_EXTINT13_NUM 13 /* (intlevel 1) */
332#define XCHAL_EXTINT14_NUM 14 /* (intlevel 1) */
333#define XCHAL_EXTINT15_NUM 15 /* (intlevel 2) */
334#define XCHAL_EXTINT16_NUM 16 /* (intlevel 2) */
335#define XCHAL_EXTINT17_NUM 17 /* (intlevel 3) */
336#define XCHAL_EXTINT18_NUM 18 /* (intlevel 3) */
337#define XCHAL_EXTINT19_NUM 19 /* (intlevel 5) */
338
339
340/*----------------------------------------------------------------------
341 EXCEPTIONS and VECTORS
342 ----------------------------------------------------------------------*/
343
344#define XCHAL_XEA_VERSION 2 /* Xtensa Exception Architecture
345 number: 1 == XEA1 (old)
346 2 == XEA2 (new)
347 0 == XEAX (extern) */
348#define XCHAL_HAVE_XEA1 0 /* Exception Architecture 1 */
349#define XCHAL_HAVE_XEA2 1 /* Exception Architecture 2 */
350#define XCHAL_HAVE_XEAX 0 /* External Exception Arch. */
351#define XCHAL_HAVE_EXCEPTIONS 1 /* exception option */
352#define XCHAL_HAVE_MEM_ECC_PARITY 0 /* local memory ECC/parity */
353#define XCHAL_HAVE_VECTOR_SELECT 0 /* relocatable vectors */
354#define XCHAL_HAVE_VECBASE 0 /* relocatable vectors */
355
356#define XCHAL_RESET_VECOFS 0x00000000
357#define XCHAL_RESET_VECTOR_VADDR 0x3FFE03D0
358#define XCHAL_RESET_VECTOR_PADDR 0x3FFE03D0
359#define XCHAL_USER_VECOFS 0x00000000
360#define XCHAL_USER_VECTOR_VADDR 0x40000220
361#define XCHAL_USER_VECTOR_PADDR 0x40000220
362#define XCHAL_KERNEL_VECOFS 0x00000000
363#define XCHAL_KERNEL_VECTOR_VADDR 0x40000200
364#define XCHAL_KERNEL_VECTOR_PADDR 0x40000200
365#define XCHAL_DOUBLEEXC_VECOFS 0x00000000
366#define XCHAL_DOUBLEEXC_VECTOR_VADDR 0x400002A0
367#define XCHAL_DOUBLEEXC_VECTOR_PADDR 0x400002A0
368#define XCHAL_WINDOW_OF4_VECOFS 0x00000000
369#define XCHAL_WINDOW_UF4_VECOFS 0x00000040
370#define XCHAL_WINDOW_OF8_VECOFS 0x00000080
371#define XCHAL_WINDOW_UF8_VECOFS 0x000000C0
372#define XCHAL_WINDOW_OF12_VECOFS 0x00000100
373#define XCHAL_WINDOW_UF12_VECOFS 0x00000140
374#define XCHAL_WINDOW_VECTORS_VADDR 0x40000000
375#define XCHAL_WINDOW_VECTORS_PADDR 0x40000000
376#define XCHAL_INTLEVEL2_VECOFS 0x00000000
377#define XCHAL_INTLEVEL2_VECTOR_VADDR 0x40000240
378#define XCHAL_INTLEVEL2_VECTOR_PADDR 0x40000240
379#define XCHAL_INTLEVEL3_VECOFS 0x00000000
380#define XCHAL_INTLEVEL3_VECTOR_VADDR 0x40000260
381#define XCHAL_INTLEVEL3_VECTOR_PADDR 0x40000260
382#define XCHAL_INTLEVEL4_VECOFS 0x00000000
383#define XCHAL_INTLEVEL4_VECTOR_VADDR 0x40000390
384#define XCHAL_INTLEVEL4_VECTOR_PADDR 0x40000390
385#define XCHAL_DEBUG_VECOFS XCHAL_INTLEVEL4_VECOFS
386#define XCHAL_DEBUG_VECTOR_VADDR XCHAL_INTLEVEL4_VECTOR_VADDR
387#define XCHAL_DEBUG_VECTOR_PADDR XCHAL_INTLEVEL4_VECTOR_PADDR
388#define XCHAL_NMI_VECOFS 0x00000000
389#define XCHAL_NMI_VECTOR_VADDR 0x400003B0
390#define XCHAL_NMI_VECTOR_PADDR 0x400003B0
391#define XCHAL_INTLEVEL5_VECOFS XCHAL_NMI_VECOFS
392#define XCHAL_INTLEVEL5_VECTOR_VADDR XCHAL_NMI_VECTOR_VADDR
393#define XCHAL_INTLEVEL5_VECTOR_PADDR XCHAL_NMI_VECTOR_PADDR
394
395
396/*----------------------------------------------------------------------
397 DEBUG
398 ----------------------------------------------------------------------*/
399
400#define XCHAL_HAVE_OCD 1 /* OnChipDebug option */
401#define XCHAL_NUM_IBREAK 2 /* number of IBREAKn regs */
402#define XCHAL_NUM_DBREAK 2 /* number of DBREAKn regs */
403#define XCHAL_HAVE_OCD_DIR_ARRAY 1 /* faster OCD option */
404
405
406/*----------------------------------------------------------------------
407 MMU
408 ----------------------------------------------------------------------*/
409
410/* See core-matmap.h header file for more details. */
411
412#define XCHAL_HAVE_TLBS 1 /* inverse of HAVE_CACHEATTR */
413#define XCHAL_HAVE_SPANNING_WAY 1 /* one way maps I+D 4GB vaddr */
414#define XCHAL_HAVE_IDENTITY_MAP 1 /* vaddr == paddr always */
415#define XCHAL_HAVE_CACHEATTR 0 /* CACHEATTR register present */
416#define XCHAL_HAVE_MIMIC_CACHEATTR 1 /* region protection */
417#define XCHAL_HAVE_XLT_CACHEATTR 0 /* region prot. w/translation */
418#define XCHAL_HAVE_PTP_MMU 0 /* full MMU (with page table
419 [autorefill] and protection)
420 usable for an MMU-based OS */
421/* If none of the above last 4 are set, it's a custom TLB configuration. */
422
423#define XCHAL_MMU_ASID_BITS 0 /* number of bits in ASIDs */
424#define XCHAL_MMU_RINGS 1 /* number of rings (1..4) */
425#define XCHAL_MMU_RING_BITS 0 /* num of bits in RING field */
426
427#endif /* !XTENSA_HAL_NON_PRIVILEGED_ONLY */
428
429
430#endif /* _XTENSA_CORE_CONFIGURATION_H */
431
diff --git a/arch/xtensa/variants/s6000/include/variant/hardware.h b/arch/xtensa/variants/s6000/include/variant/hardware.h
new file mode 100644
index 000000000000..5d9ba098d84a
--- /dev/null
+++ b/arch/xtensa/variants/s6000/include/variant/hardware.h
@@ -0,0 +1,259 @@
1#ifndef __XTENSA_S6000_HARDWARE_H
2#define __XTENSA_S6000_HARDWARE_H
3
4#define S6_SCLK 1843200
5
6#define S6_MEM_REG 0x20000000
7#define S6_MEM_EFI 0x33F00000
8#define S6_MEM_PCIE_DATARAM1 0x34000000
9#define S6_MEM_XLMI 0x37F80000
10#define S6_MEM_PIF_DATARAM1 0x37FFC000
11#define S6_MEM_GMAC 0x38000000
12#define S6_MEM_I2S 0x3A000000
13#define S6_MEM_EGIB 0x3C000000
14#define S6_MEM_PCIE_CFG 0x3E000000
15#define S6_MEM_PIF_DATARAM 0x3FFE0000
16#define S6_MEM_XLMI_DATARAM 0x3FFF0000
17#define S6_MEM_DDR 0x40000000
18#define S6_MEM_PCIE_APER 0xC0000000
19#define S6_MEM_AUX 0xF0000000
20
21/* Device addresses */
22
23#define S6_REG_SCB S6_MEM_REG
24#define S6_REG_NB (S6_REG_SCB + 0x10000)
25#define S6_REG_LMSDMA (S6_REG_SCB + 0x20000)
26#define S6_REG_NI (S6_REG_SCB + 0x30000)
27#define S6_REG_NIDMA (S6_REG_SCB + 0x40000)
28#define S6_REG_NS (S6_REG_SCB + 0x50000)
29#define S6_REG_DDR (S6_REG_SCB + 0x60000)
30#define S6_REG_GREG1 (S6_REG_SCB + 0x70000)
31#define S6_REG_DP (S6_REG_SCB + 0x80000)
32#define S6_REG_DPDMA (S6_REG_SCB + 0x90000)
33#define S6_REG_EGIB (S6_REG_SCB + 0xA0000)
34#define S6_REG_PCIE (S6_REG_SCB + 0xB0000)
35#define S6_REG_I2S (S6_REG_SCB + 0xC0000)
36#define S6_REG_GMAC (S6_REG_SCB + 0xD0000)
37#define S6_REG_HIFDMA (S6_REG_SCB + 0xE0000)
38#define S6_REG_GREG2 (S6_REG_SCB + 0xF0000)
39
40#define S6_REG_APB S6_REG_SCB
41#define S6_REG_UART (S6_REG_APB + 0x0000)
42#define S6_REG_INTC (S6_REG_APB + 0x2000)
43#define S6_REG_SPI (S6_REG_APB + 0x3000)
44#define S6_REG_I2C (S6_REG_APB + 0x4000)
45#define S6_REG_GPIO (S6_REG_APB + 0x8000)
46
47/* Global register block */
48
49#define S6_GREG1_PLL_LOCKCLEAR 0x000
50#define S6_GREG1_PLL_LOCK_SYS 0
51#define S6_GREG1_PLL_LOCK_IO 1
52#define S6_GREG1_PLL_LOCK_AIM 2
53#define S6_GREG1_PLL_LOCK_DP0 3
54#define S6_GREG1_PLL_LOCK_DP2 4
55#define S6_GREG1_PLL_LOCK_DDR 5
56#define S6_GREG1_PLL_LOCKSTAT 0x004
57#define S6_GREG1_PLL_LOCKSTAT_CURLOCK 0
58#define S6_GREG1_PLL_LOCKSTAT_EVERUNLCK 8
59#define S6_GREG1_PLLSEL 0x010
60#define S6_GREG1_PLLSEL_AIM 0
61#define S6_GREG1_PLLSEL_AIM_DDR2 0
62#define S6_GREG1_PLLSEL_AIM_300MHZ 1
63#define S6_GREG1_PLLSEL_AIM_240MHZ 2
64#define S6_GREG1_PLLSEL_AIM_200MHZ 3
65#define S6_GREG1_PLLSEL_AIM_150MHZ 4
66#define S6_GREG1_PLLSEL_AIM_120MHZ 5
67#define S6_GREG1_PLLSEL_AIM_40MHZ 6
68#define S6_GREG1_PLLSEL_AIM_PLLAIMREF 7
69#define S6_GREG1_PLLSEL_AIM_MASK 7
70#define S6_GREG1_PLLSEL_DDR 8
71#define S6_GREG1_PLLSEL_DDR_HS 0
72#define S6_GREG1_PLLSEL_DDR_333MHZ 1
73#define S6_GREG1_PLLSEL_DDR_250MHZ 2
74#define S6_GREG1_PLLSEL_DDR_200MHZ 3
75#define S6_GREG1_PLLSEL_DDR_167MHZ 4
76#define S6_GREG1_PLLSEL_DDR_100MHZ 5
77#define S6_GREG1_PLLSEL_DDR_33MHZ 6
78#define S6_GREG1_PLLSEL_DDR_PLLIOREF 7
79#define S6_GREG1_PLLSEL_DDR_MASK 7
80#define S6_GREG1_PLLSEL_GMAC 16
81#define S6_GREG1_PLLSEL_GMAC_125MHZ 0
82#define S6_GREG1_PLLSEL_GMAC_25MHZ 1
83#define S6_GREG1_PLLSEL_GMAC_2500KHZ 2
84#define S6_GREG1_PLLSEL_GMAC_EXTERN 3
85#define S6_GREG1_PLLSEL_GMAC_MASK 3
86#define S6_GREG1_PLLSEL_GMII 18
87#define S6_GREG1_PLLSEL_GMII_111MHZ 0
88#define S6_GREG1_PLLSEL_GMII_IOREF 1
89#define S6_GREG1_PLLSEL_GMII_NONE 2
90#define S6_GREG1_PLLSEL_GMII_125MHZ 3
91#define S6_GREG1_PLLSEL_GMII_MASK 3
92#define S6_GREG1_SYSUNLOCKCNT 0x020
93#define S6_GREG1_IOUNLOCKCNT 0x024
94#define S6_GREG1_AIMUNLOCKCNT 0x028
95#define S6_GREG1_DP0UNLOCKCNT 0x02C
96#define S6_GREG1_DP2UNLOCKCNT 0x030
97#define S6_GREG1_DDRUNLOCKCNT 0x034
98#define S6_GREG1_CLKBAL0 0x040
99#define S6_GREG1_CLKBAL0_LSGB 0
100#define S6_GREG1_CLKBAL0_LSPX 8
101#define S6_GREG1_CLKBAL0_MEMDO 16
102#define S6_GREG1_CLKBAL0_HSXT1 24
103#define S6_GREG1_CLKBAL1 0x044
104#define S6_GREG1_CLKBAL1_HSISEF 0
105#define S6_GREG1_CLKBAL1_HSNI 8
106#define S6_GREG1_CLKBAL1_HSNS 16
107#define S6_GREG1_CLKBAL1_HSISEFCFG 24
108#define S6_GREG1_CLKBAL2 0x048
109#define S6_GREG1_CLKBAL2_LSNB 0
110#define S6_GREG1_CLKBAL2_LSSB 8
111#define S6_GREG1_CLKBAL2_LSREST 24
112#define S6_GREG1_CLKBAL3 0x04C
113#define S6_GREG1_CLKBAL3_ISEFXAD 0
114#define S6_GREG1_CLKBAL3_ISEFLMS 8
115#define S6_GREG1_CLKBAL3_ISEFISEF 16
116#define S6_GREG1_CLKBAL3_DDRDD 24
117#define S6_GREG1_CLKBAL4 0x050
118#define S6_GREG1_CLKBAL4_DDRDP 0
119#define S6_GREG1_CLKBAL4_DDRDO 8
120#define S6_GREG1_CLKBAL4_DDRNB 16
121#define S6_GREG1_CLKBAL4_DDRLMS 24
122#define S6_GREG1_BLOCKENA 0x100
123#define S6_GREG1_BLOCK_DDR 0
124#define S6_GREG1_BLOCK_DP 1
125#define S6_GREG1_BLOCK_NSNI 2
126#define S6_GREG1_BLOCK_PCIE 3
127#define S6_GREG1_BLOCK_GMAC 4
128#define S6_GREG1_BLOCK_I2S 5
129#define S6_GREG1_BLOCK_EGIB 6
130#define S6_GREG1_BLOCK_SB 7
131#define S6_GREG1_BLOCK_XT1 8
132#define S6_GREG1_CLKGATE 0x104
133#define S6_GREG1_BGATE_AIMNORTH 9
134#define S6_GREG1_BGATE_AIMEAST 10
135#define S6_GREG1_BGATE_AIMWEST 11
136#define S6_GREG1_BGATE_AIMSOUTH 12
137#define S6_GREG1_CHIPRES 0x108
138#define S6_GREG1_CHIPRES_SOFTRES 0
139#define S6_GREG1_CHIPRES_LOSTLOCK 1
140#define S6_GREG1_RESETCAUSE 0x10C
141#define S6_GREG1_RESETCAUSE_RESETN 0
142#define S6_GREG1_RESETCAUSE_GLOBAL 1
143#define S6_GREG1_RESETCAUSE_WDOGTIMER 2
144#define S6_GREG1_RESETCAUSE_SWCHIP 3
145#define S6_GREG1_RESETCAUSE_PLLSYSLOSS 4
146#define S6_GREG1_RESETCAUSE_PCIE 5
147#define S6_GREG1_RESETCAUSE_CREATEDGLOB 6
148#define S6_GREG1_REFCLOCKCNT 0x110
149#define S6_GREG1_RESETTIMER 0x114
150#define S6_GREG1_NMITIMER 0x118
151#define S6_GREG1_GLOBAL_TIMER 0x11C
152#define S6_GREG1_TIMER0 0x180
153#define S6_GREG1_TIMER1 0x184
154#define S6_GREG1_UARTCLOCKSEL 0x204
155#define S6_GREG1_CHIPVERSPACKG 0x208
156#define S6_GREG1_CHIPVERSPACKG_CHIPVID 0
157#define S6_GREG1_CHIPVERSPACKG_PACKSEL 8
158#define S6_GREG1_ONDIETERMCTRL 0x20C
159#define S6_GREG1_ONDIETERMCTRL_WEST 0
160#define S6_GREG1_ONDIETERMCTRL_NORTH 2
161#define S6_GREG1_ONDIETERMCTRL_EAST 4
162#define S6_GREG1_ONDIETERMCTRL_SOUTH 6
163#define S6_GREG1_ONDIETERMCTRL_NONE 0
164#define S6_GREG1_ONDIETERMCTRL_75OHM 2
165#define S6_GREG1_ONDIETERMCTRL_MASK 3
166#define S6_GREG1_BOOT_CFG0 0x210
167#define S6_GREG1_BOOT_CFG0_AIMSTRONG 1
168#define S6_GREG1_BOOT_CFG0_MINIBOOTDL 2
169#define S6_GREG1_BOOT_CFG0_OCDGPIO8SET 5
170#define S6_GREG1_BOOT_CFG0_OCDGPIOENA 6
171#define S6_GREG1_BOOT_CFG0_DOWNSTREAM 7
172#define S6_GREG1_BOOT_CFG0_PLLSYSDIV 8
173#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_300MHZ 1
174#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_240MHZ 2
175#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_200MHZ 3
176#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_150MHZ 4
177#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_120MHZ 5
178#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_40MHZ 6
179#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_MASK 7
180#define S6_GREG1_BOOT_CFG0_BALHSLMS 12
181#define S6_GREG1_BOOT_CFG0_BALHSNB 18
182#define S6_GREG1_BOOT_CFG0_BALHSXAD 24
183#define S6_GREG1_BOOT_CFG1 0x214
184#define S6_GREG1_BOOT_CFG1_PCIE1LANE 1
185#define S6_GREG1_BOOT_CFG1_MPLLPRESCALE 2
186#define S6_GREG1_BOOT_CFG1_MPLLNCY 4
187#define S6_GREG1_BOOT_CFG1_MPLLNCY5 9
188#define S6_GREG1_BOOT_CFG1_BALHSREST 14
189#define S6_GREG1_BOOT_CFG1_BALHSPSMEMS 20
190#define S6_GREG1_BOOT_CFG1_BALLSGI 26
191#define S6_GREG1_BOOT_CFG2 0x218
192#define S6_GREG1_BOOT_CFG2_PEID 0
193#define S6_GREG1_BOOT_CFG3 0x21C
194#define S6_GREG1_DRAMBUSYHOLDOF 0x220
195#define S6_GREG1_DRAMBUSYHOLDOF_XT0 0
196#define S6_GREG1_DRAMBUSYHOLDOF_XT1 4
197#define S6_GREG1_DRAMBUSYHOLDOF_XT_MASK 7
198#define S6_GREG1_PCIEBAR1SIZE 0x224
199#define S6_GREG1_PCIEBAR2SIZE 0x228
200#define S6_GREG1_PCIEVENDOR 0x22C
201#define S6_GREG1_PCIEDEVICE 0x230
202#define S6_GREG1_PCIEREV 0x234
203#define S6_GREG1_PCIECLASS 0x238
204#define S6_GREG1_XT1DCACHEMISS 0x240
205#define S6_GREG1_XT1ICACHEMISS 0x244
206#define S6_GREG1_HWSEMAPHORE(n) (0x400 + 4 * (n))
207#define S6_GREG1_HWSEMAPHORE_NB 16
208
209/* peripheral interrupt numbers */
210
211#define S6_INTC_GPIO(n) (n) /* 0..3 */
212#define S6_INTC_I2C 4
213#define S6_INTC_SPI 5
214#define S6_INTC_NB_ERR 6
215#define S6_INTC_DMA_LMSERR 7
216#define S6_INTC_DMA_LMSLOWWMRK(n) (8 + (n)) /* 0..11 */
217#define S6_INTC_DMA_LMSPENDCNT(n) (20 + (n)) /* 0..11 */
218#define S6_INTC_DMA HOSTLOWWMRK(n) (32 + (n)) /* 0..6 */
219#define S6_INTC_DMA_HOSTPENDCNT(n) (39 + (n)) /* 0..6 */
220#define S6_INTC_DMA_HOSTERR 46
221#define S6_INTC_UART(n) (47 + (n)) /* 0..1 */
222#define S6_INTC_XAD 49
223#define S6_INTC_NI_ERR 50
224#define S6_INTC_NI_INFIFOFULL 51
225#define S6_INTC_DMA_NIERR 52
226#define S6_INTC_DMA_NILOWWMRK(n) (53 + (n)) /* 0..3 */
227#define S6_INTC_DMA_NIPENDCNT(n) (57 + (n)) /* 0..3 */
228#define S6_INTC_DDR 61
229#define S6_INTC_NS_ERR 62
230#define S6_INTC_EFI_CFGERR 63
231#define S6_INTC_EFI_ISEFTEST 64
232#define S6_INTC_EFI_WRITEERR 65
233#define S6_INTC_NMI_TIMER 66
234#define S6_INTC_PLLLOCK_SYS 67
235#define S6_INTC_PLLLOCK_IO 68
236#define S6_INTC_PLLLOCK_AIM 69
237#define S6_INTC_PLLLOCK_DP0 70
238#define S6_INTC_PLLLOCK_DP2 71
239#define S6_INTC_I2S_ERR 72
240#define S6_INTC_GMAC_STAT 73
241#define S6_INTC_GMAC_ERR 74
242#define S6_INTC_GIB_ERR 75
243#define S6_INTC_PCIE_ERR 76
244#define S6_INTC_PCIE_MSI(n) (77 + (n)) /* 0..3 */
245#define S6_INTC_PCIE_INTA 81
246#define S6_INTC_PCIE_INTB 82
247#define S6_INTC_PCIE_INTC 83
248#define S6_INTC_PCIE_INTD 84
249#define S6_INTC_SW(n) (85 + (n)) /* 0..9 */
250#define S6_INTC_SW_ENABLE(n) (85 + 256 + (n))
251#define S6_INTC_DMA_DP_ERR 95
252#define S6_INTC_DMA_DPLOWWMRK(n) (96 + (n)) /* 0..3 */
253#define S6_INTC_DMA_DPPENDCNT(n) (100 + (n)) /* 0..3 */
254#define S6_INTC_DMA_DPTERMCNT(n) (104 + (n)) /* 0..3 */
255#define S6_INTC_TIMER0 108
256#define S6_INTC_TIMER1 109
257#define S6_INTC_DMA_HOSTTERMCNT(n) (110 + (n)) /* 0..6 */
258
259#endif /* __XTENSA_S6000_HARDWARE_H */
diff --git a/arch/xtensa/variants/s6000/include/variant/irq.h b/arch/xtensa/variants/s6000/include/variant/irq.h
new file mode 100644
index 000000000000..fa031cb0acc4
--- /dev/null
+++ b/arch/xtensa/variants/s6000/include/variant/irq.h
@@ -0,0 +1,9 @@
1#ifndef __XTENSA_S6000_IRQ_H
2#define __XTENSA_S6000_IRQ_H
3
4#define NO_IRQ (-1)
5
6extern void variant_irq_enable(unsigned int irq);
7extern void variant_irq_disable(unsigned int irq);
8
9#endif /* __XTENSA_S6000_IRQ_H */
diff --git a/arch/xtensa/variants/s6000/include/variant/tie-asm.h b/arch/xtensa/variants/s6000/include/variant/tie-asm.h
new file mode 100644
index 000000000000..f02d0a3a2e20
--- /dev/null
+++ b/arch/xtensa/variants/s6000/include/variant/tie-asm.h
@@ -0,0 +1,304 @@
1/*
2 * This header file contains assembly-language definitions (assembly
3 * macros, etc.) for this specific Xtensa processor's TIE extensions
4 * and options. It is customized to this Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2008 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_ASM_H
14#define _XTENSA_CORE_TIE_ASM_H
15
16/* Selection parameter values for save-area save/restore macros: */
17/* Option vs. TIE: */
18#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
19#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
20/* Whether used automatically by compiler: */
21#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
22#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
23/* ABI handling across function calls: */
24#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
25#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
26#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
27/* Misc */
28#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
29
30
31
32/* Macro to save all non-coprocessor (extra) custom TIE and optional state
33 * (not including zero-overhead loop registers).
34 * Save area ptr (clobbered): ptr (16 byte aligned)
35 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
36 */
37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
38 xchal_sa_start \continue, \ofs
39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
40 xchal_sa_align \ptr, 0, 1024-4, 4, 4
41 rsr \at1, BR // boolean option
42 s32i \at1, \ptr, .Lxchal_ofs_ + 0
43 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
44 .endif
45 .endm // xchal_ncp_store
46
47/* Macro to save all non-coprocessor (extra) custom TIE and optional state
48 * (not including zero-overhead loop registers).
49 * Save area ptr (clobbered): ptr (16 byte aligned)
50 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
51 */
52 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
53 xchal_sa_start \continue, \ofs
54 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
55 xchal_sa_align \ptr, 0, 1024-4, 4, 4
56 l32i \at1, \ptr, .Lxchal_ofs_ + 0
57 wsr \at1, BR // boolean option
58 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4
59 .endif
60 .endm // xchal_ncp_load
61
62
63
64#define XCHAL_NCP_NUM_ATMPS 1
65
66
67
68/* Macro to save the state of TIE coprocessor FPU.
69 * Save area ptr (clobbered): ptr (16 byte aligned)
70 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
71 */
72#define xchal_cp_FPU_store xchal_cp0_store
73/* #define xchal_cp_FPU_store_a2 xchal_cp0_store a2 a3 a4 a5 a6 */
74 .macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
75 xchal_sa_start \continue, \ofs
76 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
77 xchal_sa_align \ptr, 0, 0, 1, 16
78 rur232 \at1 // FCR
79 s32i \at1, \ptr, 0
80 rur233 \at1 // FSR
81 s32i \at1, \ptr, 4
82 SSI f0, \ptr, 8
83 SSI f1, \ptr, 12
84 SSI f2, \ptr, 16
85 SSI f3, \ptr, 20
86 SSI f4, \ptr, 24
87 SSI f5, \ptr, 28
88 SSI f6, \ptr, 32
89 SSI f7, \ptr, 36
90 SSI f8, \ptr, 40
91 SSI f9, \ptr, 44
92 SSI f10, \ptr, 48
93 SSI f11, \ptr, 52
94 SSI f12, \ptr, 56
95 SSI f13, \ptr, 60
96 SSI f14, \ptr, 64
97 SSI f15, \ptr, 68
98 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
99 .endif
100 .endm // xchal_cp0_store
101
102/* Macro to restore the state of TIE coprocessor FPU.
103 * Save area ptr (clobbered): ptr (16 byte aligned)
104 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
105 */
106#define xchal_cp_FPU_load xchal_cp0_load
107/* #define xchal_cp_FPU_load_a2 xchal_cp0_load a2 a3 a4 a5 a6 */
108 .macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
109 xchal_sa_start \continue, \ofs
110 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
111 xchal_sa_align \ptr, 0, 0, 1, 16
112 l32i \at1, \ptr, 0
113 wur232 \at1 // FCR
114 l32i \at1, \ptr, 4
115 wur233 \at1 // FSR
116 LSI f0, \ptr, 8
117 LSI f1, \ptr, 12
118 LSI f2, \ptr, 16
119 LSI f3, \ptr, 20
120 LSI f4, \ptr, 24
121 LSI f5, \ptr, 28
122 LSI f6, \ptr, 32
123 LSI f7, \ptr, 36
124 LSI f8, \ptr, 40
125 LSI f9, \ptr, 44
126 LSI f10, \ptr, 48
127 LSI f11, \ptr, 52
128 LSI f12, \ptr, 56
129 LSI f13, \ptr, 60
130 LSI f14, \ptr, 64
131 LSI f15, \ptr, 68
132 .set .Lxchal_ofs_, .Lxchal_ofs_ + 72
133 .endif
134 .endm // xchal_cp0_load
135
136#define XCHAL_CP0_NUM_ATMPS 1
137
138/* Macro to save the state of TIE coprocessor XAD.
139 * Save area ptr (clobbered): ptr (16 byte aligned)
140 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
141 */
142#define xchal_cp_XAD_store xchal_cp6_store
143/* #define xchal_cp_XAD_store_a2 xchal_cp6_store a2 a3 a4 a5 a6 */
144 .macro xchal_cp6_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
145 xchal_sa_start \continue, \ofs
146 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
147 xchal_sa_align \ptr, 0, 0, 1, 16
148 rur0 \at1 // LDCBHI
149 s32i \at1, \ptr, 0
150 rur1 \at1 // LDCBLO
151 s32i \at1, \ptr, 4
152 rur2 \at1 // STCBHI
153 s32i \at1, \ptr, 8
154 rur3 \at1 // STCBLO
155 s32i \at1, \ptr, 12
156 rur8 \at1 // LDBRBASE
157 s32i \at1, \ptr, 16
158 rur9 \at1 // LDBROFF
159 s32i \at1, \ptr, 20
160 rur10 \at1 // LDBRINC
161 s32i \at1, \ptr, 24
162 rur11 \at1 // STBRBASE
163 s32i \at1, \ptr, 28
164 rur12 \at1 // STBROFF
165 s32i \at1, \ptr, 32
166 rur13 \at1 // STBRINC
167 s32i \at1, \ptr, 36
168 rur24 \at1 // SCRATCH0
169 s32i \at1, \ptr, 40
170 rur25 \at1 // SCRATCH1
171 s32i \at1, \ptr, 44
172 rur26 \at1 // SCRATCH2
173 s32i \at1, \ptr, 48
174 rur27 \at1 // SCRATCH3
175 s32i \at1, \ptr, 52
176 WRAS128I wra0, \ptr, 64
177 WRAS128I wra1, \ptr, 80
178 WRAS128I wra2, \ptr, 96
179 WRAS128I wra3, \ptr, 112
180 WRAS128I wra4, \ptr, 128
181 WRAS128I wra5, \ptr, 144
182 WRAS128I wra6, \ptr, 160
183 WRAS128I wra7, \ptr, 176
184 WRAS128I wra8, \ptr, 192
185 WRAS128I wra9, \ptr, 208
186 WRAS128I wra10, \ptr, 224
187 WRAS128I wra11, \ptr, 240
188 WRAS128I wra12, \ptr, 256
189 WRAS128I wra13, \ptr, 272
190 WRAS128I wra14, \ptr, 288
191 WRAS128I wra15, \ptr, 304
192 WRBS128I wrb0, \ptr, 320
193 WRBS128I wrb1, \ptr, 336
194 WRBS128I wrb2, \ptr, 352
195 WRBS128I wrb3, \ptr, 368
196 WRBS128I wrb4, \ptr, 384
197 WRBS128I wrb5, \ptr, 400
198 WRBS128I wrb6, \ptr, 416
199 WRBS128I wrb7, \ptr, 432
200 WRBS128I wrb8, \ptr, 448
201 WRBS128I wrb9, \ptr, 464
202 WRBS128I wrb10, \ptr, 480
203 WRBS128I wrb11, \ptr, 496
204 WRBS128I wrb12, \ptr, 512
205 WRBS128I wrb13, \ptr, 528
206 WRBS128I wrb14, \ptr, 544
207 WRBS128I wrb15, \ptr, 560
208 .set .Lxchal_ofs_, .Lxchal_ofs_ + 576
209 .endif
210 .endm // xchal_cp6_store
211
212/* Macro to restore the state of TIE coprocessor XAD.
213 * Save area ptr (clobbered): ptr (16 byte aligned)
214 * Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
215 */
216#define xchal_cp_XAD_load xchal_cp6_load
217/* #define xchal_cp_XAD_load_a2 xchal_cp6_load a2 a3 a4 a5 a6 */
218 .macro xchal_cp6_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
219 xchal_sa_start \continue, \ofs
220 .ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
221 xchal_sa_align \ptr, 0, 0, 1, 16
222 l32i \at1, \ptr, 0
223 wur0 \at1 // LDCBHI
224 l32i \at1, \ptr, 4
225 wur1 \at1 // LDCBLO
226 l32i \at1, \ptr, 8
227 wur2 \at1 // STCBHI
228 l32i \at1, \ptr, 12
229 wur3 \at1 // STCBLO
230 l32i \at1, \ptr, 16
231 wur8 \at1 // LDBRBASE
232 l32i \at1, \ptr, 20
233 wur9 \at1 // LDBROFF
234 l32i \at1, \ptr, 24
235 wur10 \at1 // LDBRINC
236 l32i \at1, \ptr, 28
237 wur11 \at1 // STBRBASE
238 l32i \at1, \ptr, 32
239 wur12 \at1 // STBROFF
240 l32i \at1, \ptr, 36
241 wur13 \at1 // STBRINC
242 l32i \at1, \ptr, 40
243 wur24 \at1 // SCRATCH0
244 l32i \at1, \ptr, 44
245 wur25 \at1 // SCRATCH1
246 l32i \at1, \ptr, 48
247 wur26 \at1 // SCRATCH2
248 l32i \at1, \ptr, 52
249 wur27 \at1 // SCRATCH3
250 WRBL128I wrb0, \ptr, 320
251 WRBL128I wrb1, \ptr, 336
252 WRBL128I wrb2, \ptr, 352
253 WRBL128I wrb3, \ptr, 368
254 WRBL128I wrb4, \ptr, 384
255 WRBL128I wrb5, \ptr, 400
256 WRBL128I wrb6, \ptr, 416
257 WRBL128I wrb7, \ptr, 432
258 WRBL128I wrb8, \ptr, 448
259 WRBL128I wrb9, \ptr, 464
260 WRBL128I wrb10, \ptr, 480
261 WRBL128I wrb11, \ptr, 496
262 WRBL128I wrb12, \ptr, 512
263 WRBL128I wrb13, \ptr, 528
264 WRBL128I wrb14, \ptr, 544
265 WRBL128I wrb15, \ptr, 560
266 WRAL128I wra0, \ptr, 64
267 WRAL128I wra1, \ptr, 80
268 WRAL128I wra2, \ptr, 96
269 WRAL128I wra3, \ptr, 112
270 WRAL128I wra4, \ptr, 128
271 WRAL128I wra5, \ptr, 144
272 WRAL128I wra6, \ptr, 160
273 WRAL128I wra7, \ptr, 176
274 WRAL128I wra8, \ptr, 192
275 WRAL128I wra9, \ptr, 208
276 WRAL128I wra10, \ptr, 224
277 WRAL128I wra11, \ptr, 240
278 WRAL128I wra12, \ptr, 256
279 WRAL128I wra13, \ptr, 272
280 WRAL128I wra14, \ptr, 288
281 WRAL128I wra15, \ptr, 304
282 .set .Lxchal_ofs_, .Lxchal_ofs_ + 576
283 .endif
284 .endm // xchal_cp6_load
285
286#define XCHAL_CP6_NUM_ATMPS 1
287#define XCHAL_SA_NUM_ATMPS 1
288
289 /* Empty macros for unconfigured coprocessors: */
290 .macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
291 .macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
292 .macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
293 .macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
294 .macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
295 .macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
296 .macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
297 .macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
298 .macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
299 .macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
300 .macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
301 .macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
302
303#endif /*_XTENSA_CORE_TIE_ASM_H*/
304
diff --git a/arch/xtensa/variants/s6000/include/variant/tie.h b/arch/xtensa/variants/s6000/include/variant/tie.h
new file mode 100644
index 000000000000..be7ea843d5df
--- /dev/null
+++ b/arch/xtensa/variants/s6000/include/variant/tie.h
@@ -0,0 +1,191 @@
1/*
2 * This header file describes this specific Xtensa processor's TIE extensions
3 * that extend basic Xtensa core functionality. It is customized to this
4 * Xtensa processor configuration.
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 *
10 * Copyright (C) 1999-2008 Tensilica Inc.
11 */
12
13#ifndef _XTENSA_CORE_TIE_H
14#define _XTENSA_CORE_TIE_H
15
16#define XCHAL_CP_NUM 2 /* number of coprocessors */
17#define XCHAL_CP_MAX 7 /* max CP ID + 1 (0 if none) */
18#define XCHAL_CP_MASK 0x41 /* bitmask of all CPs by ID */
19#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
20
21/* Basic parameters of each coprocessor: */
22#define XCHAL_CP0_NAME "FPU"
23#define XCHAL_CP0_IDENT FPU
24#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
25#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
26#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
27#define XCHAL_CP6_NAME "XAD"
28#define XCHAL_CP6_IDENT XAD
29#define XCHAL_CP6_SA_SIZE 576 /* size of state save area */
30#define XCHAL_CP6_SA_ALIGN 16 /* min alignment of save area */
31#define XCHAL_CP_ID_XAD 6 /* coprocessor ID (0..7) */
32
33/* Filler info for unassigned coprocessors, to simplify arrays etc: */
34#define XCHAL_CP1_SA_SIZE 0
35#define XCHAL_CP1_SA_ALIGN 1
36#define XCHAL_CP2_SA_SIZE 0
37#define XCHAL_CP2_SA_ALIGN 1
38#define XCHAL_CP3_SA_SIZE 0
39#define XCHAL_CP3_SA_ALIGN 1
40#define XCHAL_CP4_SA_SIZE 0
41#define XCHAL_CP4_SA_ALIGN 1
42#define XCHAL_CP5_SA_SIZE 0
43#define XCHAL_CP5_SA_ALIGN 1
44#define XCHAL_CP7_SA_SIZE 0
45#define XCHAL_CP7_SA_ALIGN 1
46
47/* Save area for non-coprocessor optional and custom (TIE) state: */
48#define XCHAL_NCP_SA_SIZE 4
49#define XCHAL_NCP_SA_ALIGN 4
50
51/* Total save area for optional and custom state (NCP + CPn): */
52#define XCHAL_TOTAL_SA_SIZE 672 /* with 16-byte align padding */
53#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
54
55/*
56 * Detailed contents of save areas.
57 * NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
58 * before expanding the XCHAL_xxx_SA_LIST() macros.
59 *
60 * XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
61 * dbnum,base,regnum,bitsz,gapsz,reset,x...)
62 *
63 * s = passed from XCHAL_*_LIST(s), eg. to select how to expand
64 * ccused = set if used by compiler without special options or code
65 * abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
66 * kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
67 * opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
68 * name = lowercase reg name (no quotes)
69 * galign = group byte alignment (power of 2) (galign >= align)
70 * align = register byte alignment (power of 2)
71 * asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
72 * (not including any pad bytes required to galign this or next reg)
73 * dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
74 * base = reg shortname w/o index (or sr=special, ur=TIE user reg)
75 * regnum = reg index in regfile, or special/TIE-user reg number
76 * bitsz = number of significant bits (regfile width, or ur/sr mask bits)
77 * gapsz = intervening bits, if bitsz bits not stored contiguously
78 * (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
79 * reset = register reset value (or 0 if undefined at reset)
80 * x = reserved for future use (0 until then)
81 *
82 * To filter out certain registers, e.g. to expand only the non-global
83 * registers used by the compiler, you can do something like this:
84 *
85 * #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
86 * #define SELCC0(p...)
87 * #define SELCC1(abikind,p...) SELAK##abikind(p)
88 * #define SELAK0(p...) REG(p)
89 * #define SELAK1(p...) REG(p)
90 * #define SELAK2(p...)
91 * #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
92 * ...what you want to expand...
93 */
94
95#define XCHAL_NCP_SA_NUM 1
96#define XCHAL_NCP_SA_LIST(s) \
97 XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0)
98
99#define XCHAL_CP0_SA_NUM 18
100#define XCHAL_CP0_SA_LIST(s) \
101 XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
102 XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
103 XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
104 XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
105 XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
106 XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
107 XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
108 XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
109 XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
110 XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
111 XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
112 XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
113 XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
114 XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
115 XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
116 XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
117 XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
118 XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
119
120#define XCHAL_CP1_SA_NUM 0
121#define XCHAL_CP1_SA_LIST(s) /* empty */
122
123#define XCHAL_CP2_SA_NUM 0
124#define XCHAL_CP2_SA_LIST(s) /* empty */
125
126#define XCHAL_CP3_SA_NUM 0
127#define XCHAL_CP3_SA_LIST(s) /* empty */
128
129#define XCHAL_CP4_SA_NUM 0
130#define XCHAL_CP4_SA_LIST(s) /* empty */
131
132#define XCHAL_CP5_SA_NUM 0
133#define XCHAL_CP5_SA_LIST(s) /* empty */
134
135#define XCHAL_CP6_SA_NUM 46
136#define XCHAL_CP6_SA_LIST(s) \
137 XCHAL_SA_REG(s,0,0,1,0, ldcbhi,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
138 XCHAL_SA_REG(s,0,0,1,0, ldcblo, 4, 4, 4,0x0301, ur,1 , 32,0,0,0) \
139 XCHAL_SA_REG(s,0,0,1,0, stcbhi, 4, 4, 4,0x0302, ur,2 , 32,0,0,0) \
140 XCHAL_SA_REG(s,0,0,1,0, stcblo, 4, 4, 4,0x0303, ur,3 , 32,0,0,0) \
141 XCHAL_SA_REG(s,0,0,1,0, ldbrbase, 4, 4, 4,0x0308, ur,8 , 32,0,0,0) \
142 XCHAL_SA_REG(s,0,0,1,0, ldbroff, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
143 XCHAL_SA_REG(s,0,0,1,0, ldbrinc, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
144 XCHAL_SA_REG(s,0,0,1,0, stbrbase, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
145 XCHAL_SA_REG(s,0,0,1,0, stbroff, 4, 4, 4,0x030C, ur,12 , 32,0,0,0) \
146 XCHAL_SA_REG(s,0,0,1,0, stbrinc, 4, 4, 4,0x030D, ur,13 , 32,0,0,0) \
147 XCHAL_SA_REG(s,0,0,1,0, scratch0, 4, 4, 4,0x0318, ur,24 , 32,0,0,0) \
148 XCHAL_SA_REG(s,0,0,1,0, scratch1, 4, 4, 4,0x0319, ur,25 , 32,0,0,0) \
149 XCHAL_SA_REG(s,0,0,1,0, scratch2, 4, 4, 4,0x031A, ur,26 , 32,0,0,0) \
150 XCHAL_SA_REG(s,0,0,1,0, scratch3, 4, 4, 4,0x031B, ur,27 , 32,0,0,0) \
151 XCHAL_SA_REG(s,0,0,2,0, wra0,16,16,16,0x1010, wra,0 ,128,0,0,0) \
152 XCHAL_SA_REG(s,0,0,2,0, wra1,16,16,16,0x1011, wra,1 ,128,0,0,0) \
153 XCHAL_SA_REG(s,0,0,2,0, wra2,16,16,16,0x1012, wra,2 ,128,0,0,0) \
154 XCHAL_SA_REG(s,0,0,2,0, wra3,16,16,16,0x1013, wra,3 ,128,0,0,0) \
155 XCHAL_SA_REG(s,0,0,2,0, wra4,16,16,16,0x1014, wra,4 ,128,0,0,0) \
156 XCHAL_SA_REG(s,0,0,2,0, wra5,16,16,16,0x1015, wra,5 ,128,0,0,0) \
157 XCHAL_SA_REG(s,0,0,2,0, wra6,16,16,16,0x1016, wra,6 ,128,0,0,0) \
158 XCHAL_SA_REG(s,0,0,2,0, wra7,16,16,16,0x1017, wra,7 ,128,0,0,0) \
159 XCHAL_SA_REG(s,0,0,2,0, wra8,16,16,16,0x1018, wra,8 ,128,0,0,0) \
160 XCHAL_SA_REG(s,0,0,2,0, wra9,16,16,16,0x1019, wra,9 ,128,0,0,0) \
161 XCHAL_SA_REG(s,0,0,2,0, wra10,16,16,16,0x101A, wra,10 ,128,0,0,0) \
162 XCHAL_SA_REG(s,0,0,2,0, wra11,16,16,16,0x101B, wra,11 ,128,0,0,0) \
163 XCHAL_SA_REG(s,0,0,2,0, wra12,16,16,16,0x101C, wra,12 ,128,0,0,0) \
164 XCHAL_SA_REG(s,0,0,2,0, wra13,16,16,16,0x101D, wra,13 ,128,0,0,0) \
165 XCHAL_SA_REG(s,0,0,2,0, wra14,16,16,16,0x101E, wra,14 ,128,0,0,0) \
166 XCHAL_SA_REG(s,0,0,2,0, wra15,16,16,16,0x101F, wra,15 ,128,0,0,0) \
167 XCHAL_SA_REG(s,0,0,2,0, wrb0,16,16,16,0x1020, wrb,0 ,128,0,0,0) \
168 XCHAL_SA_REG(s,0,0,2,0, wrb1,16,16,16,0x1021, wrb,1 ,128,0,0,0) \
169 XCHAL_SA_REG(s,0,0,2,0, wrb2,16,16,16,0x1022, wrb,2 ,128,0,0,0) \
170 XCHAL_SA_REG(s,0,0,2,0, wrb3,16,16,16,0x1023, wrb,3 ,128,0,0,0) \
171 XCHAL_SA_REG(s,0,0,2,0, wrb4,16,16,16,0x1024, wrb,4 ,128,0,0,0) \
172 XCHAL_SA_REG(s,0,0,2,0, wrb5,16,16,16,0x1025, wrb,5 ,128,0,0,0) \
173 XCHAL_SA_REG(s,0,0,2,0, wrb6,16,16,16,0x1026, wrb,6 ,128,0,0,0) \
174 XCHAL_SA_REG(s,0,0,2,0, wrb7,16,16,16,0x1027, wrb,7 ,128,0,0,0) \
175 XCHAL_SA_REG(s,0,0,2,0, wrb8,16,16,16,0x1028, wrb,8 ,128,0,0,0) \
176 XCHAL_SA_REG(s,0,0,2,0, wrb9,16,16,16,0x1029, wrb,9 ,128,0,0,0) \
177 XCHAL_SA_REG(s,0,0,2,0, wrb10,16,16,16,0x102A, wrb,10 ,128,0,0,0) \
178 XCHAL_SA_REG(s,0,0,2,0, wrb11,16,16,16,0x102B, wrb,11 ,128,0,0,0) \
179 XCHAL_SA_REG(s,0,0,2,0, wrb12,16,16,16,0x102C, wrb,12 ,128,0,0,0) \
180 XCHAL_SA_REG(s,0,0,2,0, wrb13,16,16,16,0x102D, wrb,13 ,128,0,0,0) \
181 XCHAL_SA_REG(s,0,0,2,0, wrb14,16,16,16,0x102E, wrb,14 ,128,0,0,0) \
182 XCHAL_SA_REG(s,0,0,2,0, wrb15,16,16,16,0x102F, wrb,15 ,128,0,0,0)
183
184#define XCHAL_CP7_SA_NUM 0
185#define XCHAL_CP7_SA_LIST(s) /* empty */
186
187/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
188#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
189
190#endif /*_XTENSA_CORE_TIE_H*/
191
diff --git a/arch/xtensa/variants/s6000/irq.c b/arch/xtensa/variants/s6000/irq.c
new file mode 100644
index 000000000000..6651e3285fcf
--- /dev/null
+++ b/arch/xtensa/variants/s6000/irq.c
@@ -0,0 +1,74 @@
1/*
2 * s6000 irq crossbar
3 *
4 * Copyright (c) 2009 emlix GmbH
5 * Authors: Johannes Weiner <jw@emlix.com>
6 * Oskar Schirmer <os@emlix.com>
7 */
8#include <linux/io.h>
9#include <asm/irq.h>
10#include <variant/hardware.h>
11
12/* S6_REG_INTC */
13#define INTC_STATUS 0x000
14#define INTC_RAW 0x010
15#define INTC_STATUS_AG 0x100
16#define INTC_CFG(n) (0x200 + 4 * (n))
17
18/*
19 * The s6000 has a crossbar that multiplexes interrupt output lines
20 * from the peripherals to input lines on the xtensa core.
21 *
22 * We leave the mapping decisions to the platform as it depends on the
23 * actually connected peripherals which distribution makes sense.
24 */
25extern const signed char *platform_irq_mappings[NR_IRQS];
26
27static unsigned long scp_to_intc_enable[] = {
28#define TO_INTC_ENABLE(n) (((n) << 1) + 1)
29 TO_INTC_ENABLE(0),
30 TO_INTC_ENABLE(1),
31 TO_INTC_ENABLE(2),
32 TO_INTC_ENABLE(3),
33 TO_INTC_ENABLE(4),
34 TO_INTC_ENABLE(5),
35 TO_INTC_ENABLE(6),
36 TO_INTC_ENABLE(7),
37 TO_INTC_ENABLE(8),
38 TO_INTC_ENABLE(9),
39 TO_INTC_ENABLE(10),
40 TO_INTC_ENABLE(11),
41 TO_INTC_ENABLE(12),
42 -1,
43 -1,
44 TO_INTC_ENABLE(13),
45 -1,
46 TO_INTC_ENABLE(14),
47 -1,
48 TO_INTC_ENABLE(15),
49#undef TO_INTC_ENABLE
50};
51
52static void irq_set(unsigned int irq, int enable)
53{
54 unsigned long en;
55 const signed char *m = platform_irq_mappings[irq];
56
57 if (!m)
58 return;
59 en = enable ? scp_to_intc_enable[irq] : 0;
60 while (*m >= 0) {
61 writel(en, S6_REG_INTC + INTC_CFG(*m));
62 m++;
63 }
64}
65
66void variant_irq_enable(unsigned int irq)
67{
68 irq_set(irq, 1);
69}
70
71void variant_irq_disable(unsigned int irq)
72{
73 irq_set(irq, 0);
74}
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