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authorHarvey Harrison <harvey.harrison@gmail.com>2009-01-07 15:19:31 -0500
committerLinus Torvalds <torvalds@linux-foundation.org>2009-01-07 15:22:04 -0500
commit8903709b054a8dafe4e8c6d9a6444034d7aba36f (patch)
treedac4ab43946fbdc2f0c104a9be5c5685098b9543 /arch/xtensa
parentdaf4b805c1711f730d42a5dfc5a65ee05b3c9ecf (diff)
xtensa: introduce swab.h
Fixes compile breakage as linux/byteorder.h was removed. Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/xtensa')
-rw-r--r--arch/xtensa/include/asm/Kbuild2
-rw-r--r--arch/xtensa/include/asm/byteorder.h72
-rw-r--r--arch/xtensa/include/asm/swab.h70
3 files changed, 75 insertions, 69 deletions
diff --git a/arch/xtensa/include/asm/Kbuild b/arch/xtensa/include/asm/Kbuild
index c68e1680da01..58c02a454130 100644
--- a/arch/xtensa/include/asm/Kbuild
+++ b/arch/xtensa/include/asm/Kbuild
@@ -1 +1,3 @@
1include include/asm-generic/Kbuild.asm 1include include/asm-generic/Kbuild.asm
2
3unifdef-y += swab.h
diff --git a/arch/xtensa/include/asm/byteorder.h b/arch/xtensa/include/asm/byteorder.h
index 07d10ad364d1..329b94591ca4 100644
--- a/arch/xtensa/include/asm/byteorder.h
+++ b/arch/xtensa/include/asm/byteorder.h
@@ -1,80 +1,14 @@
1/*
2 * include/asm-xtensa/byteorder.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_BYTEORDER_H 1#ifndef _XTENSA_BYTEORDER_H
12#define _XTENSA_BYTEORDER_H 2#define _XTENSA_BYTEORDER_H
13 3
14#include <asm/types.h> 4#include <asm/swab.h>
15#include <linux/compiler.h>
16 5
17#ifdef __XTENSA_EL__ 6#ifdef __XTENSA_EL__
18# define __LITTLE_ENDIAN 7#include <linux/byteorder/little_endian.h>
19#elif defined(__XTENSA_EB__) 8#elif defined(__XTENSA_EB__)
20# define __BIG_ENDIAN 9#include <linux/byteorder/big_endian.h>
21#else 10#else
22# error processor byte order undefined! 11# error processor byte order undefined!
23#endif 12#endif
24 13
25#define __SWAB_64_THRU_32__
26
27static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
28{
29 __u32 res;
30 /* instruction sequence from Xtensa ISA release 2/2000 */
31 __asm__("ssai 8 \n\t"
32 "srli %0, %1, 16 \n\t"
33 "src %0, %0, %1 \n\t"
34 "src %0, %0, %0 \n\t"
35 "src %0, %1, %0 \n"
36 : "=&a" (res)
37 : "a" (x)
38 );
39 return res;
40}
41#define __arch_swab32 __arch_swab32
42
43static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
44{
45 /* Given that 'short' values are signed (i.e., can be negative),
46 * we cannot assume that the upper 16-bits of the register are
47 * zero. We are careful to mask values after shifting.
48 */
49
50 /* There exists an anomaly between xt-gcc and xt-xcc. xt-gcc
51 * inserts an extui instruction after putting this function inline
52 * to ensure that it uses only the least-significant 16 bits of
53 * the result. xt-xcc doesn't use an extui, but assumes the
54 * __asm__ macro follows convention that the upper 16 bits of an
55 * 'unsigned short' result are still zero. This macro doesn't
56 * follow convention; indeed, it leaves garbage in the upport 16
57 * bits of the register.
58
59 * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
60 * types while the return type of the function is a 16-bit type
61 * forces both compilers to insert exactly one extui instruction
62 * (or equivalent) to mask off the upper 16 bits. */
63
64 __u32 res;
65 __u32 tmp;
66
67 __asm__("extui %1, %2, 8, 8\n\t"
68 "slli %0, %2, 8 \n\t"
69 "or %0, %0, %1 \n"
70 : "=&a" (res), "=&a" (tmp)
71 : "a" (x)
72 );
73
74 return res;
75}
76#define __arch_swab16 __arch_swab16
77
78#include <linux/byteorder.h>
79
80#endif /* _XTENSA_BYTEORDER_H */ 14#endif /* _XTENSA_BYTEORDER_H */
diff --git a/arch/xtensa/include/asm/swab.h b/arch/xtensa/include/asm/swab.h
new file mode 100644
index 000000000000..f50b697eb601
--- /dev/null
+++ b/arch/xtensa/include/asm/swab.h
@@ -0,0 +1,70 @@
1/*
2 * include/asm-xtensa/swab.h
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 2001 - 2005 Tensilica Inc.
9 */
10
11#ifndef _XTENSA_SWAB_H
12#define _XTENSA_SWAB_H
13
14#include <asm/types.h>
15#include <linux/compiler.h>
16
17#define __SWAB_64_THRU_32__
18
19static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
20{
21 __u32 res;
22 /* instruction sequence from Xtensa ISA release 2/2000 */
23 __asm__("ssai 8 \n\t"
24 "srli %0, %1, 16 \n\t"
25 "src %0, %0, %1 \n\t"
26 "src %0, %0, %0 \n\t"
27 "src %0, %1, %0 \n"
28 : "=&a" (res)
29 : "a" (x)
30 );
31 return res;
32}
33#define __arch_swab32 __arch_swab32
34
35static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
36{
37 /* Given that 'short' values are signed (i.e., can be negative),
38 * we cannot assume that the upper 16-bits of the register are
39 * zero. We are careful to mask values after shifting.
40 */
41
42 /* There exists an anomaly between xt-gcc and xt-xcc. xt-gcc
43 * inserts an extui instruction after putting this function inline
44 * to ensure that it uses only the least-significant 16 bits of
45 * the result. xt-xcc doesn't use an extui, but assumes the
46 * __asm__ macro follows convention that the upper 16 bits of an
47 * 'unsigned short' result are still zero. This macro doesn't
48 * follow convention; indeed, it leaves garbage in the upport 16
49 * bits of the register.
50
51 * Declaring the temporary variables 'res' and 'tmp' to be 32-bit
52 * types while the return type of the function is a 16-bit type
53 * forces both compilers to insert exactly one extui instruction
54 * (or equivalent) to mask off the upper 16 bits. */
55
56 __u32 res;
57 __u32 tmp;
58
59 __asm__("extui %1, %2, 8, 8\n\t"
60 "slli %0, %2, 8 \n\t"
61 "or %0, %0, %1 \n"
62 : "=&a" (res), "=&a" (tmp)
63 : "a" (x)
64 );
65
66 return res;
67}
68#define __arch_swab16 __arch_swab16
69
70#endif /* _XTENSA_SWAB_H */