diff options
author | Chris Zankel <chris@zankel.net> | 2008-02-12 16:17:07 -0500 |
---|---|---|
committer | Chris Zankel <chris@zankel.net> | 2008-02-13 20:41:43 -0500 |
commit | c658eac628aa8df040dfe614556d95e6da3a9ffb (patch) | |
tree | e2211e1d5c894c29e92d4c744f504b38410efe41 /arch/xtensa/kernel/traps.c | |
parent | 71d28e6c285548106f551fde13ca6d589433d843 (diff) |
[XTENSA] Add support for configurable registers and coprocessors
The Xtensa architecture allows to define custom instructions and
registers. Registers that are bound to a coprocessor are only
accessible if the corresponding enable bit is set, which allows
to implement a 'lazy' context switch mechanism. Other registers
needs to be saved and restore at the time of the context switch
or during interrupt handling.
This patch adds support for these additional states:
- save and restore registers that are used by the compiler upon
interrupt entry and exit.
- context switch additional registers unbound to any coprocessor
- 'lazy' context switch of registers bound to a coprocessor
- ptrace interface to provide access to additional registers
- update configuration files in include/asm-xtensa/variant-fsf
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/kernel/traps.c')
-rw-r--r-- | arch/xtensa/kernel/traps.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/arch/xtensa/kernel/traps.c b/arch/xtensa/kernel/traps.c index 6f722f91ba92..c7a021d9f696 100644 --- a/arch/xtensa/kernel/traps.c +++ b/arch/xtensa/kernel/traps.c | |||
@@ -118,28 +118,28 @@ static dispatch_init_table_t __initdata dispatch_init_table[] = { | |||
118 | { EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault }, | 118 | { EXCCAUSE_STORE_CACHE_ATTRIBUTE, 0, do_page_fault }, |
119 | { EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault }, | 119 | { EXCCAUSE_LOAD_CACHE_ATTRIBUTE, 0, do_page_fault }, |
120 | /* XCCHAL_EXCCAUSE_FLOATING_POINT unhandled */ | 120 | /* XCCHAL_EXCCAUSE_FLOATING_POINT unhandled */ |
121 | #if (XCHAL_CP_MASK & 1) | 121 | #if XTENSA_HAVE_COPROCESSOR(0) |
122 | COPROCESSOR(0), | 122 | COPROCESSOR(0), |
123 | #endif | 123 | #endif |
124 | #if (XCHAL_CP_MASK & 2) | 124 | #if XTENSA_HAVE_COPROCESSOR(1) |
125 | COPROCESSOR(1), | 125 | COPROCESSOR(1), |
126 | #endif | 126 | #endif |
127 | #if (XCHAL_CP_MASK & 4) | 127 | #if XTENSA_HAVE_COPROCESSOR(2) |
128 | COPROCESSOR(2), | 128 | COPROCESSOR(2), |
129 | #endif | 129 | #endif |
130 | #if (XCHAL_CP_MASK & 8) | 130 | #if XTENSA_HAVE_COPROCESSOR(3) |
131 | COPROCESSOR(3), | 131 | COPROCESSOR(3), |
132 | #endif | 132 | #endif |
133 | #if (XCHAL_CP_MASK & 16) | 133 | #if XTENSA_HAVE_COPROCESSOR(4) |
134 | COPROCESSOR(4), | 134 | COPROCESSOR(4), |
135 | #endif | 135 | #endif |
136 | #if (XCHAL_CP_MASK & 32) | 136 | #if XTENSA_HAVE_COPROCESSOR(5) |
137 | COPROCESSOR(5), | 137 | COPROCESSOR(5), |
138 | #endif | 138 | #endif |
139 | #if (XCHAL_CP_MASK & 64) | 139 | #if XTENSA_HAVE_COPROCESSOR(6) |
140 | COPROCESSOR(6), | 140 | COPROCESSOR(6), |
141 | #endif | 141 | #endif |
142 | #if (XCHAL_CP_MASK & 128) | 142 | #if XTENSA_HAVE_COPROCESSOR(7) |
143 | COPROCESSOR(7), | 143 | COPROCESSOR(7), |
144 | #endif | 144 | #endif |
145 | { EXCCAUSE_MAPPED_DEBUG, 0, do_debug }, | 145 | { EXCCAUSE_MAPPED_DEBUG, 0, do_debug }, |