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authorMax Filippov <jcmvbkbc@gmail.com>2013-12-01 03:59:49 -0500
committerChris Zankel <chris@zankel.net>2014-01-14 13:19:56 -0500
commitcbd1de2e8e46207cead11034f92ea8a018b11189 (patch)
treeaba9a9486122ed6bf3a849365424742645ad5766 /arch/xtensa/kernel/irq.c
parentc8f3a7dc0102fc9f89cc373c6dd7beb49916a695 (diff)
xtensa: move built-in PIC to drivers/irqchip
Extract xtensa built-in interrupt controller implementation from xtensa/kernel/irq.c and move it to other irqchips, providing way to instantiate it from the device tree. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/kernel/irq.c')
-rw-r--r--arch/xtensa/kernel/irq.c137
1 files changed, 30 insertions, 107 deletions
diff --git a/arch/xtensa/kernel/irq.c b/arch/xtensa/kernel/irq.c
index 6f4f9749cff7..ada1e4893dd6 100644
--- a/arch/xtensa/kernel/irq.c
+++ b/arch/xtensa/kernel/irq.c
@@ -18,28 +18,20 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/irq.h> 19#include <linux/irq.h>
20#include <linux/kernel_stat.h> 20#include <linux/kernel_stat.h>
21#include <linux/irqchip.h>
22#include <linux/irqchip/xtensa-pic.h>
21#include <linux/irqdomain.h> 23#include <linux/irqdomain.h>
22#include <linux/of.h> 24#include <linux/of.h>
23 25
24#include <asm/uaccess.h> 26#include <asm/uaccess.h>
25#include <asm/platform.h> 27#include <asm/platform.h>
26 28
27static unsigned int cached_irq_mask;
28
29atomic_t irq_err_count; 29atomic_t irq_err_count;
30 30
31static struct irq_domain *root_domain;
32
33/*
34 * do_IRQ handles all normal device IRQ's (the special
35 * SMP cross-CPU interrupts have their own specific
36 * handlers).
37 */
38
39asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs) 31asmlinkage void do_IRQ(int hwirq, struct pt_regs *regs)
40{ 32{
41 struct pt_regs *old_regs = set_irq_regs(regs); 33 struct pt_regs *old_regs = set_irq_regs(regs);
42 int irq = irq_find_mapping(root_domain, hwirq); 34 int irq = irq_find_mapping(NULL, hwirq);
43 35
44 if (hwirq >= NR_IRQS) { 36 if (hwirq >= NR_IRQS) {
45 printk(KERN_EMERG "%s: cannot handle IRQ %d\n", 37 printk(KERN_EMERG "%s: cannot handle IRQ %d\n",
@@ -74,83 +66,57 @@ int arch_show_interrupts(struct seq_file *p, int prec)
74 return 0; 66 return 0;
75} 67}
76 68
77static void xtensa_irq_mask(struct irq_data *d) 69int xtensa_irq_domain_xlate(const u32 *intspec, unsigned int intsize,
78{ 70 unsigned long int_irq, unsigned long ext_irq,
79 cached_irq_mask &= ~(1 << d->hwirq); 71 unsigned long *out_hwirq, unsigned int *out_type)
80 set_sr (cached_irq_mask, intenable);
81}
82
83static void xtensa_irq_unmask(struct irq_data *d)
84{
85 cached_irq_mask |= 1 << d->hwirq;
86 set_sr (cached_irq_mask, intenable);
87}
88
89static void xtensa_irq_enable(struct irq_data *d)
90{
91 variant_irq_enable(d->hwirq);
92 xtensa_irq_unmask(d);
93}
94
95static void xtensa_irq_disable(struct irq_data *d)
96{
97 xtensa_irq_mask(d);
98 variant_irq_disable(d->hwirq);
99}
100
101static void xtensa_irq_ack(struct irq_data *d)
102{
103 set_sr(1 << d->hwirq, intclear);
104}
105
106static int xtensa_irq_retrigger(struct irq_data *d)
107{ 72{
108 set_sr(1 << d->hwirq, intset); 73 if (WARN_ON(intsize < 1 || intsize > 2))
109 return 1; 74 return -EINVAL;
75 if (intsize == 2 && intspec[1] == 1) {
76 int_irq = xtensa_map_ext_irq(ext_irq);
77 if (int_irq < XCHAL_NUM_INTERRUPTS)
78 *out_hwirq = int_irq;
79 else
80 return -EINVAL;
81 } else {
82 *out_hwirq = int_irq;
83 }
84 *out_type = IRQ_TYPE_NONE;
85 return 0;
110} 86}
111 87
112static struct irq_chip xtensa_irq_chip = { 88int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
113 .name = "xtensa",
114 .irq_enable = xtensa_irq_enable,
115 .irq_disable = xtensa_irq_disable,
116 .irq_mask = xtensa_irq_mask,
117 .irq_unmask = xtensa_irq_unmask,
118 .irq_ack = xtensa_irq_ack,
119 .irq_retrigger = xtensa_irq_retrigger,
120};
121
122static int xtensa_irq_map(struct irq_domain *d, unsigned int irq,
123 irq_hw_number_t hw) 89 irq_hw_number_t hw)
124{ 90{
91 struct irq_chip *irq_chip = d->host_data;
125 u32 mask = 1 << hw; 92 u32 mask = 1 << hw;
126 93
127 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) { 94 if (mask & XCHAL_INTTYPE_MASK_SOFTWARE) {
128 irq_set_chip_and_handler_name(irq, &xtensa_irq_chip, 95 irq_set_chip_and_handler_name(irq, irq_chip,
129 handle_simple_irq, "level"); 96 handle_simple_irq, "level");
130 irq_set_status_flags(irq, IRQ_LEVEL); 97 irq_set_status_flags(irq, IRQ_LEVEL);
131 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) { 98 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_EDGE) {
132 irq_set_chip_and_handler_name(irq, &xtensa_irq_chip, 99 irq_set_chip_and_handler_name(irq, irq_chip,
133 handle_edge_irq, "edge"); 100 handle_edge_irq, "edge");
134 irq_clear_status_flags(irq, IRQ_LEVEL); 101 irq_clear_status_flags(irq, IRQ_LEVEL);
135 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) { 102 } else if (mask & XCHAL_INTTYPE_MASK_EXTERN_LEVEL) {
136 irq_set_chip_and_handler_name(irq, &xtensa_irq_chip, 103 irq_set_chip_and_handler_name(irq, irq_chip,
137 handle_level_irq, "level"); 104 handle_level_irq, "level");
138 irq_set_status_flags(irq, IRQ_LEVEL); 105 irq_set_status_flags(irq, IRQ_LEVEL);
139 } else if (mask & XCHAL_INTTYPE_MASK_TIMER) { 106 } else if (mask & XCHAL_INTTYPE_MASK_TIMER) {
140 irq_set_chip_and_handler_name(irq, &xtensa_irq_chip, 107 irq_set_chip_and_handler_name(irq, irq_chip,
141 handle_edge_irq, "edge"); 108 handle_percpu_irq, "timer");
142 irq_clear_status_flags(irq, IRQ_LEVEL); 109 irq_clear_status_flags(irq, IRQ_LEVEL);
143 } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */ 110 } else {/* XCHAL_INTTYPE_MASK_WRITE_ERROR */
144 /* XCHAL_INTTYPE_MASK_NMI */ 111 /* XCHAL_INTTYPE_MASK_NMI */
145 112 irq_set_chip_and_handler_name(irq, irq_chip,
146 irq_set_chip_and_handler_name(irq, &xtensa_irq_chip,
147 handle_level_irq, "level"); 113 handle_level_irq, "level");
148 irq_set_status_flags(irq, IRQ_LEVEL); 114 irq_set_status_flags(irq, IRQ_LEVEL);
149 } 115 }
150 return 0; 116 return 0;
151} 117}
152 118
153static unsigned map_ext_irq(unsigned ext_irq) 119unsigned xtensa_map_ext_irq(unsigned ext_irq)
154{ 120{
155 unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE | 121 unsigned mask = XCHAL_INTTYPE_MASK_EXTERN_EDGE |
156 XCHAL_INTTYPE_MASK_EXTERN_LEVEL; 122 XCHAL_INTTYPE_MASK_EXTERN_LEVEL;
@@ -163,55 +129,12 @@ static unsigned map_ext_irq(unsigned ext_irq)
163 return XCHAL_NUM_INTERRUPTS; 129 return XCHAL_NUM_INTERRUPTS;
164} 130}
165 131
166/*
167 * Device Tree IRQ specifier translation function which works with one or
168 * two cell bindings. First cell value maps directly to the hwirq number.
169 * Second cell if present specifies whether hwirq number is external (1) or
170 * internal (0).
171 */
172int xtensa_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr,
173 const u32 *intspec, unsigned int intsize,
174 unsigned long *out_hwirq, unsigned int *out_type)
175{
176 if (WARN_ON(intsize < 1 || intsize > 2))
177 return -EINVAL;
178 if (intsize == 2 && intspec[1] == 1) {
179 unsigned int_irq = map_ext_irq(intspec[0]);
180 if (int_irq < XCHAL_NUM_INTERRUPTS)
181 *out_hwirq = int_irq;
182 else
183 return -EINVAL;
184 } else {
185 *out_hwirq = intspec[0];
186 }
187 *out_type = IRQ_TYPE_NONE;
188 return 0;
189}
190
191static const struct irq_domain_ops xtensa_irq_domain_ops = {
192 .xlate = xtensa_irq_domain_xlate,
193 .map = xtensa_irq_map,
194};
195
196void __init init_IRQ(void) 132void __init init_IRQ(void)
197{ 133{
198 struct device_node *intc = NULL;
199
200 cached_irq_mask = 0;
201 set_sr(~0, intclear);
202
203#ifdef CONFIG_OF 134#ifdef CONFIG_OF
204 /* The interrupt controller device node is mandatory */ 135 irqchip_init();
205 intc = of_find_compatible_node(NULL, NULL, "xtensa,pic");
206 BUG_ON(!intc);
207
208 root_domain = irq_domain_add_linear(intc, NR_IRQS,
209 &xtensa_irq_domain_ops, NULL);
210#else 136#else
211 root_domain = irq_domain_add_legacy(intc, NR_IRQS, 0, 0, 137 xtensa_pic_init_legacy(NULL);
212 &xtensa_irq_domain_ops, NULL);
213#endif 138#endif
214 irq_set_default_host(root_domain);
215
216 variant_init_irq(); 139 variant_init_irq();
217} 140}