diff options
author | Max Filippov <jcmvbkbc@gmail.com> | 2012-10-14 19:55:38 -0400 |
---|---|---|
committer | Chris Zankel <chris@zankel.net> | 2012-10-16 00:48:08 -0400 |
commit | bc5378fcba974317f9657c4fdc78af227e1e1068 (patch) | |
tree | 998b8f8badf1d7a5dc0fd796f3e8501f8c5394ae /arch/xtensa/kernel/head.S | |
parent | f4349b6e01c8927a04795885702a173b6a60573c (diff) |
xtensa: reorganize SR referencing
- reference SRs by names where possible, not by numbers;
- get rid of __stringify around SR names where possible;
- remove unneeded SR names from asm/regs.h;
- add SREG_ prefix to remaining SR names;
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/kernel/head.S')
-rw-r--r-- | arch/xtensa/kernel/head.S | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/xtensa/kernel/head.S b/arch/xtensa/kernel/head.S index 3ef91a73652d..bdc50788f35e 100644 --- a/arch/xtensa/kernel/head.S +++ b/arch/xtensa/kernel/head.S | |||
@@ -61,18 +61,18 @@ _startup: | |||
61 | /* Disable interrupts and exceptions. */ | 61 | /* Disable interrupts and exceptions. */ |
62 | 62 | ||
63 | movi a0, LOCKLEVEL | 63 | movi a0, LOCKLEVEL |
64 | wsr a0, PS | 64 | wsr a0, ps |
65 | 65 | ||
66 | /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */ | 66 | /* Preserve the pointer to the boot parameter list in EXCSAVE_1 */ |
67 | 67 | ||
68 | wsr a2, EXCSAVE_1 | 68 | wsr a2, excsave1 |
69 | 69 | ||
70 | /* Start with a fresh windowbase and windowstart. */ | 70 | /* Start with a fresh windowbase and windowstart. */ |
71 | 71 | ||
72 | movi a1, 1 | 72 | movi a1, 1 |
73 | movi a0, 0 | 73 | movi a0, 0 |
74 | wsr a1, WINDOWSTART | 74 | wsr a1, windowstart |
75 | wsr a0, WINDOWBASE | 75 | wsr a0, windowbase |
76 | rsync | 76 | rsync |
77 | 77 | ||
78 | /* Set a0 to 0 for the remaining initialization. */ | 78 | /* Set a0 to 0 for the remaining initialization. */ |
@@ -82,46 +82,46 @@ _startup: | |||
82 | /* Clear debugging registers. */ | 82 | /* Clear debugging registers. */ |
83 | 83 | ||
84 | #if XCHAL_HAVE_DEBUG | 84 | #if XCHAL_HAVE_DEBUG |
85 | wsr a0, IBREAKENABLE | 85 | wsr a0, ibreakenable |
86 | wsr a0, ICOUNT | 86 | wsr a0, icount |
87 | movi a1, 15 | 87 | movi a1, 15 |
88 | wsr a0, ICOUNTLEVEL | 88 | wsr a0, icountlevel |
89 | 89 | ||
90 | .set _index, 0 | 90 | .set _index, 0 |
91 | .rept XCHAL_NUM_DBREAK - 1 | 91 | .rept XCHAL_NUM_DBREAK - 1 |
92 | wsr a0, DBREAKC + _index | 92 | wsr a0, SREG_DBREAKC + _index |
93 | .set _index, _index + 1 | 93 | .set _index, _index + 1 |
94 | .endr | 94 | .endr |
95 | #endif | 95 | #endif |
96 | 96 | ||
97 | /* Clear CCOUNT (not really necessary, but nice) */ | 97 | /* Clear CCOUNT (not really necessary, but nice) */ |
98 | 98 | ||
99 | wsr a0, CCOUNT # not really necessary, but nice | 99 | wsr a0, ccount # not really necessary, but nice |
100 | 100 | ||
101 | /* Disable zero-loops. */ | 101 | /* Disable zero-loops. */ |
102 | 102 | ||
103 | #if XCHAL_HAVE_LOOPS | 103 | #if XCHAL_HAVE_LOOPS |
104 | wsr a0, LCOUNT | 104 | wsr a0, lcount |
105 | #endif | 105 | #endif |
106 | 106 | ||
107 | /* Disable all timers. */ | 107 | /* Disable all timers. */ |
108 | 108 | ||
109 | .set _index, 0 | 109 | .set _index, 0 |
110 | .rept XCHAL_NUM_TIMERS - 1 | 110 | .rept XCHAL_NUM_TIMERS - 1 |
111 | wsr a0, CCOMPARE + _index | 111 | wsr a0, SREG_CCOMPARE + _index |
112 | .set _index, _index + 1 | 112 | .set _index, _index + 1 |
113 | .endr | 113 | .endr |
114 | 114 | ||
115 | /* Interrupt initialization. */ | 115 | /* Interrupt initialization. */ |
116 | 116 | ||
117 | movi a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE | 117 | movi a2, XCHAL_INTTYPE_MASK_SOFTWARE | XCHAL_INTTYPE_MASK_EXTERN_EDGE |
118 | wsr a0, INTENABLE | 118 | wsr a0, intenable |
119 | wsr a2, INTCLEAR | 119 | wsr a2, intclear |
120 | 120 | ||
121 | /* Disable coprocessors. */ | 121 | /* Disable coprocessors. */ |
122 | 122 | ||
123 | #if XCHAL_CP_NUM > 0 | 123 | #if XCHAL_CP_NUM > 0 |
124 | wsr a0, CPENABLE | 124 | wsr a0, cpenable |
125 | #endif | 125 | #endif |
126 | 126 | ||
127 | /* Set PS.INTLEVEL=1, PS.WOE=0, kernel stack, PS.EXCM=0 | 127 | /* Set PS.INTLEVEL=1, PS.WOE=0, kernel stack, PS.EXCM=0 |
@@ -132,7 +132,7 @@ _startup: | |||
132 | */ | 132 | */ |
133 | 133 | ||
134 | movi a1, 1 | 134 | movi a1, 1 |
135 | wsr a1, PS | 135 | wsr a1, ps |
136 | rsync | 136 | rsync |
137 | 137 | ||
138 | /* Initialize the caches. | 138 | /* Initialize the caches. |
@@ -206,18 +206,18 @@ _startup: | |||
206 | addi a1, a1, KERNEL_STACK_SIZE | 206 | addi a1, a1, KERNEL_STACK_SIZE |
207 | 207 | ||
208 | movi a2, 0x00040001 # WOE=1, INTLEVEL=1, UM=0 | 208 | movi a2, 0x00040001 # WOE=1, INTLEVEL=1, UM=0 |
209 | wsr a2, PS # (enable reg-windows; progmode stack) | 209 | wsr a2, ps # (enable reg-windows; progmode stack) |
210 | rsync | 210 | rsync |
211 | 211 | ||
212 | /* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/ | 212 | /* Set up EXCSAVE[DEBUGLEVEL] to point to the Debug Exception Handler.*/ |
213 | 213 | ||
214 | movi a2, debug_exception | 214 | movi a2, debug_exception |
215 | wsr a2, EXCSAVE + XCHAL_DEBUGLEVEL | 215 | wsr a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL |
216 | 216 | ||
217 | /* Set up EXCSAVE[1] to point to the exc_table. */ | 217 | /* Set up EXCSAVE[1] to point to the exc_table. */ |
218 | 218 | ||
219 | movi a6, exc_table | 219 | movi a6, exc_table |
220 | xsr a6, EXCSAVE_1 | 220 | xsr a6, excsave1 |
221 | 221 | ||
222 | /* init_arch kick-starts the linux kernel */ | 222 | /* init_arch kick-starts the linux kernel */ |
223 | 223 | ||