xtensa: disable IRQs while IRQ handler is running

IRQ handlers are expected to run with IRQs disabled.
See e.g. http://lwn.net/Articles/380931/ for a longer story.

This was overlooked in the commit
  2d1c645 xtensa: dispatch medium-priority interrupts
Revert to old behavior and simplify interrupt entry and exit code.
Interrupt handler still honours IRQ priority.

do_notify_resume/schedule must be called with interrupts enabled, enable
interrupts if we return from user exception.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>

1 files changed, 11 insertions, 41 deletions

diff --git a/arch/xtensa/kernel/entry.S b/arch/xtensa/kernel/entry.S
index 3729b48d798d..5082507d5631 100644
--- a/arch/xtensa/kernel/entry.S
+++ b/arch/xtensa/kernel/entry.S
@@ -354,16 +354,16 @@ common_exception:
          * so we can allow exceptions and interrupts (*) again.
          * Set PS(EXCM = 0, UM = 0, RING = 0, OWB = 0, WOE = 1, INTLEVEL = X)
          *
-         * (*) We only allow interrupts of higher priority than current IRQ
+         * (*) We only allow interrupts if they were previously enabled and
+         *     we're not handling an IRQ
          */
 
         rsr     a3, ps
-        addi    a0, a0, -4
-        movi    a2, 1
+        addi    a0, a0, -EXCCAUSE_LEVEL1_INTERRUPT
+        movi    a2, LOCKLEVEL
         extui   a3, a3, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
                                         # a3 = PS.INTLEVEL
-        movnez  a2, a3, a3              # a2 = 1: level-1, > 1: high priority
-        moveqz  a3, a2, a0              # a3 = IRQ level iff interrupt
+        moveqz  a3, a2, a0              # a3 = LOCKLEVEL iff interrupt
         movi    a2, 1 << PS_WOE_BIT
         or      a3, a3, a2
         rsr     a0, exccause
@@ -444,6 +444,8 @@ common_exception_return:
 1:      l32i    a3, a1, PT_PS
         _bbci.l a3, PS_UM_BIT, 4f
 
+        rsil    a2, 0
+
         /* Specific to a user exception exit:
          * We need to check some flags for signal handling and rescheduling,
          * and have to restore WB and WS, extra states, and all registers
@@ -684,51 +686,19 @@ common_exception_exit:
 
         l32i    a0, a1, PT_DEPC
         l32i    a3, a1, PT_AREG3
-        _bltui  a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
-
-        wsr     a0, depc
         l32i    a2, a1, PT_AREG2
-        l32i    a0, a1, PT_AREG0
-        l32i    a1, a1, PT_AREG1
-        rfde
+        _bgeui  a0, VALID_DOUBLE_EXCEPTION_ADDRESS, 1f
 
-1:
         /* Restore a0...a3 and return */
 
-        rsr     a0, ps
-        extui   a2, a0, PS_INTLEVEL_SHIFT, PS_INTLEVEL_WIDTH
-        movi    a0, 2f
-        slli    a2, a2, 4
-        add     a0, a2, a0
-        l32i    a2, a1, PT_AREG2
-        jx      a0
-
-        .macro  irq_exit_level level
-        .align  16
-        .if     XCHAL_EXCM_LEVEL >= \level
-        l32i    a0, a1, PT_PC
-        wsr     a0, epc\level
         l32i    a0, a1, PT_AREG0
         l32i    a1, a1, PT_AREG1
-        rfi     \level
-        .endif
-        .endm
+        rfe
 
-        .align  16
-2:
+1:      wsr     a0, depc
         l32i    a0, a1, PT_AREG0
         l32i    a1, a1, PT_AREG1
-        rfe
-
-        .align  16
-        /* no rfi for level-1 irq, handled by rfe above*/
-        nop
-
-        irq_exit_level 2
-        irq_exit_level 3
-        irq_exit_level 4
-        irq_exit_level 5
-        irq_exit_level 6
+        rfde
 
 ENDPROC(kernel_exception)