xtensa: add MMU v3 support

MMUv3 comes out of reset with identity vaddr -> paddr mapping in the TLB
way 6:

Way 6 (512 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0x00000000  0x00000000  0x01  0x03 RWX Bypass
        0x20000000  0x20000000  0x01  0x03 RWX Bypass
        0x40000000  0x40000000  0x01  0x03 RWX Bypass
        0x60000000  0x60000000  0x01  0x03 RWX Bypass
        0x80000000  0x80000000  0x01  0x03 RWX Bypass
        0xa0000000  0xa0000000  0x01  0x03 RWX Bypass
        0xc0000000  0xc0000000  0x01  0x03 RWX Bypass
        0xe0000000  0xe0000000  0x01  0x03 RWX Bypass

This patch adds remapping code at the reset vector or at the kernel
_start (depending on CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX) that
reconfigures MMUv3 as MMUv2:

Way 5 (128 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0xd0000000  0x00000000  0x01  0x07 RWX WB
        0xd8000000  0x00000000  0x01  0x03 RWX Bypass
Way 6 (256 MB)
        Vaddr       Paddr       ASID  Attr RWX Cache
        ----------  ----------  ----  ---- --- -------
        0xe0000000  0xf0000000  0x01  0x07 RWX WB
        0xf0000000  0xf0000000  0x01  0x03 RWX Bypass

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Chris Zankel <chris@zankel.net>

2 files changed, 232 insertions, 0 deletions

diff --git a/arch/xtensa/include/asm/initialize_mmu.h b/arch/xtensa/include/asm/initialize_mmu.h
index e1f8ba4061ed..722553f17db3 100644
--- a/arch/xtensa/include/asm/initialize_mmu.h
+++ b/arch/xtensa/include/asm/initialize_mmu.h
@@ -23,6 +23,9 @@
 #ifndef _XTENSA_INITIALIZE_MMU_H
 #define _XTENSA_INITIALIZE_MMU_H
 
+#include <asm/pgtable.h>
+#include <asm/vectors.h>
+
 #ifdef __ASSEMBLY__
 
 #define XTENSA_HWVERSION_RC_2009_0 230000
@@ -48,6 +51,110 @@
          * (XCHAL_HW_MIN_VERSION >= XTENSA_HWVERSION_RC_2009_0)
          */
 
+#if defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
+/*
+ * Have MMU v3
+ */
+
+#if !XCHAL_HAVE_VECBASE
+# error "MMU v3 requires reloc vectors"
+#endif
+
+        movi    a1, 0
+        _call0  1f
+        _j      2f
+
+        .align  4
+1:      movi    a2, 0x10000000
+        movi    a3, 0x18000000
+        add     a2, a2, a0
+9:      bgeu    a2, a3, 9b      /* PC is out of the expected range */
+
+        /* Step 1: invalidate mapping at 0x40000000..0x5FFFFFFF. */
+
+        movi    a2, 0x40000006
+        idtlb   a2
+        iitlb   a2
+        isync
+
+        /* Step 2: map 0x40000000..0x47FFFFFF to paddr containing this code
+         * and jump to the new mapping.
+         */
+#define CA_BYPASS       (_PAGE_CA_BYPASS | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
+#define CA_WRITEBACK    (_PAGE_CA_WB     | _PAGE_HW_WRITE | _PAGE_HW_EXEC)
+
+        srli    a3, a0, 27
+        slli    a3, a3, 27
+        addi    a3, a3, CA_BYPASS
+        addi    a7, a2, -1
+        wdtlb   a3, a7
+        witlb   a3, a7
+        isync
+
+        slli    a4, a0, 5
+        srli    a4, a4, 5
+        addi    a5, a2, -6
+        add     a4, a4, a5
+        jx      a4
+
+        /* Step 3: unmap everything other than current area.
+         *         Start at 0x60000000, wrap around, and end with 0x20000000
+         */
+2:      movi    a4, 0x20000000
+        add     a5, a2, a4
+3:      idtlb   a5
+        iitlb   a5
+        add     a5, a5, a4
+        bne     a5, a2, 3b
+
+        /* Step 4: Setup MMU with the old V2 mappings. */
+        movi    a6, 0x01000000
+        wsr     a6, ITLBCFG
+        wsr     a6, DTLBCFG
+        isync
+
+        movi    a5, 0xd0000005
+        movi    a4, CA_WRITEBACK
+        wdtlb   a4, a5
+        witlb   a4, a5
+
+        movi    a5, 0xd8000005
+        movi    a4, CA_BYPASS
+        wdtlb   a4, a5
+        witlb   a4, a5
+
+        movi    a5, 0xe0000006
+        movi    a4, 0xf0000000 + CA_WRITEBACK
+        wdtlb   a4, a5
+        witlb   a4, a5
+
+        movi    a5, 0xf0000006
+        movi    a4, 0xf0000000 + CA_BYPASS
+        wdtlb   a4, a5
+        witlb   a4, a5
+
+        isync
+
+        /* Jump to self, using MMU v2 mappings. */
+        movi    a4, 1f
+        jx      a4
+
+1:
+        movi    a2, VECBASE_RESET_VADDR
+        wsr     a2, vecbase
+
+        /* Step 5: remove temporary mapping. */
+        idtlb   a7
+        iitlb   a7
+        isync
+
+        movi    a0, 0
+        wsr     a0, ptevaddr
+        rsync
+
+#endif /* defined(CONFIG_MMU) && XCHAL_HAVE_PTP_MMU &&
+          XCHAL_HAVE_SPANNING_WAY */
+
         .endm
 
 #endif /*__ASSEMBLY__*/
diff --git a/arch/xtensa/include/asm/vectors.h b/arch/xtensa/include/asm/vectors.h
new file mode 100644
index 000000000000..c52b656d0310
--- /dev/null
+++ b/arch/xtensa/include/asm/vectors.h
@@ -0,0 +1,125 @@
+/*
+ * arch/xtensa/include/asm/xchal_vaddr_remap.h
+ *
+ * Xtensa macros for MMU V3 Support. Deals with re-mapping the Virtual
+ * Memory Addresses from "Virtual == Physical" to their prevvious V2 MMU
+ * mappings (KSEG at 0xD0000000 and KIO at 0XF0000000).
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2008 - 2012 Tensilica Inc.
+ *
+ * Pete Delaney <piet@tensilica.com>
+ * Marc Gauthier <marc@tensilica.com
+ */
+
+#ifndef _XTENSA_VECTORS_H
+#define _XTENSA_VECTORS_H
+
+#include <variant/core.h>
+
+#if defined(CONFIG_MMU)
+
+/* Will Become VECBASE */
+#define VIRTUAL_MEMORY_ADDRESS          0xD0000000
+
+/* Image Virtual Start Address */
+#define KERNELOFFSET                    0xD0003000
+
+#if defined(XCHAL_HAVE_PTP_MMU) && XCHAL_HAVE_PTP_MMU && XCHAL_HAVE_SPANNING_WAY
+  /* MMU v3  - XCHAL_HAVE_PTP_MMU  == 1 */
+  #define PHYSICAL_MEMORY_ADDRESS       0x00000000
+  #define LOAD_MEMORY_ADDRESS           0x00003000
+#else
+  /* MMU V2 -  XCHAL_HAVE_PTP_MMU  == 0 */
+  #define PHYSICAL_MEMORY_ADDRESS       0xD0000000
+  #define LOAD_MEMORY_ADDRESS           0xD0003000
+#endif
+
+#else /* !defined(CONFIG_MMU) */
+  /* MMU Not being used - Virtual == Physical */
+
+  /* VECBASE */
+  #define VIRTUAL_MEMORY_ADDRESS        0x00002000
+
+  /* Location of the start of the kernel text, _start */
+  #define KERNELOFFSET                  0x00003000
+  #define PHYSICAL_MEMORY_ADDRESS       0x00000000
+
+  /* Loaded just above possibly live vectors */
+  #define LOAD_MEMORY_ADDRESS           0x00003000
+
+#endif /* CONFIG_MMU */
+
+#define XC_VADDR(offset)                (VIRTUAL_MEMORY_ADDRESS  + offset)
+#define XC_PADDR(offset)                (PHYSICAL_MEMORY_ADDRESS + offset)
+
+/* Used to set VECBASE register */
+#define VECBASE_RESET_VADDR             VIRTUAL_MEMORY_ADDRESS
+
+#define RESET_VECTOR_VECOFS             (XCHAL_RESET_VECTOR_VADDR - \
+                                                VECBASE_RESET_VADDR)
+#define RESET_VECTOR_VADDR              XC_VADDR(RESET_VECTOR_VECOFS)
+
+#define RESET_VECTOR1_VECOFS            (XCHAL_RESET_VECTOR1_VADDR - \
+                                                VECBASE_RESET_VADDR)
+#define RESET_VECTOR1_VADDR             XC_VADDR(RESET_VECTOR1_VECOFS)
+
+#if XCHAL_HAVE_VECBASE
+
+#define USER_VECTOR_VADDR               XC_VADDR(XCHAL_USER_VECOFS)
+#define KERNEL_VECTOR_VADDR             XC_VADDR(XCHAL_KERNEL_VECOFS)
+#define DOUBLEEXC_VECTOR_VADDR          XC_VADDR(XCHAL_DOUBLEEXC_VECOFS)
+#define WINDOW_VECTORS_VADDR            XC_VADDR(XCHAL_WINDOW_OF4_VECOFS)
+#define INTLEVEL2_VECTOR_VADDR          XC_VADDR(XCHAL_INTLEVEL2_VECOFS)
+#define INTLEVEL3_VECTOR_VADDR          XC_VADDR(XCHAL_INTLEVEL3_VECOFS)
+#define INTLEVEL4_VECTOR_VADDR          XC_VADDR(XCHAL_INTLEVEL4_VECOFS)
+#define INTLEVEL5_VECTOR_VADDR          XC_VADDR(XCHAL_INTLEVEL5_VECOFS)
+#define INTLEVEL6_VECTOR_VADDR          XC_VADDR(XCHAL_INTLEVEL6_VECOFS)
+
+#define DEBUG_VECTOR_VADDR              XC_VADDR(XCHAL_DEBUG_VECOFS)
+
+#undef  XCHAL_NMI_VECTOR_VADDR
+#define XCHAL_NMI_VECTOR_VADDR          XC_VADDR(XCHAL_NMI_VECOFS)
+
+#undef  XCHAL_INTLEVEL7_VECTOR_VADDR
+#define XCHAL_INTLEVEL7_VECTOR_VADDR    XC_VADDR(XCHAL_INTLEVEL7_VECOFS)
+
+/*
+ * These XCHAL_* #defines from varian/core.h
+ * are not valid to use with V3 MMU. Non-XCHAL
+ * constants are defined above and should be used.
+ */
+#undef  XCHAL_VECBASE_RESET_VADDR
+#undef  XCHAL_RESET_VECTOR0_VADDR
+#undef  XCHAL_USER_VECTOR_VADDR
+#undef  XCHAL_KERNEL_VECTOR_VADDR
+#undef  XCHAL_DOUBLEEXC_VECTOR_VADDR
+#undef  XCHAL_WINDOW_VECTORS_VADDR
+#undef  XCHAL_INTLEVEL2_VECTOR_VADDR
+#undef  XCHAL_INTLEVEL3_VECTOR_VADDR
+#undef  XCHAL_INTLEVEL4_VECTOR_VADDR
+#undef  XCHAL_INTLEVEL5_VECTOR_VADDR
+#undef  XCHAL_INTLEVEL6_VECTOR_VADDR
+#undef  XCHAL_DEBUG_VECTOR_VADDR
+#undef  XCHAL_NMI_VECTOR_VADDR
+#undef  XCHAL_INTLEVEL7_VECTOR_VADDR
+
+#else
+
+#define USER_VECTOR_VADDR               XCHAL_USER_VECTOR_VADDR
+#define KERNEL_VECTOR_VADDR             XCHAL_KERNEL_VECTOR_VADDR
+#define DOUBLEEXC_VECTOR_VADDR          XCHAL_DOUBLEEXC_VECTOR_VADDR
+#define WINDOW_VECTORS_VADDR            XCHAL_WINDOW_VECTORS_VADDR
+#define INTLEVEL2_VECTOR_VADDR          XCHAL_INTLEVEL2_VECTOR_VADDR
+#define INTLEVEL3_VECTOR_VADDR          XCHAL_INTLEVEL3_VECTOR_VADDR
+#define INTLEVEL4_VECTOR_VADDR          XCHAL_INTLEVEL4_VECTOR_VADDR
+#define INTLEVEL5_VECTOR_VADDR          XCHAL_INTLEVEL5_VECTOR_VADDR
+#define INTLEVEL6_VECTOR_VADDR          XCHAL_INTLEVEL6_VECTOR_VADDR
+#define DEBUG_VECTOR_VADDR              XCHAL_DEBUG_VECTOR_VADDR
+
+#endif
+
+#endif /* _XTENSA_VECTORS_H */