diff options
author | Johannes Weiner <jw@emlix.com> | 2009-03-04 10:21:30 -0500 |
---|---|---|
committer | Chris Zankel <chris@zankel.net> | 2009-04-03 02:41:08 -0400 |
commit | c947a585ab13f310c9223284dfd502790abd05f9 (patch) | |
tree | 1295ce0f825139326eb3d894eaddcf8027953e96 /arch/xtensa/include | |
parent | 264da9f708b130122d881fa4570d1cd618440a73 (diff) |
xtensa: cope with ram beginning at higher addresses
The current assumption of the memory code is that the first RAM PFN in
the system is 0.
Adjust the relevant code to play well with setups where memory starts
at higher addresses, indicated by PLATFORM_DEFAULT_MEM_START.
The new memory model looks like this:
+----------+--+----------------------+----------------+
| | | | |
| | | RAM | |
| | | | |
+----------+--+----------------------+----------------+
| | | | |
+- PFN 0 | +- min_low_pfn +- max_low_pfn +- max_pfn
|
+- ARCH_PFN_OFFSET
+- PLATFORM_DEFAULT_MEM_START >> PAGE_SIZE
The memory map contains pages starting from pfn ARCH_PFN_OFFSET up to
max_low_pfn. The only zone used right now will span exactly the same
region.
Usually, ARCH_PFN_OFFSET and min_low_pfn are the same value. Handle
them separately for robustness. Gapping pages will be in the memory
map but marked as reserved and won't be touched.
Signed-off-by: Johannes Weiner <jw@emlix.com>
Signed-off-by: Chris Zankel <chris@zankel.net>
Diffstat (limited to 'arch/xtensa/include')
-rw-r--r-- | arch/xtensa/include/asm/page.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/xtensa/include/asm/page.h b/arch/xtensa/include/asm/page.h index 11f7dc2dbec7..a5a5d33c15d0 100644 --- a/arch/xtensa/include/asm/page.h +++ b/arch/xtensa/include/asm/page.h | |||
@@ -14,6 +14,7 @@ | |||
14 | #include <asm/processor.h> | 14 | #include <asm/processor.h> |
15 | #include <asm/types.h> | 15 | #include <asm/types.h> |
16 | #include <asm/cache.h> | 16 | #include <asm/cache.h> |
17 | #include <platform/hardware.h> | ||
17 | 18 | ||
18 | /* | 19 | /* |
19 | * Fixed TLB translations in the processor. | 20 | * Fixed TLB translations in the processor. |
@@ -150,9 +151,11 @@ extern void copy_user_page(void*, void*, unsigned long, struct page*); | |||
150 | * addresses. | 151 | * addresses. |
151 | */ | 152 | */ |
152 | 153 | ||
154 | #define ARCH_PFN_OFFSET (PLATFORM_DEFAULT_MEM_START >> PAGE_SHIFT) | ||
155 | |||
153 | #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) | 156 | #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) |
154 | #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) | 157 | #define __va(x) ((void *)((unsigned long) (x) + PAGE_OFFSET)) |
155 | #define pfn_valid(pfn) ((unsigned long)pfn < max_mapnr) | 158 | #define pfn_valid(pfn) ((pfn) >= ARCH_PFN_OFFSET && ((pfn) - ARCH_PFN_OFFSET) < max_mapnr) |
156 | #ifdef CONFIG_DISCONTIGMEM | 159 | #ifdef CONFIG_DISCONTIGMEM |
157 | # error CONFIG_DISCONTIGMEM not supported | 160 | # error CONFIG_DISCONTIGMEM not supported |
158 | #endif | 161 | #endif |