diff options
author | Chris Zankel <czankel@tensilica.com> | 2006-12-10 05:18:48 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.osdl.org> | 2006-12-10 12:55:39 -0500 |
commit | 173d6681380aa1d60dfc35ed7178bd7811ba2784 (patch) | |
tree | 9d6d4d2c6dd791499ebab558647efb67ac88ae3a /arch/xtensa/Kconfig | |
parent | fd43fe19b830d6cd0eba08a6c6a5f71a6bd9c1b0 (diff) |
[PATCH] xtensa: remove extra header files
The Xtensa port contained many header files that were never needed. This
rather lengthy patch removes all those files. Unfortunately, there were
many dependencies that needed to be updated, so this patch touches quite a
few source files.
Signed-off-by: Chris Zankel <chris@zankel.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/xtensa/Kconfig')
-rw-r--r-- | arch/xtensa/Kconfig | 21 |
1 files changed, 3 insertions, 18 deletions
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index 9eccfbd1b536..2e74cb0b7807 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig | |||
@@ -48,25 +48,10 @@ menu "Processor type and features" | |||
48 | 48 | ||
49 | choice | 49 | choice |
50 | prompt "Xtensa Processor Configuration" | 50 | prompt "Xtensa Processor Configuration" |
51 | default XTENSA_CPU_LINUX_BE | 51 | default XTENSA_VARIANT_FSF |
52 | 52 | ||
53 | config XTENSA_CPU_LINUX_BE | 53 | config XTENSA_VARIANT_FSF |
54 | bool "linux_be" | 54 | bool "fsf" |
55 | ---help--- | ||
56 | The linux_be processor configuration is the baseline Xtensa | ||
57 | configurations included in this kernel and also used by | ||
58 | binutils, gcc, and gdb. It contains no TIE, no coprocessors, | ||
59 | and the following configuration options: | ||
60 | |||
61 | Code Density Option 2 Misc Special Registers | ||
62 | NSA/NSAU Instructions 128-bit Data Bus Width | ||
63 | Processor ID 8K, 2-way I and D Caches | ||
64 | Zero-Overhead Loops 2 Inst Address Break Registers | ||
65 | Big Endian 2 Data Address Break Registers | ||
66 | 64 General-Purpose Registers JTAG Interface and Trace Port | ||
67 | 17 Interrupts MMU w/ TLBs and Autorefill | ||
68 | 3 Interrupt Levels 8 Autorefill Ways (I/D TLBs) | ||
69 | 3 Timers Unaligned Exceptions | ||
70 | endchoice | 55 | endchoice |
71 | 56 | ||
72 | config MMU | 57 | config MMU |