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authorEric W. Biederman <ebiederm@xmission.com>2006-11-08 20:44:57 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2006-11-08 21:29:24 -0500
commitec68307cc5a8dc499e48693843bb42f6b6028458 (patch)
treeba735cbdc35819837bc53ef1385a478f5800fd7a /arch/x86_64
parent64d9fe6973a9348e5211f3cc9f04b899329caeb4 (diff)
[PATCH] htirq: refactor so we only have one function that writes to the chip
This refactoring actually optimizes the code a little by caching the value that we think the device is programmed with instead of reading it back from the hardware. Which simplifies the code a little and should speed things up a bit. This patch introduces the concept of a ht_irq_msg and modifies the architecture read/write routines to update this code. There is a minor consistency fix here as well as x86_64 forgot to initialize the htirq as masked. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Cc: Andi Kleen <ak@suse.de> Acked-by: Bryan O'Sullivan <bos@pathscale.com> Cc: <olson@pathscale.com> Cc: Roland Dreier <rolandd@cisco.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/x86_64')
-rw-r--r--arch/x86_64/kernel/io_apic.c31
1 files changed, 15 insertions, 16 deletions
diff --git a/arch/x86_64/kernel/io_apic.c b/arch/x86_64/kernel/io_apic.c
index 3b8f9c68ad3c..41bfc49301ad 100644
--- a/arch/x86_64/kernel/io_apic.c
+++ b/arch/x86_64/kernel/io_apic.c
@@ -1955,18 +1955,16 @@ void arch_teardown_msi_irq(unsigned int irq)
1955 1955
1956static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector) 1956static void target_ht_irq(unsigned int irq, unsigned int dest, u8 vector)
1957{ 1957{
1958 u32 low, high; 1958 struct ht_irq_msg msg;
1959 low = read_ht_irq_low(irq); 1959 fetch_ht_irq_msg(irq, &msg);
1960 high = read_ht_irq_high(irq);
1961 1960
1962 low &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK); 1961 msg.address_lo &= ~(HT_IRQ_LOW_VECTOR_MASK | HT_IRQ_LOW_DEST_ID_MASK);
1963 high &= ~(HT_IRQ_HIGH_DEST_ID_MASK); 1962 msg.address_hi &= ~(HT_IRQ_HIGH_DEST_ID_MASK);
1964 1963
1965 low |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest); 1964 msg.address_lo |= HT_IRQ_LOW_VECTOR(vector) | HT_IRQ_LOW_DEST_ID(dest);
1966 high |= HT_IRQ_HIGH_DEST_ID(dest); 1965 msg.address_hi |= HT_IRQ_HIGH_DEST_ID(dest);
1967 1966
1968 write_ht_irq_low(irq, low); 1967 write_ht_irq_msg(irq, &msg);
1969 write_ht_irq_high(irq, high);
1970} 1968}
1971 1969
1972static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask) 1970static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
@@ -1987,7 +1985,7 @@ static void set_ht_irq_affinity(unsigned int irq, cpumask_t mask)
1987 1985
1988 dest = cpu_mask_to_apicid(tmp); 1986 dest = cpu_mask_to_apicid(tmp);
1989 1987
1990 target_ht_irq(irq, dest, vector & 0xff); 1988 target_ht_irq(irq, dest, vector);
1991 set_native_irq_info(irq, mask); 1989 set_native_irq_info(irq, mask);
1992} 1990}
1993#endif 1991#endif
@@ -2010,14 +2008,15 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2010 2008
2011 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp); 2009 vector = assign_irq_vector(irq, TARGET_CPUS, &tmp);
2012 if (vector >= 0) { 2010 if (vector >= 0) {
2013 u32 low, high; 2011 struct ht_irq_msg msg;
2014 unsigned dest; 2012 unsigned dest;
2015 2013
2016 dest = cpu_mask_to_apicid(tmp); 2014 dest = cpu_mask_to_apicid(tmp);
2017 2015
2018 high = HT_IRQ_HIGH_DEST_ID(dest); 2016 msg.address_hi = HT_IRQ_HIGH_DEST_ID(dest);
2019 2017
2020 low = HT_IRQ_LOW_BASE | 2018 msg.address_lo =
2019 HT_IRQ_LOW_BASE |
2021 HT_IRQ_LOW_DEST_ID(dest) | 2020 HT_IRQ_LOW_DEST_ID(dest) |
2022 HT_IRQ_LOW_VECTOR(vector) | 2021 HT_IRQ_LOW_VECTOR(vector) |
2023 ((INT_DEST_MODE == 0) ? 2022 ((INT_DEST_MODE == 0) ?
@@ -2026,10 +2025,10 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev)
2026 HT_IRQ_LOW_RQEOI_EDGE | 2025 HT_IRQ_LOW_RQEOI_EDGE |
2027 ((INT_DELIVERY_MODE != dest_LowestPrio) ? 2026 ((INT_DELIVERY_MODE != dest_LowestPrio) ?
2028 HT_IRQ_LOW_MT_FIXED : 2027 HT_IRQ_LOW_MT_FIXED :
2029 HT_IRQ_LOW_MT_ARBITRATED); 2028 HT_IRQ_LOW_MT_ARBITRATED) |
2029 HT_IRQ_LOW_IRQ_MASKED;
2030 2030
2031 write_ht_irq_low(irq, low); 2031 write_ht_irq_msg(irq, &msg);
2032 write_ht_irq_high(irq, high);
2033 2032
2034 set_irq_chip_and_handler_name(irq, &ht_irq_chip, 2033 set_irq_chip_and_handler_name(irq, &ht_irq_chip,
2035 handle_edge_irq, "edge"); 2034 handle_edge_irq, "edge");