aboutsummaryrefslogtreecommitdiffstats
path: root/arch/x86_64
diff options
context:
space:
mode:
authorJan Beulich <JBeulich@novell.com>2005-09-13 04:25:51 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-13 11:22:33 -0400
commit42ac8ff2ce58138ba1339296406bde6636792bd8 (patch)
tree52073317d1482904c2c621ff2721dc0cbf354c42 /arch/x86_64
parent33bf56106d9be272696b73d9179da4e56b277472 (diff)
[PATCH] x86_64: NMI watchdog frequency calculation adjustments
Like previously done for i386, get the x86_64 watchdog tick calculation into a state where it can also be used on CPUs with frequencies beyond 4GHz. Signed-off-by: Jan Beulich <jbeulich@novell.com> Acked-by: Andi Kleen <ak@muc.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/x86_64')
-rw-r--r--arch/x86_64/kernel/nmi.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/x86_64/kernel/nmi.c b/arch/x86_64/kernel/nmi.c
index 4388b8a5bae7..39d445e16f22 100644
--- a/arch/x86_64/kernel/nmi.c
+++ b/arch/x86_64/kernel/nmi.c
@@ -366,7 +366,7 @@ static void setup_k7_watchdog(void)
366 | K7_NMI_EVENT; 366 | K7_NMI_EVENT;
367 367
368 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); 368 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
369 wrmsr(MSR_K7_PERFCTR0, -(cpu_khz/nmi_hz*1000), -1); 369 wrmsrl(MSR_K7_PERFCTR0, -((u64)cpu_khz * 1000 / nmi_hz));
370 apic_write(APIC_LVTPC, APIC_DM_NMI); 370 apic_write(APIC_LVTPC, APIC_DM_NMI);
371 evntsel |= K7_EVNTSEL_ENABLE; 371 evntsel |= K7_EVNTSEL_ENABLE;
372 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0); 372 wrmsr(MSR_K7_EVNTSEL0, evntsel, 0);
@@ -407,8 +407,8 @@ static int setup_p4_watchdog(void)
407 407
408 wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0); 408 wrmsr(MSR_P4_CRU_ESCR0, P4_NMI_CRU_ESCR0, 0);
409 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0); 409 wrmsr(MSR_P4_IQ_CCCR0, P4_NMI_IQ_CCCR0 & ~P4_CCCR_ENABLE, 0);
410 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz/nmi_hz*1000)); 410 Dprintk("setting P4_IQ_COUNTER0 to 0x%08lx\n", -(cpu_khz * 1000UL / nmi_hz));
411 wrmsr(MSR_P4_IQ_COUNTER0, -(cpu_khz/nmi_hz*1000), -1); 411 wrmsrl(MSR_P4_IQ_COUNTER0, -((u64)cpu_khz * 1000 / nmi_hz));
412 apic_write(APIC_LVTPC, APIC_DM_NMI); 412 apic_write(APIC_LVTPC, APIC_DM_NMI);
413 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); 413 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
414 return 1; 414 return 1;
@@ -506,7 +506,7 @@ void nmi_watchdog_tick (struct pt_regs * regs, unsigned reason)
506 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0); 506 wrmsr(MSR_P4_IQ_CCCR0, nmi_p4_cccr_val, 0);
507 apic_write(APIC_LVTPC, APIC_DM_NMI); 507 apic_write(APIC_LVTPC, APIC_DM_NMI);
508 } 508 }
509 wrmsr(nmi_perfctr_msr, -(cpu_khz/nmi_hz*1000), -1); 509 wrmsrl(nmi_perfctr_msr, -((u64)cpu_khz * 1000 / nmi_hz));
510 } 510 }
511} 511}
512 512