diff options
author | Andi Kleen <ak@suse.de> | 2006-06-26 07:56:40 -0400 |
---|---|---|
committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-06-26 13:48:15 -0400 |
commit | a32073bffc656ca4bde6002b6cf7c1a8e0e22712 (patch) | |
tree | 5ddcd3107eca8807685a19490c2c849d728a51a6 /arch/x86_64/pci | |
parent | 7c2d9cd218916276e52a5dae827b84a159fe5c96 (diff) |
[PATCH] x86_64: Clean and enhance up K8 northbridge access code
- Factor out the duplicated access/cache code into a single file
* Shared between i386/x86-64.
- Share flush code between AGP and IOMMU
* Fix a bug: AGP didn't wait for end of flush before
- Drop 8 northbridges limit and allocate dynamically
- Add lock to serialize AGP and IOMMU GART flushes
- Add PCI ID for next AMD northbridge
- Random related cleanups
The old K8 NUMA discovery code is unchanged. New systems
should all use SRAT for this.
Cc: "Navin Boppuri" <navin.boppuri@newisys.com>
Cc: Dave Jones <davej@redhat.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/x86_64/pci')
-rw-r--r-- | arch/x86_64/pci/k8-bus.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/x86_64/pci/k8-bus.c b/arch/x86_64/pci/k8-bus.c index 3acf60ded2a0..b50a7c7c47f8 100644 --- a/arch/x86_64/pci/k8-bus.c +++ b/arch/x86_64/pci/k8-bus.c | |||
@@ -2,6 +2,7 @@ | |||
2 | #include <linux/pci.h> | 2 | #include <linux/pci.h> |
3 | #include <asm/mpspec.h> | 3 | #include <asm/mpspec.h> |
4 | #include <linux/cpumask.h> | 4 | #include <linux/cpumask.h> |
5 | #include <asm/k8.h> | ||
5 | 6 | ||
6 | /* | 7 | /* |
7 | * This discovers the pcibus <-> node mapping on AMD K8. | 8 | * This discovers the pcibus <-> node mapping on AMD K8. |
@@ -18,7 +19,6 @@ | |||
18 | #define NR_LDT_BUS_NUMBER_REGISTERS 3 | 19 | #define NR_LDT_BUS_NUMBER_REGISTERS 3 |
19 | #define SECONDARY_LDT_BUS_NUMBER(dword) ((dword >> 8) & 0xFF) | 20 | #define SECONDARY_LDT_BUS_NUMBER(dword) ((dword >> 8) & 0xFF) |
20 | #define SUBORDINATE_LDT_BUS_NUMBER(dword) ((dword >> 16) & 0xFF) | 21 | #define SUBORDINATE_LDT_BUS_NUMBER(dword) ((dword >> 16) & 0xFF) |
21 | #define PCI_DEVICE_ID_K8HTCONFIG 0x1100 | ||
22 | 22 | ||
23 | /** | 23 | /** |
24 | * fill_mp_bus_to_cpumask() | 24 | * fill_mp_bus_to_cpumask() |
@@ -28,8 +28,7 @@ | |||
28 | __init static int | 28 | __init static int |
29 | fill_mp_bus_to_cpumask(void) | 29 | fill_mp_bus_to_cpumask(void) |
30 | { | 30 | { |
31 | struct pci_dev *nb_dev = NULL; | 31 | int i, j, k; |
32 | int i, j; | ||
33 | u32 ldtbus, nid; | 32 | u32 ldtbus, nid; |
34 | static int lbnr[3] = { | 33 | static int lbnr[3] = { |
35 | LDT_BUS_NUMBER_REGISTER_0, | 34 | LDT_BUS_NUMBER_REGISTER_0, |
@@ -37,8 +36,9 @@ fill_mp_bus_to_cpumask(void) | |||
37 | LDT_BUS_NUMBER_REGISTER_2 | 36 | LDT_BUS_NUMBER_REGISTER_2 |
38 | }; | 37 | }; |
39 | 38 | ||
40 | while ((nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, | 39 | cache_k8_northbridges(); |
41 | PCI_DEVICE_ID_K8HTCONFIG, nb_dev))) { | 40 | for (k = 0; k < num_k8_northbridges; k++) { |
41 | struct pci_dev *nb_dev = k8_northbridges[k]; | ||
42 | pci_read_config_dword(nb_dev, NODE_ID_REGISTER, &nid); | 42 | pci_read_config_dword(nb_dev, NODE_ID_REGISTER, &nid); |
43 | 43 | ||
44 | for (i = 0; i < NR_LDT_BUS_NUMBER_REGISTERS; i++) { | 44 | for (i = 0; i < NR_LDT_BUS_NUMBER_REGISTERS; i++) { |