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authorAndi Kleen <ak@suse.de>2006-01-26 20:03:50 -0500
committerGreg Kroah-Hartman <gregkh@suse.de>2006-01-31 21:00:13 -0500
commit3103039cc2a8dc6ababc29afac5c3cadbfa69af9 (patch)
treef89e6a1ca25281fbf78f6438c0463d06251ae3a3 /arch/x86_64/pci/mmconfig.c
parent877be3f0304de16a77f11b2b47f1291b800d5479 (diff)
[PATCH] PCI: handle bogus MCFG entries
Handle more bogus MCFG entries Some Asus P4 boards seem to have broken MCFG tables with only a single entry for busses 0-0. Special case these and assume they mean all busses can be accessed. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
Diffstat (limited to 'arch/x86_64/pci/mmconfig.c')
-rw-r--r--arch/x86_64/pci/mmconfig.c19
1 files changed, 14 insertions, 5 deletions
diff --git a/arch/x86_64/pci/mmconfig.c b/arch/x86_64/pci/mmconfig.c
index f16c0d57c552..00d4ddbf980c 100644
--- a/arch/x86_64/pci/mmconfig.c
+++ b/arch/x86_64/pci/mmconfig.c
@@ -29,11 +29,8 @@ static char __iomem *get_virt(unsigned int seg, unsigned bus)
29 29
30 while (1) { 30 while (1) {
31 ++cfg_num; 31 ++cfg_num;
32 if (cfg_num >= pci_mmcfg_config_num) { 32 if (cfg_num >= pci_mmcfg_config_num)
33 /* Not found - fall back to type 1. This happens 33 break;
34 e.g. on the internal devices of a K8 northbridge. */
35 return NULL;
36 }
37 cfg = pci_mmcfg_virt[cfg_num].cfg; 34 cfg = pci_mmcfg_virt[cfg_num].cfg;
38 if (cfg->pci_segment_group_number != seg) 35 if (cfg->pci_segment_group_number != seg)
39 continue; 36 continue;
@@ -41,6 +38,18 @@ static char __iomem *get_virt(unsigned int seg, unsigned bus)
41 (cfg->end_bus_number >= bus)) 38 (cfg->end_bus_number >= bus))
42 return pci_mmcfg_virt[cfg_num].virt; 39 return pci_mmcfg_virt[cfg_num].virt;
43 } 40 }
41
42 /* Handle more broken MCFG tables on Asus etc.
43 They only contain a single entry for bus 0-0. Assume
44 this applies to all busses. */
45 cfg = &pci_mmcfg_config[0];
46 if (pci_mmcfg_config_num == 1 &&
47 cfg->pci_segment_group_number == 0 &&
48 (cfg->start_bus_number | cfg->end_bus_number) == 0)
49 return cfg->base_address;
50
51 /* Fall back to type 0 */
52 return 0;
44} 53}
45 54
46static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn) 55static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)