diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2007-10-11 05:14:54 -0400 |
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committer | Thomas Gleixner <tglx@linutronix.de> | 2007-10-11 05:14:54 -0400 |
commit | abb11834c6515161babea211a7be1fc6dcb893dc (patch) | |
tree | 0c3101e18acd60aea9454e7bb26df1db96257de2 /arch/x86_64/kernel/time.c | |
parent | 96a6674c5ad6a6f596aab6ac826b93f5cd846749 (diff) |
x86_64: prepare shared kernel/time.c
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86_64/kernel/time.c')
-rw-r--r-- | arch/x86_64/kernel/time.c | 447 |
1 files changed, 0 insertions, 447 deletions
diff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c deleted file mode 100644 index 6d48a4e826d9..000000000000 --- a/arch/x86_64/kernel/time.c +++ /dev/null | |||
@@ -1,447 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/x86-64/kernel/time.c | ||
3 | * | ||
4 | * "High Precision Event Timer" based timekeeping. | ||
5 | * | ||
6 | * Copyright (c) 1991,1992,1995 Linus Torvalds | ||
7 | * Copyright (c) 1994 Alan Modra | ||
8 | * Copyright (c) 1995 Markus Kuhn | ||
9 | * Copyright (c) 1996 Ingo Molnar | ||
10 | * Copyright (c) 1998 Andrea Arcangeli | ||
11 | * Copyright (c) 2002,2006 Vojtech Pavlik | ||
12 | * Copyright (c) 2003 Andi Kleen | ||
13 | * RTC support code taken from arch/i386/kernel/timers/time_hpet.c | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/sched.h> | ||
18 | #include <linux/interrupt.h> | ||
19 | #include <linux/init.h> | ||
20 | #include <linux/mc146818rtc.h> | ||
21 | #include <linux/time.h> | ||
22 | #include <linux/ioport.h> | ||
23 | #include <linux/module.h> | ||
24 | #include <linux/device.h> | ||
25 | #include <linux/sysdev.h> | ||
26 | #include <linux/bcd.h> | ||
27 | #include <linux/notifier.h> | ||
28 | #include <linux/cpu.h> | ||
29 | #include <linux/kallsyms.h> | ||
30 | #include <linux/acpi.h> | ||
31 | #ifdef CONFIG_ACPI | ||
32 | #include <acpi/achware.h> /* for PM timer frequency */ | ||
33 | #include <acpi/acpi_bus.h> | ||
34 | #endif | ||
35 | #include <asm/8253pit.h> | ||
36 | #include <asm/i8253.h> | ||
37 | #include <asm/pgtable.h> | ||
38 | #include <asm/vsyscall.h> | ||
39 | #include <asm/timex.h> | ||
40 | #include <asm/proto.h> | ||
41 | #include <asm/hpet.h> | ||
42 | #include <asm/sections.h> | ||
43 | #include <linux/hpet.h> | ||
44 | #include <asm/apic.h> | ||
45 | #include <asm/hpet.h> | ||
46 | #include <asm/mpspec.h> | ||
47 | #include <asm/nmi.h> | ||
48 | #include <asm/vgtod.h> | ||
49 | |||
50 | static char *timename = NULL; | ||
51 | |||
52 | DEFINE_SPINLOCK(rtc_lock); | ||
53 | EXPORT_SYMBOL(rtc_lock); | ||
54 | DEFINE_SPINLOCK(i8253_lock); | ||
55 | EXPORT_SYMBOL(i8253_lock); | ||
56 | |||
57 | volatile unsigned long __jiffies __section_jiffies = INITIAL_JIFFIES; | ||
58 | |||
59 | unsigned long profile_pc(struct pt_regs *regs) | ||
60 | { | ||
61 | unsigned long pc = instruction_pointer(regs); | ||
62 | |||
63 | /* Assume the lock function has either no stack frame or a copy | ||
64 | of eflags from PUSHF | ||
65 | Eflags always has bits 22 and up cleared unlike kernel addresses. */ | ||
66 | if (!user_mode(regs) && in_lock_functions(pc)) { | ||
67 | unsigned long *sp = (unsigned long *)regs->rsp; | ||
68 | if (sp[0] >> 22) | ||
69 | return sp[0]; | ||
70 | if (sp[1] >> 22) | ||
71 | return sp[1]; | ||
72 | } | ||
73 | return pc; | ||
74 | } | ||
75 | EXPORT_SYMBOL(profile_pc); | ||
76 | |||
77 | /* | ||
78 | * In order to set the CMOS clock precisely, set_rtc_mmss has to be called 500 | ||
79 | * ms after the second nowtime has started, because when nowtime is written | ||
80 | * into the registers of the CMOS clock, it will jump to the next second | ||
81 | * precisely 500 ms later. Check the Motorola MC146818A or Dallas DS12887 data | ||
82 | * sheet for details. | ||
83 | */ | ||
84 | |||
85 | static int set_rtc_mmss(unsigned long nowtime) | ||
86 | { | ||
87 | int retval = 0; | ||
88 | int real_seconds, real_minutes, cmos_minutes; | ||
89 | unsigned char control, freq_select; | ||
90 | |||
91 | /* | ||
92 | * IRQs are disabled when we're called from the timer interrupt, | ||
93 | * no need for spin_lock_irqsave() | ||
94 | */ | ||
95 | |||
96 | spin_lock(&rtc_lock); | ||
97 | |||
98 | /* | ||
99 | * Tell the clock it's being set and stop it. | ||
100 | */ | ||
101 | |||
102 | control = CMOS_READ(RTC_CONTROL); | ||
103 | CMOS_WRITE(control | RTC_SET, RTC_CONTROL); | ||
104 | |||
105 | freq_select = CMOS_READ(RTC_FREQ_SELECT); | ||
106 | CMOS_WRITE(freq_select | RTC_DIV_RESET2, RTC_FREQ_SELECT); | ||
107 | |||
108 | cmos_minutes = CMOS_READ(RTC_MINUTES); | ||
109 | BCD_TO_BIN(cmos_minutes); | ||
110 | |||
111 | /* | ||
112 | * since we're only adjusting minutes and seconds, don't interfere with hour | ||
113 | * overflow. This avoids messing with unknown time zones but requires your RTC | ||
114 | * not to be off by more than 15 minutes. Since we're calling it only when | ||
115 | * our clock is externally synchronized using NTP, this shouldn't be a problem. | ||
116 | */ | ||
117 | |||
118 | real_seconds = nowtime % 60; | ||
119 | real_minutes = nowtime / 60; | ||
120 | if (((abs(real_minutes - cmos_minutes) + 15) / 30) & 1) | ||
121 | real_minutes += 30; /* correct for half hour time zone */ | ||
122 | real_minutes %= 60; | ||
123 | |||
124 | if (abs(real_minutes - cmos_minutes) >= 30) { | ||
125 | printk(KERN_WARNING "time.c: can't update CMOS clock " | ||
126 | "from %d to %d\n", cmos_minutes, real_minutes); | ||
127 | retval = -1; | ||
128 | } else { | ||
129 | BIN_TO_BCD(real_seconds); | ||
130 | BIN_TO_BCD(real_minutes); | ||
131 | CMOS_WRITE(real_seconds, RTC_SECONDS); | ||
132 | CMOS_WRITE(real_minutes, RTC_MINUTES); | ||
133 | } | ||
134 | |||
135 | /* | ||
136 | * The following flags have to be released exactly in this order, otherwise the | ||
137 | * DS12887 (popular MC146818A clone with integrated battery and quartz) will | ||
138 | * not reset the oscillator and will not update precisely 500 ms later. You | ||
139 | * won't find this mentioned in the Dallas Semiconductor data sheets, but who | ||
140 | * believes data sheets anyway ... -- Markus Kuhn | ||
141 | */ | ||
142 | |||
143 | CMOS_WRITE(control, RTC_CONTROL); | ||
144 | CMOS_WRITE(freq_select, RTC_FREQ_SELECT); | ||
145 | |||
146 | spin_unlock(&rtc_lock); | ||
147 | |||
148 | return retval; | ||
149 | } | ||
150 | |||
151 | int update_persistent_clock(struct timespec now) | ||
152 | { | ||
153 | return set_rtc_mmss(now.tv_sec); | ||
154 | } | ||
155 | |||
156 | void main_timer_handler(void) | ||
157 | { | ||
158 | /* | ||
159 | * Here we are in the timer irq handler. We have irqs locally disabled (so we | ||
160 | * don't need spin_lock_irqsave()) but we don't know if the timer_bh is running | ||
161 | * on the other CPU, so we need a lock. We also need to lock the vsyscall | ||
162 | * variables, because both do_timer() and us change them -arca+vojtech | ||
163 | */ | ||
164 | |||
165 | write_seqlock(&xtime_lock); | ||
166 | |||
167 | /* | ||
168 | * Do the timer stuff. | ||
169 | */ | ||
170 | |||
171 | do_timer(1); | ||
172 | #ifndef CONFIG_SMP | ||
173 | update_process_times(user_mode(get_irq_regs())); | ||
174 | #endif | ||
175 | |||
176 | /* | ||
177 | * In the SMP case we use the local APIC timer interrupt to do the profiling, | ||
178 | * except when we simulate SMP mode on a uniprocessor system, in that case we | ||
179 | * have to call the local interrupt handler. | ||
180 | */ | ||
181 | |||
182 | if (!using_apic_timer) | ||
183 | smp_local_timer_interrupt(); | ||
184 | |||
185 | write_sequnlock(&xtime_lock); | ||
186 | } | ||
187 | |||
188 | static irqreturn_t timer_interrupt(int irq, void *dev_id) | ||
189 | { | ||
190 | if (apic_runs_main_timer > 1) | ||
191 | return IRQ_HANDLED; | ||
192 | main_timer_handler(); | ||
193 | if (using_apic_timer) | ||
194 | smp_send_timer_broadcast_ipi(); | ||
195 | return IRQ_HANDLED; | ||
196 | } | ||
197 | |||
198 | unsigned long read_persistent_clock(void) | ||
199 | { | ||
200 | unsigned int year, mon, day, hour, min, sec; | ||
201 | unsigned long flags; | ||
202 | unsigned century = 0; | ||
203 | |||
204 | spin_lock_irqsave(&rtc_lock, flags); | ||
205 | |||
206 | do { | ||
207 | sec = CMOS_READ(RTC_SECONDS); | ||
208 | min = CMOS_READ(RTC_MINUTES); | ||
209 | hour = CMOS_READ(RTC_HOURS); | ||
210 | day = CMOS_READ(RTC_DAY_OF_MONTH); | ||
211 | mon = CMOS_READ(RTC_MONTH); | ||
212 | year = CMOS_READ(RTC_YEAR); | ||
213 | #ifdef CONFIG_ACPI | ||
214 | if (acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID && | ||
215 | acpi_gbl_FADT.century) | ||
216 | century = CMOS_READ(acpi_gbl_FADT.century); | ||
217 | #endif | ||
218 | } while (sec != CMOS_READ(RTC_SECONDS)); | ||
219 | |||
220 | spin_unlock_irqrestore(&rtc_lock, flags); | ||
221 | |||
222 | /* | ||
223 | * We know that x86-64 always uses BCD format, no need to check the | ||
224 | * config register. | ||
225 | */ | ||
226 | |||
227 | BCD_TO_BIN(sec); | ||
228 | BCD_TO_BIN(min); | ||
229 | BCD_TO_BIN(hour); | ||
230 | BCD_TO_BIN(day); | ||
231 | BCD_TO_BIN(mon); | ||
232 | BCD_TO_BIN(year); | ||
233 | |||
234 | if (century) { | ||
235 | BCD_TO_BIN(century); | ||
236 | year += century * 100; | ||
237 | printk(KERN_INFO "Extended CMOS year: %d\n", century * 100); | ||
238 | } else { | ||
239 | /* | ||
240 | * x86-64 systems only exists since 2002. | ||
241 | * This will work up to Dec 31, 2100 | ||
242 | */ | ||
243 | year += 2000; | ||
244 | } | ||
245 | |||
246 | return mktime(year, mon, day, hour, min, sec); | ||
247 | } | ||
248 | |||
249 | /* calibrate_cpu is used on systems with fixed rate TSCs to determine | ||
250 | * processor frequency */ | ||
251 | #define TICK_COUNT 100000000 | ||
252 | static unsigned int __init tsc_calibrate_cpu_khz(void) | ||
253 | { | ||
254 | int tsc_start, tsc_now; | ||
255 | int i, no_ctr_free; | ||
256 | unsigned long evntsel3 = 0, pmc3 = 0, pmc_now = 0; | ||
257 | unsigned long flags; | ||
258 | |||
259 | for (i = 0; i < 4; i++) | ||
260 | if (avail_to_resrv_perfctr_nmi_bit(i)) | ||
261 | break; | ||
262 | no_ctr_free = (i == 4); | ||
263 | if (no_ctr_free) { | ||
264 | i = 3; | ||
265 | rdmsrl(MSR_K7_EVNTSEL3, evntsel3); | ||
266 | wrmsrl(MSR_K7_EVNTSEL3, 0); | ||
267 | rdmsrl(MSR_K7_PERFCTR3, pmc3); | ||
268 | } else { | ||
269 | reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i); | ||
270 | reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i); | ||
271 | } | ||
272 | local_irq_save(flags); | ||
273 | /* start meauring cycles, incrementing from 0 */ | ||
274 | wrmsrl(MSR_K7_PERFCTR0 + i, 0); | ||
275 | wrmsrl(MSR_K7_EVNTSEL0 + i, 1 << 22 | 3 << 16 | 0x76); | ||
276 | rdtscl(tsc_start); | ||
277 | do { | ||
278 | rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now); | ||
279 | tsc_now = get_cycles_sync(); | ||
280 | } while ((tsc_now - tsc_start) < TICK_COUNT); | ||
281 | |||
282 | local_irq_restore(flags); | ||
283 | if (no_ctr_free) { | ||
284 | wrmsrl(MSR_K7_EVNTSEL3, 0); | ||
285 | wrmsrl(MSR_K7_PERFCTR3, pmc3); | ||
286 | wrmsrl(MSR_K7_EVNTSEL3, evntsel3); | ||
287 | } else { | ||
288 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); | ||
289 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); | ||
290 | } | ||
291 | |||
292 | return pmc_now * tsc_khz / (tsc_now - tsc_start); | ||
293 | } | ||
294 | |||
295 | /* | ||
296 | * pit_calibrate_tsc() uses the speaker output (channel 2) of | ||
297 | * the PIT. This is better than using the timer interrupt output, | ||
298 | * because we can read the value of the speaker with just one inb(), | ||
299 | * where we need three i/o operations for the interrupt channel. | ||
300 | * We count how many ticks the TSC does in 50 ms. | ||
301 | */ | ||
302 | |||
303 | static unsigned int __init pit_calibrate_tsc(void) | ||
304 | { | ||
305 | unsigned long start, end; | ||
306 | unsigned long flags; | ||
307 | |||
308 | spin_lock_irqsave(&i8253_lock, flags); | ||
309 | |||
310 | outb((inb(0x61) & ~0x02) | 0x01, 0x61); | ||
311 | |||
312 | outb(0xb0, 0x43); | ||
313 | outb((PIT_TICK_RATE / (1000 / 50)) & 0xff, 0x42); | ||
314 | outb((PIT_TICK_RATE / (1000 / 50)) >> 8, 0x42); | ||
315 | start = get_cycles_sync(); | ||
316 | while ((inb(0x61) & 0x20) == 0); | ||
317 | end = get_cycles_sync(); | ||
318 | |||
319 | spin_unlock_irqrestore(&i8253_lock, flags); | ||
320 | |||
321 | return (end - start) / 50; | ||
322 | } | ||
323 | |||
324 | #define PIT_MODE 0x43 | ||
325 | #define PIT_CH0 0x40 | ||
326 | |||
327 | static void __pit_init(int val, u8 mode) | ||
328 | { | ||
329 | unsigned long flags; | ||
330 | |||
331 | spin_lock_irqsave(&i8253_lock, flags); | ||
332 | outb_p(mode, PIT_MODE); | ||
333 | outb_p(val & 0xff, PIT_CH0); /* LSB */ | ||
334 | outb_p(val >> 8, PIT_CH0); /* MSB */ | ||
335 | spin_unlock_irqrestore(&i8253_lock, flags); | ||
336 | } | ||
337 | |||
338 | void __init pit_init(void) | ||
339 | { | ||
340 | __pit_init(LATCH, 0x34); /* binary, mode 2, LSB/MSB, ch 0 */ | ||
341 | } | ||
342 | |||
343 | void pit_stop_interrupt(void) | ||
344 | { | ||
345 | __pit_init(0, 0x30); /* mode 0 */ | ||
346 | } | ||
347 | |||
348 | void stop_timer_interrupt(void) | ||
349 | { | ||
350 | char *name; | ||
351 | if (hpet_address) { | ||
352 | name = "HPET"; | ||
353 | hpet_timer_stop_set_go(0); | ||
354 | } else { | ||
355 | name = "PIT"; | ||
356 | pit_stop_interrupt(); | ||
357 | } | ||
358 | printk(KERN_INFO "timer: %s interrupt stopped.\n", name); | ||
359 | } | ||
360 | |||
361 | static struct irqaction irq0 = { | ||
362 | .handler = timer_interrupt, | ||
363 | .flags = IRQF_DISABLED | IRQF_IRQPOLL, | ||
364 | .mask = CPU_MASK_NONE, | ||
365 | .name = "timer" | ||
366 | }; | ||
367 | |||
368 | void __init time_init(void) | ||
369 | { | ||
370 | if (nohpet) | ||
371 | hpet_address = 0; | ||
372 | |||
373 | if (hpet_arch_init()) | ||
374 | hpet_address = 0; | ||
375 | |||
376 | if (hpet_use_timer) { | ||
377 | /* set tick_nsec to use the proper rate for HPET */ | ||
378 | tick_nsec = TICK_NSEC_HPET; | ||
379 | tsc_khz = hpet_calibrate_tsc(); | ||
380 | timename = "HPET"; | ||
381 | } else { | ||
382 | pit_init(); | ||
383 | tsc_khz = pit_calibrate_tsc(); | ||
384 | timename = "PIT"; | ||
385 | } | ||
386 | |||
387 | cpu_khz = tsc_khz; | ||
388 | if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) && | ||
389 | boot_cpu_data.x86_vendor == X86_VENDOR_AMD && | ||
390 | boot_cpu_data.x86 == 16) | ||
391 | cpu_khz = tsc_calibrate_cpu_khz(); | ||
392 | |||
393 | if (unsynchronized_tsc()) | ||
394 | mark_tsc_unstable("TSCs unsynchronized"); | ||
395 | |||
396 | if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP)) | ||
397 | vgetcpu_mode = VGETCPU_RDTSCP; | ||
398 | else | ||
399 | vgetcpu_mode = VGETCPU_LSL; | ||
400 | |||
401 | set_cyc2ns_scale(tsc_khz); | ||
402 | printk(KERN_INFO "time.c: Detected %d.%03d MHz processor.\n", | ||
403 | cpu_khz / 1000, cpu_khz % 1000); | ||
404 | init_tsc_clocksource(); | ||
405 | |||
406 | setup_irq(0, &irq0); | ||
407 | } | ||
408 | |||
409 | /* | ||
410 | * sysfs support for the timer. | ||
411 | */ | ||
412 | |||
413 | static int timer_suspend(struct sys_device *dev, pm_message_t state) | ||
414 | { | ||
415 | return 0; | ||
416 | } | ||
417 | |||
418 | static int timer_resume(struct sys_device *dev) | ||
419 | { | ||
420 | if (hpet_address) | ||
421 | hpet_reenable(); | ||
422 | else | ||
423 | i8254_timer_resume(); | ||
424 | return 0; | ||
425 | } | ||
426 | |||
427 | static struct sysdev_class timer_sysclass = { | ||
428 | .resume = timer_resume, | ||
429 | .suspend = timer_suspend, | ||
430 | set_kset_name("timer"), | ||
431 | }; | ||
432 | |||
433 | /* XXX this sysfs stuff should probably go elsewhere later -john */ | ||
434 | static struct sys_device device_timer = { | ||
435 | .id = 0, | ||
436 | .cls = &timer_sysclass, | ||
437 | }; | ||
438 | |||
439 | static int time_init_device(void) | ||
440 | { | ||
441 | int error = sysdev_class_register(&timer_sysclass); | ||
442 | if (!error) | ||
443 | error = sysdev_register(&device_timer); | ||
444 | return error; | ||
445 | } | ||
446 | |||
447 | device_initcall(time_init_device); | ||