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authorClemens Ladisch <clemens@ladisch.de>2005-10-30 18:03:36 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2005-10-30 20:37:29 -0500
commit5f819949ee4e5a06c2e0054cbb42f3f0d170d779 (patch)
tree85dfb0366a13b3e0ae073b5838ec8d457fd89518 /arch/x86_64/kernel/time.c
parentf00c96f313b07d2eb2845305b9a3395e14385767 (diff)
[PATCH] hpet-RTC: fix timer config register accesses
Make sure that the RTC timer is in non-periodic mode; some stupid BIOS might have initialized it to periodic mode. Furthermore, don't set the SETVAL bit in the config register. This wouldn't have any effect unless the timer was in period mode (which it isn't), and then the actual timer frequency would be half that of the desired one because incrementing the comparator in the interrupt handler would be done after the hardware has already incremented it itself. Signed-off-by: Clemens Ladisch <clemens@ladisch.de> Acked-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/x86_64/kernel/time.c')
-rw-r--r--arch/x86_64/kernel/time.c9
1 files changed, 2 insertions, 7 deletions
diff --git a/arch/x86_64/kernel/time.c b/arch/x86_64/kernel/time.c
index 7037ca668c63..35a896ef4c35 100644
--- a/arch/x86_64/kernel/time.c
+++ b/arch/x86_64/kernel/time.c
@@ -1128,7 +1128,8 @@ int hpet_rtc_timer_init(void)
1128 local_irq_restore(flags); 1128 local_irq_restore(flags);
1129 1129
1130 cfg = hpet_readl(HPET_T1_CFG); 1130 cfg = hpet_readl(HPET_T1_CFG);
1131 cfg |= HPET_TN_ENABLE | HPET_TN_SETVAL | HPET_TN_32BIT; 1131 cfg &= ~HPET_TN_PERIODIC;
1132 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1132 hpet_writel(cfg, HPET_T1_CFG); 1133 hpet_writel(cfg, HPET_T1_CFG);
1133 1134
1134 return 1; 1135 return 1;
@@ -1154,12 +1155,6 @@ static void hpet_rtc_timer_reinit(void)
1154 cnt = hpet_readl(HPET_T1_CMP); 1155 cnt = hpet_readl(HPET_T1_CMP);
1155 cnt += hpet_tick*HZ/hpet_rtc_int_freq; 1156 cnt += hpet_tick*HZ/hpet_rtc_int_freq;
1156 hpet_writel(cnt, HPET_T1_CMP); 1157 hpet_writel(cnt, HPET_T1_CMP);
1157
1158 cfg = hpet_readl(HPET_T1_CFG);
1159 cfg |= HPET_TN_ENABLE | HPET_TN_SETVAL | HPET_TN_32BIT;
1160 hpet_writel(cfg, HPET_T1_CFG);
1161
1162 return;
1163} 1158}
1164 1159
1165/* 1160/*