[PATCH] i386/x86-64: Generalize X86_FEATURE_CONSTANT_TSC flag

Define it for i386 too.

This is a synthetic flag that signifies that the CPU's TSC runs
at a constant P state invariant frequency.

Fix up the logic on x86-64/i386 to set it on all known CPUs.
Use the AMD defined bit to set it on future AMD CPUs.

Cc: venkatesh.pallipadi@intel.com

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

1 files changed, 3 insertions, 2 deletions

diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index 754a05f9b4db..d9c1c3bd6150 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -1032,7 +1032,8 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
         if (c->x86 == 15)
                 c->x86_cache_alignment = c->x86_clflush_size * 2;
-        if (c->x86 >= 15)
+        if ((c->x86 == 0xf && c->x86_model >= 0x03) ||
+            (c->x86 == 0x6 && c->x86_model >= 0x0e))
                 set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
         c->x86_max_cores = intel_num_cpu_cores(c);
 
@@ -1273,7 +1274,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
                 "tm",
                 "stc"
                 "?",
-                "constant_tsc",
+                /* nothing */   /* constant_tsc - moved to flags */
         };