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authorAndi Kleen <ak@suse.de>2005-09-29 16:05:55 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-29 18:41:42 -0400
commit7d318d774789657c37a5e994a4a2cf59d4879ae7 (patch)
treeac48b3dd2cd7c8bedb049f4062ef9959bc5c73bb /arch/x86_64/kernel/setup.c
parent5acbc5cb507e6c381b70093b1081854708e82b16 (diff)
[PATCH] Fix up TLB flush filter disabling
I checked with AMD and they requested to only disable it for family 15. Also disable it for i386 too. And some style fixes. Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'arch/x86_64/kernel/setup.c')
-rw-r--r--arch/x86_64/kernel/setup.c22
1 files changed, 12 insertions, 10 deletions
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index 238f73e1a834..257f5ba17902 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -831,8 +831,6 @@ static void __init amd_detect_cmp(struct cpuinfo_x86 *c)
831#endif 831#endif
832} 832}
833 833
834#define HWCR 0xc0010015
835
836static int __init init_amd(struct cpuinfo_x86 *c) 834static int __init init_amd(struct cpuinfo_x86 *c)
837{ 835{
838 int r; 836 int r;
@@ -841,14 +839,18 @@ static int __init init_amd(struct cpuinfo_x86 *c)
841#ifdef CONFIG_SMP 839#ifdef CONFIG_SMP
842 unsigned long value; 840 unsigned long value;
843 841
844 // Disable TLB flush filter by setting HWCR.FFDIS: 842 /*
845 // bit 6 of msr C001_0015 843 * Disable TLB flush filter by setting HWCR.FFDIS on K8
846 // 844 * bit 6 of msr C001_0015
847 // Errata 63 for SH-B3 steppings 845 *
848 // Errata 122 for all(?) steppings 846 * Errata 63 for SH-B3 steppings
849 rdmsrl(HWCR, value); 847 * Errata 122 for all steppings (F+ have it disabled by default)
850 value |= 1 << 6; 848 */
851 wrmsrl(HWCR, value); 849 if (c->x86 == 15) {
850 rdmsrl(MSR_K8_HWCR, value);
851 value |= 1 << 6;
852 wrmsrl(MSR_K8_HWCR, value);
853 }
852#endif 854#endif
853 855
854 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; 856 /* Bit 31 in normal CPUID used for nonstandard 3DNow ID;