i386: Add L3 cache support to AMD CPUID4 emulation

With that an L3 cache is correctly reported in the cache information in /sys

With fixes from Andreas Herrmann and Dean Gaudet and Joachim Deguara

Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>

1 files changed, 5 insertions, 2 deletions

diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index 675b3d6de10b..6fa0a302e2aa 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -602,8 +602,11 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         if (c->extended_cpuid_level >= 0x80000008)
                 amd_detect_cmp(c);
 
-        /* Fix cpuid4 emulation for more */
-        num_cache_leaves = 3;
+        if (c->extended_cpuid_level >= 0x80000006 &&
+                (cpuid_edx(0x80000006) & 0xf000))
+                num_cache_leaves = 4;
+        else
+                num_cache_leaves = 3;
 
         /* RDTSC can be speculated around */
         clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);