diff options
author | Robert Richter <robert.richter@amd.com> | 2011-05-30 10:31:11 -0400 |
---|---|---|
committer | Robert Richter <robert.richter@amd.com> | 2011-05-30 10:36:54 -0400 |
commit | cbf74cea070fa1f705de4712e25d9e56ae6543c7 (patch) | |
tree | dce39e94a735df4953415720d85d7ed106f71075 /arch/x86 | |
parent | b76a06e08d94b2a63e47837dfe46bbbf0a3af6c2 (diff) |
oprofile, x86: Add comments to IBS LVT offset initialization
Adding a comment in the code as IBS LVT setup is not obvious at all ...
Signed-off-by: Robert Richter <robert.richter@amd.com>
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/kernel/apic/apic.c | 3 | ||||
-rw-r--r-- | arch/x86/oprofile/op_model_amd.c | 13 |
2 files changed, 11 insertions, 5 deletions
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c index fabf01eff771..a0bf78a0918c 100644 --- a/arch/x86/kernel/apic/apic.c +++ b/arch/x86/kernel/apic/apic.c | |||
@@ -390,7 +390,8 @@ static unsigned int reserve_eilvt_offset(int offset, unsigned int new) | |||
390 | 390 | ||
391 | /* | 391 | /* |
392 | * If mask=1, the LVT entry does not generate interrupts while mask=0 | 392 | * If mask=1, the LVT entry does not generate interrupts while mask=0 |
393 | * enables the vector. See also the BKDGs. | 393 | * enables the vector. See also the BKDGs. Must be called with |
394 | * preemption disabled. | ||
394 | */ | 395 | */ |
395 | 396 | ||
396 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) | 397 | int setup_APIC_eilvt(u8 offset, u8 vector, u8 msg_type, u8 mask) |
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index 9fd8a567fe1e..9cbb710dc94b 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c | |||
@@ -609,16 +609,21 @@ static int setup_ibs_ctl(int ibs_eilvt_off) | |||
609 | return 0; | 609 | return 0; |
610 | } | 610 | } |
611 | 611 | ||
612 | /* | ||
613 | * This runs only on the current cpu. We try to find an LVT offset and | ||
614 | * setup the local APIC. For this we must disable preemption. On | ||
615 | * success we initialize all nodes with this offset. This updates then | ||
616 | * the offset in the IBS_CTL per-node msr. The per-core APIC setup of | ||
617 | * the IBS interrupt vector is called from op_amd_setup_ctrs()/op_- | ||
618 | * amd_cpu_shutdown() using the new offset. | ||
619 | */ | ||
612 | static int force_ibs_eilvt_setup(void) | 620 | static int force_ibs_eilvt_setup(void) |
613 | { | 621 | { |
614 | int offset; | 622 | int offset; |
615 | int ret; | 623 | int ret; |
616 | 624 | ||
617 | /* | ||
618 | * find the next free available EILVT entry, skip offset 0, | ||
619 | * pin search to this cpu | ||
620 | */ | ||
621 | preempt_disable(); | 625 | preempt_disable(); |
626 | /* find the next free available EILVT entry, skip offset 0 */ | ||
622 | for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) { | 627 | for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) { |
623 | if (get_eilvt(offset)) | 628 | if (get_eilvt(offset)) |
624 | break; | 629 | break; |