diff options
author | Thomas Gleixner <tglx@linutronix.de> | 2008-05-16 16:55:26 -0400 |
---|---|---|
committer | Thomas Gleixner <tglx@linutronix.de> | 2008-05-17 16:57:20 -0400 |
commit | e9623b35599fcdbc00c16535cbefbb4d5578f4ab (patch) | |
tree | ba75fcf20f221c3db04aaee49db36c5f73f71622 /arch/x86 | |
parent | 31f4d870b02e1590260ab7f2a9ff74306bd27e88 (diff) |
x86: disable mwait for AMD family 10H/11H CPUs
The previous revert of 0c07ee38c9d4eb081758f5ad14bbffa7197e1aec left
out the mwait disable condition for AMD family 10H/11H CPUs.
Andreas Herrman said:
It depends on the CPU. For AMD CPUs that support MWAIT this is wrong.
Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings then
depend on a clock divisor and current Pstate of the core.
If all cores of a processor are in halt state (C1) the processor can
enter the C1E (C1 enhanced) state. If mwait is used this will never
happen.
Thus HLT saves more power than MWAIT here.
It might be best to switch off the mwait flag for these AMD CPU
families like it was introduced with commit
f039b754714a422959027cb18bb33760eb8153f0 (x86: Don't use MWAIT on AMD
Family 10)
Re-add the AMD families 10H/11H check and disable the mwait usage for
those.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/kernel/process.c | 29 |
1 files changed, 28 insertions, 1 deletions
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c index c7b6a694ca22..ba370dc8685b 100644 --- a/arch/x86/kernel/process.c +++ b/arch/x86/kernel/process.c | |||
@@ -110,6 +110,33 @@ static void poll_idle(void) | |||
110 | cpu_relax(); | 110 | cpu_relax(); |
111 | } | 111 | } |
112 | 112 | ||
113 | /* | ||
114 | * mwait selection logic: | ||
115 | * | ||
116 | * It depends on the CPU. For AMD CPUs that support MWAIT this is | ||
117 | * wrong. Family 0x10 and 0x11 CPUs will enter C1 on HLT. Powersavings | ||
118 | * then depend on a clock divisor and current Pstate of the core. If | ||
119 | * all cores of a processor are in halt state (C1) the processor can | ||
120 | * enter the C1E (C1 enhanced) state. If mwait is used this will never | ||
121 | * happen. | ||
122 | * | ||
123 | * idle=mwait overrides this decision and forces the usage of mwait. | ||
124 | */ | ||
125 | static int __cpuinit mwait_usable(const struct cpuinfo_x86 *c) | ||
126 | { | ||
127 | if (force_mwait) | ||
128 | return 1; | ||
129 | |||
130 | if (c->x86_vendor == X86_VENDOR_AMD) { | ||
131 | switch(c->x86) { | ||
132 | case 0x10: | ||
133 | case 0x11: | ||
134 | return 0; | ||
135 | } | ||
136 | } | ||
137 | return 1; | ||
138 | } | ||
139 | |||
113 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) | 140 | void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) |
114 | { | 141 | { |
115 | static int selected; | 142 | static int selected; |
@@ -122,7 +149,7 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c) | |||
122 | " performance may degrade.\n"); | 149 | " performance may degrade.\n"); |
123 | } | 150 | } |
124 | #endif | 151 | #endif |
125 | if (cpu_has(c, X86_FEATURE_MWAIT)) { | 152 | if (cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c)) { |
126 | /* | 153 | /* |
127 | * Skip, if setup has overridden idle. | 154 | * Skip, if setup has overridden idle. |
128 | * One CPU supports mwait => All CPUs supports mwait | 155 | * One CPU supports mwait => All CPUs supports mwait |