diff options
author | Matthew Wilcox <matthew@wil.cx> | 2008-02-10 23:18:15 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2008-02-11 11:15:03 -0500 |
commit | 9585ca02f8f9e844b64e7ff4d167ccc1390a99ab (patch) | |
tree | eeb7cb866c579a5b3a2e9b8eaac47fff64b2f006 /arch/x86 | |
parent | 19af35546de68c872dcb687613e0902a602cb20e (diff) |
Use proper abstractions in quirk_intel_irqbalance
Since we may not have a pci_dev for the device we need to access, we can't
use pci_read_config_word. But raw_pci_read is an internal implementation
detail; it's better to use the architected pci_bus_read_config_word
interface. Using PCI_DEVFN instead of a mysterious constant helps
reassure everyone that we really do intend to access device 8.
[ Thanks to Grant Grundler for pointing out to me that this is exactly
what the write immediately above this is doing -- enabling device 8 to
respond to config space cycles.
- Matthew
Grant also says:
"Can you also add a comment which points at the Intel
documentation?
The 'Intel E7320 Memory Controller Hub (MCH) Datasheet' at
http://download.intel.com/design/chipsets/datashts/30300702.pdf
Page 69 documents register F4h (DEVPRES1).
And I just doubled checked that the 0xf4 register value is
restored later in the quirk (obvious when you look at the code
but not from the patch"
so here it is.
- Linus ]
Signed-off-by: Matthew Wilcox <willy@linux.intel.com>
Acked-by: Grant Grundler <grundler@parisc-linux.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/kernel/quirks.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/x86/kernel/quirks.c b/arch/x86/kernel/quirks.c index 1941482d4ca3..c47208fc5932 100644 --- a/arch/x86/kernel/quirks.c +++ b/arch/x86/kernel/quirks.c | |||
@@ -11,7 +11,7 @@ | |||
11 | static void __devinit quirk_intel_irqbalance(struct pci_dev *dev) | 11 | static void __devinit quirk_intel_irqbalance(struct pci_dev *dev) |
12 | { | 12 | { |
13 | u8 config, rev; | 13 | u8 config, rev; |
14 | u32 word; | 14 | u16 word; |
15 | 15 | ||
16 | /* BIOS may enable hardware IRQ balancing for | 16 | /* BIOS may enable hardware IRQ balancing for |
17 | * E7520/E7320/E7525(revision ID 0x9 and below) | 17 | * E7520/E7320/E7525(revision ID 0x9 and below) |
@@ -26,8 +26,11 @@ static void __devinit quirk_intel_irqbalance(struct pci_dev *dev) | |||
26 | pci_read_config_byte(dev, 0xf4, &config); | 26 | pci_read_config_byte(dev, 0xf4, &config); |
27 | pci_write_config_byte(dev, 0xf4, config|0x2); | 27 | pci_write_config_byte(dev, 0xf4, config|0x2); |
28 | 28 | ||
29 | /* read xTPR register */ | 29 | /* |
30 | raw_pci_read(0, 0, 0x40, 0x4c, 2, &word); | 30 | * read xTPR register. We may not have a pci_dev for device 8 |
31 | * because it might be hidden until the above write. | ||
32 | */ | ||
33 | pci_bus_read_config_word(dev->bus, PCI_DEVFN(8, 0), 0x4c, &word); | ||
31 | 34 | ||
32 | if (!(word & (1 << 13))) { | 35 | if (!(word & (1 << 13))) { |
33 | dev_info(&dev->dev, "Intel E7520/7320/7525 detected; " | 36 | dev_info(&dev->dev, "Intel E7520/7320/7525 detected; " |