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authorIngo Molnar <mingo@elte.hu>2009-05-17 13:37:25 -0400
committerIngo Molnar <mingo@elte.hu>2009-05-18 03:37:09 -0400
commitb68f1d2e7aa21029d73c7d453a8046e95d351740 (patch)
tree2fa9e94f340e84e037bce4d3e3ffd5a6f88a9039 /arch/x86
parentc0daaf3f1f672defa3a45ca449b76d0e86c55892 (diff)
perf_counter, x86: speed up the scheduling fast-path
We have to set up the LVT entry only at counter init time, not at every switch-in time. There's friction between NMI and non-NMI use here - we'll probably remove the per counter configurability of it - but until then, dont slow down things ... [ Impact: micro-optimization ] Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Srivatsa Vaddagiri <vatsa@in.ibm.com> Cc: Paul Mackerras <paulus@samba.org> Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Marcelo Tosatti <mtosatti@redhat.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/kernel/cpu/perf_counter.c5
1 files changed, 2 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 5bfd30ab3920..c109819c2cb9 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -285,6 +285,7 @@ static int __hw_perf_counter_init(struct perf_counter *counter)
285 return -EACCES; 285 return -EACCES;
286 hwc->nmi = 1; 286 hwc->nmi = 1;
287 } 287 }
288 perf_counters_lapic_init(hwc->nmi);
288 289
289 if (!hwc->irq_period) 290 if (!hwc->irq_period)
290 hwc->irq_period = x86_pmu.max_period; 291 hwc->irq_period = x86_pmu.max_period;
@@ -603,8 +604,6 @@ try_generic:
603 hwc->counter_base = x86_pmu.perfctr; 604 hwc->counter_base = x86_pmu.perfctr;
604 } 605 }
605 606
606 perf_counters_lapic_init(hwc->nmi);
607
608 x86_pmu.disable(hwc, idx); 607 x86_pmu.disable(hwc, idx);
609 608
610 cpuc->counters[idx] = counter; 609 cpuc->counters[idx] = counter;
@@ -1054,7 +1053,7 @@ void __init init_hw_perf_counters(void)
1054 1053
1055 pr_info("... counter mask: %016Lx\n", perf_counter_mask); 1054 pr_info("... counter mask: %016Lx\n", perf_counter_mask);
1056 1055
1057 perf_counters_lapic_init(0); 1056 perf_counters_lapic_init(1);
1058 register_die_notifier(&perf_counter_nmi_notifier); 1057 register_die_notifier(&perf_counter_nmi_notifier);
1059} 1058}
1060 1059