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authorIngo Molnar <mingo@elte.hu>2008-07-10 10:45:50 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-10 12:55:45 -0400
commit62fa572f6933038b3d79558812de88702bda176f (patch)
treefa407f9ff8f3853fb263e22cc5405b1902e0785e /arch/x86
parent26dd9fcfc2abc298e3c60597bbe6405826aabf91 (diff)
x86, VisWS: turn into generic arch, remove leftover files
remove leftover arch/x86/mach-visws/* files. Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/Makefile4
-rw-r--r--arch/x86/mach-visws/Makefile7
-rw-r--r--arch/x86/mach-visws/setup.c174
-rw-r--r--arch/x86/mach-visws/setup_visws.c331
-rw-r--r--arch/x86/mach-visws/traps.c71
-rw-r--r--arch/x86/mach-visws/visws_apic.c295
-rw-r--r--arch/x86/pci/Makefile2
7 files changed, 0 insertions, 884 deletions
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index ce04b031f68b..919ce21ea654 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -113,10 +113,6 @@ mcore-y := arch/x86/mach-default/
113mflags-$(CONFIG_X86_VOYAGER) := -Iinclude/asm-x86/mach-voyager 113mflags-$(CONFIG_X86_VOYAGER) := -Iinclude/asm-x86/mach-voyager
114mcore-$(CONFIG_X86_VOYAGER) := arch/x86/mach-voyager/ 114mcore-$(CONFIG_X86_VOYAGER) := arch/x86/mach-voyager/
115 115
116# VISWS subarch support
117#mflags-$(CONFIG_X86_VISWS) := -Iinclude/asm-x86/mach-visws
118#mcore-$(CONFIG_X86_VISWS) := arch/x86/mach-visws/
119
120# generic subarchitecture 116# generic subarchitecture
121mflags-$(CONFIG_X86_GENERICARCH):= -Iinclude/asm-x86/mach-generic 117mflags-$(CONFIG_X86_GENERICARCH):= -Iinclude/asm-x86/mach-generic
122fcore-$(CONFIG_X86_GENERICARCH) += arch/x86/mach-generic/ 118fcore-$(CONFIG_X86_GENERICARCH) += arch/x86/mach-generic/
diff --git a/arch/x86/mach-visws/Makefile b/arch/x86/mach-visws/Makefile
deleted file mode 100644
index 7469df1340c1..000000000000
--- a/arch/x86/mach-visws/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1#
2# Makefile for the linux kernel.
3#
4
5obj-y := setup.o setup_visws.o traps.o
6
7obj-$(CONFIG_X86_VISWS_APIC) += visws_apic.o
diff --git a/arch/x86/mach-visws/setup.c b/arch/x86/mach-visws/setup.c
deleted file mode 100644
index b8054c3ffce3..000000000000
--- a/arch/x86/mach-visws/setup.c
+++ /dev/null
@@ -1,174 +0,0 @@
1/*
2 * Machine specific setup for generic
3 */
4
5#include <linux/smp.h>
6#include <linux/init.h>
7#include <linux/interrupt.h>
8#include <asm/acpi.h>
9#include <asm/arch_hooks.h>
10#include <asm/e820.h>
11#include <asm/setup.h>
12
13/*
14 * Any quirks to be performed to initialize timers/irqs/etc?
15 */
16int (*arch_time_init_quirk)(void);
17int (*arch_pre_intr_init_quirk)(void);
18int (*arch_intr_init_quirk)(void);
19int (*arch_trap_init_quirk)(void);
20
21#ifdef CONFIG_HOTPLUG_CPU
22#define DEFAULT_SEND_IPI (1)
23#else
24#define DEFAULT_SEND_IPI (0)
25#endif
26
27int no_broadcast=DEFAULT_SEND_IPI;
28
29/**
30 * pre_intr_init_hook - initialisation prior to setting up interrupt vectors
31 *
32 * Description:
33 * Perform any necessary interrupt initialisation prior to setting up
34 * the "ordinary" interrupt call gates. For legacy reasons, the ISA
35 * interrupts should be initialised here if the machine emulates a PC
36 * in any way.
37 **/
38void __init pre_intr_init_hook(void)
39{
40 if (arch_pre_intr_init_quirk) {
41 if (arch_pre_intr_init_quirk())
42 return;
43 }
44 init_ISA_irqs();
45}
46
47/*
48 * IRQ2 is cascade interrupt to second interrupt controller
49 */
50static struct irqaction irq2 = {
51 .handler = no_action,
52 .mask = CPU_MASK_NONE,
53 .name = "cascade",
54};
55
56/**
57 * intr_init_hook - post gate setup interrupt initialisation
58 *
59 * Description:
60 * Fill in any interrupts that may have been left out by the general
61 * init_IRQ() routine. interrupts having to do with the machine rather
62 * than the devices on the I/O bus (like APIC interrupts in intel MP
63 * systems) are started here.
64 **/
65void __init intr_init_hook(void)
66{
67 if (arch_intr_init_quirk) {
68 if (arch_intr_init_quirk())
69 return;
70 }
71#ifdef CONFIG_X86_LOCAL_APIC
72 apic_intr_init();
73#endif
74
75 if (!acpi_ioapic)
76 setup_irq(2, &irq2);
77}
78
79/**
80 * pre_setup_arch_hook - hook called prior to any setup_arch() execution
81 *
82 * Description:
83 * generally used to activate any machine specific identification
84 * routines that may be needed before setup_arch() runs. On VISWS
85 * this is used to get the board revision and type.
86 **/
87void __init pre_setup_arch_hook(void)
88{
89}
90
91/**
92 * trap_init_hook - initialise system specific traps
93 *
94 * Description:
95 * Called as the final act of trap_init(). Used in VISWS to initialise
96 * the various board specific APIC traps.
97 **/
98void __init trap_init_hook(void)
99{
100 if (arch_trap_init_quirk) {
101 if (arch_trap_init_quirk())
102 return;
103 }
104}
105
106static struct irqaction irq0 = {
107 .handler = timer_interrupt,
108 .flags = IRQF_DISABLED | IRQF_NOBALANCING | IRQF_IRQPOLL,
109 .mask = CPU_MASK_NONE,
110 .name = "timer"
111};
112
113/**
114 * time_init_hook - do any specific initialisations for the system timer.
115 *
116 * Description:
117 * Must plug the system timer interrupt source at HZ into the IRQ listed
118 * in irq_vectors.h:TIMER_IRQ
119 **/
120void __init time_init_hook(void)
121{
122 if (arch_time_init_quirk) {
123 /*
124 * A nonzero return code does not mean failure, it means
125 * that the architecture quirk does not want any
126 * generic (timer) setup to be performed after this:
127 */
128 if (arch_time_init_quirk())
129 return;
130 }
131
132 irq0.mask = cpumask_of_cpu(0);
133 setup_irq(0, &irq0);
134}
135
136#ifdef CONFIG_MCA
137/**
138 * mca_nmi_hook - hook into MCA specific NMI chain
139 *
140 * Description:
141 * The MCA (Microchannel Architecture) has an NMI chain for NMI sources
142 * along the MCA bus. Use this to hook into that chain if you will need
143 * it.
144 **/
145void mca_nmi_hook(void)
146{
147 /* If I recall correctly, there's a whole bunch of other things that
148 * we can do to check for NMI problems, but that's all I know about
149 * at the moment.
150 */
151
152 printk("NMI generated from unknown source!\n");
153}
154#endif
155
156static __init int no_ipi_broadcast(char *str)
157{
158 get_option(&str, &no_broadcast);
159 printk ("Using %s mode\n", no_broadcast ? "No IPI Broadcast" :
160 "IPI Broadcast");
161 return 1;
162}
163
164__setup("no_ipi_broadcast=", no_ipi_broadcast);
165
166static int __init print_ipi_mode(void)
167{
168 printk ("Using IPI %s mode\n", no_broadcast ? "No-Shortcut" :
169 "Shortcut");
170 return 0;
171}
172
173late_initcall(print_ipi_mode);
174
diff --git a/arch/x86/mach-visws/setup_visws.c b/arch/x86/mach-visws/setup_visws.c
deleted file mode 100644
index e95e9499c8cd..000000000000
--- a/arch/x86/mach-visws/setup_visws.c
+++ /dev/null
@@ -1,331 +0,0 @@
1/*
2 * Unmaintained SGI Visual Workstation support.
3 * Split out from setup.c by davej@suse.de
4 */
5
6#include <linux/interrupt.h>
7#include <linux/module.h>
8#include <linux/init.h>
9#include <linux/smp.h>
10
11#include <asm/visws/cobalt.h>
12#include <asm/visws/piix4.h>
13#include <asm/arch_hooks.h>
14#include <asm/fixmap.h>
15#include <asm/reboot.h>
16#include <asm/setup.h>
17#include <asm/e820.h>
18#include <asm/smp.h>
19#include <asm/io.h>
20
21#include <mach_ipi.h>
22
23#include "mach_apic.h"
24
25#include <linux/init.h>
26#include <linux/smp.h>
27
28char visws_board_type = -1;
29char visws_board_rev = -1;
30
31int is_visws_box(void)
32{
33 return visws_board_type >= 0;
34}
35
36static int __init visws_time_init_quirk(void)
37{
38 printk(KERN_INFO "Starting Cobalt Timer system clock\n");
39
40 /* Set the countdown value */
41 co_cpu_write(CO_CPU_TIMEVAL, CO_TIME_HZ/HZ);
42
43 /* Start the timer */
44 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) | CO_CTRL_TIMERUN);
45
46 /* Enable (unmask) the timer interrupt */
47 co_cpu_write(CO_CPU_CTRL, co_cpu_read(CO_CPU_CTRL) & ~CO_CTRL_TIMEMASK);
48
49 /*
50 * Zero return means the generic timer setup code will set up
51 * the standard vector:
52 */
53 return 0;
54}
55
56static int __init visws_pre_intr_init_quirk(void)
57{
58 init_VISWS_APIC_irqs();
59
60 /*
61 * We dont want ISA irqs to be set up by the generic code:
62 */
63 return 1;
64}
65
66/* Quirk for machine specific memory setup. */
67
68#define MB (1024 * 1024)
69
70unsigned long sgivwfb_mem_phys;
71unsigned long sgivwfb_mem_size;
72EXPORT_SYMBOL(sgivwfb_mem_phys);
73EXPORT_SYMBOL(sgivwfb_mem_size);
74
75long long mem_size __initdata = 0;
76
77static char * __init visws_memory_setup_quirk(void)
78{
79 long long gfx_mem_size = 8 * MB;
80
81 mem_size = boot_params.alt_mem_k;
82
83 if (!mem_size) {
84 printk(KERN_WARNING "Bootloader didn't set memory size, upgrade it !\n");
85 mem_size = 128 * MB;
86 }
87
88 /*
89 * this hardcodes the graphics memory to 8 MB
90 * it really should be sized dynamically (or at least
91 * set as a boot param)
92 */
93 if (!sgivwfb_mem_size) {
94 printk(KERN_WARNING "Defaulting to 8 MB framebuffer size\n");
95 sgivwfb_mem_size = 8 * MB;
96 }
97
98 /*
99 * Trim to nearest MB
100 */
101 sgivwfb_mem_size &= ~((1 << 20) - 1);
102 sgivwfb_mem_phys = mem_size - gfx_mem_size;
103
104 e820_add_region(0, LOWMEMSIZE(), E820_RAM);
105 e820_add_region(HIGH_MEMORY, mem_size - sgivwfb_mem_size - HIGH_MEMORY, E820_RAM);
106 e820_add_region(sgivwfb_mem_phys, sgivwfb_mem_size, E820_RESERVED);
107
108 return "PROM";
109}
110
111static void visws_machine_emergency_restart(void)
112{
113 /*
114 * Visual Workstations restart after this
115 * register is poked on the PIIX4
116 */
117 outb(PIIX4_RESET_VAL, PIIX4_RESET_PORT);
118}
119
120static void visws_machine_power_off(void)
121{
122 unsigned short pm_status;
123/* extern unsigned int pci_bus0; */
124
125 while ((pm_status = inw(PMSTS_PORT)) & 0x100)
126 outw(pm_status, PMSTS_PORT);
127
128 outw(PM_SUSPEND_ENABLE, PMCNTRL_PORT);
129
130 mdelay(10);
131
132#define PCI_CONF1_ADDRESS(bus, devfn, reg) \
133 (0x80000000 | (bus << 16) | (devfn << 8) | (reg & ~3))
134
135/* outl(PCI_CONF1_ADDRESS(pci_bus0, SPECIAL_DEV, SPECIAL_REG), 0xCF8); */
136 outl(PIIX_SPECIAL_STOP, 0xCFC);
137}
138
139static int __init visws_get_smp_config_quirk(unsigned int early)
140{
141 /*
142 * Prevent MP-table parsing by the generic code:
143 */
144 return 1;
145}
146
147extern unsigned int __cpuinitdata maxcpus;
148
149/*
150 * The Visual Workstation is Intel MP compliant in the hardware
151 * sense, but it doesn't have a BIOS(-configuration table).
152 * No problem for Linux.
153 */
154
155static void __init MP_processor_info (struct mpc_config_processor *m)
156{
157 int ver, logical_apicid;
158 physid_mask_t apic_cpus;
159
160 if (!(m->mpc_cpuflag & CPU_ENABLED))
161 return;
162
163 logical_apicid = m->mpc_apicid;
164 printk(KERN_INFO "%sCPU #%d %u:%u APIC version %d\n",
165 m->mpc_cpuflag & CPU_BOOTPROCESSOR ? "Bootup " : "",
166 m->mpc_apicid,
167 (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
168 (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
169 m->mpc_apicver);
170
171 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR)
172 boot_cpu_physical_apicid = m->mpc_apicid;
173
174 ver = m->mpc_apicver;
175 if ((ver >= 0x14 && m->mpc_apicid >= 0xff) || m->mpc_apicid >= 0xf) {
176 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
177 m->mpc_apicid, MAX_APICS);
178 return;
179 }
180
181 apic_cpus = apicid_to_cpu_present(m->mpc_apicid);
182 physids_or(phys_cpu_present_map, phys_cpu_present_map, apic_cpus);
183 /*
184 * Validate version
185 */
186 if (ver == 0x0) {
187 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! "
188 "fixing up to 0x10. (tell your hw vendor)\n",
189 m->mpc_apicid);
190 ver = 0x10;
191 }
192 apic_version[m->mpc_apicid] = ver;
193}
194
195int __init visws_find_smp_config_quirk(unsigned int reserve)
196{
197 struct mpc_config_processor *mp = phys_to_virt(CO_CPU_TAB_PHYS);
198 unsigned short ncpus = readw(phys_to_virt(CO_CPU_NUM_PHYS));
199
200 if (ncpus > CO_CPU_MAX) {
201 printk(KERN_WARNING "find_visws_smp: got cpu count of %d at %p\n",
202 ncpus, mp);
203
204 ncpus = CO_CPU_MAX;
205 }
206
207 if (ncpus > maxcpus)
208 ncpus = maxcpus;
209
210#ifdef CONFIG_X86_LOCAL_APIC
211 smp_found_config = 1;
212#endif
213 while (ncpus--)
214 MP_processor_info(mp++);
215
216 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
217
218 return 1;
219}
220
221extern int visws_trap_init_quirk(void);
222
223void __init visws_early_detect(void)
224{
225 int raw;
226
227 visws_board_type = (char)(inb_p(PIIX_GPI_BD_REG) & PIIX_GPI_BD_REG)
228 >> PIIX_GPI_BD_SHIFT;
229
230 if (visws_board_type < 0)
231 return;
232
233 /*
234 * Install special quirks for timer, interrupt and memory setup:
235 */
236 arch_time_init_quirk = visws_time_init_quirk;
237 arch_pre_intr_init_quirk = visws_pre_intr_init_quirk;
238 arch_memory_setup_quirk = visws_memory_setup_quirk;
239
240 /*
241 * Fall back to generic behavior for traps:
242 */
243 arch_intr_init_quirk = NULL;
244 arch_trap_init_quirk = visws_trap_init_quirk;
245
246 /*
247 * Install reboot quirks:
248 */
249 pm_power_off = visws_machine_power_off;
250 machine_ops.emergency_restart = visws_machine_emergency_restart;
251
252 /*
253 * Do not use broadcast IPIs:
254 */
255 no_broadcast = 0;
256
257 /*
258 * Override generic MP-table parsing:
259 */
260 mach_get_smp_config_quirk = visws_get_smp_config_quirk;
261 mach_find_smp_config_quirk = visws_find_smp_config_quirk;
262
263 /*
264 * Get Board rev.
265 * First, we have to initialize the 307 part to allow us access
266 * to the GPIO registers. Let's map them at 0x0fc0 which is right
267 * after the PIIX4 PM section.
268 */
269 outb_p(SIO_DEV_SEL, SIO_INDEX);
270 outb_p(SIO_GP_DEV, SIO_DATA); /* Talk to GPIO regs. */
271
272 outb_p(SIO_DEV_MSB, SIO_INDEX);
273 outb_p(SIO_GP_MSB, SIO_DATA); /* MSB of GPIO base address */
274
275 outb_p(SIO_DEV_LSB, SIO_INDEX);
276 outb_p(SIO_GP_LSB, SIO_DATA); /* LSB of GPIO base address */
277
278 outb_p(SIO_DEV_ENB, SIO_INDEX);
279 outb_p(1, SIO_DATA); /* Enable GPIO registers. */
280
281 /*
282 * Now, we have to map the power management section to write
283 * a bit which enables access to the GPIO registers.
284 * What lunatic came up with this shit?
285 */
286 outb_p(SIO_DEV_SEL, SIO_INDEX);
287 outb_p(SIO_PM_DEV, SIO_DATA); /* Talk to GPIO regs. */
288
289 outb_p(SIO_DEV_MSB, SIO_INDEX);
290 outb_p(SIO_PM_MSB, SIO_DATA); /* MSB of PM base address */
291
292 outb_p(SIO_DEV_LSB, SIO_INDEX);
293 outb_p(SIO_PM_LSB, SIO_DATA); /* LSB of PM base address */
294
295 outb_p(SIO_DEV_ENB, SIO_INDEX);
296 outb_p(1, SIO_DATA); /* Enable PM registers. */
297
298 /*
299 * Now, write the PM register which enables the GPIO registers.
300 */
301 outb_p(SIO_PM_FER2, SIO_PM_INDEX);
302 outb_p(SIO_PM_GP_EN, SIO_PM_DATA);
303
304 /*
305 * Now, initialize the GPIO registers.
306 * We want them all to be inputs which is the
307 * power on default, so let's leave them alone.
308 * So, let's just read the board rev!
309 */
310 raw = inb_p(SIO_GP_DATA1);
311 raw &= 0x7f; /* 7 bits of valid board revision ID. */
312
313 if (visws_board_type == VISWS_320) {
314 if (raw < 0x6) {
315 visws_board_rev = 4;
316 } else if (raw < 0xc) {
317 visws_board_rev = 5;
318 } else {
319 visws_board_rev = 6;
320 }
321 } else if (visws_board_type == VISWS_540) {
322 visws_board_rev = 2;
323 } else {
324 visws_board_rev = raw;
325 }
326
327 printk(KERN_INFO "Silicon Graphics Visual Workstation %s (rev %d) detected\n",
328 (visws_board_type == VISWS_320 ? "320" :
329 (visws_board_type == VISWS_540 ? "540" :
330 "unknown")), visws_board_rev);
331}
diff --git a/arch/x86/mach-visws/traps.c b/arch/x86/mach-visws/traps.c
deleted file mode 100644
index e5e6492c2676..000000000000
--- a/arch/x86/mach-visws/traps.c
+++ /dev/null
@@ -1,71 +0,0 @@
1/* VISWS traps */
2
3#include <linux/sched.h>
4#include <linux/kernel.h>
5#include <linux/init.h>
6#include <linux/pci.h>
7#include <linux/pci_ids.h>
8
9#include <asm/io.h>
10#include <asm/apic.h>
11#include <asm/arch_hooks.h>
12#include <asm/visws/cobalt.h>
13#include <asm/visws/lithium.h>
14
15
16#define A01234 (LI_INTA_0 | LI_INTA_1 | LI_INTA_2 | LI_INTA_3 | LI_INTA_4)
17#define BCD (LI_INTB | LI_INTC | LI_INTD)
18#define ALLDEVS (A01234 | BCD)
19
20static __init void lithium_init(void)
21{
22 set_fixmap(FIX_LI_PCIA, LI_PCI_A_PHYS);
23 set_fixmap(FIX_LI_PCIB, LI_PCI_B_PHYS);
24
25 if ((li_pcia_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
26 (li_pcia_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
27 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'A');
28/* panic("This machine is not SGI Visual Workstation 320/540"); */
29 }
30
31 if ((li_pcib_read16(PCI_VENDOR_ID) != PCI_VENDOR_ID_SGI) ||
32 (li_pcib_read16(PCI_DEVICE_ID) != PCI_DEVICE_ID_SGI_LITHIUM)) {
33 printk(KERN_EMERG "Lithium hostbridge %c not found\n", 'B');
34/* panic("This machine is not SGI Visual Workstation 320/540"); */
35 }
36
37 li_pcia_write16(LI_PCI_INTEN, ALLDEVS);
38 li_pcib_write16(LI_PCI_INTEN, ALLDEVS);
39}
40
41static __init void cobalt_init(void)
42{
43 /*
44 * On normal SMP PC this is used only with SMP, but we have to
45 * use it and set it up here to start the Cobalt clock
46 */
47 set_fixmap(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
48 setup_local_APIC();
49 printk(KERN_INFO "Local APIC Version %#x, ID %#x\n",
50 (unsigned int)apic_read(APIC_LVR),
51 (unsigned int)apic_read(APIC_ID));
52
53 set_fixmap(FIX_CO_CPU, CO_CPU_PHYS);
54 set_fixmap(FIX_CO_APIC, CO_APIC_PHYS);
55 printk(KERN_INFO "Cobalt Revision %#lx, APIC ID %#lx\n",
56 co_cpu_read(CO_CPU_REV), co_apic_read(CO_APIC_ID));
57
58 /* Enable Cobalt APIC being careful to NOT change the ID! */
59 co_apic_write(CO_APIC_ID, co_apic_read(CO_APIC_ID) | CO_APIC_ENABLE);
60
61 printk(KERN_INFO "Cobalt APIC enabled: ID reg %#lx\n",
62 co_apic_read(CO_APIC_ID));
63}
64
65int __init visws_trap_init_quirk(void)
66{
67 lithium_init();
68 cobalt_init();
69
70 return 1;
71}
diff --git a/arch/x86/mach-visws/visws_apic.c b/arch/x86/mach-visws/visws_apic.c
deleted file mode 100644
index 6c02c8d09932..000000000000
--- a/arch/x86/mach-visws/visws_apic.c
+++ /dev/null
@@ -1,295 +0,0 @@
1/*
2 * Copyright (C) 1999 Bent Hagemark, Ingo Molnar
3 *
4 * SGI Visual Workstation interrupt controller
5 *
6 * The Cobalt system ASIC in the Visual Workstation contains a "Cobalt" APIC
7 * which serves as the main interrupt controller in the system. Non-legacy
8 * hardware in the system uses this controller directly. Legacy devices
9 * are connected to the PIIX4 which in turn has its 8259(s) connected to
10 * a of the Cobalt APIC entry.
11 *
12 * 09/02/2000 - Updated for 2.4 by jbarnes@sgi.com
13 *
14 * 25/11/2002 - Updated for 2.5 by Andrey Panin <pazke@orbita1.ru>
15 */
16
17#include <linux/kernel_stat.h>
18#include <linux/interrupt.h>
19#include <linux/init.h>
20
21#include <asm/io.h>
22#include <asm/apic.h>
23#include <asm/i8259.h>
24#include <asm/irq_vectors.h>
25#include <asm/visws/cobalt.h>
26
27static DEFINE_SPINLOCK(cobalt_lock);
28
29/*
30 * Set the given Cobalt APIC Redirection Table entry to point
31 * to the given IDT vector/index.
32 */
33static inline void co_apic_set(int entry, int irq)
34{
35 co_apic_write(CO_APIC_LO(entry), CO_APIC_LEVEL | (irq + FIRST_EXTERNAL_VECTOR));
36 co_apic_write(CO_APIC_HI(entry), 0);
37}
38
39/*
40 * Cobalt (IO)-APIC functions to handle PCI devices.
41 */
42static inline int co_apic_ide0_hack(void)
43{
44 extern char visws_board_type;
45 extern char visws_board_rev;
46
47 if (visws_board_type == VISWS_320 && visws_board_rev == 5)
48 return 5;
49 return CO_APIC_IDE0;
50}
51
52static int is_co_apic(unsigned int irq)
53{
54 if (IS_CO_APIC(irq))
55 return CO_APIC(irq);
56
57 switch (irq) {
58 case 0: return CO_APIC_CPU;
59 case CO_IRQ_IDE0: return co_apic_ide0_hack();
60 case CO_IRQ_IDE1: return CO_APIC_IDE1;
61 default: return -1;
62 }
63}
64
65
66/*
67 * This is the SGI Cobalt (IO-)APIC:
68 */
69
70static void enable_cobalt_irq(unsigned int irq)
71{
72 co_apic_set(is_co_apic(irq), irq);
73}
74
75static void disable_cobalt_irq(unsigned int irq)
76{
77 int entry = is_co_apic(irq);
78
79 co_apic_write(CO_APIC_LO(entry), CO_APIC_MASK);
80 co_apic_read(CO_APIC_LO(entry));
81}
82
83/*
84 * "irq" really just serves to identify the device. Here is where we
85 * map this to the Cobalt APIC entry where it's physically wired.
86 * This is called via request_irq -> setup_irq -> irq_desc->startup()
87 */
88static unsigned int startup_cobalt_irq(unsigned int irq)
89{
90 unsigned long flags;
91
92 spin_lock_irqsave(&cobalt_lock, flags);
93 if ((irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING)))
94 irq_desc[irq].status &= ~(IRQ_DISABLED | IRQ_INPROGRESS | IRQ_WAITING);
95 enable_cobalt_irq(irq);
96 spin_unlock_irqrestore(&cobalt_lock, flags);
97 return 0;
98}
99
100static void ack_cobalt_irq(unsigned int irq)
101{
102 unsigned long flags;
103
104 spin_lock_irqsave(&cobalt_lock, flags);
105 disable_cobalt_irq(irq);
106 apic_write(APIC_EOI, APIC_EIO_ACK);
107 spin_unlock_irqrestore(&cobalt_lock, flags);
108}
109
110static void end_cobalt_irq(unsigned int irq)
111{
112 unsigned long flags;
113
114 spin_lock_irqsave(&cobalt_lock, flags);
115 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
116 enable_cobalt_irq(irq);
117 spin_unlock_irqrestore(&cobalt_lock, flags);
118}
119
120static struct irq_chip cobalt_irq_type = {
121 .typename = "Cobalt-APIC",
122 .startup = startup_cobalt_irq,
123 .shutdown = disable_cobalt_irq,
124 .enable = enable_cobalt_irq,
125 .disable = disable_cobalt_irq,
126 .ack = ack_cobalt_irq,
127 .end = end_cobalt_irq,
128};
129
130
131/*
132 * This is the PIIX4-based 8259 that is wired up indirectly to Cobalt
133 * -- not the manner expected by the code in i8259.c.
134 *
135 * there is a 'master' physical interrupt source that gets sent to
136 * the CPU. But in the chipset there are various 'virtual' interrupts
137 * waiting to be handled. We represent this to Linux through a 'master'
138 * interrupt controller type, and through a special virtual interrupt-
139 * controller. Device drivers only see the virtual interrupt sources.
140 */
141static unsigned int startup_piix4_master_irq(unsigned int irq)
142{
143 init_8259A(0);
144
145 return startup_cobalt_irq(irq);
146}
147
148static void end_piix4_master_irq(unsigned int irq)
149{
150 unsigned long flags;
151
152 spin_lock_irqsave(&cobalt_lock, flags);
153 enable_cobalt_irq(irq);
154 spin_unlock_irqrestore(&cobalt_lock, flags);
155}
156
157static struct irq_chip piix4_master_irq_type = {
158 .typename = "PIIX4-master",
159 .startup = startup_piix4_master_irq,
160 .ack = ack_cobalt_irq,
161 .end = end_piix4_master_irq,
162};
163
164
165static struct irq_chip piix4_virtual_irq_type = {
166 .typename = "PIIX4-virtual",
167 .shutdown = disable_8259A_irq,
168 .enable = enable_8259A_irq,
169 .disable = disable_8259A_irq,
170};
171
172
173/*
174 * PIIX4-8259 master/virtual functions to handle interrupt requests
175 * from legacy devices: floppy, parallel, serial, rtc.
176 *
177 * None of these get Cobalt APIC entries, neither do they have IDT
178 * entries. These interrupts are purely virtual and distributed from
179 * the 'master' interrupt source: CO_IRQ_8259.
180 *
181 * When the 8259 interrupts its handler figures out which of these
182 * devices is interrupting and dispatches to its handler.
183 *
184 * CAREFUL: devices see the 'virtual' interrupt only. Thus disable/
185 * enable_irq gets the right irq. This 'master' irq is never directly
186 * manipulated by any driver.
187 */
188static irqreturn_t piix4_master_intr(int irq, void *dev_id)
189{
190 int realirq;
191 irq_desc_t *desc;
192 unsigned long flags;
193
194 spin_lock_irqsave(&i8259A_lock, flags);
195
196 /* Find out what's interrupting in the PIIX4 master 8259 */
197 outb(0x0c, 0x20); /* OCW3 Poll command */
198 realirq = inb(0x20);
199
200 /*
201 * Bit 7 == 0 means invalid/spurious
202 */
203 if (unlikely(!(realirq & 0x80)))
204 goto out_unlock;
205
206 realirq &= 7;
207
208 if (unlikely(realirq == 2)) {
209 outb(0x0c, 0xa0);
210 realirq = inb(0xa0);
211
212 if (unlikely(!(realirq & 0x80)))
213 goto out_unlock;
214
215 realirq = (realirq & 7) + 8;
216 }
217
218 /* mask and ack interrupt */
219 cached_irq_mask |= 1 << realirq;
220 if (unlikely(realirq > 7)) {
221 inb(0xa1);
222 outb(cached_slave_mask, 0xa1);
223 outb(0x60 + (realirq & 7), 0xa0);
224 outb(0x60 + 2, 0x20);
225 } else {
226 inb(0x21);
227 outb(cached_master_mask, 0x21);
228 outb(0x60 + realirq, 0x20);
229 }
230
231 spin_unlock_irqrestore(&i8259A_lock, flags);
232
233 desc = irq_desc + realirq;
234
235 /*
236 * handle this 'virtual interrupt' as a Cobalt one now.
237 */
238 kstat_cpu(smp_processor_id()).irqs[realirq]++;
239
240 if (likely(desc->action != NULL))
241 handle_IRQ_event(realirq, desc->action);
242
243 if (!(desc->status & IRQ_DISABLED))
244 enable_8259A_irq(realirq);
245
246 return IRQ_HANDLED;
247
248out_unlock:
249 spin_unlock_irqrestore(&i8259A_lock, flags);
250 return IRQ_NONE;
251}
252
253static struct irqaction master_action = {
254 .handler = piix4_master_intr,
255 .name = "PIIX4-8259",
256};
257
258static struct irqaction cascade_action = {
259 .handler = no_action,
260 .name = "cascade",
261};
262
263
264void init_VISWS_APIC_irqs(void)
265{
266 int i;
267
268 for (i = 0; i < CO_IRQ_APIC0 + CO_APIC_LAST + 1; i++) {
269 irq_desc[i].status = IRQ_DISABLED;
270 irq_desc[i].action = 0;
271 irq_desc[i].depth = 1;
272
273 if (i == 0) {
274 irq_desc[i].chip = &cobalt_irq_type;
275 }
276 else if (i == CO_IRQ_IDE0) {
277 irq_desc[i].chip = &cobalt_irq_type;
278 }
279 else if (i == CO_IRQ_IDE1) {
280 irq_desc[i].chip = &cobalt_irq_type;
281 }
282 else if (i == CO_IRQ_8259) {
283 irq_desc[i].chip = &piix4_master_irq_type;
284 }
285 else if (i < CO_IRQ_APIC0) {
286 irq_desc[i].chip = &piix4_virtual_irq_type;
287 }
288 else if (IS_CO_APIC(i)) {
289 irq_desc[i].chip = &cobalt_irq_type;
290 }
291 }
292
293 setup_irq(CO_IRQ_8259, &master_action);
294 setup_irq(2, &cascade_action);
295}
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index c03c2094864f..e515e8db842a 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -9,8 +9,6 @@ pci-y := fixup.o
9pci-$(CONFIG_ACPI) += acpi.o 9pci-$(CONFIG_ACPI) += acpi.o
10pci-y += legacy.o irq.o 10pci-y += legacy.o irq.o
11 11
12# Careful: VISWS overrule the pci-y above. The colons are
13# therefor correct. This needs a proper fix by distangling the code.
14pci-$(CONFIG_X86_VISWS) += visws.o 12pci-$(CONFIG_X86_VISWS) += visws.o
15 13
16pci-$(CONFIG_X86_NUMAQ) += numa.o 14pci-$(CONFIG_X86_NUMAQ) += numa.o
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-27 07:14:38 -0500