x86_64: move pci

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

4 files changed, 258 insertions, 1 deletions

diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index b3e54c45d408..c5c8e485fc44 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -1,5 +1,5 @@
 ifeq ($(CONFIG_X86_32),y)
 include ${srctree}/arch/x86/pci/Makefile_32
 else
-include ${srctree}/arch/x86_64/pci/Makefile_64
+include ${srctree}/arch/x86/pci/Makefile_64
 endif
diff --git a/arch/x86/pci/Makefile_64 b/arch/x86/pci/Makefile_64
new file mode 100644
index 000000000000..7d8c467bf143
--- /dev/null
+++ b/arch/x86/pci/Makefile_64
@@ -0,0 +1,17 @@
+#
+# Makefile for X86_64 specific PCI routines
+#
+# Reuse the i386 PCI subsystem
+#
+EXTRA_CFLAGS += -Iarch/x86/pci
+
+obj-y           := i386.o
+obj-$(CONFIG_PCI_DIRECT)+= direct.o
+obj-y           += fixup.o init.o
+obj-$(CONFIG_ACPI)      += acpi.o
+obj-y                   += legacy.o irq.o common.o early.o
+# mmconfig has a 64bit special
+obj-$(CONFIG_PCI_MMCONFIG) += mmconfig_64.o direct.o mmconfig-shared.o
+
+obj-$(CONFIG_NUMA)      += k8-bus_64.o
+
diff --git a/arch/x86/pci/k8-bus_64.c b/arch/x86/pci/k8-bus_64.c
new file mode 100644
index 000000000000..9cc813e29706
--- /dev/null
+++ b/arch/x86/pci/k8-bus_64.c
@@ -0,0 +1,83 @@
+#include <linux/init.h>
+#include <linux/pci.h>
+#include <asm/mpspec.h>
+#include <linux/cpumask.h>
+
+/*
+ * This discovers the pcibus <-> node mapping on AMD K8.
+ *
+ * RED-PEN need to call this again on PCI hotplug
+ * RED-PEN empty cpus get reported wrong
+ */
+
+#define NODE_ID_REGISTER 0x60
+#define NODE_ID(dword) (dword & 0x07)
+#define LDT_BUS_NUMBER_REGISTER_0 0x94
+#define LDT_BUS_NUMBER_REGISTER_1 0xB4
+#define LDT_BUS_NUMBER_REGISTER_2 0xD4
+#define NR_LDT_BUS_NUMBER_REGISTERS 3
+#define SECONDARY_LDT_BUS_NUMBER(dword) ((dword >> 8) & 0xFF)
+#define SUBORDINATE_LDT_BUS_NUMBER(dword) ((dword >> 16) & 0xFF)
+#define PCI_DEVICE_ID_K8HTCONFIG 0x1100
+
+/**
+ * fill_mp_bus_to_cpumask()
+ * fills the mp_bus_to_cpumask array based according to the LDT Bus Number
+ * Registers found in the K8 northbridge
+ */
+__init static int
+fill_mp_bus_to_cpumask(void)
+{
+        struct pci_dev *nb_dev = NULL;
+        int i, j;
+        u32 ldtbus, nid;
+        static int lbnr[3] = {
+                LDT_BUS_NUMBER_REGISTER_0,
+                LDT_BUS_NUMBER_REGISTER_1,
+                LDT_BUS_NUMBER_REGISTER_2
+        };
+
+        while ((nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
+                        PCI_DEVICE_ID_K8HTCONFIG, nb_dev))) {
+                pci_read_config_dword(nb_dev, NODE_ID_REGISTER, &nid);
+
+                for (i = 0; i < NR_LDT_BUS_NUMBER_REGISTERS; i++) {
+                        pci_read_config_dword(nb_dev, lbnr[i], &ldtbus);
+                        /*
+                         * if there are no busses hanging off of the current
+                         * ldt link then both the secondary and subordinate
+                         * bus number fields are set to 0.
+                         * 
+                         * RED-PEN
+                         * This is slightly broken because it assumes
+                         * HT node IDs == Linux node ids, which is not always
+                         * true. However it is probably mostly true.
+                         */
+                        if (!(SECONDARY_LDT_BUS_NUMBER(ldtbus) == 0
+                                && SUBORDINATE_LDT_BUS_NUMBER(ldtbus) == 0)) {
+                                for (j = SECONDARY_LDT_BUS_NUMBER(ldtbus);
+                                     j <= SUBORDINATE_LDT_BUS_NUMBER(ldtbus);
+                                     j++) { 
+                                        struct pci_bus *bus;
+                                        struct pci_sysdata *sd;
+
+                                        long node = NODE_ID(nid);
+                                        /* Algorithm a bit dumb, but
+                                           it shouldn't matter here */
+                                        bus = pci_find_bus(0, j);
+                                        if (!bus)
+                                                continue;
+                                        if (!node_online(node))
+                                                node = 0;
+
+                                        sd = bus->sysdata;
+                                        sd->node = node;
+                                }               
+                        }
+                }
+        }
+
+        return 0;
+}
+
+fs_initcall(fill_mp_bus_to_cpumask);
diff --git a/arch/x86/pci/mmconfig_64.c b/arch/x86/pci/mmconfig_64.c
new file mode 100644
index 000000000000..4095e4d66a1d
--- /dev/null
+++ b/arch/x86/pci/mmconfig_64.c
@@ -0,0 +1,157 @@
+/*
+ * mmconfig.c - Low-level direct PCI config space access via MMCONFIG
+ *
+ * This is an 64bit optimized version that always keeps the full mmconfig
+ * space mapped. This allows lockless config space operation.
+ */
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/acpi.h>
+#include <linux/bitmap.h>
+#include <asm/e820.h>
+
+#include "pci.h"
+
+/* Static virtual mapping of the MMCONFIG aperture */
+struct mmcfg_virt {
+        struct acpi_mcfg_allocation *cfg;
+        char __iomem *virt;
+};
+static struct mmcfg_virt *pci_mmcfg_virt;
+
+static char __iomem *get_virt(unsigned int seg, unsigned bus)
+{
+        struct acpi_mcfg_allocation *cfg;
+        int cfg_num;
+
+        for (cfg_num = 0; cfg_num < pci_mmcfg_config_num; cfg_num++) {
+                cfg = pci_mmcfg_virt[cfg_num].cfg;
+                if (cfg->pci_segment == seg &&
+                    (cfg->start_bus_number <= bus) &&
+                    (cfg->end_bus_number >= bus))
+                        return pci_mmcfg_virt[cfg_num].virt;
+        }
+
+        /* Fall back to type 0 */
+        return NULL;
+}
+
+static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
+{
+        char __iomem *addr;
+        if (seg == 0 && bus < PCI_MMCFG_MAX_CHECK_BUS &&
+                test_bit(32*bus + PCI_SLOT(devfn), pci_mmcfg_fallback_slots))
+                return NULL;
+        addr = get_virt(seg, bus);
+        if (!addr)
+                return NULL;
+        return addr + ((bus << 20) | (devfn << 12));
+}
+
+static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
+                          unsigned int devfn, int reg, int len, u32 *value)
+{
+        char __iomem *addr;
+
+        /* Why do we have this when nobody checks it. How about a BUG()!? -AK */
+        if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095))) {
+                *value = -1;
+                return -EINVAL;
+        }
+
+        addr = pci_dev_base(seg, bus, devfn);
+        if (!addr)
+                return pci_conf1_read(seg,bus,devfn,reg,len,value);
+
+        switch (len) {
+        case 1:
+                *value = mmio_config_readb(addr + reg);
+                break;
+        case 2:
+                *value = mmio_config_readw(addr + reg);
+                break;
+        case 4:
+                *value = mmio_config_readl(addr + reg);
+                break;
+        }
+
+        return 0;
+}
+
+static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
+                           unsigned int devfn, int reg, int len, u32 value)
+{
+        char __iomem *addr;
+
+        /* Why do we have this when nobody checks it. How about a BUG()!? -AK */
+        if (unlikely((bus > 255) || (devfn > 255) || (reg > 4095)))
+                return -EINVAL;
+
+        addr = pci_dev_base(seg, bus, devfn);
+        if (!addr)
+                return pci_conf1_write(seg,bus,devfn,reg,len,value);
+
+        switch (len) {
+        case 1:
+                mmio_config_writeb(addr + reg, value);
+                break;
+        case 2:
+                mmio_config_writew(addr + reg, value);
+                break;
+        case 4:
+                mmio_config_writel(addr + reg, value);
+                break;
+        }
+
+        return 0;
+}
+
+static struct pci_raw_ops pci_mmcfg = {
+        .read =         pci_mmcfg_read,
+        .write =        pci_mmcfg_write,
+};
+
+static void __iomem * __init mcfg_ioremap(struct acpi_mcfg_allocation *cfg)
+{
+        void __iomem *addr;
+        u32 size;
+
+        size = (cfg->end_bus_number + 1) << 20;
+        addr = ioremap_nocache(cfg->address, size);
+        if (addr) {
+                printk(KERN_INFO "PCI: Using MMCONFIG at %Lx - %Lx\n",
+                       cfg->address, cfg->address + size - 1);
+        }
+        return addr;
+}
+
+int __init pci_mmcfg_arch_reachable(unsigned int seg, unsigned int bus,
+                                    unsigned int devfn)
+{
+        return pci_dev_base(seg, bus, devfn) != NULL;
+}
+
+int __init pci_mmcfg_arch_init(void)
+{
+        int i;
+        pci_mmcfg_virt = kmalloc(sizeof(*pci_mmcfg_virt) *
+                                 pci_mmcfg_config_num, GFP_KERNEL);
+        if (pci_mmcfg_virt == NULL) {
+                printk(KERN_ERR "PCI: Can not allocate memory for mmconfig structures\n");
+                return 0;
+        }
+
+        for (i = 0; i < pci_mmcfg_config_num; ++i) {
+                pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
+                pci_mmcfg_virt[i].virt = mcfg_ioremap(&pci_mmcfg_config[i]);
+                if (!pci_mmcfg_virt[i].virt) {
+                        printk(KERN_ERR "PCI: Cannot map mmconfig aperture for "
+                                        "segment %d\n",
+                                pci_mmcfg_config[i].pci_segment);
+                        return 0;
+                }
+        }
+        raw_pci_ops = &pci_mmcfg;
+        return 1;
+}