diff options
author | Ingo Molnar <mingo@elte.hu> | 2009-01-27 22:09:58 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2009-01-28 17:20:13 -0500 |
commit | 9b5bc8dc12421a4b17047061f473d85c1797d543 (patch) | |
tree | 69799378fb9e55dd8c23ceb39c646d7bf47523f8 /arch/x86 | |
parent | f8987a1093cc7a896137e264c24e04d4048e9f95 (diff) |
x86, apic: remove IRQ_DEST_MODE / IRQ_DELIVERY_MODE
Remove the wrapper macros IRQ_DEST_MODE and IRQ_DELIVERY_MODE.
The typical 32-bit and the 64-bit build all dereference via the genapic,
so it's pointless to hide that indirection via these ugly macros.
Furthermore, it also obscures subarchitecture details.
So replace it with apic->irq_dest_mode / etc. accesses.
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/include/asm/bigsmp/apic.h | 4 | ||||
-rw-r--r-- | arch/x86/include/asm/es7000/apic.h | 4 | ||||
-rw-r--r-- | arch/x86/include/asm/mach-default/mach_apic.h | 5 | ||||
-rw-r--r-- | arch/x86/include/asm/mach-generic/mach_apic.h | 2 | ||||
-rw-r--r-- | arch/x86/include/asm/numaq/apic.h | 4 | ||||
-rw-r--r-- | arch/x86/include/asm/summit/apic.h | 4 | ||||
-rw-r--r-- | arch/x86/kernel/io_apic.c | 30 | ||||
-rw-r--r-- | arch/x86/mach-generic/bigsmp.c | 4 | ||||
-rw-r--r-- | arch/x86/mach-generic/default.c | 4 | ||||
-rw-r--r-- | arch/x86/mach-generic/es7000.c | 4 | ||||
-rw-r--r-- | arch/x86/mach-generic/numaq.c | 4 | ||||
-rw-r--r-- | arch/x86/mach-generic/summit.c | 4 |
12 files changed, 35 insertions, 38 deletions
diff --git a/arch/x86/include/asm/bigsmp/apic.h b/arch/x86/include/asm/bigsmp/apic.h index 8ff8bba88338..293551b0e610 100644 --- a/arch/x86/include/asm/bigsmp/apic.h +++ b/arch/x86/include/asm/bigsmp/apic.h | |||
@@ -21,8 +21,8 @@ static inline const cpumask_t *target_cpus(void) | |||
21 | #undef APIC_DEST_LOGICAL | 21 | #undef APIC_DEST_LOGICAL |
22 | #define APIC_DEST_LOGICAL 0 | 22 | #define APIC_DEST_LOGICAL 0 |
23 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | 23 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) |
24 | #define IRQ_DELIVERY_MODE (dest_Fixed) | 24 | #define BIGSMP_IRQ_DELIVERY_MODE (dest_Fixed) |
25 | #define IRQ_DEST_MODE (0) /* phys delivery to target proc */ | 25 | #define BIGSMP_IRQ_DEST_MODE (0) /* phys delivery to target proc */ |
26 | #define NO_BALANCE_IRQ (0) | 26 | #define NO_BALANCE_IRQ (0) |
27 | 27 | ||
28 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) | 28 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) |
diff --git a/arch/x86/include/asm/es7000/apic.h b/arch/x86/include/asm/es7000/apic.h index 830e8731cc05..690016683f21 100644 --- a/arch/x86/include/asm/es7000/apic.h +++ b/arch/x86/include/asm/es7000/apic.h | |||
@@ -27,8 +27,8 @@ static inline const cpumask_t *target_cpus(void) | |||
27 | #define NO_BALANCE_IRQ_CLUSTER (1) | 27 | #define NO_BALANCE_IRQ_CLUSTER (1) |
28 | 28 | ||
29 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) | 29 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) |
30 | #define IRQ_DELIVERY_MODE (dest_Fixed) | 30 | #define ES7000_IRQ_DELIVERY_MODE (dest_Fixed) |
31 | #define IRQ_DEST_MODE (0) /* phys delivery to target procs */ | 31 | #define ES7000_IRQ_DEST_MODE (0) /* phys delivery to target procs */ |
32 | #define NO_BALANCE_IRQ (0) | 32 | #define NO_BALANCE_IRQ (0) |
33 | #undef APIC_DEST_LOGICAL | 33 | #undef APIC_DEST_LOGICAL |
34 | #define APIC_DEST_LOGICAL 0x0 | 34 | #define APIC_DEST_LOGICAL 0x0 |
diff --git a/arch/x86/include/asm/mach-default/mach_apic.h b/arch/x86/include/asm/mach-default/mach_apic.h index b5364793262a..eafbf4f20387 100644 --- a/arch/x86/include/asm/mach-default/mach_apic.h +++ b/arch/x86/include/asm/mach-default/mach_apic.h | |||
@@ -22,7 +22,6 @@ static inline const struct cpumask *target_cpus(void) | |||
22 | 22 | ||
23 | #ifdef CONFIG_X86_64 | 23 | #ifdef CONFIG_X86_64 |
24 | #include <asm/genapic.h> | 24 | #include <asm/genapic.h> |
25 | #define IRQ_DELIVERY_MODE (apic->irq_delivery_mode) | ||
26 | #define IRQ_DEST_MODE (apic->irq_dest_mode) | 25 | #define IRQ_DEST_MODE (apic->irq_dest_mode) |
27 | #define TARGET_CPUS (apic->target_cpus()) | 26 | #define TARGET_CPUS (apic->target_cpus()) |
28 | #define init_apic_ldr (apic->init_apic_ldr) | 27 | #define init_apic_ldr (apic->init_apic_ldr) |
@@ -35,8 +34,8 @@ static inline const struct cpumask *target_cpus(void) | |||
35 | #define wakeup_secondary_cpu (apic->wakeup_cpu) | 34 | #define wakeup_secondary_cpu (apic->wakeup_cpu) |
36 | extern void setup_apic_routing(void); | 35 | extern void setup_apic_routing(void); |
37 | #else | 36 | #else |
38 | #define IRQ_DELIVERY_MODE dest_LowestPrio | 37 | #define DEFAULT_IRQ_DELIVERY_MODE dest_LowestPrio |
39 | #define IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */ | 38 | #define DEFAULT_IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */ |
40 | #define TARGET_CPUS (target_cpus()) | 39 | #define TARGET_CPUS (target_cpus()) |
41 | #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init | 40 | #define wakeup_secondary_cpu wakeup_secondary_cpu_via_init |
42 | /* | 41 | /* |
diff --git a/arch/x86/include/asm/mach-generic/mach_apic.h b/arch/x86/include/asm/mach-generic/mach_apic.h index 03492f2219ed..387a5d00c43d 100644 --- a/arch/x86/include/asm/mach-generic/mach_apic.h +++ b/arch/x86/include/asm/mach-generic/mach_apic.h | |||
@@ -5,8 +5,6 @@ | |||
5 | 5 | ||
6 | #define esr_disable (apic->ESR_DISABLE) | 6 | #define esr_disable (apic->ESR_DISABLE) |
7 | #define NO_BALANCE_IRQ (apic->no_balance_irq) | 7 | #define NO_BALANCE_IRQ (apic->no_balance_irq) |
8 | #define IRQ_DELIVERY_MODE (apic->irq_delivery_mode) | ||
9 | #define IRQ_DEST_MODE (apic->irq_dest_mode) | ||
10 | #undef APIC_DEST_LOGICAL | 8 | #undef APIC_DEST_LOGICAL |
11 | #define APIC_DEST_LOGICAL (apic->apic_destination_logical) | 9 | #define APIC_DEST_LOGICAL (apic->apic_destination_logical) |
12 | #define TARGET_CPUS (apic->target_cpus()) | 10 | #define TARGET_CPUS (apic->target_cpus()) |
diff --git a/arch/x86/include/asm/numaq/apic.h b/arch/x86/include/asm/numaq/apic.h index d885e35df18e..7746035c5911 100644 --- a/arch/x86/include/asm/numaq/apic.h +++ b/arch/x86/include/asm/numaq/apic.h | |||
@@ -15,8 +15,8 @@ static inline const cpumask_t *target_cpus(void) | |||
15 | #define NO_BALANCE_IRQ (1) | 15 | #define NO_BALANCE_IRQ (1) |
16 | #define esr_disable (1) | 16 | #define esr_disable (1) |
17 | 17 | ||
18 | #define IRQ_DELIVERY_MODE dest_LowestPrio | 18 | #define NUMAQ_IRQ_DELIVERY_MODE dest_LowestPrio |
19 | #define IRQ_DEST_MODE 0 /* physical delivery on LOCAL quad */ | 19 | #define NUMAQ_IRQ_DEST_MODE 0 /* physical delivery on LOCAL quad */ |
20 | 20 | ||
21 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) | 21 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) |
22 | { | 22 | { |
diff --git a/arch/x86/include/asm/summit/apic.h b/arch/x86/include/asm/summit/apic.h index 0b7d0d14e568..ea2abe9b5979 100644 --- a/arch/x86/include/asm/summit/apic.h +++ b/arch/x86/include/asm/summit/apic.h | |||
@@ -24,8 +24,8 @@ static inline const cpumask_t *target_cpus(void) | |||
24 | return &cpumask_of_cpu(0); | 24 | return &cpumask_of_cpu(0); |
25 | } | 25 | } |
26 | 26 | ||
27 | #define IRQ_DELIVERY_MODE (dest_LowestPrio) | 27 | #define SUMMIT_IRQ_DELIVERY_MODE (dest_LowestPrio) |
28 | #define IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */ | 28 | #define SUMMIT_IRQ_DEST_MODE 1 /* logical delivery broadcast to all procs */ |
29 | 29 | ||
30 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) | 30 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) |
31 | { | 31 | { |
diff --git a/arch/x86/kernel/io_apic.c b/arch/x86/kernel/io_apic.c index 5f967b9c9afd..301b6571d700 100644 --- a/arch/x86/kernel/io_apic.c +++ b/arch/x86/kernel/io_apic.c | |||
@@ -1514,9 +1514,9 @@ static int setup_ioapic_entry(int apic_id, int irq, | |||
1514 | memset(&irte, 0, sizeof(irte)); | 1514 | memset(&irte, 0, sizeof(irte)); |
1515 | 1515 | ||
1516 | irte.present = 1; | 1516 | irte.present = 1; |
1517 | irte.dst_mode = IRQ_DEST_MODE; | 1517 | irte.dst_mode = apic->irq_dest_mode; |
1518 | irte.trigger_mode = trigger; | 1518 | irte.trigger_mode = trigger; |
1519 | irte.dlvry_mode = IRQ_DELIVERY_MODE; | 1519 | irte.dlvry_mode = apic->irq_delivery_mode; |
1520 | irte.vector = vector; | 1520 | irte.vector = vector; |
1521 | irte.dest_id = IRTE_DEST(destination); | 1521 | irte.dest_id = IRTE_DEST(destination); |
1522 | 1522 | ||
@@ -1529,8 +1529,8 @@ static int setup_ioapic_entry(int apic_id, int irq, | |||
1529 | } else | 1529 | } else |
1530 | #endif | 1530 | #endif |
1531 | { | 1531 | { |
1532 | entry->delivery_mode = IRQ_DELIVERY_MODE; | 1532 | entry->delivery_mode = apic->irq_delivery_mode; |
1533 | entry->dest_mode = IRQ_DEST_MODE; | 1533 | entry->dest_mode = apic->irq_dest_mode; |
1534 | entry->dest = destination; | 1534 | entry->dest = destination; |
1535 | } | 1535 | } |
1536 | 1536 | ||
@@ -1659,10 +1659,10 @@ static void __init setup_timer_IRQ0_pin(unsigned int apic_id, unsigned int pin, | |||
1659 | * We use logical delivery to get the timer IRQ | 1659 | * We use logical delivery to get the timer IRQ |
1660 | * to the first CPU. | 1660 | * to the first CPU. |
1661 | */ | 1661 | */ |
1662 | entry.dest_mode = IRQ_DEST_MODE; | 1662 | entry.dest_mode = apic->irq_dest_mode; |
1663 | entry.mask = 1; /* mask IRQ now */ | 1663 | entry.mask = 1; /* mask IRQ now */ |
1664 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); | 1664 | entry.dest = cpu_mask_to_apicid(TARGET_CPUS); |
1665 | entry.delivery_mode = IRQ_DELIVERY_MODE; | 1665 | entry.delivery_mode = apic->irq_delivery_mode; |
1666 | entry.polarity = 0; | 1666 | entry.polarity = 0; |
1667 | entry.trigger = 0; | 1667 | entry.trigger = 0; |
1668 | entry.vector = vector; | 1668 | entry.vector = vector; |
@@ -3279,9 +3279,9 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms | |||
3279 | memset (&irte, 0, sizeof(irte)); | 3279 | memset (&irte, 0, sizeof(irte)); |
3280 | 3280 | ||
3281 | irte.present = 1; | 3281 | irte.present = 1; |
3282 | irte.dst_mode = IRQ_DEST_MODE; | 3282 | irte.dst_mode = apic->irq_dest_mode; |
3283 | irte.trigger_mode = 0; /* edge */ | 3283 | irte.trigger_mode = 0; /* edge */ |
3284 | irte.dlvry_mode = IRQ_DELIVERY_MODE; | 3284 | irte.dlvry_mode = apic->irq_delivery_mode; |
3285 | irte.vector = cfg->vector; | 3285 | irte.vector = cfg->vector; |
3286 | irte.dest_id = IRTE_DEST(dest); | 3286 | irte.dest_id = IRTE_DEST(dest); |
3287 | 3287 | ||
@@ -3299,10 +3299,10 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms | |||
3299 | msg->address_hi = MSI_ADDR_BASE_HI; | 3299 | msg->address_hi = MSI_ADDR_BASE_HI; |
3300 | msg->address_lo = | 3300 | msg->address_lo = |
3301 | MSI_ADDR_BASE_LO | | 3301 | MSI_ADDR_BASE_LO | |
3302 | ((IRQ_DEST_MODE == 0) ? | 3302 | ((apic->irq_dest_mode == 0) ? |
3303 | MSI_ADDR_DEST_MODE_PHYSICAL: | 3303 | MSI_ADDR_DEST_MODE_PHYSICAL: |
3304 | MSI_ADDR_DEST_MODE_LOGICAL) | | 3304 | MSI_ADDR_DEST_MODE_LOGICAL) | |
3305 | ((IRQ_DELIVERY_MODE != dest_LowestPrio) ? | 3305 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
3306 | MSI_ADDR_REDIRECTION_CPU: | 3306 | MSI_ADDR_REDIRECTION_CPU: |
3307 | MSI_ADDR_REDIRECTION_LOWPRI) | | 3307 | MSI_ADDR_REDIRECTION_LOWPRI) | |
3308 | MSI_ADDR_DEST_ID(dest); | 3308 | MSI_ADDR_DEST_ID(dest); |
@@ -3310,7 +3310,7 @@ static int msi_compose_msg(struct pci_dev *pdev, unsigned int irq, struct msi_ms | |||
3310 | msg->data = | 3310 | msg->data = |
3311 | MSI_DATA_TRIGGER_EDGE | | 3311 | MSI_DATA_TRIGGER_EDGE | |
3312 | MSI_DATA_LEVEL_ASSERT | | 3312 | MSI_DATA_LEVEL_ASSERT | |
3313 | ((IRQ_DELIVERY_MODE != dest_LowestPrio) ? | 3313 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
3314 | MSI_DATA_DELIVERY_FIXED: | 3314 | MSI_DATA_DELIVERY_FIXED: |
3315 | MSI_DATA_DELIVERY_LOWPRI) | | 3315 | MSI_DATA_DELIVERY_LOWPRI) | |
3316 | MSI_DATA_VECTOR(cfg->vector); | 3316 | MSI_DATA_VECTOR(cfg->vector); |
@@ -3711,11 +3711,11 @@ int arch_setup_ht_irq(unsigned int irq, struct pci_dev *dev) | |||
3711 | HT_IRQ_LOW_BASE | | 3711 | HT_IRQ_LOW_BASE | |
3712 | HT_IRQ_LOW_DEST_ID(dest) | | 3712 | HT_IRQ_LOW_DEST_ID(dest) | |
3713 | HT_IRQ_LOW_VECTOR(cfg->vector) | | 3713 | HT_IRQ_LOW_VECTOR(cfg->vector) | |
3714 | ((IRQ_DEST_MODE == 0) ? | 3714 | ((apic->irq_dest_mode == 0) ? |
3715 | HT_IRQ_LOW_DM_PHYSICAL : | 3715 | HT_IRQ_LOW_DM_PHYSICAL : |
3716 | HT_IRQ_LOW_DM_LOGICAL) | | 3716 | HT_IRQ_LOW_DM_LOGICAL) | |
3717 | HT_IRQ_LOW_RQEOI_EDGE | | 3717 | HT_IRQ_LOW_RQEOI_EDGE | |
3718 | ((IRQ_DELIVERY_MODE != dest_LowestPrio) ? | 3718 | ((apic->irq_delivery_mode != dest_LowestPrio) ? |
3719 | HT_IRQ_LOW_MT_FIXED : | 3719 | HT_IRQ_LOW_MT_FIXED : |
3720 | HT_IRQ_LOW_MT_ARBITRATED) | | 3720 | HT_IRQ_LOW_MT_ARBITRATED) | |
3721 | HT_IRQ_LOW_IRQ_MASKED; | 3721 | HT_IRQ_LOW_IRQ_MASKED; |
@@ -3763,8 +3763,8 @@ int arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade, | |||
3763 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); | 3763 | BUG_ON(sizeof(struct uv_IO_APIC_route_entry) != sizeof(unsigned long)); |
3764 | 3764 | ||
3765 | entry->vector = cfg->vector; | 3765 | entry->vector = cfg->vector; |
3766 | entry->delivery_mode = IRQ_DELIVERY_MODE; | 3766 | entry->delivery_mode = apic->irq_delivery_mode; |
3767 | entry->dest_mode = IRQ_DEST_MODE; | 3767 | entry->dest_mode = apic->irq_dest_mode; |
3768 | entry->polarity = 0; | 3768 | entry->polarity = 0; |
3769 | entry->trigger = 0; | 3769 | entry->trigger = 0; |
3770 | entry->mask = 0; | 3770 | entry->mask = 0; |
diff --git a/arch/x86/mach-generic/bigsmp.c b/arch/x86/mach-generic/bigsmp.c index c15c1aa2dc7f..e8c1ceca7c94 100644 --- a/arch/x86/mach-generic/bigsmp.c +++ b/arch/x86/mach-generic/bigsmp.c | |||
@@ -64,8 +64,8 @@ struct genapic apic_bigsmp = { | |||
64 | .acpi_madt_oem_check = NULL, | 64 | .acpi_madt_oem_check = NULL, |
65 | .apic_id_registered = bigsmp_apic_id_registered, | 65 | .apic_id_registered = bigsmp_apic_id_registered, |
66 | 66 | ||
67 | .irq_delivery_mode = IRQ_DELIVERY_MODE, | 67 | .irq_delivery_mode = BIGSMP_IRQ_DELIVERY_MODE, |
68 | .irq_dest_mode = IRQ_DEST_MODE, | 68 | .irq_dest_mode = BIGSMP_IRQ_DEST_MODE, |
69 | 69 | ||
70 | .target_cpus = target_cpus, | 70 | .target_cpus = target_cpus, |
71 | .ESR_DISABLE = esr_disable, | 71 | .ESR_DISABLE = esr_disable, |
diff --git a/arch/x86/mach-generic/default.c b/arch/x86/mach-generic/default.c index d32b175eff88..0482106f0e19 100644 --- a/arch/x86/mach-generic/default.c +++ b/arch/x86/mach-generic/default.c | |||
@@ -31,8 +31,8 @@ struct genapic apic_default = { | |||
31 | .acpi_madt_oem_check = NULL, | 31 | .acpi_madt_oem_check = NULL, |
32 | .apic_id_registered = default_apic_id_registered, | 32 | .apic_id_registered = default_apic_id_registered, |
33 | 33 | ||
34 | .irq_delivery_mode = IRQ_DELIVERY_MODE, | 34 | .irq_delivery_mode = DEFAULT_IRQ_DELIVERY_MODE, |
35 | .irq_dest_mode = IRQ_DEST_MODE, | 35 | .irq_dest_mode = DEFAULT_IRQ_DEST_MODE, |
36 | 36 | ||
37 | .target_cpus = target_cpus, | 37 | .target_cpus = target_cpus, |
38 | .ESR_DISABLE = esr_disable, | 38 | .ESR_DISABLE = esr_disable, |
diff --git a/arch/x86/mach-generic/es7000.c b/arch/x86/mach-generic/es7000.c index 06653892953e..5d97408919bb 100644 --- a/arch/x86/mach-generic/es7000.c +++ b/arch/x86/mach-generic/es7000.c | |||
@@ -107,8 +107,8 @@ struct genapic apic_es7000 = { | |||
107 | .acpi_madt_oem_check = es7000_acpi_madt_oem_check, | 107 | .acpi_madt_oem_check = es7000_acpi_madt_oem_check, |
108 | .apic_id_registered = es7000_apic_id_registered, | 108 | .apic_id_registered = es7000_apic_id_registered, |
109 | 109 | ||
110 | .irq_delivery_mode = IRQ_DELIVERY_MODE, | 110 | .irq_delivery_mode = ES7000_IRQ_DELIVERY_MODE, |
111 | .irq_dest_mode = IRQ_DEST_MODE, | 111 | .irq_dest_mode = ES7000_IRQ_DEST_MODE, |
112 | 112 | ||
113 | .target_cpus = target_cpus, | 113 | .target_cpus = target_cpus, |
114 | .ESR_DISABLE = esr_disable, | 114 | .ESR_DISABLE = esr_disable, |
diff --git a/arch/x86/mach-generic/numaq.c b/arch/x86/mach-generic/numaq.c index 401957142fda..77ac66935fdd 100644 --- a/arch/x86/mach-generic/numaq.c +++ b/arch/x86/mach-generic/numaq.c | |||
@@ -51,8 +51,8 @@ struct genapic apic_numaq = { | |||
51 | .acpi_madt_oem_check = NULL, | 51 | .acpi_madt_oem_check = NULL, |
52 | .apic_id_registered = numaq_apic_id_registered, | 52 | .apic_id_registered = numaq_apic_id_registered, |
53 | 53 | ||
54 | .irq_delivery_mode = IRQ_DELIVERY_MODE, | 54 | .irq_delivery_mode = NUMAQ_IRQ_DELIVERY_MODE, |
55 | .irq_dest_mode = IRQ_DEST_MODE, | 55 | .irq_dest_mode = NUMAQ_IRQ_DEST_MODE, |
56 | 56 | ||
57 | .target_cpus = target_cpus, | 57 | .target_cpus = target_cpus, |
58 | .ESR_DISABLE = esr_disable, | 58 | .ESR_DISABLE = esr_disable, |
diff --git a/arch/x86/mach-generic/summit.c b/arch/x86/mach-generic/summit.c index 946da7aa7622..7b3f43caf2ae 100644 --- a/arch/x86/mach-generic/summit.c +++ b/arch/x86/mach-generic/summit.c | |||
@@ -44,8 +44,8 @@ struct genapic apic_summit = { | |||
44 | .acpi_madt_oem_check = summit_acpi_madt_oem_check, | 44 | .acpi_madt_oem_check = summit_acpi_madt_oem_check, |
45 | .apic_id_registered = summit_apic_id_registered, | 45 | .apic_id_registered = summit_apic_id_registered, |
46 | 46 | ||
47 | .irq_delivery_mode = IRQ_DELIVERY_MODE, | 47 | .irq_delivery_mode = SUMMIT_IRQ_DELIVERY_MODE, |
48 | .irq_dest_mode = IRQ_DEST_MODE, | 48 | .irq_dest_mode = SUMMIT_IRQ_DEST_MODE, |
49 | 49 | ||
50 | .target_cpus = target_cpus, | 50 | .target_cpus = target_cpus, |
51 | .ESR_DISABLE = esr_disable, | 51 | .ESR_DISABLE = esr_disable, |