diff options
author | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-09 15:43:06 -0500 |
---|---|---|
committer | Linus Torvalds <torvalds@linux-foundation.org> | 2009-01-09 15:43:06 -0500 |
commit | 4ce5f24193cef2e26f182ce708e94ba1f5fafc0c (patch) | |
tree | 300373440be70af7c8ce662d4b30d8103e7c6026 /arch/x86 | |
parent | 7c51d57e9d7fbce89f79c41dc8da383101dbe9c6 (diff) | |
parent | a076aa4f96f40fc75451ae835a1a665ce1faf951 (diff) |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rric/oprofile
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rric/oprofile: (31 commits)
powerpc/oprofile: fix whitespaces in op_model_cell.c
powerpc/oprofile: IBM CELL: add SPU event profiling support
powerpc/oprofile: fix cell/pr_util.h
powerpc/oprofile: IBM CELL: cleanup and restructuring
oprofile: make new cpu buffer functions part of the api
oprofile: remove #ifdef CONFIG_OPROFILE_IBS in non-ibs code
ring_buffer: fix ring_buffer_event_length()
oprofile: use new data sample format for ibs
oprofile: add op_cpu_buffer_get_data()
oprofile: add op_cpu_buffer_add_data()
oprofile: rework implementation of cpu buffer events
oprofile: modify op_cpu_buffer_read_entry()
oprofile: add op_cpu_buffer_write_reserve()
oprofile: rename variables in add_ibs_begin()
oprofile: rename add_sample() in cpu_buffer.c
oprofile: rename variable ibs_allowed to has_ibs in op_model_amd.c
oprofile: making add_sample_entry() inline
oprofile: remove backtrace code for ibs
oprofile: remove unused ibs macro
oprofile: remove unused components in struct oprofile_cpu_buffer
...
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/oprofile/op_model_amd.c | 149 |
1 files changed, 52 insertions, 97 deletions
diff --git a/arch/x86/oprofile/op_model_amd.c b/arch/x86/oprofile/op_model_amd.c index 98658f25f542..8fdf06e4edf9 100644 --- a/arch/x86/oprofile/op_model_amd.c +++ b/arch/x86/oprofile/op_model_amd.c | |||
@@ -2,7 +2,7 @@ | |||
2 | * @file op_model_amd.c | 2 | * @file op_model_amd.c |
3 | * athlon / K7 / K8 / Family 10h model-specific MSR operations | 3 | * athlon / K7 / K8 / Family 10h model-specific MSR operations |
4 | * | 4 | * |
5 | * @remark Copyright 2002-2008 OProfile authors | 5 | * @remark Copyright 2002-2009 OProfile authors |
6 | * @remark Read the file COPYING | 6 | * @remark Read the file COPYING |
7 | * | 7 | * |
8 | * @author John Levon | 8 | * @author John Levon |
@@ -10,7 +10,7 @@ | |||
10 | * @author Graydon Hoare | 10 | * @author Graydon Hoare |
11 | * @author Robert Richter <robert.richter@amd.com> | 11 | * @author Robert Richter <robert.richter@amd.com> |
12 | * @author Barry Kasindorf | 12 | * @author Barry Kasindorf |
13 | */ | 13 | */ |
14 | 14 | ||
15 | #include <linux/oprofile.h> | 15 | #include <linux/oprofile.h> |
16 | #include <linux/device.h> | 16 | #include <linux/device.h> |
@@ -60,53 +60,10 @@ static unsigned long reset_value[NUM_COUNTERS]; | |||
60 | #define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */ | 60 | #define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */ |
61 | #define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */ | 61 | #define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */ |
62 | 62 | ||
63 | /* Codes used in cpu_buffer.c */ | 63 | #define IBS_FETCH_SIZE 6 |
64 | /* This produces duplicate code, need to be fixed */ | 64 | #define IBS_OP_SIZE 12 |
65 | #define IBS_FETCH_BEGIN 3 | ||
66 | #define IBS_OP_BEGIN 4 | ||
67 | |||
68 | /* | ||
69 | * The function interface needs to be fixed, something like add | ||
70 | * data. Should then be added to linux/oprofile.h. | ||
71 | */ | ||
72 | extern void | ||
73 | oprofile_add_ibs_sample(struct pt_regs * const regs, | ||
74 | unsigned int * const ibs_sample, int ibs_code); | ||
75 | |||
76 | struct ibs_fetch_sample { | ||
77 | /* MSRC001_1031 IBS Fetch Linear Address Register */ | ||
78 | unsigned int ibs_fetch_lin_addr_low; | ||
79 | unsigned int ibs_fetch_lin_addr_high; | ||
80 | /* MSRC001_1030 IBS Fetch Control Register */ | ||
81 | unsigned int ibs_fetch_ctl_low; | ||
82 | unsigned int ibs_fetch_ctl_high; | ||
83 | /* MSRC001_1032 IBS Fetch Physical Address Register */ | ||
84 | unsigned int ibs_fetch_phys_addr_low; | ||
85 | unsigned int ibs_fetch_phys_addr_high; | ||
86 | }; | ||
87 | |||
88 | struct ibs_op_sample { | ||
89 | /* MSRC001_1034 IBS Op Logical Address Register (IbsRIP) */ | ||
90 | unsigned int ibs_op_rip_low; | ||
91 | unsigned int ibs_op_rip_high; | ||
92 | /* MSRC001_1035 IBS Op Data Register */ | ||
93 | unsigned int ibs_op_data1_low; | ||
94 | unsigned int ibs_op_data1_high; | ||
95 | /* MSRC001_1036 IBS Op Data 2 Register */ | ||
96 | unsigned int ibs_op_data2_low; | ||
97 | unsigned int ibs_op_data2_high; | ||
98 | /* MSRC001_1037 IBS Op Data 3 Register */ | ||
99 | unsigned int ibs_op_data3_low; | ||
100 | unsigned int ibs_op_data3_high; | ||
101 | /* MSRC001_1038 IBS DC Linear Address Register (IbsDcLinAd) */ | ||
102 | unsigned int ibs_dc_linear_low; | ||
103 | unsigned int ibs_dc_linear_high; | ||
104 | /* MSRC001_1039 IBS DC Physical Address Register (IbsDcPhysAd) */ | ||
105 | unsigned int ibs_dc_phys_low; | ||
106 | unsigned int ibs_dc_phys_high; | ||
107 | }; | ||
108 | 65 | ||
109 | static int ibs_allowed; /* AMD Family10h and later */ | 66 | static int has_ibs; /* AMD Family10h and later */ |
110 | 67 | ||
111 | struct op_ibs_config { | 68 | struct op_ibs_config { |
112 | unsigned long op_enabled; | 69 | unsigned long op_enabled; |
@@ -197,31 +154,29 @@ static inline int | |||
197 | op_amd_handle_ibs(struct pt_regs * const regs, | 154 | op_amd_handle_ibs(struct pt_regs * const regs, |
198 | struct op_msrs const * const msrs) | 155 | struct op_msrs const * const msrs) |
199 | { | 156 | { |
200 | unsigned int low, high; | 157 | u32 low, high; |
201 | struct ibs_fetch_sample ibs_fetch; | 158 | u64 msr; |
202 | struct ibs_op_sample ibs_op; | 159 | struct op_entry entry; |
203 | 160 | ||
204 | if (!ibs_allowed) | 161 | if (!has_ibs) |
205 | return 1; | 162 | return 1; |
206 | 163 | ||
207 | if (ibs_config.fetch_enabled) { | 164 | if (ibs_config.fetch_enabled) { |
208 | rdmsr(MSR_AMD64_IBSFETCHCTL, low, high); | 165 | rdmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
209 | if (high & IBS_FETCH_HIGH_VALID_BIT) { | 166 | if (high & IBS_FETCH_HIGH_VALID_BIT) { |
210 | ibs_fetch.ibs_fetch_ctl_high = high; | 167 | rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr); |
211 | ibs_fetch.ibs_fetch_ctl_low = low; | 168 | oprofile_write_reserve(&entry, regs, msr, |
212 | rdmsr(MSR_AMD64_IBSFETCHLINAD, low, high); | 169 | IBS_FETCH_CODE, IBS_FETCH_SIZE); |
213 | ibs_fetch.ibs_fetch_lin_addr_high = high; | 170 | oprofile_add_data(&entry, (u32)msr); |
214 | ibs_fetch.ibs_fetch_lin_addr_low = low; | 171 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
215 | rdmsr(MSR_AMD64_IBSFETCHPHYSAD, low, high); | 172 | oprofile_add_data(&entry, low); |
216 | ibs_fetch.ibs_fetch_phys_addr_high = high; | 173 | oprofile_add_data(&entry, high); |
217 | ibs_fetch.ibs_fetch_phys_addr_low = low; | 174 | rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr); |
218 | 175 | oprofile_add_data(&entry, (u32)msr); | |
219 | oprofile_add_ibs_sample(regs, | 176 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
220 | (unsigned int *)&ibs_fetch, | 177 | oprofile_write_commit(&entry); |
221 | IBS_FETCH_BEGIN); | ||
222 | 178 | ||
223 | /* reenable the IRQ */ | 179 | /* reenable the IRQ */ |
224 | rdmsr(MSR_AMD64_IBSFETCHCTL, low, high); | ||
225 | high &= ~IBS_FETCH_HIGH_VALID_BIT; | 180 | high &= ~IBS_FETCH_HIGH_VALID_BIT; |
226 | high |= IBS_FETCH_HIGH_ENABLE; | 181 | high |= IBS_FETCH_HIGH_ENABLE; |
227 | low &= IBS_FETCH_LOW_MAX_CNT_MASK; | 182 | low &= IBS_FETCH_LOW_MAX_CNT_MASK; |
@@ -232,30 +187,29 @@ op_amd_handle_ibs(struct pt_regs * const regs, | |||
232 | if (ibs_config.op_enabled) { | 187 | if (ibs_config.op_enabled) { |
233 | rdmsr(MSR_AMD64_IBSOPCTL, low, high); | 188 | rdmsr(MSR_AMD64_IBSOPCTL, low, high); |
234 | if (low & IBS_OP_LOW_VALID_BIT) { | 189 | if (low & IBS_OP_LOW_VALID_BIT) { |
235 | rdmsr(MSR_AMD64_IBSOPRIP, low, high); | 190 | rdmsrl(MSR_AMD64_IBSOPRIP, msr); |
236 | ibs_op.ibs_op_rip_low = low; | 191 | oprofile_write_reserve(&entry, regs, msr, |
237 | ibs_op.ibs_op_rip_high = high; | 192 | IBS_OP_CODE, IBS_OP_SIZE); |
238 | rdmsr(MSR_AMD64_IBSOPDATA, low, high); | 193 | oprofile_add_data(&entry, (u32)msr); |
239 | ibs_op.ibs_op_data1_low = low; | 194 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
240 | ibs_op.ibs_op_data1_high = high; | 195 | rdmsrl(MSR_AMD64_IBSOPDATA, msr); |
241 | rdmsr(MSR_AMD64_IBSOPDATA2, low, high); | 196 | oprofile_add_data(&entry, (u32)msr); |
242 | ibs_op.ibs_op_data2_low = low; | 197 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
243 | ibs_op.ibs_op_data2_high = high; | 198 | rdmsrl(MSR_AMD64_IBSOPDATA2, msr); |
244 | rdmsr(MSR_AMD64_IBSOPDATA3, low, high); | 199 | oprofile_add_data(&entry, (u32)msr); |
245 | ibs_op.ibs_op_data3_low = low; | 200 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
246 | ibs_op.ibs_op_data3_high = high; | 201 | rdmsrl(MSR_AMD64_IBSOPDATA3, msr); |
247 | rdmsr(MSR_AMD64_IBSDCLINAD, low, high); | 202 | oprofile_add_data(&entry, (u32)msr); |
248 | ibs_op.ibs_dc_linear_low = low; | 203 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
249 | ibs_op.ibs_dc_linear_high = high; | 204 | rdmsrl(MSR_AMD64_IBSDCLINAD, msr); |
250 | rdmsr(MSR_AMD64_IBSDCPHYSAD, low, high); | 205 | oprofile_add_data(&entry, (u32)msr); |
251 | ibs_op.ibs_dc_phys_low = low; | 206 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
252 | ibs_op.ibs_dc_phys_high = high; | 207 | rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr); |
208 | oprofile_add_data(&entry, (u32)msr); | ||
209 | oprofile_add_data(&entry, (u32)(msr >> 32)); | ||
210 | oprofile_write_commit(&entry); | ||
253 | 211 | ||
254 | /* reenable the IRQ */ | 212 | /* reenable the IRQ */ |
255 | oprofile_add_ibs_sample(regs, | ||
256 | (unsigned int *)&ibs_op, | ||
257 | IBS_OP_BEGIN); | ||
258 | rdmsr(MSR_AMD64_IBSOPCTL, low, high); | ||
259 | high = 0; | 213 | high = 0; |
260 | low &= ~IBS_OP_LOW_VALID_BIT; | 214 | low &= ~IBS_OP_LOW_VALID_BIT; |
261 | low |= IBS_OP_LOW_ENABLE; | 215 | low |= IBS_OP_LOW_ENABLE; |
@@ -305,14 +259,14 @@ static void op_amd_start(struct op_msrs const * const msrs) | |||
305 | } | 259 | } |
306 | 260 | ||
307 | #ifdef CONFIG_OPROFILE_IBS | 261 | #ifdef CONFIG_OPROFILE_IBS |
308 | if (ibs_allowed && ibs_config.fetch_enabled) { | 262 | if (has_ibs && ibs_config.fetch_enabled) { |
309 | low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF; | 263 | low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF; |
310 | high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */ | 264 | high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */ |
311 | + IBS_FETCH_HIGH_ENABLE; | 265 | + IBS_FETCH_HIGH_ENABLE; |
312 | wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); | 266 | wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
313 | } | 267 | } |
314 | 268 | ||
315 | if (ibs_allowed && ibs_config.op_enabled) { | 269 | if (has_ibs && ibs_config.op_enabled) { |
316 | low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF) | 270 | low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF) |
317 | + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */ | 271 | + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */ |
318 | + IBS_OP_LOW_ENABLE; | 272 | + IBS_OP_LOW_ENABLE; |
@@ -341,14 +295,14 @@ static void op_amd_stop(struct op_msrs const * const msrs) | |||
341 | } | 295 | } |
342 | 296 | ||
343 | #ifdef CONFIG_OPROFILE_IBS | 297 | #ifdef CONFIG_OPROFILE_IBS |
344 | if (ibs_allowed && ibs_config.fetch_enabled) { | 298 | if (has_ibs && ibs_config.fetch_enabled) { |
345 | /* clear max count and enable */ | 299 | /* clear max count and enable */ |
346 | low = 0; | 300 | low = 0; |
347 | high = 0; | 301 | high = 0; |
348 | wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); | 302 | wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
349 | } | 303 | } |
350 | 304 | ||
351 | if (ibs_allowed && ibs_config.op_enabled) { | 305 | if (has_ibs && ibs_config.op_enabled) { |
352 | /* clear max count and enable */ | 306 | /* clear max count and enable */ |
353 | low = 0; | 307 | low = 0; |
354 | high = 0; | 308 | high = 0; |
@@ -409,6 +363,7 @@ static int init_ibs_nmi(void) | |||
409 | | IBSCTL_LVTOFFSETVAL); | 363 | | IBSCTL_LVTOFFSETVAL); |
410 | pci_read_config_dword(cpu_cfg, IBSCTL, &value); | 364 | pci_read_config_dword(cpu_cfg, IBSCTL, &value); |
411 | if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) { | 365 | if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) { |
366 | pci_dev_put(cpu_cfg); | ||
412 | printk(KERN_DEBUG "Failed to setup IBS LVT offset, " | 367 | printk(KERN_DEBUG "Failed to setup IBS LVT offset, " |
413 | "IBSCTL = 0x%08x", value); | 368 | "IBSCTL = 0x%08x", value); |
414 | return 1; | 369 | return 1; |
@@ -436,20 +391,20 @@ static int init_ibs_nmi(void) | |||
436 | /* uninitialize the APIC for the IBS interrupts if needed */ | 391 | /* uninitialize the APIC for the IBS interrupts if needed */ |
437 | static void clear_ibs_nmi(void) | 392 | static void clear_ibs_nmi(void) |
438 | { | 393 | { |
439 | if (ibs_allowed) | 394 | if (has_ibs) |
440 | on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1); | 395 | on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1); |
441 | } | 396 | } |
442 | 397 | ||
443 | /* initialize the APIC for the IBS interrupts if available */ | 398 | /* initialize the APIC for the IBS interrupts if available */ |
444 | static void ibs_init(void) | 399 | static void ibs_init(void) |
445 | { | 400 | { |
446 | ibs_allowed = boot_cpu_has(X86_FEATURE_IBS); | 401 | has_ibs = boot_cpu_has(X86_FEATURE_IBS); |
447 | 402 | ||
448 | if (!ibs_allowed) | 403 | if (!has_ibs) |
449 | return; | 404 | return; |
450 | 405 | ||
451 | if (init_ibs_nmi()) { | 406 | if (init_ibs_nmi()) { |
452 | ibs_allowed = 0; | 407 | has_ibs = 0; |
453 | return; | 408 | return; |
454 | } | 409 | } |
455 | 410 | ||
@@ -458,7 +413,7 @@ static void ibs_init(void) | |||
458 | 413 | ||
459 | static void ibs_exit(void) | 414 | static void ibs_exit(void) |
460 | { | 415 | { |
461 | if (!ibs_allowed) | 416 | if (!has_ibs) |
462 | return; | 417 | return; |
463 | 418 | ||
464 | clear_ibs_nmi(); | 419 | clear_ibs_nmi(); |
@@ -478,7 +433,7 @@ static int setup_ibs_files(struct super_block *sb, struct dentry *root) | |||
478 | if (ret) | 433 | if (ret) |
479 | return ret; | 434 | return ret; |
480 | 435 | ||
481 | if (!ibs_allowed) | 436 | if (!has_ibs) |
482 | return ret; | 437 | return ret; |
483 | 438 | ||
484 | /* model specific files */ | 439 | /* model specific files */ |