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authorYinghai Lu <yhlu.kernel@gmail.com>2008-08-24 05:01:56 -0400
committerIngo Molnar <mingo@elte.hu>2008-10-16 10:53:03 -0400
commit0f611ffaea81b8e1c69682188ba1ccaf7683a2ba (patch)
tree9e046359ee3693f6a22b5fae75ef32f2477a40c0 /arch/x86
parent6c15822752a13748241e1a34068f2b15b660d28e (diff)
x86: rename apic_32.c and apic_64.c to apic.c
Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/kernel/Makefile2
-rw-r--r--arch/x86/kernel/apic.c (renamed from arch/x86/kernel/apic_64.c)0
-rw-r--r--arch/x86/kernel/apic_32.c2312
3 files changed, 1 insertions, 2313 deletions
diff --git a/arch/x86/kernel/Makefile b/arch/x86/kernel/Makefile
index 7264f9c3af8f..45cecc59d894 100644
--- a/arch/x86/kernel/Makefile
+++ b/arch/x86/kernel/Makefile
@@ -60,7 +60,7 @@ obj-$(CONFIG_X86_32_SMP) += smpcommon.o
60obj-$(CONFIG_X86_64_SMP) += tsc_sync.o smpcommon.o 60obj-$(CONFIG_X86_64_SMP) += tsc_sync.o smpcommon.o
61obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o 61obj-$(CONFIG_X86_TRAMPOLINE) += trampoline_$(BITS).o
62obj-$(CONFIG_X86_MPPARSE) += mpparse.o 62obj-$(CONFIG_X86_MPPARSE) += mpparse.o
63obj-$(CONFIG_X86_LOCAL_APIC) += apic_$(BITS).o nmi.o 63obj-$(CONFIG_X86_LOCAL_APIC) += apic.o nmi.o
64obj-$(CONFIG_X86_IO_APIC) += io_apic.o 64obj-$(CONFIG_X86_IO_APIC) += io_apic.o
65obj-$(CONFIG_X86_REBOOTFIXUPS) += reboot_fixups_32.o 65obj-$(CONFIG_X86_REBOOTFIXUPS) += reboot_fixups_32.o
66obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o 66obj-$(CONFIG_DYNAMIC_FTRACE) += ftrace.o
diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic.c
index 6e99af5ce678..6e99af5ce678 100644
--- a/arch/x86/kernel/apic_64.c
+++ b/arch/x86/kernel/apic.c
diff --git a/arch/x86/kernel/apic_32.c b/arch/x86/kernel/apic_32.c
deleted file mode 100644
index 0b11d6e3f091..000000000000
--- a/arch/x86/kernel/apic_32.c
+++ /dev/null
@@ -1,2312 +0,0 @@
1/*
2 * Local APIC handling, local APIC timers
3 *
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
5 *
6 * Fixes
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
9 * and Rolf G. Tews
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
13 * Pavel Machek and
14 * Mikael Pettersson : PM converted to driver model.
15 */
16
17#include <linux/init.h>
18
19#include <linux/mm.h>
20#include <linux/delay.h>
21#include <linux/bootmem.h>
22#include <linux/interrupt.h>
23#include <linux/mc146818rtc.h>
24#include <linux/kernel_stat.h>
25#include <linux/sysdev.h>
26#include <linux/ioport.h>
27#include <linux/cpu.h>
28#include <linux/clockchips.h>
29#include <linux/acpi_pmtmr.h>
30#include <linux/module.h>
31#include <linux/dmi.h>
32#include <linux/dmar.h>
33
34#include <asm/atomic.h>
35#include <asm/smp.h>
36#include <asm/mtrr.h>
37#include <asm/mpspec.h>
38#include <asm/desc.h>
39#include <asm/arch_hooks.h>
40#include <asm/hpet.h>
41#include <asm/pgalloc.h>
42#include <asm/i8253.h>
43#include <asm/nmi.h>
44#include <asm/idle.h>
45#include <asm/proto.h>
46#include <asm/timex.h>
47#include <asm/apic.h>
48#include <asm/i8259.h>
49
50#include <mach_apic.h>
51#include <mach_apicdef.h>
52#include <mach_ipi.h>
53
54/*
55 * Sanity check
56 */
57#if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F)
58# error SPURIOUS_APIC_VECTOR definition error
59#endif
60
61#ifdef CONFIG_X86_32
62/*
63 * Knob to control our willingness to enable the local APIC.
64 *
65 * +1=force-enable
66 */
67static int force_enable_local_apic;
68/*
69 * APIC command line parameters
70 */
71static int __init parse_lapic(char *arg)
72{
73 force_enable_local_apic = 1;
74 return 0;
75}
76early_param("lapic", parse_lapic);
77/* Local APIC was disabled by the BIOS and enabled by the kernel */
78static int enabled_via_apicbase;
79
80#endif
81
82#ifdef CONFIG_X86_64
83static int apic_calibrate_pmtmr __initdata;
84static __init int setup_apicpmtimer(char *s)
85{
86 apic_calibrate_pmtmr = 1;
87 notsc_setup(NULL);
88 return 0;
89}
90__setup("apicpmtimer", setup_apicpmtimer);
91#endif
92
93#ifdef CONFIG_X86_64
94#define HAVE_X2APIC
95#endif
96
97#ifdef HAVE_X2APIC
98int x2apic;
99/* x2apic enabled before OS handover */
100int x2apic_preenabled;
101int disable_x2apic;
102static __init int setup_nox2apic(char *str)
103{
104 disable_x2apic = 1;
105 setup_clear_cpu_cap(X86_FEATURE_X2APIC);
106 return 0;
107}
108early_param("nox2apic", setup_nox2apic);
109#endif
110
111unsigned long mp_lapic_addr;
112int disable_apic;
113/* Disable local APIC timer from the kernel commandline or via dmi quirk */
114static int disable_apic_timer __cpuinitdata;
115/* Local APIC timer works in C2 */
116int local_apic_timer_c2_ok;
117EXPORT_SYMBOL_GPL(local_apic_timer_c2_ok);
118
119int first_system_vector = 0xfe;
120
121char system_vectors[NR_VECTORS] = { [0 ... NR_VECTORS-1] = SYS_VECTOR_FREE};
122
123/*
124 * Debug level, exported for io_apic.c
125 */
126unsigned int apic_verbosity;
127
128int pic_mode;
129
130/* Have we found an MP table */
131int smp_found_config;
132
133static struct resource lapic_resource = {
134 .name = "Local APIC",
135 .flags = IORESOURCE_MEM | IORESOURCE_BUSY,
136};
137
138static unsigned int calibration_result;
139
140static int lapic_next_event(unsigned long delta,
141 struct clock_event_device *evt);
142static void lapic_timer_setup(enum clock_event_mode mode,
143 struct clock_event_device *evt);
144static void lapic_timer_broadcast(cpumask_t mask);
145static void apic_pm_activate(void);
146
147/*
148 * The local apic timer can be used for any function which is CPU local.
149 */
150static struct clock_event_device lapic_clockevent = {
151 .name = "lapic",
152 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT
153 | CLOCK_EVT_FEAT_C3STOP | CLOCK_EVT_FEAT_DUMMY,
154 .shift = 32,
155 .set_mode = lapic_timer_setup,
156 .set_next_event = lapic_next_event,
157 .broadcast = lapic_timer_broadcast,
158 .rating = 100,
159 .irq = -1,
160};
161static DEFINE_PER_CPU(struct clock_event_device, lapic_events);
162
163static unsigned long apic_phys;
164
165/*
166 * Get the LAPIC version
167 */
168static inline int lapic_get_version(void)
169{
170 return GET_APIC_VERSION(apic_read(APIC_LVR));
171}
172
173/*
174 * Check, if the APIC is integrated or a separate chip
175 */
176static inline int lapic_is_integrated(void)
177{
178#ifdef CONFIG_X86_64
179 return 1;
180#else
181 return APIC_INTEGRATED(lapic_get_version());
182#endif
183}
184
185/*
186 * Check, whether this is a modern or a first generation APIC
187 */
188static int modern_apic(void)
189{
190 /* AMD systems use old APIC versions, so check the CPU */
191 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD &&
192 boot_cpu_data.x86 >= 0xf)
193 return 1;
194 return lapic_get_version() >= 0x14;
195}
196
197/*
198 * Paravirt kernels also might be using these below ops. So we still
199 * use generic apic_read()/apic_write(), which might be pointing to different
200 * ops in PARAVIRT case.
201 */
202void xapic_wait_icr_idle(void)
203{
204 while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
205 cpu_relax();
206}
207
208u32 safe_xapic_wait_icr_idle(void)
209{
210 u32 send_status;
211 int timeout;
212
213 timeout = 0;
214 do {
215 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
216 if (!send_status)
217 break;
218 udelay(100);
219 } while (timeout++ < 1000);
220
221 return send_status;
222}
223
224void xapic_icr_write(u32 low, u32 id)
225{
226 apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(id));
227 apic_write(APIC_ICR, low);
228}
229
230u64 xapic_icr_read(void)
231{
232 u32 icr1, icr2;
233
234 icr2 = apic_read(APIC_ICR2);
235 icr1 = apic_read(APIC_ICR);
236
237 return icr1 | ((u64)icr2 << 32);
238}
239
240static struct apic_ops xapic_ops = {
241 .read = native_apic_mem_read,
242 .write = native_apic_mem_write,
243 .icr_read = xapic_icr_read,
244 .icr_write = xapic_icr_write,
245 .wait_icr_idle = xapic_wait_icr_idle,
246 .safe_wait_icr_idle = safe_xapic_wait_icr_idle,
247};
248
249struct apic_ops __read_mostly *apic_ops = &xapic_ops;
250EXPORT_SYMBOL_GPL(apic_ops);
251
252#ifdef HAVE_X2APIC
253static void x2apic_wait_icr_idle(void)
254{
255 /* no need to wait for icr idle in x2apic */
256 return;
257}
258
259static u32 safe_x2apic_wait_icr_idle(void)
260{
261 /* no need to wait for icr idle in x2apic */
262 return 0;
263}
264
265void x2apic_icr_write(u32 low, u32 id)
266{
267 wrmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), ((__u64) id) << 32 | low);
268}
269
270u64 x2apic_icr_read(void)
271{
272 unsigned long val;
273
274 rdmsrl(APIC_BASE_MSR + (APIC_ICR >> 4), val);
275 return val;
276}
277
278static struct apic_ops x2apic_ops = {
279 .read = native_apic_msr_read,
280 .write = native_apic_msr_write,
281 .icr_read = x2apic_icr_read,
282 .icr_write = x2apic_icr_write,
283 .wait_icr_idle = x2apic_wait_icr_idle,
284 .safe_wait_icr_idle = safe_x2apic_wait_icr_idle,
285};
286#endif
287
288/**
289 * enable_NMI_through_LVT0 - enable NMI through local vector table 0
290 */
291void __cpuinit enable_NMI_through_LVT0(void)
292{
293 unsigned int v;
294
295 /* unmask and set to NMI */
296 v = APIC_DM_NMI;
297
298 /* Level triggered for 82489DX (32bit mode) */
299 if (!lapic_is_integrated())
300 v |= APIC_LVT_LEVEL_TRIGGER;
301
302 apic_write(APIC_LVT0, v);
303}
304
305#ifdef CONFIG_X86_32
306/**
307 * get_physical_broadcast - Get number of physical broadcast IDs
308 */
309int get_physical_broadcast(void)
310{
311 return modern_apic() ? 0xff : 0xf;
312}
313#endif
314
315/**
316 * lapic_get_maxlvt - get the maximum number of local vector table entries
317 */
318int lapic_get_maxlvt(void)
319{
320 unsigned int v;
321
322 v = apic_read(APIC_LVR);
323 /*
324 * - we always have APIC integrated on 64bit mode
325 * - 82489DXs do not report # of LVT entries
326 */
327 return APIC_INTEGRATED(GET_APIC_VERSION(v)) ? GET_APIC_MAXLVT(v) : 2;
328}
329
330/*
331 * Local APIC timer
332 */
333
334/* Clock divisor */
335#ifdef CONFG_X86_64
336#define APIC_DIVISOR 1
337#else
338#define APIC_DIVISOR 16
339#endif
340
341/*
342 * This function sets up the local APIC timer, with a timeout of
343 * 'clocks' APIC bus clock. During calibration we actually call
344 * this function twice on the boot CPU, once with a bogus timeout
345 * value, second time for real. The other (noncalibrating) CPUs
346 * call this function only once, with the real, calibrated value.
347 *
348 * We do reads before writes even if unnecessary, to get around the
349 * P5 APIC double write bug.
350 */
351static void __setup_APIC_LVTT(unsigned int clocks, int oneshot, int irqen)
352{
353 unsigned int lvtt_value, tmp_value;
354
355 lvtt_value = LOCAL_TIMER_VECTOR;
356 if (!oneshot)
357 lvtt_value |= APIC_LVT_TIMER_PERIODIC;
358 if (!lapic_is_integrated())
359 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
360
361 if (!irqen)
362 lvtt_value |= APIC_LVT_MASKED;
363
364 apic_write(APIC_LVTT, lvtt_value);
365
366 /*
367 * Divide PICLK by 16
368 */
369 tmp_value = apic_read(APIC_TDCR);
370 apic_write(APIC_TDCR,
371 (tmp_value & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE)) |
372 APIC_TDR_DIV_16);
373
374 if (!oneshot)
375 apic_write(APIC_TMICT, clocks / APIC_DIVISOR);
376}
377
378/*
379 * Setup extended LVT, AMD specific (K8, family 10h)
380 *
381 * Vector mappings are hard coded. On K8 only offset 0 (APIC500) and
382 * MCE interrupts are supported. Thus MCE offset must be set to 0.
383 *
384 * If mask=1, the LVT entry does not generate interrupts while mask=0
385 * enables the vector. See also the BKDGs.
386 */
387
388#define APIC_EILVT_LVTOFF_MCE 0
389#define APIC_EILVT_LVTOFF_IBS 1
390
391static void setup_APIC_eilvt(u8 lvt_off, u8 vector, u8 msg_type, u8 mask)
392{
393 unsigned long reg = (lvt_off << 4) + APIC_EILVT0;
394 unsigned int v = (mask << 16) | (msg_type << 8) | vector;
395
396 apic_write(reg, v);
397}
398
399u8 setup_APIC_eilvt_mce(u8 vector, u8 msg_type, u8 mask)
400{
401 setup_APIC_eilvt(APIC_EILVT_LVTOFF_MCE, vector, msg_type, mask);
402 return APIC_EILVT_LVTOFF_MCE;
403}
404
405u8 setup_APIC_eilvt_ibs(u8 vector, u8 msg_type, u8 mask)
406{
407 setup_APIC_eilvt(APIC_EILVT_LVTOFF_IBS, vector, msg_type, mask);
408 return APIC_EILVT_LVTOFF_IBS;
409}
410EXPORT_SYMBOL_GPL(setup_APIC_eilvt_ibs);
411
412/*
413 * Program the next event, relative to now
414 */
415static int lapic_next_event(unsigned long delta,
416 struct clock_event_device *evt)
417{
418 apic_write(APIC_TMICT, delta);
419 return 0;
420}
421
422/*
423 * Setup the lapic timer in periodic or oneshot mode
424 */
425static void lapic_timer_setup(enum clock_event_mode mode,
426 struct clock_event_device *evt)
427{
428 unsigned long flags;
429 unsigned int v;
430
431 /* Lapic used as dummy for broadcast ? */
432 if (evt->features & CLOCK_EVT_FEAT_DUMMY)
433 return;
434
435 local_irq_save(flags);
436
437 switch (mode) {
438 case CLOCK_EVT_MODE_PERIODIC:
439 case CLOCK_EVT_MODE_ONESHOT:
440 __setup_APIC_LVTT(calibration_result,
441 mode != CLOCK_EVT_MODE_PERIODIC, 1);
442 break;
443 case CLOCK_EVT_MODE_UNUSED:
444 case CLOCK_EVT_MODE_SHUTDOWN:
445 v = apic_read(APIC_LVTT);
446 v |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
447 apic_write(APIC_LVTT, v);
448 break;
449 case CLOCK_EVT_MODE_RESUME:
450 /* Nothing to do here */
451 break;
452 }
453
454 local_irq_restore(flags);
455}
456
457/*
458 * Local APIC timer broadcast function
459 */
460static void lapic_timer_broadcast(cpumask_t mask)
461{
462#ifdef CONFIG_SMP
463 send_IPI_mask(mask, LOCAL_TIMER_VECTOR);
464#endif
465}
466
467/*
468 * Setup the local APIC timer for this CPU. Copy the initilized values
469 * of the boot CPU and register the clock event in the framework.
470 */
471static void __cpuinit setup_APIC_timer(void)
472{
473 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
474
475 memcpy(levt, &lapic_clockevent, sizeof(*levt));
476 levt->cpumask = cpumask_of_cpu(smp_processor_id());
477
478 clockevents_register_device(levt);
479}
480
481#ifdef CONFIG_X86_64
482/*
483 * In this function we calibrate APIC bus clocks to the external
484 * timer. Unfortunately we cannot use jiffies and the timer irq
485 * to calibrate, since some later bootup code depends on getting
486 * the first irq? Ugh.
487 *
488 * We want to do the calibration only once since we
489 * want to have local timer irqs syncron. CPUs connected
490 * by the same APIC bus have the very same bus frequency.
491 * And we want to have irqs off anyways, no accidental
492 * APIC irq that way.
493 */
494
495#define TICK_COUNT 100000000
496
497static int __init calibrate_APIC_clock(void)
498{
499 unsigned apic, apic_start;
500 unsigned long tsc, tsc_start;
501 int result;
502
503 local_irq_disable();
504
505 /*
506 * Put whatever arbitrary (but long enough) timeout
507 * value into the APIC clock, we just want to get the
508 * counter running for calibration.
509 *
510 * No interrupt enable !
511 */
512 __setup_APIC_LVTT(250000000, 0, 0);
513
514 apic_start = apic_read(APIC_TMCCT);
515#ifdef CONFIG_X86_PM_TIMER
516 if (apic_calibrate_pmtmr && pmtmr_ioport) {
517 pmtimer_wait(5000); /* 5ms wait */
518 apic = apic_read(APIC_TMCCT);
519 result = (apic_start - apic) * 1000L / 5;
520 } else
521#endif
522 {
523 rdtscll(tsc_start);
524
525 do {
526 apic = apic_read(APIC_TMCCT);
527 rdtscll(tsc);
528 } while ((tsc - tsc_start) < TICK_COUNT &&
529 (apic_start - apic) < TICK_COUNT);
530
531 result = (apic_start - apic) * 1000L * tsc_khz /
532 (tsc - tsc_start);
533 }
534
535 local_irq_enable();
536
537 printk(KERN_DEBUG "APIC timer calibration result %d\n", result);
538
539 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
540 result / 1000 / 1000, result / 1000 % 1000);
541
542 /* Calculate the scaled math multiplication factor */
543 lapic_clockevent.mult = div_sc(result, NSEC_PER_SEC,
544 lapic_clockevent.shift);
545 lapic_clockevent.max_delta_ns =
546 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
547 lapic_clockevent.min_delta_ns =
548 clockevent_delta2ns(0xF, &lapic_clockevent);
549
550 calibration_result = (result * APIC_DIVISOR) / HZ;
551
552 /*
553 * Do a sanity check on the APIC calibration result
554 */
555 if (calibration_result < (1000000 / HZ)) {
556 printk(KERN_WARNING
557 "APIC frequency too slow, disabling apic timer\n");
558 return -1;
559 }
560
561 return 0;
562}
563
564#else
565/*
566 * In this functions we calibrate APIC bus clocks to the external timer.
567 *
568 * We want to do the calibration only once since we want to have local timer
569 * irqs syncron. CPUs connected by the same APIC bus have the very same bus
570 * frequency.
571 *
572 * This was previously done by reading the PIT/HPET and waiting for a wrap
573 * around to find out, that a tick has elapsed. I have a box, where the PIT
574 * readout is broken, so it never gets out of the wait loop again. This was
575 * also reported by others.
576 *
577 * Monitoring the jiffies value is inaccurate and the clockevents
578 * infrastructure allows us to do a simple substitution of the interrupt
579 * handler.
580 *
581 * The calibration routine also uses the pm_timer when possible, as the PIT
582 * happens to run way too slow (factor 2.3 on my VAIO CoreDuo, which goes
583 * back to normal later in the boot process).
584 */
585
586#define LAPIC_CAL_LOOPS (HZ/10)
587
588static __initdata int lapic_cal_loops = -1;
589static __initdata long lapic_cal_t1, lapic_cal_t2;
590static __initdata unsigned long long lapic_cal_tsc1, lapic_cal_tsc2;
591static __initdata unsigned long lapic_cal_pm1, lapic_cal_pm2;
592static __initdata unsigned long lapic_cal_j1, lapic_cal_j2;
593
594/*
595 * Temporary interrupt handler.
596 */
597static void __init lapic_cal_handler(struct clock_event_device *dev)
598{
599 unsigned long long tsc = 0;
600 long tapic = apic_read(APIC_TMCCT);
601 unsigned long pm = acpi_pm_read_early();
602
603 if (cpu_has_tsc)
604 rdtscll(tsc);
605
606 switch (lapic_cal_loops++) {
607 case 0:
608 lapic_cal_t1 = tapic;
609 lapic_cal_tsc1 = tsc;
610 lapic_cal_pm1 = pm;
611 lapic_cal_j1 = jiffies;
612 break;
613
614 case LAPIC_CAL_LOOPS:
615 lapic_cal_t2 = tapic;
616 lapic_cal_tsc2 = tsc;
617 if (pm < lapic_cal_pm1)
618 pm += ACPI_PM_OVRRUN;
619 lapic_cal_pm2 = pm;
620 lapic_cal_j2 = jiffies;
621 break;
622 }
623}
624
625static int __init calibrate_APIC_clock(void)
626{
627 struct clock_event_device *levt = &__get_cpu_var(lapic_events);
628 const long pm_100ms = PMTMR_TICKS_PER_SEC/10;
629 const long pm_thresh = pm_100ms/100;
630 void (*real_handler)(struct clock_event_device *dev);
631 unsigned long deltaj;
632 long delta, deltapm;
633 int pm_referenced = 0;
634
635 local_irq_disable();
636
637 /* Replace the global interrupt handler */
638 real_handler = global_clock_event->event_handler;
639 global_clock_event->event_handler = lapic_cal_handler;
640
641 /*
642 * Setup the APIC counter to 1e9. There is no way the lapic
643 * can underflow in the 100ms detection time frame
644 */
645 __setup_APIC_LVTT(1000000000, 0, 0);
646
647 /* Let the interrupts run */
648 local_irq_enable();
649
650 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
651 cpu_relax();
652
653 local_irq_disable();
654
655 /* Restore the real event handler */
656 global_clock_event->event_handler = real_handler;
657
658 /* Build delta t1-t2 as apic timer counts down */
659 delta = lapic_cal_t1 - lapic_cal_t2;
660 apic_printk(APIC_VERBOSE, "... lapic delta = %ld\n", delta);
661
662 /* Check, if the PM timer is available */
663 deltapm = lapic_cal_pm2 - lapic_cal_pm1;
664 apic_printk(APIC_VERBOSE, "... PM timer delta = %ld\n", deltapm);
665
666 if (deltapm) {
667 unsigned long mult;
668 u64 res;
669
670 mult = clocksource_hz2mult(PMTMR_TICKS_PER_SEC, 22);
671
672 if (deltapm > (pm_100ms - pm_thresh) &&
673 deltapm < (pm_100ms + pm_thresh)) {
674 apic_printk(APIC_VERBOSE, "... PM timer result ok\n");
675 } else {
676 res = (((u64) deltapm) * mult) >> 22;
677 do_div(res, 1000000);
678 printk(KERN_WARNING "APIC calibration not consistent "
679 "with PM Timer: %ldms instead of 100ms\n",
680 (long)res);
681 /* Correct the lapic counter value */
682 res = (((u64) delta) * pm_100ms);
683 do_div(res, deltapm);
684 printk(KERN_INFO "APIC delta adjusted to PM-Timer: "
685 "%lu (%ld)\n", (unsigned long) res, delta);
686 delta = (long) res;
687 }
688 pm_referenced = 1;
689 }
690
691 /* Calculate the scaled math multiplication factor */
692 lapic_clockevent.mult = div_sc(delta, TICK_NSEC * LAPIC_CAL_LOOPS,
693 lapic_clockevent.shift);
694 lapic_clockevent.max_delta_ns =
695 clockevent_delta2ns(0x7FFFFF, &lapic_clockevent);
696 lapic_clockevent.min_delta_ns =
697 clockevent_delta2ns(0xF, &lapic_clockevent);
698
699 calibration_result = (delta * APIC_DIVISOR) / LAPIC_CAL_LOOPS;
700
701 apic_printk(APIC_VERBOSE, "..... delta %ld\n", delta);
702 apic_printk(APIC_VERBOSE, "..... mult: %ld\n", lapic_clockevent.mult);
703 apic_printk(APIC_VERBOSE, "..... calibration result: %u\n",
704 calibration_result);
705
706 if (cpu_has_tsc) {
707 delta = (long)(lapic_cal_tsc2 - lapic_cal_tsc1);
708 apic_printk(APIC_VERBOSE, "..... CPU clock speed is "
709 "%ld.%04ld MHz.\n",
710 (delta / LAPIC_CAL_LOOPS) / (1000000 / HZ),
711 (delta / LAPIC_CAL_LOOPS) % (1000000 / HZ));
712 }
713
714 apic_printk(APIC_VERBOSE, "..... host bus clock speed is "
715 "%u.%04u MHz.\n",
716 calibration_result / (1000000 / HZ),
717 calibration_result % (1000000 / HZ));
718
719 /*
720 * Do a sanity check on the APIC calibration result
721 */
722 if (calibration_result < (1000000 / HZ)) {
723 local_irq_enable();
724 printk(KERN_WARNING
725 "APIC frequency too slow, disabling apic timer\n");
726 return -1;
727 }
728
729 levt->features &= ~CLOCK_EVT_FEAT_DUMMY;
730
731 /* We trust the pm timer based calibration */
732 if (!pm_referenced) {
733 apic_printk(APIC_VERBOSE, "... verify APIC timer\n");
734
735 /*
736 * Setup the apic timer manually
737 */
738 levt->event_handler = lapic_cal_handler;
739 lapic_timer_setup(CLOCK_EVT_MODE_PERIODIC, levt);
740 lapic_cal_loops = -1;
741
742 /* Let the interrupts run */
743 local_irq_enable();
744
745 while (lapic_cal_loops <= LAPIC_CAL_LOOPS)
746 cpu_relax();
747
748 local_irq_disable();
749
750 /* Stop the lapic timer */
751 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, levt);
752
753 local_irq_enable();
754
755 /* Jiffies delta */
756 deltaj = lapic_cal_j2 - lapic_cal_j1;
757 apic_printk(APIC_VERBOSE, "... jiffies delta = %lu\n", deltaj);
758
759 /* Check, if the jiffies result is consistent */
760 if (deltaj >= LAPIC_CAL_LOOPS-2 && deltaj <= LAPIC_CAL_LOOPS+2)
761 apic_printk(APIC_VERBOSE, "... jiffies result ok\n");
762 else
763 levt->features |= CLOCK_EVT_FEAT_DUMMY;
764 } else
765 local_irq_enable();
766
767 if (levt->features & CLOCK_EVT_FEAT_DUMMY) {
768 printk(KERN_WARNING
769 "APIC timer disabled due to verification failure.\n");
770 return -1;
771 }
772
773 return 0;
774}
775
776#endif
777
778/*
779 * Setup the boot APIC
780 *
781 * Calibrate and verify the result.
782 */
783void __init setup_boot_APIC_clock(void)
784{
785 /*
786 * The local apic timer can be disabled via the kernel
787 * commandline or from the CPU detection code. Register the lapic
788 * timer as a dummy clock event source on SMP systems, so the
789 * broadcast mechanism is used. On UP systems simply ignore it.
790 */
791 if (disable_apic_timer) {
792 printk(KERN_INFO "Disabling APIC timer\n");
793 /* No broadcast on UP ! */
794 if (num_possible_cpus() > 1) {
795 lapic_clockevent.mult = 1;
796 setup_APIC_timer();
797 }
798 return;
799 }
800
801 apic_printk(APIC_VERBOSE, "Using local APIC timer interrupts.\n"
802 "calibrating APIC timer ...\n");
803
804 if (calibrate_APIC_clock()) {
805 /* No broadcast on UP ! */
806 if (num_possible_cpus() > 1)
807 setup_APIC_timer();
808 return;
809 }
810
811 /*
812 * If nmi_watchdog is set to IO_APIC, we need the
813 * PIT/HPET going. Otherwise register lapic as a dummy
814 * device.
815 */
816 if (nmi_watchdog != NMI_IO_APIC)
817 lapic_clockevent.features &= ~CLOCK_EVT_FEAT_DUMMY;
818 else
819 printk(KERN_WARNING "APIC timer registered as dummy,"
820 " due to nmi_watchdog=%d!\n", nmi_watchdog);
821
822 /* Setup the lapic or request the broadcast */
823 setup_APIC_timer();
824}
825
826void __cpuinit setup_secondary_APIC_clock(void)
827{
828 setup_APIC_timer();
829}
830
831/*
832 * The guts of the apic timer interrupt
833 */
834static void local_apic_timer_interrupt(void)
835{
836 int cpu = smp_processor_id();
837 struct clock_event_device *evt = &per_cpu(lapic_events, cpu);
838
839 /*
840 * Normally we should not be here till LAPIC has been initialized but
841 * in some cases like kdump, its possible that there is a pending LAPIC
842 * timer interrupt from previous kernel's context and is delivered in
843 * new kernel the moment interrupts are enabled.
844 *
845 * Interrupts are enabled early and LAPIC is setup much later, hence
846 * its possible that when we get here evt->event_handler is NULL.
847 * Check for event_handler being NULL and discard the interrupt as
848 * spurious.
849 */
850 if (!evt->event_handler) {
851 printk(KERN_WARNING
852 "Spurious LAPIC timer interrupt on cpu %d\n", cpu);
853 /* Switch it off */
854 lapic_timer_setup(CLOCK_EVT_MODE_SHUTDOWN, evt);
855 return;
856 }
857
858 /*
859 * the NMI deadlock-detector uses this.
860 */
861#ifdef CONFIG_X86_64
862 add_pda(apic_timer_irqs, 1);
863#else
864 per_cpu(irq_stat, cpu).apic_timer_irqs++;
865#endif
866
867 evt->event_handler(evt);
868}
869
870/*
871 * Local APIC timer interrupt. This is the most natural way for doing
872 * local interrupts, but local timer interrupts can be emulated by
873 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
874 *
875 * [ if a single-CPU system runs an SMP kernel then we call the local
876 * interrupt as well. Thus we cannot inline the local irq ... ]
877 */
878void smp_apic_timer_interrupt(struct pt_regs *regs)
879{
880 struct pt_regs *old_regs = set_irq_regs(regs);
881
882 /*
883 * NOTE! We'd better ACK the irq immediately,
884 * because timer handling can be slow.
885 */
886 ack_APIC_irq();
887 /*
888 * update_process_times() expects us to have done irq_enter().
889 * Besides, if we don't timer interrupts ignore the global
890 * interrupt lock, which is the WrongThing (tm) to do.
891 */
892#ifdef CONFIG_X86_64
893 exit_idle();
894#endif
895 irq_enter();
896 local_apic_timer_interrupt();
897 irq_exit();
898
899 set_irq_regs(old_regs);
900}
901
902int setup_profiling_timer(unsigned int multiplier)
903{
904 return -EINVAL;
905}
906
907/*
908 * Local APIC start and shutdown
909 */
910
911/**
912 * clear_local_APIC - shutdown the local APIC
913 *
914 * This is called, when a CPU is disabled and before rebooting, so the state of
915 * the local APIC has no dangling leftovers. Also used to cleanout any BIOS
916 * leftovers during boot.
917 */
918void clear_local_APIC(void)
919{
920 int maxlvt;
921 u32 v;
922
923 /* APIC hasn't been mapped yet */
924 if (!apic_phys)
925 return;
926
927 maxlvt = lapic_get_maxlvt();
928 /*
929 * Masking an LVT entry can trigger a local APIC error
930 * if the vector is zero. Mask LVTERR first to prevent this.
931 */
932 if (maxlvt >= 3) {
933 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
934 apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
935 }
936 /*
937 * Careful: we have to set masks only first to deassert
938 * any level-triggered sources.
939 */
940 v = apic_read(APIC_LVTT);
941 apic_write(APIC_LVTT, v | APIC_LVT_MASKED);
942 v = apic_read(APIC_LVT0);
943 apic_write(APIC_LVT0, v | APIC_LVT_MASKED);
944 v = apic_read(APIC_LVT1);
945 apic_write(APIC_LVT1, v | APIC_LVT_MASKED);
946 if (maxlvt >= 4) {
947 v = apic_read(APIC_LVTPC);
948 apic_write(APIC_LVTPC, v | APIC_LVT_MASKED);
949 }
950
951 /* lets not touch this if we didn't frob it */
952#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(X86_MCE_INTEL)
953 if (maxlvt >= 5) {
954 v = apic_read(APIC_LVTTHMR);
955 apic_write(APIC_LVTTHMR, v | APIC_LVT_MASKED);
956 }
957#endif
958 /*
959 * Clean APIC state for other OSs:
960 */
961 apic_write(APIC_LVTT, APIC_LVT_MASKED);
962 apic_write(APIC_LVT0, APIC_LVT_MASKED);
963 apic_write(APIC_LVT1, APIC_LVT_MASKED);
964 if (maxlvt >= 3)
965 apic_write(APIC_LVTERR, APIC_LVT_MASKED);
966 if (maxlvt >= 4)
967 apic_write(APIC_LVTPC, APIC_LVT_MASKED);
968
969 /* Integrated APIC (!82489DX) ? */
970 if (lapic_is_integrated()) {
971 if (maxlvt > 3)
972 /* Clear ESR due to Pentium errata 3AP and 11AP */
973 apic_write(APIC_ESR, 0);
974 apic_read(APIC_ESR);
975 }
976}
977
978/**
979 * disable_local_APIC - clear and disable the local APIC
980 */
981void disable_local_APIC(void)
982{
983 unsigned int value;
984
985 clear_local_APIC();
986
987 /*
988 * Disable APIC (implies clearing of registers
989 * for 82489DX!).
990 */
991 value = apic_read(APIC_SPIV);
992 value &= ~APIC_SPIV_APIC_ENABLED;
993 apic_write(APIC_SPIV, value);
994
995#ifdef CONFIG_X86_32
996 /*
997 * When LAPIC was disabled by the BIOS and enabled by the kernel,
998 * restore the disabled state.
999 */
1000 if (enabled_via_apicbase) {
1001 unsigned int l, h;
1002
1003 rdmsr(MSR_IA32_APICBASE, l, h);
1004 l &= ~MSR_IA32_APICBASE_ENABLE;
1005 wrmsr(MSR_IA32_APICBASE, l, h);
1006 }
1007#endif
1008}
1009
1010/*
1011 * If Linux enabled the LAPIC against the BIOS default disable it down before
1012 * re-entering the BIOS on shutdown. Otherwise the BIOS may get confused and
1013 * not power-off. Additionally clear all LVT entries before disable_local_APIC
1014 * for the case where Linux didn't enable the LAPIC.
1015 */
1016void lapic_shutdown(void)
1017{
1018 unsigned long flags;
1019
1020 if (!cpu_has_apic)
1021 return;
1022
1023 local_irq_save(flags);
1024
1025#ifdef CONFIG_X86_32
1026 if (!enabled_via_apicbase)
1027 clear_local_APIC();
1028 else
1029#endif
1030 disable_local_APIC();
1031
1032
1033 local_irq_restore(flags);
1034}
1035
1036/*
1037 * This is to verify that we're looking at a real local APIC.
1038 * Check these against your board if the CPUs aren't getting
1039 * started for no apparent reason.
1040 */
1041int __init verify_local_APIC(void)
1042{
1043 unsigned int reg0, reg1;
1044
1045 /*
1046 * The version register is read-only in a real APIC.
1047 */
1048 reg0 = apic_read(APIC_LVR);
1049 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
1050 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
1051 reg1 = apic_read(APIC_LVR);
1052 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
1053
1054 /*
1055 * The two version reads above should print the same
1056 * numbers. If the second one is different, then we
1057 * poke at a non-APIC.
1058 */
1059 if (reg1 != reg0)
1060 return 0;
1061
1062 /*
1063 * Check if the version looks reasonably.
1064 */
1065 reg1 = GET_APIC_VERSION(reg0);
1066 if (reg1 == 0x00 || reg1 == 0xff)
1067 return 0;
1068 reg1 = lapic_get_maxlvt();
1069 if (reg1 < 0x02 || reg1 == 0xff)
1070 return 0;
1071
1072 /*
1073 * The ID register is read/write in a real APIC.
1074 */
1075 reg0 = apic_read(APIC_ID);
1076 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
1077 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
1078 reg1 = apic_read(APIC_ID);
1079 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
1080 apic_write(APIC_ID, reg0);
1081 if (reg1 != (reg0 ^ APIC_ID_MASK))
1082 return 0;
1083
1084 /*
1085 * The next two are just to see if we have sane values.
1086 * They're only really relevant if we're in Virtual Wire
1087 * compatibility mode, but most boxes are anymore.
1088 */
1089 reg0 = apic_read(APIC_LVT0);
1090 apic_printk(APIC_DEBUG, "Getting LVT0: %x\n", reg0);
1091 reg1 = apic_read(APIC_LVT1);
1092 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
1093
1094 return 1;
1095}
1096
1097/**
1098 * sync_Arb_IDs - synchronize APIC bus arbitration IDs
1099 */
1100void __init sync_Arb_IDs(void)
1101{
1102 /*
1103 * Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 And not
1104 * needed on AMD.
1105 */
1106 if (modern_apic() || boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1107 return;
1108
1109 /*
1110 * Wait for idle.
1111 */
1112 apic_wait_icr_idle();
1113
1114 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
1115 apic_write(APIC_ICR, APIC_DEST_ALLINC |
1116 APIC_INT_LEVELTRIG | APIC_DM_INIT);
1117}
1118
1119/*
1120 * An initial setup of the virtual wire mode.
1121 */
1122void __init init_bsp_APIC(void)
1123{
1124 unsigned int value;
1125
1126 /*
1127 * Don't do the setup now if we have a SMP BIOS as the
1128 * through-I/O-APIC virtual wire mode might be active.
1129 */
1130 if (smp_found_config || !cpu_has_apic)
1131 return;
1132
1133 /*
1134 * Do not trust the local APIC being empty at bootup.
1135 */
1136 clear_local_APIC();
1137
1138 /*
1139 * Enable APIC.
1140 */
1141 value = apic_read(APIC_SPIV);
1142 value &= ~APIC_VECTOR_MASK;
1143 value |= APIC_SPIV_APIC_ENABLED;
1144
1145#ifdef CONFIG_X86_32
1146 /* This bit is reserved on P4/Xeon and should be cleared */
1147 if ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) &&
1148 (boot_cpu_data.x86 == 15))
1149 value &= ~APIC_SPIV_FOCUS_DISABLED;
1150 else
1151#endif
1152 value |= APIC_SPIV_FOCUS_DISABLED;
1153 value |= SPURIOUS_APIC_VECTOR;
1154 apic_write(APIC_SPIV, value);
1155
1156 /*
1157 * Set up the virtual wire mode.
1158 */
1159 apic_write(APIC_LVT0, APIC_DM_EXTINT);
1160 value = APIC_DM_NMI;
1161 if (!lapic_is_integrated()) /* 82489DX */
1162 value |= APIC_LVT_LEVEL_TRIGGER;
1163 apic_write(APIC_LVT1, value);
1164}
1165
1166static void __cpuinit lapic_setup_esr(void)
1167{
1168 unsigned long oldvalue, value, maxlvt;
1169 if (lapic_is_integrated() && !esr_disable) {
1170 if (esr_disable) {
1171 /*
1172 * Something untraceable is creating bad interrupts on
1173 * secondary quads ... for the moment, just leave the
1174 * ESR disabled - we can't do anything useful with the
1175 * errors anyway - mbligh
1176 */
1177 printk(KERN_INFO "Leaving ESR disabled.\n");
1178 return;
1179 }
1180 /* !82489DX */
1181 maxlvt = lapic_get_maxlvt();
1182 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1183 apic_write(APIC_ESR, 0);
1184 oldvalue = apic_read(APIC_ESR);
1185
1186 /* enables sending errors */
1187 value = ERROR_APIC_VECTOR;
1188 apic_write(APIC_LVTERR, value);
1189 /*
1190 * spec says clear errors after enabling vector.
1191 */
1192 if (maxlvt > 3)
1193 apic_write(APIC_ESR, 0);
1194 value = apic_read(APIC_ESR);
1195 if (value != oldvalue)
1196 apic_printk(APIC_VERBOSE, "ESR value before enabling "
1197 "vector: 0x%08lx after: 0x%08lx\n",
1198 oldvalue, value);
1199 } else {
1200 printk(KERN_INFO "No ESR for 82489DX.\n");
1201 }
1202}
1203
1204
1205/**
1206 * setup_local_APIC - setup the local APIC
1207 */
1208void __cpuinit setup_local_APIC(void)
1209{
1210 unsigned int value;
1211 int i, j;
1212
1213#ifdef CONFIG_X86_32
1214 /* Pound the ESR really hard over the head with a big hammer - mbligh */
1215 if (esr_disable) {
1216 apic_write(APIC_ESR, 0);
1217 apic_write(APIC_ESR, 0);
1218 apic_write(APIC_ESR, 0);
1219 apic_write(APIC_ESR, 0);
1220 }
1221#endif
1222
1223 preempt_disable();
1224
1225 /*
1226 * Double-check whether this APIC is really registered.
1227 * This is meaningless in clustered apic mode, so we skip it.
1228 */
1229 if (!apic_id_registered())
1230 BUG();
1231
1232 /*
1233 * Intel recommends to set DFR, LDR and TPR before enabling
1234 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
1235 * document number 292116). So here it goes...
1236 */
1237 init_apic_ldr();
1238
1239 /*
1240 * Set Task Priority to 'accept all'. We never change this
1241 * later on.
1242 */
1243 value = apic_read(APIC_TASKPRI);
1244 value &= ~APIC_TPRI_MASK;
1245 apic_write(APIC_TASKPRI, value);
1246
1247 /*
1248 * After a crash, we no longer service the interrupts and a pending
1249 * interrupt from previous kernel might still have ISR bit set.
1250 *
1251 * Most probably by now CPU has serviced that pending interrupt and
1252 * it might not have done the ack_APIC_irq() because it thought,
1253 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
1254 * does not clear the ISR bit and cpu thinks it has already serivced
1255 * the interrupt. Hence a vector might get locked. It was noticed
1256 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
1257 */
1258 for (i = APIC_ISR_NR - 1; i >= 0; i--) {
1259 value = apic_read(APIC_ISR + i*0x10);
1260 for (j = 31; j >= 0; j--) {
1261 if (value & (1<<j))
1262 ack_APIC_irq();
1263 }
1264 }
1265
1266 /*
1267 * Now that we are all set up, enable the APIC
1268 */
1269 value = apic_read(APIC_SPIV);
1270 value &= ~APIC_VECTOR_MASK;
1271 /*
1272 * Enable APIC
1273 */
1274 value |= APIC_SPIV_APIC_ENABLED;
1275
1276#ifdef CONFIG_X86_32
1277 /*
1278 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
1279 * certain networking cards. If high frequency interrupts are
1280 * happening on a particular IOAPIC pin, plus the IOAPIC routing
1281 * entry is masked/unmasked at a high rate as well then sooner or
1282 * later IOAPIC line gets 'stuck', no more interrupts are received
1283 * from the device. If focus CPU is disabled then the hang goes
1284 * away, oh well :-(
1285 *
1286 * [ This bug can be reproduced easily with a level-triggered
1287 * PCI Ne2000 networking cards and PII/PIII processors, dual
1288 * BX chipset. ]
1289 */
1290 /*
1291 * Actually disabling the focus CPU check just makes the hang less
1292 * frequent as it makes the interrupt distributon model be more
1293 * like LRU than MRU (the short-term load is more even across CPUs).
1294 * See also the comment in end_level_ioapic_irq(). --macro
1295 */
1296
1297 /*
1298 * - enable focus processor (bit==0)
1299 * - 64bit mode always use processor focus
1300 * so no need to set it
1301 */
1302 value &= ~APIC_SPIV_FOCUS_DISABLED;
1303#endif
1304
1305 /*
1306 * Set spurious IRQ vector
1307 */
1308 value |= SPURIOUS_APIC_VECTOR;
1309 apic_write(APIC_SPIV, value);
1310
1311 /*
1312 * Set up LVT0, LVT1:
1313 *
1314 * set up through-local-APIC on the BP's LINT0. This is not
1315 * strictly necessary in pure symmetric-IO mode, but sometimes
1316 * we delegate interrupts to the 8259A.
1317 */
1318 /*
1319 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
1320 */
1321 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
1322 if (!smp_processor_id() && (pic_mode || !value)) {
1323 value = APIC_DM_EXTINT;
1324 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
1325 smp_processor_id());
1326 } else {
1327 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
1328 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
1329 smp_processor_id());
1330 }
1331 apic_write(APIC_LVT0, value);
1332
1333 /*
1334 * only the BP should see the LINT1 NMI signal, obviously.
1335 */
1336 if (!smp_processor_id())
1337 value = APIC_DM_NMI;
1338 else
1339 value = APIC_DM_NMI | APIC_LVT_MASKED;
1340 if (!lapic_is_integrated()) /* 82489DX */
1341 value |= APIC_LVT_LEVEL_TRIGGER;
1342 apic_write(APIC_LVT1, value);
1343
1344 preempt_enable();
1345}
1346
1347void __cpuinit end_local_APIC_setup(void)
1348{
1349 lapic_setup_esr();
1350
1351#ifdef CONFIG_X86_32
1352 {
1353 unsigned int value;
1354 /* Disable the local apic timer */
1355 value = apic_read(APIC_LVTT);
1356 value |= (APIC_LVT_MASKED | LOCAL_TIMER_VECTOR);
1357 apic_write(APIC_LVTT, value);
1358 }
1359#endif
1360
1361 setup_apic_nmi_watchdog(NULL);
1362 apic_pm_activate();
1363}
1364
1365#ifdef HAVE_X2APIC
1366void check_x2apic(void)
1367{
1368 int msr, msr2;
1369
1370 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1371
1372 if (msr & X2APIC_ENABLE) {
1373 printk("x2apic enabled by BIOS, switching to x2apic ops\n");
1374 x2apic_preenabled = x2apic = 1;
1375 apic_ops = &x2apic_ops;
1376 }
1377}
1378
1379void enable_x2apic(void)
1380{
1381 int msr, msr2;
1382
1383 rdmsr(MSR_IA32_APICBASE, msr, msr2);
1384 if (!(msr & X2APIC_ENABLE)) {
1385 printk("Enabling x2apic\n");
1386 wrmsr(MSR_IA32_APICBASE, msr | X2APIC_ENABLE, 0);
1387 }
1388}
1389
1390void enable_IR_x2apic(void)
1391{
1392#ifdef CONFIG_INTR_REMAP
1393 int ret;
1394 unsigned long flags;
1395
1396 if (!cpu_has_x2apic)
1397 return;
1398
1399 if (!x2apic_preenabled && disable_x2apic) {
1400 printk(KERN_INFO
1401 "Skipped enabling x2apic and Interrupt-remapping "
1402 "because of nox2apic\n");
1403 return;
1404 }
1405
1406 if (x2apic_preenabled && disable_x2apic)
1407 panic("Bios already enabled x2apic, can't enforce nox2apic");
1408
1409 if (!x2apic_preenabled && skip_ioapic_setup) {
1410 printk(KERN_INFO
1411 "Skipped enabling x2apic and Interrupt-remapping "
1412 "because of skipping io-apic setup\n");
1413 return;
1414 }
1415
1416 ret = dmar_table_init();
1417 if (ret) {
1418 printk(KERN_INFO
1419 "dmar_table_init() failed with %d:\n", ret);
1420
1421 if (x2apic_preenabled)
1422 panic("x2apic enabled by bios. But IR enabling failed");
1423 else
1424 printk(KERN_INFO
1425 "Not enabling x2apic,Intr-remapping\n");
1426 return;
1427 }
1428
1429 local_irq_save(flags);
1430 mask_8259A();
1431 save_mask_IO_APIC_setup();
1432
1433 ret = enable_intr_remapping(1);
1434
1435 if (ret && x2apic_preenabled) {
1436 local_irq_restore(flags);
1437 panic("x2apic enabled by bios. But IR enabling failed");
1438 }
1439
1440 if (ret)
1441 goto end;
1442
1443 if (!x2apic) {
1444 x2apic = 1;
1445 apic_ops = &x2apic_ops;
1446 enable_x2apic();
1447 }
1448end:
1449 if (ret)
1450 /*
1451 * IR enabling failed
1452 */
1453 restore_IO_APIC_setup();
1454 else
1455 reinit_intr_remapped_IO_APIC(x2apic_preenabled);
1456
1457 unmask_8259A();
1458 local_irq_restore(flags);
1459
1460 if (!ret) {
1461 if (!x2apic_preenabled)
1462 printk(KERN_INFO
1463 "Enabled x2apic and interrupt-remapping\n");
1464 else
1465 printk(KERN_INFO
1466 "Enabled Interrupt-remapping\n");
1467 } else
1468 printk(KERN_ERR
1469 "Failed to enable Interrupt-remapping and x2apic\n");
1470#else
1471 if (!cpu_has_x2apic)
1472 return;
1473
1474 if (x2apic_preenabled)
1475 panic("x2apic enabled prior OS handover,"
1476 " enable CONFIG_INTR_REMAP");
1477
1478 printk(KERN_INFO "Enable CONFIG_INTR_REMAP for enabling intr-remapping "
1479 " and x2apic\n");
1480#endif
1481
1482 return;
1483}
1484#endif /* HAVE_X2APIC */
1485
1486#ifdef CONFIG_X86_64
1487/*
1488 * Detect and enable local APICs on non-SMP boards.
1489 * Original code written by Keir Fraser.
1490 * On AMD64 we trust the BIOS - if it says no APIC it is likely
1491 * not correctly set up (usually the APIC timer won't work etc.)
1492 */
1493static int __init detect_init_APIC(void)
1494{
1495 if (!cpu_has_apic) {
1496 printk(KERN_INFO "No local APIC present\n");
1497 return -1;
1498 }
1499
1500 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1501 boot_cpu_physical_apicid = 0;
1502 return 0;
1503}
1504#else
1505/*
1506 * Detect and initialize APIC
1507 */
1508static int __init detect_init_APIC(void)
1509{
1510 u32 h, l, features;
1511
1512 /* Disabled by kernel option? */
1513 if (disable_apic)
1514 return -1;
1515
1516 switch (boot_cpu_data.x86_vendor) {
1517 case X86_VENDOR_AMD:
1518 if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model > 1) ||
1519 (boot_cpu_data.x86 == 15))
1520 break;
1521 goto no_apic;
1522 case X86_VENDOR_INTEL:
1523 if (boot_cpu_data.x86 == 6 || boot_cpu_data.x86 == 15 ||
1524 (boot_cpu_data.x86 == 5 && cpu_has_apic))
1525 break;
1526 goto no_apic;
1527 default:
1528 goto no_apic;
1529 }
1530
1531 if (!cpu_has_apic) {
1532 /*
1533 * Over-ride BIOS and try to enable the local APIC only if
1534 * "lapic" specified.
1535 */
1536 if (!force_enable_local_apic) {
1537 printk(KERN_INFO "Local APIC disabled by BIOS -- "
1538 "you can enable it with \"lapic\"\n");
1539 return -1;
1540 }
1541 /*
1542 * Some BIOSes disable the local APIC in the APIC_BASE
1543 * MSR. This can only be done in software for Intel P6 or later
1544 * and AMD K7 (Model > 1) or later.
1545 */
1546 rdmsr(MSR_IA32_APICBASE, l, h);
1547 if (!(l & MSR_IA32_APICBASE_ENABLE)) {
1548 printk(KERN_INFO
1549 "Local APIC disabled by BIOS -- reenabling.\n");
1550 l &= ~MSR_IA32_APICBASE_BASE;
1551 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
1552 wrmsr(MSR_IA32_APICBASE, l, h);
1553 enabled_via_apicbase = 1;
1554 }
1555 }
1556 /*
1557 * The APIC feature bit should now be enabled
1558 * in `cpuid'
1559 */
1560 features = cpuid_edx(1);
1561 if (!(features & (1 << X86_FEATURE_APIC))) {
1562 printk(KERN_WARNING "Could not enable APIC!\n");
1563 return -1;
1564 }
1565 set_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1566 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
1567
1568 /* The BIOS may have set up the APIC at some other address */
1569 rdmsr(MSR_IA32_APICBASE, l, h);
1570 if (l & MSR_IA32_APICBASE_ENABLE)
1571 mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
1572
1573 printk(KERN_INFO "Found and enabled local APIC!\n");
1574
1575 apic_pm_activate();
1576
1577 return 0;
1578
1579no_apic:
1580 printk(KERN_INFO "No local APIC present or hardware disabled\n");
1581 return -1;
1582}
1583#endif
1584
1585#ifdef CONFIG_X86_64
1586void __init early_init_lapic_mapping(void)
1587{
1588 unsigned long phys_addr;
1589
1590 /*
1591 * If no local APIC can be found then go out
1592 * : it means there is no mpatable and MADT
1593 */
1594 if (!smp_found_config)
1595 return;
1596
1597 phys_addr = mp_lapic_addr;
1598
1599 set_fixmap_nocache(FIX_APIC_BASE, phys_addr);
1600 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1601 APIC_BASE, phys_addr);
1602
1603 /*
1604 * Fetch the APIC ID of the BSP in case we have a
1605 * default configuration (or the MP table is broken).
1606 */
1607 boot_cpu_physical_apicid = read_apic_id();
1608}
1609#endif
1610
1611/**
1612 * init_apic_mappings - initialize APIC mappings
1613 */
1614void __init init_apic_mappings(void)
1615{
1616#ifdef HAVE_X2APIC
1617 if (x2apic) {
1618 boot_cpu_physical_apicid = read_apic_id();
1619 return;
1620 }
1621#endif
1622
1623 /*
1624 * If no local APIC can be found then set up a fake all
1625 * zeroes page to simulate the local APIC and another
1626 * one for the IO-APIC.
1627 */
1628 if (!smp_found_config && detect_init_APIC()) {
1629 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
1630 apic_phys = __pa(apic_phys);
1631 } else
1632 apic_phys = mp_lapic_addr;
1633
1634 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
1635 apic_printk(APIC_VERBOSE, "mapped APIC to %16lx (%16lx)\n",
1636 APIC_BASE, apic_phys);
1637
1638 /*
1639 * Fetch the APIC ID of the BSP in case we have a
1640 * default configuration (or the MP table is broken).
1641 */
1642 if (boot_cpu_physical_apicid == -1U)
1643 boot_cpu_physical_apicid = read_apic_id();
1644}
1645
1646/*
1647 * This initializes the IO-APIC and APIC hardware if this is
1648 * a UP kernel.
1649 */
1650int apic_version[MAX_APICS];
1651
1652int __init APIC_init_uniprocessor(void)
1653{
1654#ifdef CONFIG_X86_64
1655 if (disable_apic) {
1656 printk(KERN_INFO "Apic disabled\n");
1657 return -1;
1658 }
1659 if (!cpu_has_apic) {
1660 disable_apic = 1;
1661 printk(KERN_INFO "Apic disabled by BIOS\n");
1662 return -1;
1663 }
1664#else
1665 if (!smp_found_config && !cpu_has_apic)
1666 return -1;
1667
1668 /*
1669 * Complain if the BIOS pretends there is one.
1670 */
1671 if (!cpu_has_apic &&
1672 APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
1673 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
1674 boot_cpu_physical_apicid);
1675 clear_cpu_cap(&boot_cpu_data, X86_FEATURE_APIC);
1676 return -1;
1677 }
1678#endif
1679
1680#ifdef HAVE_X2APIC
1681 enable_IR_x2apic();
1682#endif
1683#ifdef CONFIG_X86_64
1684 setup_apic_routing();
1685#endif
1686
1687 verify_local_APIC();
1688 connect_bsp_APIC();
1689
1690#ifdef CONFIG_X86_64
1691 apic_write(APIC_ID, SET_APIC_ID(boot_cpu_physical_apicid));
1692#else
1693 /*
1694 * Hack: In case of kdump, after a crash, kernel might be booting
1695 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1696 * might be zero if read from MP tables. Get it from LAPIC.
1697 */
1698# ifdef CONFIG_CRASH_DUMP
1699 boot_cpu_physical_apicid = read_apic_id();
1700# endif
1701#endif
1702 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1703 setup_local_APIC();
1704
1705#ifdef CONFIG_X86_64
1706 /*
1707 * Now enable IO-APICs, actually call clear_IO_APIC
1708 * We need clear_IO_APIC before enabling vector on BP
1709 */
1710 if (!skip_ioapic_setup && nr_ioapics)
1711 enable_IO_APIC();
1712#endif
1713
1714#ifdef CONFIG_X86_IO_APIC
1715 if (!smp_found_config || skip_ioapic_setup || !nr_ioapics)
1716#endif
1717 localise_nmi_watchdog();
1718 end_local_APIC_setup();
1719
1720#ifdef CONFIG_X86_IO_APIC
1721 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1722 setup_IO_APIC();
1723# ifdef CONFIG_X86_64
1724 else
1725 nr_ioapics = 0;
1726# endif
1727#endif
1728
1729#ifdef CONFIG_X86_64
1730 setup_boot_APIC_clock();
1731 check_nmi_watchdog();
1732#else
1733 setup_boot_clock();
1734#endif
1735
1736 return 0;
1737}
1738
1739/*
1740 * Local APIC interrupts
1741 */
1742
1743/*
1744 * This interrupt should _never_ happen with our APIC/SMP architecture
1745 */
1746#ifdef CONFIG_X86_64
1747asmlinkage void smp_spurious_interrupt(void)
1748#else
1749void smp_spurious_interrupt(struct pt_regs *regs)
1750#endif
1751{
1752 u32 v;
1753
1754#ifdef CONFIG_X86_64
1755 exit_idle();
1756#endif
1757 irq_enter();
1758 /*
1759 * Check if this really is a spurious interrupt and ACK it
1760 * if it is a vectored one. Just in case...
1761 * Spurious interrupts should not be ACKed.
1762 */
1763 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
1764 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
1765 ack_APIC_irq();
1766
1767#ifdef CONFIG_X86_64
1768 add_pda(irq_spurious_count, 1);
1769#else
1770 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1771 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, "
1772 "should never happen.\n", smp_processor_id());
1773 __get_cpu_var(irq_stat).irq_spurious_count++;
1774#endif
1775 irq_exit();
1776}
1777
1778/*
1779 * This interrupt should never happen with our APIC/SMP architecture
1780 */
1781#ifdef CONFIG_X86_64
1782asmlinkage void smp_error_interrupt(void)
1783#else
1784void smp_error_interrupt(struct pt_regs *regs)
1785#endif
1786{
1787 u32 v, v1;
1788
1789#ifdef CONFIG_X86_64
1790 exit_idle();
1791#endif
1792 irq_enter();
1793 /* First tickle the hardware, only then report what went on. -- REW */
1794 v = apic_read(APIC_ESR);
1795 apic_write(APIC_ESR, 0);
1796 v1 = apic_read(APIC_ESR);
1797 ack_APIC_irq();
1798 atomic_inc(&irq_err_count);
1799
1800 /* Here is what the APIC error bits mean:
1801 0: Send CS error
1802 1: Receive CS error
1803 2: Send accept error
1804 3: Receive accept error
1805 4: Reserved
1806 5: Send illegal vector
1807 6: Received illegal vector
1808 7: Illegal register address
1809 */
1810 printk(KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1811 smp_processor_id(), v , v1);
1812 irq_exit();
1813}
1814
1815/**
1816 * connect_bsp_APIC - attach the APIC to the interrupt system
1817 */
1818void __init connect_bsp_APIC(void)
1819{
1820#ifdef CONFIG_X86_32
1821 if (pic_mode) {
1822 /*
1823 * Do not trust the local APIC being empty at bootup.
1824 */
1825 clear_local_APIC();
1826 /*
1827 * PIC mode, enable APIC mode in the IMCR, i.e. connect BSP's
1828 * local APIC to INT and NMI lines.
1829 */
1830 apic_printk(APIC_VERBOSE, "leaving PIC mode, "
1831 "enabling APIC mode.\n");
1832 outb(0x70, 0x22);
1833 outb(0x01, 0x23);
1834 }
1835#endif
1836 enable_apic_mode();
1837}
1838
1839/**
1840 * disconnect_bsp_APIC - detach the APIC from the interrupt system
1841 * @virt_wire_setup: indicates, whether virtual wire mode is selected
1842 *
1843 * Virtual wire mode is necessary to deliver legacy interrupts even when the
1844 * APIC is disabled.
1845 */
1846void disconnect_bsp_APIC(int virt_wire_setup)
1847{
1848 unsigned int value;
1849
1850#ifdef CONFIG_X86_32
1851 if (pic_mode) {
1852 /*
1853 * Put the board back into PIC mode (has an effect only on
1854 * certain older boards). Note that APIC interrupts, including
1855 * IPIs, won't work beyond this point! The only exception are
1856 * INIT IPIs.
1857 */
1858 apic_printk(APIC_VERBOSE, "disabling APIC mode, "
1859 "entering PIC mode.\n");
1860 outb(0x70, 0x22);
1861 outb(0x00, 0x23);
1862 return;
1863 }
1864#endif
1865
1866 /* Go back to Virtual Wire compatibility mode */
1867
1868 /* For the spurious interrupt use vector F, and enable it */
1869 value = apic_read(APIC_SPIV);
1870 value &= ~APIC_VECTOR_MASK;
1871 value |= APIC_SPIV_APIC_ENABLED;
1872 value |= 0xf;
1873 apic_write(APIC_SPIV, value);
1874
1875 if (!virt_wire_setup) {
1876 /*
1877 * For LVT0 make it edge triggered, active high,
1878 * external and enabled
1879 */
1880 value = apic_read(APIC_LVT0);
1881 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1882 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1883 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1884 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1885 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_EXTINT);
1886 apic_write(APIC_LVT0, value);
1887 } else {
1888 /* Disable LVT0 */
1889 apic_write(APIC_LVT0, APIC_LVT_MASKED);
1890 }
1891
1892 /*
1893 * For LVT1 make it edge triggered, active high,
1894 * nmi and enabled
1895 */
1896 value = apic_read(APIC_LVT1);
1897 value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
1898 APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
1899 APIC_LVT_LEVEL_TRIGGER | APIC_LVT_MASKED);
1900 value |= APIC_LVT_REMOTE_IRR | APIC_SEND_PENDING;
1901 value = SET_APIC_DELIVERY_MODE(value, APIC_MODE_NMI);
1902 apic_write(APIC_LVT1, value);
1903}
1904
1905void __cpuinit generic_processor_info(int apicid, int version)
1906{
1907 int cpu;
1908 cpumask_t tmp_map;
1909
1910 /*
1911 * Validate version
1912 */
1913 if (version == 0x0) {
1914 printk(KERN_WARNING "BIOS bug, APIC version is 0 for CPU#%d! "
1915 "fixing up to 0x10. (tell your hw vendor)\n",
1916 version);
1917 version = 0x10;
1918 }
1919 apic_version[apicid] = version;
1920
1921 if (num_processors >= NR_CPUS) {
1922 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
1923 " Processor ignored.\n", NR_CPUS);
1924 return;
1925 }
1926
1927 num_processors++;
1928 cpus_complement(tmp_map, cpu_present_map);
1929 cpu = first_cpu(tmp_map);
1930
1931 physid_set(apicid, phys_cpu_present_map);
1932 if (apicid == boot_cpu_physical_apicid) {
1933 /*
1934 * x86_bios_cpu_apicid is required to have processors listed
1935 * in same order as logical cpu numbers. Hence the first
1936 * entry is BSP, and so on.
1937 */
1938 cpu = 0;
1939 }
1940 if (apicid > max_physical_apicid)
1941 max_physical_apicid = apicid;
1942
1943#ifdef CONFIG_X86_32
1944 /*
1945 * Would be preferable to switch to bigsmp when CONFIG_HOTPLUG_CPU=y
1946 * but we need to work other dependencies like SMP_SUSPEND etc
1947 * before this can be done without some confusion.
1948 * if (CPU_HOTPLUG_ENABLED || num_processors > 8)
1949 * - Ashok Raj <ashok.raj@intel.com>
1950 */
1951 if (max_physical_apicid >= 8) {
1952 switch (boot_cpu_data.x86_vendor) {
1953 case X86_VENDOR_INTEL:
1954 if (!APIC_XAPIC(version)) {
1955 def_to_bigsmp = 0;
1956 break;
1957 }
1958 /* If P4 and above fall through */
1959 case X86_VENDOR_AMD:
1960 def_to_bigsmp = 1;
1961 }
1962 }
1963#endif
1964
1965#if defined(CONFIG_X86_SMP) || defined(CONFIG_X86_64)
1966 /* are we being called early in kernel startup? */
1967 if (early_per_cpu_ptr(x86_cpu_to_apicid)) {
1968 u16 *cpu_to_apicid = early_per_cpu_ptr(x86_cpu_to_apicid);
1969 u16 *bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
1970
1971 cpu_to_apicid[cpu] = apicid;
1972 bios_cpu_apicid[cpu] = apicid;
1973 } else {
1974 per_cpu(x86_cpu_to_apicid, cpu) = apicid;
1975 per_cpu(x86_bios_cpu_apicid, cpu) = apicid;
1976 }
1977#endif
1978
1979 cpu_set(cpu, cpu_possible_map);
1980 cpu_set(cpu, cpu_present_map);
1981}
1982
1983#ifdef CONFIG_X86_64
1984int hard_smp_processor_id(void)
1985{
1986 return read_apic_id();
1987}
1988#endif
1989
1990/*
1991 * Power management
1992 */
1993#ifdef CONFIG_PM
1994
1995static struct {
1996 /*
1997 * 'active' is true if the local APIC was enabled by us and
1998 * not the BIOS; this signifies that we are also responsible
1999 * for disabling it before entering apm/acpi suspend
2000 */
2001 int active;
2002 /* r/w apic fields */
2003 unsigned int apic_id;
2004 unsigned int apic_taskpri;
2005 unsigned int apic_ldr;
2006 unsigned int apic_dfr;
2007 unsigned int apic_spiv;
2008 unsigned int apic_lvtt;
2009 unsigned int apic_lvtpc;
2010 unsigned int apic_lvt0;
2011 unsigned int apic_lvt1;
2012 unsigned int apic_lvterr;
2013 unsigned int apic_tmict;
2014 unsigned int apic_tdcr;
2015 unsigned int apic_thmr;
2016} apic_pm_state;
2017
2018static int lapic_suspend(struct sys_device *dev, pm_message_t state)
2019{
2020 unsigned long flags;
2021 int maxlvt;
2022
2023 if (!apic_pm_state.active)
2024 return 0;
2025
2026 maxlvt = lapic_get_maxlvt();
2027
2028 apic_pm_state.apic_id = apic_read(APIC_ID);
2029 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
2030 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
2031 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
2032 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
2033 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
2034 if (maxlvt >= 4)
2035 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
2036 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
2037 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
2038 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
2039 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
2040 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
2041#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2042 if (maxlvt >= 5)
2043 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
2044#endif
2045
2046 local_irq_save(flags);
2047 disable_local_APIC();
2048 local_irq_restore(flags);
2049 return 0;
2050}
2051
2052static int lapic_resume(struct sys_device *dev)
2053{
2054 unsigned int l, h;
2055 unsigned long flags;
2056 int maxlvt;
2057
2058 if (!apic_pm_state.active)
2059 return 0;
2060
2061 maxlvt = lapic_get_maxlvt();
2062
2063 local_irq_save(flags);
2064
2065#ifdef HAVE_X2APIC
2066 if (x2apic)
2067 enable_x2apic();
2068 else
2069#endif
2070 {
2071 /*
2072 * Make sure the APICBASE points to the right address
2073 *
2074 * FIXME! This will be wrong if we ever support suspend on
2075 * SMP! We'll need to do this as part of the CPU restore!
2076 */
2077 rdmsr(MSR_IA32_APICBASE, l, h);
2078 l &= ~MSR_IA32_APICBASE_BASE;
2079 l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
2080 wrmsr(MSR_IA32_APICBASE, l, h);
2081 }
2082
2083 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
2084 apic_write(APIC_ID, apic_pm_state.apic_id);
2085 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
2086 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
2087 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
2088 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
2089 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
2090 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
2091#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
2092 if (maxlvt >= 5)
2093 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
2094#endif
2095 if (maxlvt >= 4)
2096 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
2097 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
2098 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
2099 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
2100 apic_write(APIC_ESR, 0);
2101 apic_read(APIC_ESR);
2102 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
2103 apic_write(APIC_ESR, 0);
2104 apic_read(APIC_ESR);
2105
2106 local_irq_restore(flags);
2107
2108 return 0;
2109}
2110
2111/*
2112 * This device has no shutdown method - fully functioning local APICs
2113 * are needed on every CPU up until machine_halt/restart/poweroff.
2114 */
2115
2116static struct sysdev_class lapic_sysclass = {
2117 .name = "lapic",
2118 .resume = lapic_resume,
2119 .suspend = lapic_suspend,
2120};
2121
2122static struct sys_device device_lapic = {
2123 .id = 0,
2124 .cls = &lapic_sysclass,
2125};
2126
2127static void __cpuinit apic_pm_activate(void)
2128{
2129 apic_pm_state.active = 1;
2130}
2131
2132static int __init init_lapic_sysfs(void)
2133{
2134 int error;
2135
2136 if (!cpu_has_apic)
2137 return 0;
2138 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
2139
2140 error = sysdev_class_register(&lapic_sysclass);
2141 if (!error)
2142 error = sysdev_register(&device_lapic);
2143 return error;
2144}
2145device_initcall(init_lapic_sysfs);
2146
2147#else /* CONFIG_PM */
2148
2149static void apic_pm_activate(void) { }
2150
2151#endif /* CONFIG_PM */
2152
2153#ifdef CONFIG_X86_64
2154/*
2155 * apic_is_clustered_box() -- Check if we can expect good TSC
2156 *
2157 * Thus far, the major user of this is IBM's Summit2 series:
2158 *
2159 * Clustered boxes may have unsynced TSC problems if they are
2160 * multi-chassis. Use available data to take a good guess.
2161 * If in doubt, go HPET.
2162 */
2163__cpuinit int apic_is_clustered_box(void)
2164{
2165 int i, clusters, zeros;
2166 unsigned id;
2167 u16 *bios_cpu_apicid;
2168 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
2169
2170 /*
2171 * there is not this kind of box with AMD CPU yet.
2172 * Some AMD box with quadcore cpu and 8 sockets apicid
2173 * will be [4, 0x23] or [8, 0x27] could be thought to
2174 * vsmp box still need checking...
2175 */
2176 if ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && !is_vsmp_box())
2177 return 0;
2178
2179 bios_cpu_apicid = early_per_cpu_ptr(x86_bios_cpu_apicid);
2180 bitmap_zero(clustermap, NUM_APIC_CLUSTERS);
2181
2182 for (i = 0; i < NR_CPUS; i++) {
2183 /* are we being called early in kernel startup? */
2184 if (bios_cpu_apicid) {
2185 id = bios_cpu_apicid[i];
2186 }
2187 else if (i < nr_cpu_ids) {
2188 if (cpu_present(i))
2189 id = per_cpu(x86_bios_cpu_apicid, i);
2190 else
2191 continue;
2192 }
2193 else
2194 break;
2195
2196 if (id != BAD_APICID)
2197 __set_bit(APIC_CLUSTERID(id), clustermap);
2198 }
2199
2200 /* Problem: Partially populated chassis may not have CPUs in some of
2201 * the APIC clusters they have been allocated. Only present CPUs have
2202 * x86_bios_cpu_apicid entries, thus causing zeroes in the bitmap.
2203 * Since clusters are allocated sequentially, count zeros only if
2204 * they are bounded by ones.
2205 */
2206 clusters = 0;
2207 zeros = 0;
2208 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
2209 if (test_bit(i, clustermap)) {
2210 clusters += 1 + zeros;
2211 zeros = 0;
2212 } else
2213 ++zeros;
2214 }
2215
2216 /* ScaleMP vSMPowered boxes have one cluster per board and TSCs are
2217 * not guaranteed to be synced between boards
2218 */
2219 if (is_vsmp_box() && clusters > 1)
2220 return 1;
2221
2222 /*
2223 * If clusters > 2, then should be multi-chassis.
2224 * May have to revisit this when multi-core + hyperthreaded CPUs come
2225 * out, but AFAIK this will work even for them.
2226 */
2227 return (clusters > 2);
2228}
2229#endif
2230
2231/*
2232 * APIC command line parameters
2233 */
2234static int __init setup_disableapic(char *arg)
2235{
2236 disable_apic = 1;
2237 setup_clear_cpu_cap(X86_FEATURE_APIC);
2238 return 0;
2239}
2240early_param("disableapic", setup_disableapic);
2241
2242/* same as disableapic, for compatibility */
2243static int __init setup_nolapic(char *arg)
2244{
2245 return setup_disableapic(arg);
2246}
2247early_param("nolapic", setup_nolapic);
2248
2249static int __init parse_lapic_timer_c2_ok(char *arg)
2250{
2251 local_apic_timer_c2_ok = 1;
2252 return 0;
2253}
2254early_param("lapic_timer_c2_ok", parse_lapic_timer_c2_ok);
2255
2256static int __init parse_disable_apic_timer(char *arg)
2257{
2258 disable_apic_timer = 1;
2259 return 0;
2260}
2261early_param("noapictimer", parse_disable_apic_timer);
2262
2263static int __init parse_nolapic_timer(char *arg)
2264{
2265 disable_apic_timer = 1;
2266 return 0;
2267}
2268early_param("nolapic_timer", parse_nolapic_timer);
2269
2270static int __init apic_set_verbosity(char *arg)
2271{
2272 if (!arg) {
2273#ifdef CONFIG_X86_64
2274 skip_ioapic_setup = 0;
2275 ioapic_force = 1;
2276 return 0;
2277#endif
2278 return -EINVAL;
2279 }
2280
2281 if (strcmp("debug", arg) == 0)
2282 apic_verbosity = APIC_DEBUG;
2283 else if (strcmp("verbose", arg) == 0)
2284 apic_verbosity = APIC_VERBOSE;
2285 else {
2286 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
2287 " use apic=verbose or apic=debug\n", arg);
2288 return -EINVAL;
2289 }
2290
2291 return 0;
2292}
2293early_param("apic", apic_set_verbosity);
2294
2295static int __init lapic_insert_resource(void)
2296{
2297 if (!apic_phys)
2298 return -1;
2299
2300 /* Put local APIC into the resource map. */
2301 lapic_resource.start = apic_phys;
2302 lapic_resource.end = lapic_resource.start + PAGE_SIZE - 1;
2303 insert_resource(&iomem_resource, &lapic_resource);
2304
2305 return 0;
2306}
2307
2308/*
2309 * need call insert after e820_reserve_resources()
2310 * that is using request_resource
2311 */
2312late_initcall(lapic_insert_resource);
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-15 12:52:20 -0500