KVM: x86: fix lapic.timer_mode on restore

lapic.timer_mode was not properly initialized after migration, which
broke few useful things, like login, by making every sleep eternal.

Fix this by calling apic_update_lvtt in kvm_apic_post_state_restore.

There are other slowpaths that update lvtt, so this patch makes sure
something similar doesn't happen again by calling apic_update_lvtt
after every modification.

Cc: stable@vger.kernel.org
Fixes: f30ebc312ca9 ("KVM: x86: optimize some accesses to LVTT and SPIV")
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>

1 files changed, 16 insertions, 10 deletions

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 629af0f1c5c4..4c7deb4f78a1 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -1090,6 +1090,17 @@ static void update_divide_count(struct kvm_lapic *apic)
                                    apic->divide_count);
 }
 
+static void apic_update_lvtt(struct kvm_lapic *apic)
+{
+        u32 timer_mode = kvm_apic_get_reg(apic, APIC_LVTT) &
+                        apic->lapic_timer.timer_mode_mask;
+
+        if (apic->lapic_timer.timer_mode != timer_mode) {
+                apic->lapic_timer.timer_mode = timer_mode;
+                hrtimer_cancel(&apic->lapic_timer.timer);
+        }
+}
+
 static void apic_timer_expired(struct kvm_lapic *apic)
 {
         struct kvm_vcpu *vcpu = apic->vcpu;
@@ -1298,6 +1309,7 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
                                 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
                                              lvt_val | APIC_LVT_MASKED);
                         }
+                        apic_update_lvtt(apic);
                         atomic_set(&apic->lapic_timer.pending, 0);
 
                 }
@@ -1330,20 +1342,13 @@ static int apic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
 
                 break;
 
-        case APIC_LVTT: {
-                u32 timer_mode = val & apic->lapic_timer.timer_mode_mask;
-
-                if (apic->lapic_timer.timer_mode != timer_mode) {
-                        apic->lapic_timer.timer_mode = timer_mode;
-                        hrtimer_cancel(&apic->lapic_timer.timer);
-                }
-
+        case APIC_LVTT:
                 if (!kvm_apic_sw_enabled(apic))
                         val |= APIC_LVT_MASKED;
                 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
                 apic_set_reg(apic, APIC_LVTT, val);
+                apic_update_lvtt(apic);
                 break;
-        }
 
         case APIC_TMICT:
                 if (apic_lvtt_tscdeadline(apic))
@@ -1576,7 +1581,7 @@ void kvm_lapic_reset(struct kvm_vcpu *vcpu)
 
         for (i = 0; i < APIC_LVT_NUM; i++)
                 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
-        apic->lapic_timer.timer_mode = 0;
+        apic_update_lvtt(apic);
         apic_set_reg(apic, APIC_LVT0,
                      SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
 
@@ -1802,6 +1807,7 @@ void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu,
 
         apic_update_ppr(apic);
         hrtimer_cancel(&apic->lapic_timer.timer);
+        apic_update_lvtt(apic);
         update_divide_count(apic);
         start_apic_timer(apic);
         apic->irr_pending = true;