diff options
author | Peter Zijlstra <a.p.zijlstra@chello.nl> | 2010-03-06 12:57:38 -0500 |
---|---|---|
committer | Ingo Molnar <mingo@elte.hu> | 2010-03-10 07:23:38 -0500 |
commit | 12ab854d744f04bfc5c6c4db723b7e31fc03eb29 (patch) | |
tree | 806836c7ad911d206978e800a14000f4b6ae4441 /arch/x86 | |
parent | d329527e47851f84b1e7944ed9601205f35f1b93 (diff) |
perf, x86: Deal with multiple state bits for pebs-fmt1
Its unclear if the PEBS state record will have only a single bit set, in
case it does not and accumulates bits, deal with that by only processing
each event once.
Also, robustify some of the code.
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: Arnaldo Carvalho de Melo <acme@infradead.org>
Cc: paulus@samba.org
Cc: eranian@google.com
Cc: robert.richter@amd.com
Cc: fweisbec@gmail.com
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
-rw-r--r-- | arch/x86/kernel/cpu/perf_event_intel_ds.c | 16 |
1 files changed, 13 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c b/arch/x86/kernel/cpu/perf_event_intel_ds.c index 9ad0e67b9c82..b4680daecf19 100644 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c | |||
@@ -538,6 +538,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) | |||
538 | struct perf_event *event = NULL; | 538 | struct perf_event *event = NULL; |
539 | struct perf_raw_record raw; | 539 | struct perf_raw_record raw; |
540 | struct pt_regs regs; | 540 | struct pt_regs regs; |
541 | u64 status = 0; | ||
541 | int bit, n; | 542 | int bit, n; |
542 | 543 | ||
543 | if (!ds || !x86_pmu.pebs) | 544 | if (!ds || !x86_pmu.pebs) |
@@ -561,13 +562,22 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs) | |||
561 | 562 | ||
562 | for ( ; at < top; at++) { | 563 | for ( ; at < top; at++) { |
563 | for_each_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) { | 564 | for_each_bit(bit, (unsigned long *)&at->status, MAX_PEBS_EVENTS) { |
564 | if (!cpuc->events[bit]->attr.precise) | 565 | event = cpuc->events[bit]; |
566 | if (!test_bit(bit, cpuc->active_mask)) | ||
565 | continue; | 567 | continue; |
566 | 568 | ||
567 | event = cpuc->events[bit]; | 569 | WARN_ON_ONCE(!event); |
570 | |||
571 | if (!event->attr.precise) | ||
572 | continue; | ||
573 | |||
574 | if (__test_and_set_bit(bit, (unsigned long *)&status)) | ||
575 | continue; | ||
576 | |||
577 | break; | ||
568 | } | 578 | } |
569 | 579 | ||
570 | if (!event) | 580 | if (!event || bit >= MAX_PEBS_EVENTS) |
571 | continue; | 581 | continue; |
572 | 582 | ||
573 | if (!intel_pmu_save_and_restart(event)) | 583 | if (!intel_pmu_save_and_restart(event)) |