Merge branch 'perf/urgent' into perf/core

Merge reason: we need to queue up dependent patch

Signed-off-by: Ingo Molnar <mingo@elte.hu>

11 files changed, 44 insertions, 18 deletions

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 5e3969c36d7f..3c896946f4cc 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -233,6 +233,7 @@ extern void sync_Arb_IDs(void);
 extern void init_bsp_APIC(void);
 extern void setup_local_APIC(void);
 extern void end_local_APIC_setup(void);
+extern void bsp_end_local_APIC_setup(void);
 extern void init_apic_mappings(void);
 void register_lapic_address(unsigned long address);
 extern void setup_boot_APIC_clock(void);
diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h
index 6e6e7558e702..4564c8e28a33 100644
--- a/arch/x86/include/asm/cpu.h
+++ b/arch/x86/include/asm/cpu.h
@@ -32,6 +32,6 @@ extern void arch_unregister_cpu(int);
 
 DECLARE_PER_CPU(int, cpu_state);
 
-int __cpuinit mwait_usable(const struct cpuinfo_x86 *);
+int mwait_usable(const struct cpuinfo_x86 *);
 
 #endif /* _ASM_X86_CPU_H */
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index e2f6a99f14ab..cc29086e30cd 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -22,6 +22,7 @@
 
 #define ARCH_P4_CNTRVAL_BITS    (40)
 #define ARCH_P4_CNTRVAL_MASK    ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
+#define ARCH_P4_UNFLAGGED_BIT   ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
 
 #define P4_ESCR_EVENT_MASK      0x7e000000U
 #define P4_ESCR_EVENT_SHIFT     25
diff --git a/arch/x86/kernel/alternative.c b/arch/x86/kernel/alternative.c
index 123608531c8f..7038b95d363f 100644
--- a/arch/x86/kernel/alternative.c
+++ b/arch/x86/kernel/alternative.c
@@ -671,7 +671,7 @@ void __kprobes text_poke_smp_batch(struct text_poke_param *params, int n)
 
         atomic_set(&stop_machine_first, 1);
         wrote_text = 0;
-        stop_machine(stop_machine_text_poke, (void *)&tpp, NULL);
+        __stop_machine(stop_machine_text_poke, (void *)&tpp, NULL);
 }
 
 #if defined(CONFIG_DYNAMIC_FTRACE) || defined(HAVE_JUMP_LABEL)
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 06c196d7e59c..76b96d74978a 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1381,12 +1381,17 @@ void __cpuinit end_local_APIC_setup(void)
 #endif
 
         apic_pm_activate();
+}
+
+void __init bsp_end_local_APIC_setup(void)
+{
+        end_local_APIC_setup();
 
         /*
          * Now that local APIC setup is completed for BP, configure the fault
          * handling for interrupt remapping.
          */
-        if (!smp_processor_id() && intr_remapping_enabled)
+        if (intr_remapping_enabled)
                 enable_drhd_fault_handling();
 
 }
@@ -1756,7 +1761,7 @@ int __init APIC_init_uniprocessor(void)
                 enable_IO_APIC();
 #endif
 
-        end_local_APIC_setup();
+        bsp_end_local_APIC_setup();
 
 #ifdef CONFIG_X86_IO_APIC
         if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 697dc34b7b87..ca9e2a3545a9 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -4002,6 +4002,9 @@ int mp_find_ioapic(u32 gsi)
 {
         int i = 0;
 
+        if (nr_ioapics == 0)
+                return -1;
+
         /* Find the IOAPIC that manages this GSI. */
         for (i = 0; i < nr_ioapics; i++) {
                 if ((gsi >= mp_gsi_routing[i].gsi_base)
diff --git a/arch/x86/kernel/cpu/perf_event_p4.c b/arch/x86/kernel/cpu/perf_event_p4.c
index f7a0993c1e7c..ff751a9f182b 100644
--- a/arch/x86/kernel/cpu/perf_event_p4.c
+++ b/arch/x86/kernel/cpu/perf_event_p4.c
@@ -770,9 +770,14 @@ static inline int p4_pmu_clear_cccr_ovf(struct hw_perf_event *hwc)
                 return 1;
         }
 
-        /* it might be unflagged overflow */
-        rdmsrl(hwc->event_base + hwc->idx, v);
-        if (!(v & ARCH_P4_CNTRVAL_MASK))
+        /*
+         * In some circumstances the overflow might issue an NMI but did
+         * not set P4_CCCR_OVF bit. Because a counter holds a negative value
+         * we simply check for high bit being set, if it's cleared it means
+         * the counter has reached zero value and continued counting before
+         * real NMI signal was received:
+         */
+        if (!(v & ARCH_P4_UNFLAGGED_BIT))
                 return 1;
 
         return 0;
diff --git a/arch/x86/kernel/irq.c b/arch/x86/kernel/irq.c
index 52945da52a94..387b6a0c9e81 100644
--- a/arch/x86/kernel/irq.c
+++ b/arch/x86/kernel/irq.c
@@ -367,7 +367,8 @@ void fixup_irqs(void)
                 if (irr  & (1 << (vector % 32))) {
                         irq = __this_cpu_read(vector_irq[vector]);
 
-                        data = irq_get_irq_data(irq);
+                        desc = irq_to_desc(irq);
+                        data = &desc->irq_data;
                         raw_spin_lock(&desc->lock);
                         if (data->chip->irq_retrigger)
                                 data->chip->irq_retrigger(data);
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index e764fc05d700..ff4554198981 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -92,21 +92,31 @@ void show_regs(struct pt_regs *regs)
 
 void show_regs_common(void)
 {
-        const char *board, *product;
+        const char *vendor, *product, *board;
 
-        board = dmi_get_system_info(DMI_BOARD_NAME);
-        if (!board)
-                board = "";
+        vendor = dmi_get_system_info(DMI_SYS_VENDOR);
+        if (!vendor)
+                vendor = "";
         product = dmi_get_system_info(DMI_PRODUCT_NAME);
         if (!product)
                 product = "";
 
+        /* Board Name is optional */
+        board = dmi_get_system_info(DMI_BOARD_NAME);
+
         printk(KERN_CONT "\n");
-        printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s/%s\n",
+        printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s",
                 current->pid, current->comm, print_tainted(),
                 init_utsname()->release,
                 (int)strcspn(init_utsname()->version, " "),
-                init_utsname()->version, board, product);
+                init_utsname()->version);
+        printk(KERN_CONT " ");
+        printk(KERN_CONT "%s %s", vendor, product);
+        if (board) {
+                printk(KERN_CONT "/");
+                printk(KERN_CONT "%s", board);
+        }
+        printk(KERN_CONT "\n");
 }
 
 void flush_thread(void)
@@ -506,7 +516,7 @@ static void poll_idle(void)
 #define MWAIT_ECX_EXTENDED_INFO         0x01
 #define MWAIT_EDX_C1                    0xf0
 
-int __cpuinit mwait_usable(const struct cpuinfo_x86 *c)
+int mwait_usable(const struct cpuinfo_x86 *c)
 {
         u32 eax, ebx, ecx, edx;
 
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index 03273b6c272c..08776a953487 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -1060,7 +1060,7 @@ static int __init smp_sanity_check(unsigned max_cpus)
 
                 connect_bsp_APIC();
                 setup_local_APIC();
-                end_local_APIC_setup();
+                bsp_end_local_APIC_setup();
                 return -1;
         }
 
@@ -1137,7 +1137,7 @@ void __init native_smp_prepare_cpus(unsigned int max_cpus)
         if (!skip_ioapic_setup && nr_ioapics)
                 enable_IO_APIC();
 
-        end_local_APIC_setup();
+        bsp_end_local_APIC_setup();
 
         map_cpu_to_logical_apicid();
 
diff --git a/arch/x86/kvm/svm.c b/arch/x86/kvm/svm.c
index 25bd1bc5aad2..54ce246a383e 100644
--- a/arch/x86/kvm/svm.c
+++ b/arch/x86/kvm/svm.c
@@ -1150,8 +1150,8 @@ static void svm_vcpu_put(struct kvm_vcpu *vcpu)
         kvm_load_ldt(svm->host.ldt);
 #ifdef CONFIG_X86_64
         loadsegment(fs, svm->host.fs);
-        load_gs_index(svm->host.gs);
         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
+        load_gs_index(svm->host.gs);
 #else
         loadsegment(gs, svm->host.gs);
 #endif