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authorRobert Richter <robert.richter@amd.com>2008-07-22 15:08:56 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-26 05:48:05 -0400
commit7939d2bf7e30353d40d14f967b7fe2b2a7be5bd9 (patch)
treea2b4224019e6c9c6ea4f39aba2363c23c2d7b89d /arch/x86
parent56784f11df473b4c1d9d0e37777fd7c0b77b6bca (diff)
x86/oprofile: separating the IBS handler
Signed-off-by: Robert Richter <robert.richter@amd.com> Cc: oprofile-list <oprofile-list@lists.sourceforge.net> Cc: Barry Kasindorf <barry.kasindorf@amd.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/oprofile/op_model_athlon.c45
1 files changed, 28 insertions, 17 deletions
diff --git a/arch/x86/oprofile/op_model_athlon.c b/arch/x86/oprofile/op_model_athlon.c
index 229e0b4e21e3..a2c8e2e372bb 100644
--- a/arch/x86/oprofile/op_model_athlon.c
+++ b/arch/x86/oprofile/op_model_athlon.c
@@ -195,27 +195,18 @@ static void op_amd_setup_ctrs(struct op_msrs const * const msrs)
195 } 195 }
196} 196}
197 197
198 198static inline int
199static int op_amd_check_ctrs(struct pt_regs * const regs, 199op_amd_handle_ibs(struct pt_regs * const regs,
200 struct op_msrs const * const msrs) 200 struct op_msrs const * const msrs)
201{ 201{
202 unsigned int low, high; 202 unsigned int low, high;
203 int i;
204 struct ibs_fetch_sample ibs_fetch; 203 struct ibs_fetch_sample ibs_fetch;
205 struct ibs_op_sample ibs_op; 204 struct ibs_op_sample ibs_op;
206 205
207 for (i = 0 ; i < NUM_COUNTERS; ++i) { 206 if (!ibs_allowed)
208 if (!reset_value[i]) 207 return 1;
209 continue;
210 CTR_READ(low, high, msrs, i);
211 if (CTR_OVERFLOWED(low)) {
212 oprofile_add_sample(regs, i);
213 CTR_WRITE(reset_value[i], msrs, i);
214 }
215 }
216 208
217 /*If AMD and IBS is available */ 209 if (ibs_config.fetch_enabled) {
218 if (ibs_allowed && ibs_config.fetch_enabled) {
219 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high); 210 rdmsr(MSR_AMD64_IBSFETCHCTL, low, high);
220 if (high & IBS_FETCH_VALID_BIT) { 211 if (high & IBS_FETCH_VALID_BIT) {
221 ibs_fetch.ibs_fetch_ctl_high = high; 212 ibs_fetch.ibs_fetch_ctl_high = high;
@@ -240,7 +231,7 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
240 } 231 }
241 } 232 }
242 233
243 if (ibs_allowed && ibs_config.op_enabled) { 234 if (ibs_config.op_enabled) {
244 rdmsr(MSR_AMD64_IBSOPCTL, low, high); 235 rdmsr(MSR_AMD64_IBSOPCTL, low, high);
245 if (low & IBS_OP_VALID_BIT) { 236 if (low & IBS_OP_VALID_BIT) {
246 rdmsr(MSR_AMD64_IBSOPRIP, low, high); 237 rdmsr(MSR_AMD64_IBSOPRIP, low, high);
@@ -273,10 +264,30 @@ static int op_amd_check_ctrs(struct pt_regs * const regs,
273 } 264 }
274 } 265 }
275 266
276 /* See op_model_ppro.c */
277 return 1; 267 return 1;
278} 268}
279 269
270static int op_amd_check_ctrs(struct pt_regs * const regs,
271 struct op_msrs const * const msrs)
272{
273 unsigned int low, high;
274 int i;
275
276 for (i = 0 ; i < NUM_COUNTERS; ++i) {
277 if (!reset_value[i])
278 continue;
279 CTR_READ(low, high, msrs, i);
280 if (CTR_OVERFLOWED(low)) {
281 oprofile_add_sample(regs, i);
282 CTR_WRITE(reset_value[i], msrs, i);
283 }
284 }
285
286 op_amd_handle_ibs(regs, msrs);
287
288 /* See op_model_ppro.c */
289 return 1;
290}
280 291
281static void op_amd_start(struct op_msrs const * const msrs) 292static void op_amd_start(struct op_msrs const * const msrs)
282{ 293{