diff options
| author | Suresh Siddha <suresh.b.siddha@intel.com> | 2011-08-25 15:01:12 -0400 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2011-09-21 04:26:26 -0400 |
| commit | e57253a81d9cc7049e9e43bd806ce6cdd297ec1c (patch) | |
| tree | 979900bd7e7fe8fd60e28fcd79b2652bd92fa84a /arch/x86 | |
| parent | 1e75b31d638d5242ca8e9771dfdcbd28a5f041df (diff) | |
x86, ioapic: Restore the mask bit correctly in eoi_ioapic_irq()
For older IO-APIC's, we were clearing the remote-IRR by changing
the RTE trigger mode to edge and then back to level. We wanted
to mask the RTE during this process, so we were essentially
doing mask+edge and then to unmask+level.
As part of the commit ca64c47cecd0321b2e0dcbd7aaff44b68ce20654,
we moved this EOI process earlier where the IO-APIC RTE is
masked. So we were wrongly unmasking it in the eoi_ioapic_irq().
So change the remote-IRR clear sequence in eoi_ioapic_irq() to
mask + edge and then restore the previous RTE entry which will
restore the mask status as well as the level trigger.
Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: Maciej W. Rozycki <macro@linux-mips.org>
Cc: Thomas Renninger <trenn@suse.de>
Cc: Rafael Wysocki <rjw@novell.com>
Cc: lchiquitto@novell.com
Cc: jbeulich@novell.com
Cc: yinghai@kernel.org
Link: http://lkml.kernel.org/r/20110825190657.210286410@sbsiddha-desk.sc.intel.com
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
| -rw-r--r-- | arch/x86/kernel/apic/io_apic.c | 43 |
1 files changed, 27 insertions, 16 deletions
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c index 913d4bd2913a..85050c9ab755 100644 --- a/arch/x86/kernel/apic/io_apic.c +++ b/arch/x86/kernel/apic/io_apic.c | |||
| @@ -394,13 +394,21 @@ union entry_union { | |||
| 394 | struct IO_APIC_route_entry entry; | 394 | struct IO_APIC_route_entry entry; |
| 395 | }; | 395 | }; |
| 396 | 396 | ||
| 397 | static struct IO_APIC_route_entry __ioapic_read_entry(int apic, int pin) | ||
| 398 | { | ||
| 399 | union entry_union eu; | ||
| 400 | |||
| 401 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | ||
| 402 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | ||
| 403 | return eu.entry; | ||
| 404 | } | ||
| 405 | |||
| 397 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) | 406 | static struct IO_APIC_route_entry ioapic_read_entry(int apic, int pin) |
| 398 | { | 407 | { |
| 399 | union entry_union eu; | 408 | union entry_union eu; |
| 400 | unsigned long flags; | 409 | unsigned long flags; |
| 401 | raw_spin_lock_irqsave(&ioapic_lock, flags); | 410 | raw_spin_lock_irqsave(&ioapic_lock, flags); |
| 402 | eu.w1 = io_apic_read(apic, 0x10 + 2 * pin); | 411 | eu.entry = __ioapic_read_entry(apic, pin); |
| 403 | eu.w2 = io_apic_read(apic, 0x11 + 2 * pin); | ||
| 404 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | 412 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |
| 405 | return eu.entry; | 413 | return eu.entry; |
| 406 | } | 414 | } |
| @@ -529,18 +537,6 @@ static void io_apic_modify_irq(struct irq_cfg *cfg, | |||
| 529 | __io_apic_modify_irq(entry, mask_and, mask_or, final); | 537 | __io_apic_modify_irq(entry, mask_and, mask_or, final); |
| 530 | } | 538 | } |
| 531 | 539 | ||
| 532 | static void __mask_and_edge_IO_APIC_irq(struct irq_pin_list *entry) | ||
| 533 | { | ||
| 534 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_LEVEL_TRIGGER, | ||
| 535 | IO_APIC_REDIR_MASKED, NULL); | ||
| 536 | } | ||
| 537 | |||
| 538 | static void __unmask_and_level_IO_APIC_irq(struct irq_pin_list *entry) | ||
| 539 | { | ||
| 540 | __io_apic_modify_irq(entry, ~IO_APIC_REDIR_MASKED, | ||
| 541 | IO_APIC_REDIR_LEVEL_TRIGGER, NULL); | ||
| 542 | } | ||
| 543 | |||
| 544 | static void io_apic_sync(struct irq_pin_list *entry) | 540 | static void io_apic_sync(struct irq_pin_list *entry) |
| 545 | { | 541 | { |
| 546 | /* | 542 | /* |
| @@ -2496,8 +2492,23 @@ static void eoi_ioapic_irq(unsigned int irq, struct irq_cfg *cfg) | |||
| 2496 | else | 2492 | else |
| 2497 | io_apic_eoi(entry->apic, cfg->vector); | 2493 | io_apic_eoi(entry->apic, cfg->vector); |
| 2498 | } else { | 2494 | } else { |
| 2499 | __mask_and_edge_IO_APIC_irq(entry); | 2495 | struct IO_APIC_route_entry rte, rte1; |
| 2500 | __unmask_and_level_IO_APIC_irq(entry); | 2496 | |
| 2497 | rte = rte1 = | ||
| 2498 | __ioapic_read_entry(entry->apic, entry->pin); | ||
| 2499 | |||
| 2500 | /* | ||
| 2501 | * Mask the entry and change the trigger mode to edge. | ||
| 2502 | */ | ||
| 2503 | rte1.mask = 1; | ||
| 2504 | rte1.trigger = IOAPIC_EDGE; | ||
| 2505 | |||
| 2506 | __ioapic_write_entry(apic, pin, rte1); | ||
| 2507 | |||
| 2508 | /* | ||
| 2509 | * Restore the previous level triggered entry. | ||
| 2510 | */ | ||
| 2511 | __ioapic_write_entry(apic, pin, rte); | ||
| 2501 | } | 2512 | } |
| 2502 | } | 2513 | } |
| 2503 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); | 2514 | raw_spin_unlock_irqrestore(&ioapic_lock, flags); |