x86: use cpuinfo to check for interrupt pending message msr

Simplify code: no need to do a cpuid(1) again. The cpuinfo structure
has all necessary information already.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@elte.hu>

2 files changed, 30 insertions, 49 deletions

diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 30b5055be355..e76b49e7a916 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -25,35 +25,24 @@ extern void vide(void);
 __asm__(".align 4\nvide: ret");
 
 #ifdef CONFIG_X86_LOCAL_APIC
-#define CPUID_PROCESSOR_SIGNATURE       1
-#define CPUID_XFAM              0x0ff00000
-#define CPUID_XFAM_K8           0x00000000
-#define CPUID_XFAM_10H          0x00100000
-#define CPUID_XFAM_11H          0x00200000
-#define CPUID_XMOD              0x000f0000
-#define CPUID_XMOD_REV_F        0x00040000
 
 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
-static __cpuinit int amd_apic_timer_broken(void)
+static __cpuinit int amd_apic_timer_broken(struct cpuinfo_x86 *c)
 {
         u32 lo, hi;
-        u32 eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
-        switch (eax & CPUID_XFAM) {
-        case CPUID_XFAM_K8:
-                if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
-                        break;
-        case CPUID_XFAM_10H:
-        case CPUID_XFAM_11H:
-                rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
-                if (lo & K8_INTP_C1E_ACTIVE_MASK) {
-                        if (smp_processor_id() != boot_cpu_physical_apicid)
-                                printk(KERN_INFO "AMD C1E detected late. "
-                                       "        Force timer broadcast.\n");
-                        return 1;
-                }
-                break;
-        default:
-                /* err on the side of caution */
+
+        if (c->x86 < 0x0F)
+                return 0;
+
+        /* Family 0x0f models < rev F do not have this MSR */
+        if (c->x86 == 0x0f && c->x86_model < 0x40)
+                return 0;
+
+        rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
+        if (lo & K8_INTP_C1E_ACTIVE_MASK) {
+                if (smp_processor_id() != boot_cpu_physical_apicid)
+                        printk(KERN_INFO "AMD C1E detected late. "
+                               "Force timer broadcast.\n");
                 return 1;
         }
         return 0;
@@ -297,7 +286,7 @@ static void __cpuinit init_amd(struct cpuinfo_x86 *c)
         }
 
 #ifdef CONFIG_X86_LOCAL_APIC
-        if (amd_apic_timer_broken())
+        if (amd_apic_timer_broken(c))
                 local_apic_timer_disabled = 1;
 #endif
 
diff --git a/arch/x86/kernel/cpu/amd_64.c b/arch/x86/kernel/cpu/amd_64.c
index 6eef3c79d151..f5fc161d8f2a 100644
--- a/arch/x86/kernel/cpu/amd_64.c
+++ b/arch/x86/kernel/cpu/amd_64.c
@@ -110,31 +110,23 @@ static void __cpuinit early_init_amd_mc(struct cpuinfo_x86 *c)
 #endif
 }
 
-#define CPUID_PROCESSOR_SIGNATURE       1
-#define CPUID_XFAM              0x0ff00000
-#define CPUID_XFAM_K8           0x00000000
-#define CPUID_XFAM_10H          0x00100000
-#define CPUID_XFAM_11H          0x00200000
-#define CPUID_XMOD              0x000f0000
-#define CPUID_XMOD_REV_F        0x00040000
-
 /* AMD systems with C1E don't have a working lAPIC timer. Check for that. */
-static __cpuinit int amd_apic_timer_broken(void)
+static __cpuinit int amd_apic_timer_broken(struct cpuinfo_x86 *c)
 {
-        u32 lo, hi, eax = cpuid_eax(CPUID_PROCESSOR_SIGNATURE);
+        u32 lo, hi;
 
-        switch (eax & CPUID_XFAM) {
-        case CPUID_XFAM_K8:
-                if ((eax & CPUID_XMOD) < CPUID_XMOD_REV_F)
-                        break;
-        case CPUID_XFAM_10H:
-        case CPUID_XFAM_11H:
-                rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
-                if (lo & K8_INTP_C1E_ACTIVE_MASK)
-                        return 1;
-                break;
-        default:
-                /* err on the side of caution */
+        if (c->x86 < 0x0F)
+                return 0;
+
+        /* Family 0x0f models < rev F do not have this MSR */
+        if (c->x86 == 0x0f && c->x86_model < 0x40)
+                return 0;
+
+        rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
+        if (lo & K8_INTP_C1E_ACTIVE_MASK) {
+                if (smp_processor_id() != boot_cpu_physical_apicid)
+                        printk(KERN_INFO "AMD C1E detected late. "
+                               "Force timer broadcast.\n");
                 return 1;
         }
         return 0;
@@ -220,7 +212,7 @@ void __cpuinit init_amd(struct cpuinfo_x86 *c)
         if (c->x86 == 0x10)
                 amd_enable_pci_ext_cfg(c);
 
-        if (amd_apic_timer_broken())
+        if (amd_apic_timer_broken(c))
                 disable_apic_timer = 1;
 
         if (c == &boot_cpu_data && c->x86 >= 0xf && c->x86 <= 0x11) {