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authorThomas Gleixner <tglx@linutronix.de>2011-05-14 06:06:36 -0400
committerThomas Gleixner <tglx@linutronix.de>2011-05-14 06:06:36 -0400
commita18f22a968de17b29f2310cdb7ba69163e65ec15 (patch)
treea7d56d88fad5e444d7661484109758a2f436129e /arch/x86/platform
parenta1c57e0fec53defe745e64417eacdbd3618c3e66 (diff)
parent798778b8653f64b7b2162ac70eca10367cff6ce8 (diff)
Merge branch 'consolidate-clksrc-i8253' of master.kernel.org:~rmk/linux-2.6-arm into timers/clocksource
Conflicts: arch/ia64/kernel/cyclone.c arch/mips/kernel/i8253.c arch/x86/kernel/i8253.c Reason: Resolve conflicts so further cleanups do not conflict further Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/platform')
-rw-r--r--arch/x86/platform/ce4100/ce4100.c26
-rw-r--r--arch/x86/platform/ce4100/falconfalls.dts430
-rw-r--r--arch/x86/platform/mrst/mrst.c12
-rw-r--r--arch/x86/platform/mrst/vrtc.c18
-rw-r--r--arch/x86/platform/olpc/Makefile4
-rw-r--r--arch/x86/platform/olpc/olpc-xo1.c25
-rw-r--r--arch/x86/platform/olpc/olpc_dt.c3
-rw-r--r--arch/x86/platform/uv/tlb_uv.c5
-rw-r--r--arch/x86/platform/uv/uv_irq.c4
-rw-r--r--arch/x86/platform/visws/visws_quirks.c24
10 files changed, 491 insertions, 60 deletions
diff --git a/arch/x86/platform/ce4100/ce4100.c b/arch/x86/platform/ce4100/ce4100.c
index d2c0d51a7178..28071bb31db7 100644
--- a/arch/x86/platform/ce4100/ce4100.c
+++ b/arch/x86/platform/ce4100/ce4100.c
@@ -15,21 +15,20 @@
15#include <linux/serial_reg.h> 15#include <linux/serial_reg.h>
16#include <linux/serial_8250.h> 16#include <linux/serial_8250.h>
17 17
18#include <asm/ce4100.h>
19#include <asm/prom.h>
18#include <asm/setup.h> 20#include <asm/setup.h>
21#include <asm/i8259.h>
19#include <asm/io.h> 22#include <asm/io.h>
23#include <asm/io_apic.h>
20 24
21static int ce4100_i8042_detect(void) 25static int ce4100_i8042_detect(void)
22{ 26{
23 return 0; 27 return 0;
24} 28}
25 29
26static void __init sdv_find_smp_config(void)
27{
28}
29
30#ifdef CONFIG_SERIAL_8250 30#ifdef CONFIG_SERIAL_8250
31 31
32
33static unsigned int mem_serial_in(struct uart_port *p, int offset) 32static unsigned int mem_serial_in(struct uart_port *p, int offset)
34{ 33{
35 offset = offset << p->regshift; 34 offset = offset << p->regshift;
@@ -118,6 +117,15 @@ static void __init sdv_arch_setup(void)
118 sdv_serial_fixup(); 117 sdv_serial_fixup();
119} 118}
120 119
120#ifdef CONFIG_X86_IO_APIC
121static void __cpuinit sdv_pci_init(void)
122{
123 x86_of_pci_init();
124 /* We can't set this earlier, because we need to calibrate the timer */
125 legacy_pic = &null_legacy_pic;
126}
127#endif
128
121/* 129/*
122 * CE4100 specific x86_init function overrides and early setup 130 * CE4100 specific x86_init function overrides and early setup
123 * calls. 131 * calls.
@@ -128,5 +136,11 @@ void __init x86_ce4100_early_setup(void)
128 x86_platform.i8042_detect = ce4100_i8042_detect; 136 x86_platform.i8042_detect = ce4100_i8042_detect;
129 x86_init.resources.probe_roms = x86_init_noop; 137 x86_init.resources.probe_roms = x86_init_noop;
130 x86_init.mpparse.get_smp_config = x86_init_uint_noop; 138 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
131 x86_init.mpparse.find_smp_config = sdv_find_smp_config; 139 x86_init.mpparse.find_smp_config = x86_init_noop;
140 x86_init.pci.init = ce4100_pci_init;
141
142#ifdef CONFIG_X86_IO_APIC
143 x86_init.pci.init_irq = sdv_pci_init;
144 x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc_nocheck;
145#endif
132} 146}
diff --git a/arch/x86/platform/ce4100/falconfalls.dts b/arch/x86/platform/ce4100/falconfalls.dts
new file mode 100644
index 000000000000..e70be38ce039
--- /dev/null
+++ b/arch/x86/platform/ce4100/falconfalls.dts
@@ -0,0 +1,430 @@
1/*
2 * CE4100 on Falcon Falls
3 *
4 * (c) Copyright 2010 Intel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License.
9 */
10/dts-v1/;
11/ {
12 model = "intel,falconfalls";
13 compatible = "intel,falconfalls";
14 #address-cells = <1>;
15 #size-cells = <1>;
16
17 cpus {
18 #address-cells = <1>;
19 #size-cells = <0>;
20
21 cpu@0 {
22 device_type = "cpu";
23 compatible = "intel,ce4100";
24 reg = <0>;
25 lapic = <&lapic0>;
26 };
27 };
28
29 soc@0 {
30 #address-cells = <1>;
31 #size-cells = <1>;
32 compatible = "intel,ce4100-cp";
33 ranges;
34
35 ioapic1: interrupt-controller@fec00000 {
36 #interrupt-cells = <2>;
37 compatible = "intel,ce4100-ioapic";
38 interrupt-controller;
39 reg = <0xfec00000 0x1000>;
40 };
41
42 timer@fed00000 {
43 compatible = "intel,ce4100-hpet";
44 reg = <0xfed00000 0x200>;
45 };
46
47 lapic0: interrupt-controller@fee00000 {
48 compatible = "intel,ce4100-lapic";
49 reg = <0xfee00000 0x1000>;
50 };
51
52 pci@3fc {
53 #address-cells = <3>;
54 #size-cells = <2>;
55 compatible = "intel,ce4100-pci", "pci";
56 device_type = "pci";
57 bus-range = <0 0>;
58 ranges = <0x2000000 0 0xbffff000 0xbffff000 0 0x1000
59 0x2000000 0 0xdffe0000 0xdffe0000 0 0x1000
60 0x0000000 0 0x0 0x0 0 0x100>;
61
62 /* Secondary IO-APIC */
63 ioapic2: interrupt-controller@0,1 {
64 #interrupt-cells = <2>;
65 compatible = "intel,ce4100-ioapic";
66 interrupt-controller;
67 reg = <0x100 0x0 0x0 0x0 0x0>;
68 assigned-addresses = <0x02000000 0x0 0xbffff000 0x0 0x1000>;
69 };
70
71 pci@1,0 {
72 #address-cells = <3>;
73 #size-cells = <2>;
74 compatible = "intel,ce4100-pci", "pci";
75 device_type = "pci";
76 bus-range = <1 1>;
77 reg = <0x0800 0x0 0x0 0x0 0x0>;
78 ranges = <0x2000000 0 0xdffe0000 0x2000000 0 0xdffe0000 0 0x1000>;
79
80 interrupt-parent = <&ioapic2>;
81
82 display@2,0 {
83 compatible = "pci8086,2e5b.2",
84 "pci8086,2e5b",
85 "pciclass038000",
86 "pciclass0380";
87
88 reg = <0x11000 0x0 0x0 0x0 0x0>;
89 interrupts = <0 1>;
90 };
91
92 multimedia@3,0 {
93 compatible = "pci8086,2e5c.2",
94 "pci8086,2e5c",
95 "pciclass048000",
96 "pciclass0480";
97
98 reg = <0x11800 0x0 0x0 0x0 0x0>;
99 interrupts = <2 1>;
100 };
101
102 multimedia@4,0 {
103 compatible = "pci8086,2e5d.2",
104 "pci8086,2e5d",
105 "pciclass048000",
106 "pciclass0480";
107
108 reg = <0x12000 0x0 0x0 0x0 0x0>;
109 interrupts = <4 1>;
110 };
111
112 multimedia@4,1 {
113 compatible = "pci8086,2e5e.2",
114 "pci8086,2e5e",
115 "pciclass048000",
116 "pciclass0480";
117
118 reg = <0x12100 0x0 0x0 0x0 0x0>;
119 interrupts = <5 1>;
120 };
121
122 sound@6,0 {
123 compatible = "pci8086,2e5f.2",
124 "pci8086,2e5f",
125 "pciclass040100",
126 "pciclass0401";
127
128 reg = <0x13000 0x0 0x0 0x0 0x0>;
129 interrupts = <6 1>;
130 };
131
132 sound@6,1 {
133 compatible = "pci8086,2e5f.2",
134 "pci8086,2e5f",
135 "pciclass040100",
136 "pciclass0401";
137
138 reg = <0x13100 0x0 0x0 0x0 0x0>;
139 interrupts = <7 1>;
140 };
141
142 sound@6,2 {
143 compatible = "pci8086,2e60.2",
144 "pci8086,2e60",
145 "pciclass040100",
146 "pciclass0401";
147
148 reg = <0x13200 0x0 0x0 0x0 0x0>;
149 interrupts = <8 1>;
150 };
151
152 display@8,0 {
153 compatible = "pci8086,2e61.2",
154 "pci8086,2e61",
155 "pciclass038000",
156 "pciclass0380";
157
158 reg = <0x14000 0x0 0x0 0x0 0x0>;
159 interrupts = <9 1>;
160 };
161
162 display@8,1 {
163 compatible = "pci8086,2e62.2",
164 "pci8086,2e62",
165 "pciclass038000",
166 "pciclass0380";
167
168 reg = <0x14100 0x0 0x0 0x0 0x0>;
169 interrupts = <10 1>;
170 };
171
172 multimedia@8,2 {
173 compatible = "pci8086,2e63.2",
174 "pci8086,2e63",
175 "pciclass048000",
176 "pciclass0480";
177
178 reg = <0x14200 0x0 0x0 0x0 0x0>;
179 interrupts = <11 1>;
180 };
181
182 entertainment-encryption@9,0 {
183 compatible = "pci8086,2e64.2",
184 "pci8086,2e64",
185 "pciclass101000",
186 "pciclass1010";
187
188 reg = <0x14800 0x0 0x0 0x0 0x0>;
189 interrupts = <12 1>;
190 };
191
192 localbus@a,0 {
193 compatible = "pci8086,2e65.2",
194 "pci8086,2e65",
195 "pciclassff0000",
196 "pciclassff00";
197
198 reg = <0x15000 0x0 0x0 0x0 0x0>;
199 };
200
201 serial@b,0 {
202 compatible = "pci8086,2e66.2",
203 "pci8086,2e66",
204 "pciclass070003",
205 "pciclass0700";
206
207 reg = <0x15800 0x0 0x0 0x0 0x0>;
208 interrupts = <14 1>;
209 };
210
211 gpio@b,1 {
212 compatible = "pci8086,2e67.2",
213 "pci8086,2e67",
214 "pciclassff0000",
215 "pciclassff00";
216
217 #gpio-cells = <2>;
218 reg = <0x15900 0x0 0x0 0x0 0x0>;
219 interrupts = <15 1>;
220 gpio-controller;
221 };
222
223 i2c-controller@b,2 {
224 #address-cells = <2>;
225 #size-cells = <1>;
226 compatible = "pci8086,2e68.2",
227 "pci8086,2e68",
228 "pciclass,ff0000",
229 "pciclass,ff00";
230
231 reg = <0x15a00 0x0 0x0 0x0 0x0>;
232 interrupts = <16 1>;
233 ranges = <0 0 0x02000000 0 0xdffe0500 0x100
234 1 0 0x02000000 0 0xdffe0600 0x100
235 2 0 0x02000000 0 0xdffe0700 0x100>;
236
237 i2c@0 {
238 #address-cells = <1>;
239 #size-cells = <0>;
240 compatible = "intel,ce4100-i2c-controller";
241 reg = <0 0 0x100>;
242 };
243
244 i2c@1 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "intel,ce4100-i2c-controller";
248 reg = <1 0 0x100>;
249
250 gpio@26 {
251 #gpio-cells = <2>;
252 compatible = "ti,pcf8575";
253 reg = <0x26>;
254 gpio-controller;
255 };
256 };
257
258 i2c@2 {
259 #address-cells = <1>;
260 #size-cells = <0>;
261 compatible = "intel,ce4100-i2c-controller";
262 reg = <2 0 0x100>;
263
264 gpio@26 {
265 #gpio-cells = <2>;
266 compatible = "ti,pcf8575";
267 reg = <0x26>;
268 gpio-controller;
269 };
270 };
271 };
272
273 smard-card@b,3 {
274 compatible = "pci8086,2e69.2",
275 "pci8086,2e69",
276 "pciclass070500",
277 "pciclass0705";
278
279 reg = <0x15b00 0x0 0x0 0x0 0x0>;
280 interrupts = <15 1>;
281 };
282
283 spi-controller@b,4 {
284 #address-cells = <1>;
285 #size-cells = <0>;
286 compatible =
287 "pci8086,2e6a.2",
288 "pci8086,2e6a",
289 "pciclass,ff0000",
290 "pciclass,ff00";
291
292 reg = <0x15c00 0x0 0x0 0x0 0x0>;
293 interrupts = <15 1>;
294
295 dac@0 {
296 compatible = "ti,pcm1755";
297 reg = <0>;
298 spi-max-frequency = <115200>;
299 };
300
301 dac@1 {
302 compatible = "ti,pcm1609a";
303 reg = <1>;
304 spi-max-frequency = <115200>;
305 };
306
307 eeprom@2 {
308 compatible = "atmel,at93c46";
309 reg = <2>;
310 spi-max-frequency = <115200>;
311 };
312 };
313
314 multimedia@b,7 {
315 compatible = "pci8086,2e6d.2",
316 "pci8086,2e6d",
317 "pciclassff0000",
318 "pciclassff00";
319
320 reg = <0x15f00 0x0 0x0 0x0 0x0>;
321 };
322
323 ethernet@c,0 {
324 compatible = "pci8086,2e6e.2",
325 "pci8086,2e6e",
326 "pciclass020000",
327 "pciclass0200";
328
329 reg = <0x16000 0x0 0x0 0x0 0x0>;
330 interrupts = <21 1>;
331 };
332
333 clock@c,1 {
334 compatible = "pci8086,2e6f.2",
335 "pci8086,2e6f",
336 "pciclassff0000",
337 "pciclassff00";
338
339 reg = <0x16100 0x0 0x0 0x0 0x0>;
340 interrupts = <3 1>;
341 };
342
343 usb@d,0 {
344 compatible = "pci8086,2e70.2",
345 "pci8086,2e70",
346 "pciclass0c0320",
347 "pciclass0c03";
348
349 reg = <0x16800 0x0 0x0 0x0 0x0>;
350 interrupts = <22 1>;
351 };
352
353 usb@d,1 {
354 compatible = "pci8086,2e70.2",
355 "pci8086,2e70",
356 "pciclass0c0320",
357 "pciclass0c03";
358
359 reg = <0x16900 0x0 0x0 0x0 0x0>;
360 interrupts = <22 1>;
361 };
362
363 sata@e,0 {
364 compatible = "pci8086,2e71.0",
365 "pci8086,2e71",
366 "pciclass010601",
367 "pciclass0106";
368
369 reg = <0x17000 0x0 0x0 0x0 0x0>;
370 interrupts = <23 1>;
371 };
372
373 flash@f,0 {
374 compatible = "pci8086,701.1",
375 "pci8086,701",
376 "pciclass050100",
377 "pciclass0501";
378
379 reg = <0x17800 0x0 0x0 0x0 0x0>;
380 interrupts = <13 1>;
381 };
382
383 entertainment-encryption@10,0 {
384 compatible = "pci8086,702.1",
385 "pci8086,702",
386 "pciclass101000",
387 "pciclass1010";
388
389 reg = <0x18000 0x0 0x0 0x0 0x0>;
390 };
391
392 co-processor@11,0 {
393 compatible = "pci8086,703.1",
394 "pci8086,703",
395 "pciclass0b4000",
396 "pciclass0b40";
397
398 reg = <0x18800 0x0 0x0 0x0 0x0>;
399 interrupts = <1 1>;
400 };
401
402 multimedia@12,0 {
403 compatible = "pci8086,704.0",
404 "pci8086,704",
405 "pciclass048000",
406 "pciclass0480";
407
408 reg = <0x19000 0x0 0x0 0x0 0x0>;
409 };
410 };
411
412 isa@1f,0 {
413 #address-cells = <2>;
414 #size-cells = <1>;
415 compatible = "isa";
416 reg = <0xf800 0x0 0x0 0x0 0x0>;
417 ranges = <1 0 0 0 0 0x100>;
418
419 rtc@70 {
420 compatible = "intel,ce4100-rtc", "motorola,mc146818";
421 interrupts = <8 3>;
422 interrupt-parent = <&ioapic1>;
423 ctrl-reg = <2>;
424 freq-reg = <0x26>;
425 reg = <1 0x70 2>;
426 };
427 };
428 };
429 };
430};
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c
index ea6529e93c6f..275dbc19e2cf 100644
--- a/arch/x86/platform/mrst/mrst.c
+++ b/arch/x86/platform/mrst/mrst.c
@@ -31,6 +31,7 @@
31#include <asm/apic.h> 31#include <asm/apic.h>
32#include <asm/io_apic.h> 32#include <asm/io_apic.h>
33#include <asm/mrst.h> 33#include <asm/mrst.h>
34#include <asm/mrst-vrtc.h>
34#include <asm/io.h> 35#include <asm/io.h>
35#include <asm/i8259.h> 36#include <asm/i8259.h>
36#include <asm/intel_scu_ipc.h> 37#include <asm/intel_scu_ipc.h>
@@ -96,11 +97,11 @@ static int __init sfi_parse_mtmr(struct sfi_table_header *table)
96 pentry->freq_hz, pentry->irq); 97 pentry->freq_hz, pentry->irq);
97 if (!pentry->irq) 98 if (!pentry->irq)
98 continue; 99 continue;
99 mp_irq.type = MP_IOAPIC; 100 mp_irq.type = MP_INTSRC;
100 mp_irq.irqtype = mp_INT; 101 mp_irq.irqtype = mp_INT;
101/* triggering mode edge bit 2-3, active high polarity bit 0-1 */ 102/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
102 mp_irq.irqflag = 5; 103 mp_irq.irqflag = 5;
103 mp_irq.srcbus = 0; 104 mp_irq.srcbus = MP_BUS_ISA;
104 mp_irq.srcbusirq = pentry->irq; /* IRQ */ 105 mp_irq.srcbusirq = pentry->irq; /* IRQ */
105 mp_irq.dstapic = MP_APIC_ALL; 106 mp_irq.dstapic = MP_APIC_ALL;
106 mp_irq.dstirq = pentry->irq; 107 mp_irq.dstirq = pentry->irq;
@@ -167,10 +168,10 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table)
167 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) { 168 for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
168 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n", 169 pr_debug("RTC[%d]: paddr = 0x%08x, irq = %d\n",
169 totallen, (u32)pentry->phys_addr, pentry->irq); 170 totallen, (u32)pentry->phys_addr, pentry->irq);
170 mp_irq.type = MP_IOAPIC; 171 mp_irq.type = MP_INTSRC;
171 mp_irq.irqtype = mp_INT; 172 mp_irq.irqtype = mp_INT;
172 mp_irq.irqflag = 0xf; /* level trigger and active low */ 173 mp_irq.irqflag = 0xf; /* level trigger and active low */
173 mp_irq.srcbus = 0; 174 mp_irq.srcbus = MP_BUS_ISA;
174 mp_irq.srcbusirq = pentry->irq; /* IRQ */ 175 mp_irq.srcbusirq = pentry->irq; /* IRQ */
175 mp_irq.dstapic = MP_APIC_ALL; 176 mp_irq.dstapic = MP_APIC_ALL;
176 mp_irq.dstirq = pentry->irq; 177 mp_irq.dstirq = pentry->irq;
@@ -268,6 +269,7 @@ void __init x86_mrst_early_setup(void)
268 269
269 x86_platform.calibrate_tsc = mrst_calibrate_tsc; 270 x86_platform.calibrate_tsc = mrst_calibrate_tsc;
270 x86_platform.i8042_detect = mrst_i8042_detect; 271 x86_platform.i8042_detect = mrst_i8042_detect;
272 x86_init.timers.wallclock_init = mrst_rtc_init;
271 x86_init.pci.init = pci_mrst_init; 273 x86_init.pci.init = pci_mrst_init;
272 x86_init.pci.fixup_irqs = x86_init_noop; 274 x86_init.pci.fixup_irqs = x86_init_noop;
273 275
@@ -280,7 +282,7 @@ void __init x86_mrst_early_setup(void)
280 /* Avoid searching for BIOS MP tables */ 282 /* Avoid searching for BIOS MP tables */
281 x86_init.mpparse.find_smp_config = x86_init_noop; 283 x86_init.mpparse.find_smp_config = x86_init_noop;
282 x86_init.mpparse.get_smp_config = x86_init_uint_noop; 284 x86_init.mpparse.get_smp_config = x86_init_uint_noop;
283 285 set_bit(MP_BUS_ISA, mp_bus_not_pci);
284} 286}
285 287
286/* 288/*
diff --git a/arch/x86/platform/mrst/vrtc.c b/arch/x86/platform/mrst/vrtc.c
index 32cd7edd71a0..73d70d65e76e 100644
--- a/arch/x86/platform/mrst/vrtc.c
+++ b/arch/x86/platform/mrst/vrtc.c
@@ -100,22 +100,16 @@ int vrtc_set_mmss(unsigned long nowtime)
100 100
101void __init mrst_rtc_init(void) 101void __init mrst_rtc_init(void)
102{ 102{
103 unsigned long rtc_paddr; 103 unsigned long vrtc_paddr;
104 void __iomem *virt_base;
105 104
106 sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc); 105 sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
107 if (!sfi_mrtc_num)
108 return;
109
110 rtc_paddr = sfi_mrtc_array[0].phys_addr;
111 106
112 /* vRTC's register address may not be page aligned */ 107 vrtc_paddr = sfi_mrtc_array[0].phys_addr;
113 set_fixmap_nocache(FIX_LNW_VRTC, rtc_paddr); 108 if (!sfi_mrtc_num || !vrtc_paddr)
114 109 return;
115 virt_base = (void __iomem *)__fix_to_virt(FIX_LNW_VRTC);
116 virt_base += rtc_paddr & ~PAGE_MASK;
117 vrtc_virt_base = virt_base;
118 110
111 vrtc_virt_base = (void __iomem *)set_fixmap_offset_nocache(FIX_LNW_VRTC,
112 vrtc_paddr);
119 x86_platform.get_wallclock = vrtc_get_time; 113 x86_platform.get_wallclock = vrtc_get_time;
120 x86_platform.set_wallclock = vrtc_set_mmss; 114 x86_platform.set_wallclock = vrtc_set_mmss;
121} 115}
diff --git a/arch/x86/platform/olpc/Makefile b/arch/x86/platform/olpc/Makefile
index e797428b163b..c2a8cab65e5d 100644
--- a/arch/x86/platform/olpc/Makefile
+++ b/arch/x86/platform/olpc/Makefile
@@ -1,4 +1,4 @@
1obj-$(CONFIG_OLPC) += olpc.o 1obj-$(CONFIG_OLPC) += olpc.o
2obj-$(CONFIG_OLPC_XO1) += olpc-xo1.o 2obj-$(CONFIG_OLPC_XO1) += olpc-xo1.o
3obj-$(CONFIG_OLPC_OPENFIRMWARE) += olpc_ofw.o 3obj-$(CONFIG_OLPC) += olpc_ofw.o
4obj-$(CONFIG_OLPC_OPENFIRMWARE_DT) += olpc_dt.o 4obj-$(CONFIG_OF_PROMTREE) += olpc_dt.o
diff --git a/arch/x86/platform/olpc/olpc-xo1.c b/arch/x86/platform/olpc/olpc-xo1.c
index 127775696d6c..ab81fb271760 100644
--- a/arch/x86/platform/olpc/olpc-xo1.c
+++ b/arch/x86/platform/olpc/olpc-xo1.c
@@ -15,6 +15,7 @@
15#include <linux/module.h> 15#include <linux/module.h>
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/pm.h> 17#include <linux/pm.h>
18#include <linux/mfd/core.h>
18 19
19#include <asm/io.h> 20#include <asm/io.h>
20#include <asm/olpc.h> 21#include <asm/olpc.h>
@@ -56,25 +57,24 @@ static void xo1_power_off(void)
56static int __devinit olpc_xo1_probe(struct platform_device *pdev) 57static int __devinit olpc_xo1_probe(struct platform_device *pdev)
57{ 58{
58 struct resource *res; 59 struct resource *res;
60 int err;
59 61
60 /* don't run on non-XOs */ 62 /* don't run on non-XOs */
61 if (!machine_is_olpc()) 63 if (!machine_is_olpc())
62 return -ENODEV; 64 return -ENODEV;
63 65
66 err = mfd_cell_enable(pdev);
67 if (err)
68 return err;
69
64 res = platform_get_resource(pdev, IORESOURCE_IO, 0); 70 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
65 if (!res) { 71 if (!res) {
66 dev_err(&pdev->dev, "can't fetch device resource info\n"); 72 dev_err(&pdev->dev, "can't fetch device resource info\n");
67 return -EIO; 73 return -EIO;
68 } 74 }
69
70 if (!request_region(res->start, resource_size(res), DRV_NAME)) {
71 dev_err(&pdev->dev, "can't request region\n");
72 return -EIO;
73 }
74
75 if (strcmp(pdev->name, "cs5535-pms") == 0) 75 if (strcmp(pdev->name, "cs5535-pms") == 0)
76 pms_base = res->start; 76 pms_base = res->start;
77 else if (strcmp(pdev->name, "cs5535-acpi") == 0) 77 else if (strcmp(pdev->name, "olpc-xo1-pm-acpi") == 0)
78 acpi_base = res->start; 78 acpi_base = res->start;
79 79
80 /* If we have both addresses, we can override the poweroff hook */ 80 /* If we have both addresses, we can override the poweroff hook */
@@ -88,14 +88,11 @@ static int __devinit olpc_xo1_probe(struct platform_device *pdev)
88 88
89static int __devexit olpc_xo1_remove(struct platform_device *pdev) 89static int __devexit olpc_xo1_remove(struct platform_device *pdev)
90{ 90{
91 struct resource *r; 91 mfd_cell_disable(pdev);
92
93 r = platform_get_resource(pdev, IORESOURCE_IO, 0);
94 release_region(r->start, resource_size(r));
95 92
96 if (strcmp(pdev->name, "cs5535-pms") == 0) 93 if (strcmp(pdev->name, "cs5535-pms") == 0)
97 pms_base = 0; 94 pms_base = 0;
98 else if (strcmp(pdev->name, "cs5535-acpi") == 0) 95 else if (strcmp(pdev->name, "olpc-xo1-pm-acpi") == 0)
99 acpi_base = 0; 96 acpi_base = 0;
100 97
101 pm_power_off = NULL; 98 pm_power_off = NULL;
@@ -113,7 +110,7 @@ static struct platform_driver cs5535_pms_drv = {
113 110
114static struct platform_driver cs5535_acpi_drv = { 111static struct platform_driver cs5535_acpi_drv = {
115 .driver = { 112 .driver = {
116 .name = "cs5535-acpi", 113 .name = "olpc-xo1-pm-acpi",
117 .owner = THIS_MODULE, 114 .owner = THIS_MODULE,
118 }, 115 },
119 .probe = olpc_xo1_probe, 116 .probe = olpc_xo1_probe,
@@ -143,7 +140,7 @@ static void __exit olpc_xo1_exit(void)
143 140
144MODULE_AUTHOR("Daniel Drake <dsd@laptop.org>"); 141MODULE_AUTHOR("Daniel Drake <dsd@laptop.org>");
145MODULE_LICENSE("GPL"); 142MODULE_LICENSE("GPL");
146MODULE_ALIAS("platform:olpc-xo1"); 143MODULE_ALIAS("platform:cs5535-pms");
147 144
148module_init(olpc_xo1_init); 145module_init(olpc_xo1_init);
149module_exit(olpc_xo1_exit); 146module_exit(olpc_xo1_exit);
diff --git a/arch/x86/platform/olpc/olpc_dt.c b/arch/x86/platform/olpc/olpc_dt.c
index dab874647530..044bda5b3174 100644
--- a/arch/x86/platform/olpc/olpc_dt.c
+++ b/arch/x86/platform/olpc/olpc_dt.c
@@ -140,8 +140,7 @@ void * __init prom_early_alloc(unsigned long size)
140 * wasted bootmem) and hand off chunks of it to callers. 140 * wasted bootmem) and hand off chunks of it to callers.
141 */ 141 */
142 res = alloc_bootmem(chunk_size); 142 res = alloc_bootmem(chunk_size);
143 if (!res) 143 BUG_ON(!res);
144 return NULL;
145 prom_early_allocated += chunk_size; 144 prom_early_allocated += chunk_size;
146 memset(res, 0, chunk_size); 145 memset(res, 0, chunk_size);
147 free_mem = chunk_size; 146 free_mem = chunk_size;
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index df58e9cad96a..7cb6424317f6 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -11,6 +11,7 @@
11#include <linux/debugfs.h> 11#include <linux/debugfs.h>
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/slab.h> 13#include <linux/slab.h>
14#include <linux/delay.h>
14 15
15#include <asm/mmu_context.h> 16#include <asm/mmu_context.h>
16#include <asm/uv/uv.h> 17#include <asm/uv/uv.h>
@@ -1364,11 +1365,11 @@ uv_activation_descriptor_init(int node, int pnode)
1364 memset(bd2, 0, sizeof(struct bau_desc)); 1365 memset(bd2, 0, sizeof(struct bau_desc));
1365 bd2->header.sw_ack_flag = 1; 1366 bd2->header.sw_ack_flag = 1;
1366 /* 1367 /*
1367 * base_dest_nodeid is the nasid (pnode<<1) of the first uvhub 1368 * base_dest_nodeid is the nasid of the first uvhub
1368 * in the partition. The bit map will indicate uvhub numbers, 1369 * in the partition. The bit map will indicate uvhub numbers,
1369 * which are 0-N in a partition. Pnodes are unique system-wide. 1370 * which are 0-N in a partition. Pnodes are unique system-wide.
1370 */ 1371 */
1371 bd2->header.base_dest_nodeid = uv_partition_base_pnode << 1; 1372 bd2->header.base_dest_nodeid = UV_PNODE_TO_NASID(uv_partition_base_pnode);
1372 bd2->header.dest_subnodeid = 0x10; /* the LB */ 1373 bd2->header.dest_subnodeid = 0x10; /* the LB */
1373 bd2->header.command = UV_NET_ENDPOINT_INTD; 1374 bd2->header.command = UV_NET_ENDPOINT_INTD;
1374 bd2->header.int_both = 1; 1375 bd2->header.int_both = 1;
diff --git a/arch/x86/platform/uv/uv_irq.c b/arch/x86/platform/uv/uv_irq.c
index 7b24460917d5..374a05d8ad22 100644
--- a/arch/x86/platform/uv/uv_irq.c
+++ b/arch/x86/platform/uv/uv_irq.c
@@ -131,7 +131,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
131 unsigned long mmr_offset, int limit) 131 unsigned long mmr_offset, int limit)
132{ 132{
133 const struct cpumask *eligible_cpu = cpumask_of(cpu); 133 const struct cpumask *eligible_cpu = cpumask_of(cpu);
134 struct irq_cfg *cfg = get_irq_chip_data(irq); 134 struct irq_cfg *cfg = irq_get_chip_data(irq);
135 unsigned long mmr_value; 135 unsigned long mmr_value;
136 struct uv_IO_APIC_route_entry *entry; 136 struct uv_IO_APIC_route_entry *entry;
137 int mmr_pnode, err; 137 int mmr_pnode, err;
@@ -148,7 +148,7 @@ arch_enable_uv_irq(char *irq_name, unsigned int irq, int cpu, int mmr_blade,
148 else 148 else
149 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT); 149 irq_set_status_flags(irq, IRQ_MOVE_PCNTXT);
150 150
151 set_irq_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq, 151 irq_set_chip_and_handler_name(irq, &uv_irq_chip, handle_percpu_irq,
152 irq_name); 152 irq_name);
153 153
154 mmr_value = 0; 154 mmr_value = 0;
diff --git a/arch/x86/platform/visws/visws_quirks.c b/arch/x86/platform/visws/visws_quirks.c
index 632037671746..c7abf13a213f 100644
--- a/arch/x86/platform/visws/visws_quirks.c
+++ b/arch/x86/platform/visws/visws_quirks.c
@@ -471,15 +471,7 @@ static unsigned int startup_piix4_master_irq(struct irq_data *data)
471{ 471{
472 legacy_pic->init(0); 472 legacy_pic->init(0);
473 enable_cobalt_irq(data); 473 enable_cobalt_irq(data);
474} 474 return 0;
475
476static void end_piix4_master_irq(struct irq_data *data)
477{
478 unsigned long flags;
479
480 spin_lock_irqsave(&cobalt_lock, flags);
481 enable_cobalt_irq(data);
482 spin_unlock_irqrestore(&cobalt_lock, flags);
483} 475}
484 476
485static struct irq_chip piix4_master_irq_type = { 477static struct irq_chip piix4_master_irq_type = {
@@ -492,7 +484,7 @@ static void pii4_mask(struct irq_data *data) { }
492 484
493static struct irq_chip piix4_virtual_irq_type = { 485static struct irq_chip piix4_virtual_irq_type = {
494 .name = "PIIX4-virtual", 486 .name = "PIIX4-virtual",
495 .mask = pii4_mask, 487 .irq_mask = pii4_mask,
496}; 488};
497 489
498/* 490/*
@@ -569,18 +561,20 @@ out_unlock:
569static struct irqaction master_action = { 561static struct irqaction master_action = {
570 .handler = piix4_master_intr, 562 .handler = piix4_master_intr,
571 .name = "PIIX4-8259", 563 .name = "PIIX4-8259",
564 .flags = IRQF_NO_THREAD,
572}; 565};
573 566
574static struct irqaction cascade_action = { 567static struct irqaction cascade_action = {
575 .handler = no_action, 568 .handler = no_action,
576 .name = "cascade", 569 .name = "cascade",
570 .flags = IRQF_NO_THREAD,
577}; 571};
578 572
579static inline void set_piix4_virtual_irq_type(void) 573static inline void set_piix4_virtual_irq_type(void)
580{ 574{
581 piix4_virtual_irq_type.enable = i8259A_chip.unmask; 575 piix4_virtual_irq_type.irq_enable = i8259A_chip.irq_unmask;
582 piix4_virtual_irq_type.disable = i8259A_chip.mask; 576 piix4_virtual_irq_type.irq_disable = i8259A_chip.irq_mask;
583 piix4_virtual_irq_type.unmask = i8259A_chip.unmask; 577 piix4_virtual_irq_type.irq_unmask = i8259A_chip.irq_unmask;
584} 578}
585 579
586static void __init visws_pre_intr_init(void) 580static void __init visws_pre_intr_init(void)
@@ -597,7 +591,7 @@ static void __init visws_pre_intr_init(void)
597 else if (i == CO_IRQ_IDE0) 591 else if (i == CO_IRQ_IDE0)
598 chip = &cobalt_irq_type; 592 chip = &cobalt_irq_type;
599 else if (i == CO_IRQ_IDE1) 593 else if (i == CO_IRQ_IDE1)
600 >chip = &cobalt_irq_type; 594 chip = &cobalt_irq_type;
601 else if (i == CO_IRQ_8259) 595 else if (i == CO_IRQ_8259)
602 chip = &piix4_master_irq_type; 596 chip = &piix4_master_irq_type;
603 else if (i < CO_IRQ_APIC0) 597 else if (i < CO_IRQ_APIC0)
@@ -606,7 +600,7 @@ static void __init visws_pre_intr_init(void)
606 chip = &cobalt_irq_type; 600 chip = &cobalt_irq_type;
607 601
608 if (chip) 602 if (chip)
609 set_irq_chip(i, chip); 603 irq_set_chip(i, chip);
610 } 604 }
611 605
612 setup_irq(CO_IRQ_8259, &master_action); 606 setup_irq(CO_IRQ_8259, &master_action);