diff options
author | Dirk Brandewie <dirk.brandewie@gmail.com> | 2011-11-10 08:42:53 -0500 |
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committer | Ingo Molnar <mingo@elte.hu> | 2011-11-10 10:20:59 -0500 |
commit | 0a9153261d54c432bc0bdc88607f24c835ac729c (patch) | |
tree | 25fe6a310d3f3ecb9f873c8e49c852f1f4c5abe1 /arch/x86/platform/mrst | |
parent | 1ade93efd0a3dda5b0c0afda8ab8f4bd12938c1b (diff) |
x86/mrst: Add support for Penwell clock calibration
Signed-off-by: Dirk Brandewie <dirk.brandewie@gmail.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/platform/mrst')
-rw-r--r-- | arch/x86/platform/mrst/mrst.c | 33 |
1 files changed, 28 insertions, 5 deletions
diff --git a/arch/x86/platform/mrst/mrst.c b/arch/x86/platform/mrst/mrst.c index 6ed7afdaf4af..b7f14e5b2c66 100644 --- a/arch/x86/platform/mrst/mrst.c +++ b/arch/x86/platform/mrst/mrst.c | |||
@@ -187,11 +187,34 @@ int __init sfi_parse_mrtc(struct sfi_table_header *table) | |||
187 | static unsigned long __init mrst_calibrate_tsc(void) | 187 | static unsigned long __init mrst_calibrate_tsc(void) |
188 | { | 188 | { |
189 | unsigned long flags, fast_calibrate; | 189 | unsigned long flags, fast_calibrate; |
190 | 190 | if (__mrst_cpu_chip == MRST_CPU_CHIP_PENWELL) { | |
191 | local_irq_save(flags); | 191 | u32 lo, hi, ratio, fsb; |
192 | fast_calibrate = apbt_quick_calibrate(); | 192 | |
193 | local_irq_restore(flags); | 193 | rdmsr(MSR_IA32_PERF_STATUS, lo, hi); |
194 | 194 | pr_debug("IA32 perf status is 0x%x, 0x%0x\n", lo, hi); | |
195 | ratio = (hi >> 8) & 0x1f; | ||
196 | pr_debug("ratio is %d\n", ratio); | ||
197 | if (!ratio) { | ||
198 | pr_err("read a zero ratio, should be incorrect!\n"); | ||
199 | pr_err("force tsc ratio to 16 ...\n"); | ||
200 | ratio = 16; | ||
201 | } | ||
202 | rdmsr(MSR_FSB_FREQ, lo, hi); | ||
203 | if ((lo & 0x7) == 0x7) | ||
204 | fsb = PENWELL_FSB_FREQ_83SKU; | ||
205 | else | ||
206 | fsb = PENWELL_FSB_FREQ_100SKU; | ||
207 | fast_calibrate = ratio * fsb; | ||
208 | pr_debug("read penwell tsc %lu khz\n", fast_calibrate); | ||
209 | lapic_timer_frequency = fsb * 1000 / HZ; | ||
210 | /* mark tsc clocksource as reliable */ | ||
211 | set_cpu_cap(&boot_cpu_data, X86_FEATURE_TSC_RELIABLE); | ||
212 | } else { | ||
213 | local_irq_save(flags); | ||
214 | fast_calibrate = apbt_quick_calibrate(); | ||
215 | local_irq_restore(flags); | ||
216 | } | ||
217 | |||
195 | if (fast_calibrate) | 218 | if (fast_calibrate) |
196 | return fast_calibrate; | 219 | return fast_calibrate; |
197 | 220 | ||