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| author | Lachlan McIlroy <lachlan@redback.melbourne.sgi.com> | 2008-12-04 23:27:43 -0500 |
|---|---|---|
| committer | Lachlan McIlroy <lachlan@redback.melbourne.sgi.com> | 2008-12-04 23:27:43 -0500 |
| commit | 14d676f56fad26fd3c31eeff5d4ef8ea4a163571 (patch) | |
| tree | 5e740c5931daecf44a6e74c230f2deb291290f4b /arch/x86/pci | |
| parent | 797eaed40e1df4a3b9ece6894a71ce2b568bca38 (diff) | |
| parent | feaf3848a813a106f163013af6fcf6c4bfec92d9 (diff) | |
Merge git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux-2.6
Diffstat (limited to 'arch/x86/pci')
| -rw-r--r-- | arch/x86/pci/fixup.c | 25 |
1 files changed, 14 insertions, 11 deletions
diff --git a/arch/x86/pci/fixup.c b/arch/x86/pci/fixup.c index 3c27a809393b..2051dc96b8e9 100644 --- a/arch/x86/pci/fixup.c +++ b/arch/x86/pci/fixup.c | |||
| @@ -496,21 +496,24 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SIEMENS, 0x0015, | |||
| 496 | pci_siemens_interrupt_controller); | 496 | pci_siemens_interrupt_controller); |
| 497 | 497 | ||
| 498 | /* | 498 | /* |
| 499 | * Regular PCI devices have 256 bytes, but AMD Family 10h Opteron ext config | 499 | * Regular PCI devices have 256 bytes, but AMD Family 10h/11h CPUs have |
| 500 | * have 4096 bytes. Even if the device is capable, that doesn't mean we can | 500 | * 4096 bytes configuration space for each function of their processor |
| 501 | * access it. Maybe we don't have a way to generate extended config space | 501 | * configuration space. |
| 502 | * accesses. So check it | ||
| 503 | */ | 502 | */ |
| 504 | static void fam10h_pci_cfg_space_size(struct pci_dev *dev) | 503 | static void amd_cpu_pci_cfg_space_size(struct pci_dev *dev) |
| 505 | { | 504 | { |
| 506 | dev->cfg_size = pci_cfg_space_size_ext(dev); | 505 | dev->cfg_size = pci_cfg_space_size_ext(dev); |
| 507 | } | 506 | } |
| 508 | 507 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, amd_cpu_pci_cfg_space_size); | |
| 509 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1200, fam10h_pci_cfg_space_size); | 508 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, amd_cpu_pci_cfg_space_size); |
| 510 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1201, fam10h_pci_cfg_space_size); | 509 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, amd_cpu_pci_cfg_space_size); |
| 511 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1202, fam10h_pci_cfg_space_size); | 510 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, amd_cpu_pci_cfg_space_size); |
| 512 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1203, fam10h_pci_cfg_space_size); | 511 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, amd_cpu_pci_cfg_space_size); |
| 513 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1204, fam10h_pci_cfg_space_size); | 512 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1300, amd_cpu_pci_cfg_space_size); |
| 513 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1301, amd_cpu_pci_cfg_space_size); | ||
| 514 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1302, amd_cpu_pci_cfg_space_size); | ||
| 515 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1303, amd_cpu_pci_cfg_space_size); | ||
| 516 | DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x1304, amd_cpu_pci_cfg_space_size); | ||
| 514 | 517 | ||
| 515 | /* | 518 | /* |
| 516 | * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from | 519 | * SB600: Disable BAR1 on device 14.0 to avoid HPET resources from |