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authorLinus Torvalds <torvalds@linux-foundation.org>2014-08-13 20:23:32 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2014-08-13 20:23:32 -0400
commit81c02a21b293faecab725f691d709111831e1944 (patch)
tree146d41d8ff3ad03dca611b8fa8ab03c46c5d8978 /arch/x86/pci
parentd27c0d90184a13e9e9f28c38e84f889a259f6b5f (diff)
parent3eec595235c17a74094daa1e02d1b0af2e9a7125 (diff)
Merge branch 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull x86/apic updates from Thomas Gleixner: "This is a major overhaul to the x86 apic subsystem consisting of the following parts: - Remove obsolete APIC driver abstractions (David Rientjes) - Use the irqdomain facilities to dynamically allocate IRQs for IOAPICs. This is a prerequisite to enable IOAPIC hotplug support, and it also frees up wasted vectors (Jiang Liu) - Misc fixlets. Despite the hickup in Ingos previous pull request - caused by the missing fixup for the suspend/resume issue reported by Borislav - I strongly recommend that this update finds its way into 3.17. Some history for you: This is preparatory work for physical IOAPIC hotplug. The first attempt to support this was done by Yinghai and I shot it down because it just added another layer of obscurity and complexity to the already existing mess without tackling the underlying shortcomings of the current implementation. After quite some on- and offlist discussions, I requested that the design of this functionality must use generic infrastructure, i.e. irq domains, which provide all the mechanisms to dynamically map linux interrupt numbers to physical interrupts. Jiang picked up the idea and did a great job of consolidating the existing interfaces to manage the x86 (IOAPIC) interrupt system by utilizing irq domains. The testing in tip, Linux-next and inside of Intel on various machines did not unearth any oddities until Borislav exposed it to one of his oddball machines. The issue was resolved quickly, but unfortunately the fix fell through the cracks and did not hit the tip tree before Ingo sent the pull request. Not entirely Ingos fault, I also assumed that the fix was already merged when Ingo asked me whether he could send it. Nevertheless this work has a proper design, has undergone several rounds of review and the final fallout after applying it to tip and integrating it into Linux-next has been more than moderate. It's the ground work not only for IOAPIC hotplug, it will also allow us to move the lowlevel vector allocation into the irqdomain hierarchy, which will benefit other architectures as well. Patches are posted already, but they are on hold for two weeks, see below. I really appreciate the competence and responsiveness Jiang has shown in course of this endavour. So I'm sure that any fallout of this will be addressed in a timely manner. FYI, I'm vanishing for 2 weeks into my annual kids summer camp kitchen duty^Wvacation, while you folks are drooling at KS/LinuxCon :) But HPA will have a look at the hopefully zero fallout until I'm back" * 'x86-apic-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (53 commits) x86, irq, PCI: Keep IRQ assignment for PCI devices during suspend/hibernation x86/apic/vsmp: Make is_vsmp_box() static x86, apic: Remove enable_apic_mode callback x86, apic: Remove setup_portio_remap callback x86, apic: Remove multi_timer_check callback x86, apic: Replace noop_check_apicid_used x86, apic: Remove check_apicid_present callback x86, apic: Remove mps_oem_check callback x86, apic: Remove smp_callin_clear_local_apic callback x86, apic: Replace trampoline physical addresses with defaults x86, apic: Remove x86_32_numa_cpu_node callback x86: intel-mid: Use the new io_apic interfaces x86, vsmp: Remove is_vsmp_box() from apic_is_clustered_box() x86, irq: Clean up irqdomain transition code x86, irq, devicetree: Release IOAPIC pin when PCI device is disabled x86, irq, SFI: Release IOAPIC pin when PCI device is disabled x86, irq, mpparse: Release IOAPIC pin when PCI device is disabled x86, irq, ACPI: Release IOAPIC pin when PCI device is disabled x86, irq: Introduce helper functions to release IOAPIC pin x86, irq: Simplify the way to handle ISA IRQ ...
Diffstat (limited to 'arch/x86/pci')
-rw-r--r--arch/x86/pci/acpi.c6
-rw-r--r--arch/x86/pci/intel_mid_pci.c27
-rw-r--r--arch/x86/pci/irq.c16
-rw-r--r--arch/x86/pci/xen.c7
4 files changed, 35 insertions, 21 deletions
diff --git a/arch/x86/pci/acpi.c b/arch/x86/pci/acpi.c
index 5075371ab593..cfd1b132b8e3 100644
--- a/arch/x86/pci/acpi.c
+++ b/arch/x86/pci/acpi.c
@@ -448,7 +448,7 @@ static void probe_pci_root_info(struct pci_root_info *info,
448 return; 448 return;
449 449
450 size = sizeof(*info->res) * info->res_num; 450 size = sizeof(*info->res) * info->res_num;
451 info->res = kzalloc(size, GFP_KERNEL); 451 info->res = kzalloc_node(size, GFP_KERNEL, info->sd.node);
452 if (!info->res) { 452 if (!info->res) {
453 info->res_num = 0; 453 info->res_num = 0;
454 return; 454 return;
@@ -456,7 +456,7 @@ static void probe_pci_root_info(struct pci_root_info *info,
456 456
457 size = sizeof(*info->res_offset) * info->res_num; 457 size = sizeof(*info->res_offset) * info->res_num;
458 info->res_num = 0; 458 info->res_num = 0;
459 info->res_offset = kzalloc(size, GFP_KERNEL); 459 info->res_offset = kzalloc_node(size, GFP_KERNEL, info->sd.node);
460 if (!info->res_offset) { 460 if (!info->res_offset) {
461 kfree(info->res); 461 kfree(info->res);
462 info->res = NULL; 462 info->res = NULL;
@@ -499,7 +499,7 @@ struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
499 if (node != NUMA_NO_NODE && !node_online(node)) 499 if (node != NUMA_NO_NODE && !node_online(node))
500 node = NUMA_NO_NODE; 500 node = NUMA_NO_NODE;
501 501
502 info = kzalloc(sizeof(*info), GFP_KERNEL); 502 info = kzalloc_node(sizeof(*info), GFP_KERNEL, node);
503 if (!info) { 503 if (!info) {
504 printk(KERN_WARNING "pci_bus %04x:%02x: " 504 printk(KERN_WARNING "pci_bus %04x:%02x: "
505 "ignored (out of memory)\n", domain, busnum); 505 "ignored (out of memory)\n", domain, busnum);
diff --git a/arch/x86/pci/intel_mid_pci.c b/arch/x86/pci/intel_mid_pci.c
index 84b9d672843d..3865116c51fb 100644
--- a/arch/x86/pci/intel_mid_pci.c
+++ b/arch/x86/pci/intel_mid_pci.c
@@ -208,27 +208,31 @@ static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
208 208
209static int intel_mid_pci_irq_enable(struct pci_dev *dev) 209static int intel_mid_pci_irq_enable(struct pci_dev *dev)
210{ 210{
211 u8 pin; 211 int polarity;
212 struct io_apic_irq_attr irq_attr;
213 212
214 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 213 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER)
214 polarity = 0; /* active high */
215 else
216 polarity = 1; /* active low */
215 217
216 /* 218 /*
217 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to 219 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
218 * IOAPIC RTE entries, so we just enable RTE for the device. 220 * IOAPIC RTE entries, so we just enable RTE for the device.
219 */ 221 */
220 irq_attr.ioapic = mp_find_ioapic(dev->irq); 222 if (mp_set_gsi_attr(dev->irq, 1, polarity, dev_to_node(&dev->dev)))
221 irq_attr.ioapic_pin = dev->irq; 223 return -EBUSY;
222 irq_attr.trigger = 1; /* level */ 224 if (mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC) < 0)
223 if (intel_mid_identify_cpu() == INTEL_MID_CPU_CHIP_TANGIER) 225 return -EBUSY;
224 irq_attr.polarity = 0; /* active high */
225 else
226 irq_attr.polarity = 1; /* active low */
227 io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr);
228 226
229 return 0; 227 return 0;
230} 228}
231 229
230static void intel_mid_pci_irq_disable(struct pci_dev *dev)
231{
232 if (!dev->dev.power.is_prepared && dev->irq > 0)
233 mp_unmap_irq(dev->irq);
234}
235
232struct pci_ops intel_mid_pci_ops = { 236struct pci_ops intel_mid_pci_ops = {
233 .read = pci_read, 237 .read = pci_read,
234 .write = pci_write, 238 .write = pci_write,
@@ -245,6 +249,7 @@ int __init intel_mid_pci_init(void)
245 pr_info("Intel MID platform detected, using MID PCI ops\n"); 249 pr_info("Intel MID platform detected, using MID PCI ops\n");
246 pci_mmcfg_late_init(); 250 pci_mmcfg_late_init();
247 pcibios_enable_irq = intel_mid_pci_irq_enable; 251 pcibios_enable_irq = intel_mid_pci_irq_enable;
252 pcibios_disable_irq = intel_mid_pci_irq_disable;
248 pci_root_ops = intel_mid_pci_ops; 253 pci_root_ops = intel_mid_pci_ops;
249 pci_soc_mode = 1; 254 pci_soc_mode = 1;
250 /* Continue with standard init */ 255 /* Continue with standard init */
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 84112f55dd7a..bc1a2c341891 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -26,6 +26,7 @@ static int acer_tm360_irqrouting;
26static struct irq_routing_table *pirq_table; 26static struct irq_routing_table *pirq_table;
27 27
28static int pirq_enable_irq(struct pci_dev *dev); 28static int pirq_enable_irq(struct pci_dev *dev);
29static void pirq_disable_irq(struct pci_dev *dev);
29 30
30/* 31/*
31 * Never use: 0, 1, 2 (timer, keyboard, and cascade) 32 * Never use: 0, 1, 2 (timer, keyboard, and cascade)
@@ -53,7 +54,7 @@ struct irq_router_handler {
53}; 54};
54 55
55int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq; 56int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
56void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL; 57void (*pcibios_disable_irq)(struct pci_dev *dev) = pirq_disable_irq;
57 58
58/* 59/*
59 * Check passed address for the PCI IRQ Routing Table signature 60 * Check passed address for the PCI IRQ Routing Table signature
@@ -1186,7 +1187,7 @@ void pcibios_penalize_isa_irq(int irq, int active)
1186 1187
1187static int pirq_enable_irq(struct pci_dev *dev) 1188static int pirq_enable_irq(struct pci_dev *dev)
1188{ 1189{
1189 u8 pin; 1190 u8 pin = 0;
1190 1191
1191 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); 1192 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1192 if (pin && !pcibios_lookup_irq(dev, 1)) { 1193 if (pin && !pcibios_lookup_irq(dev, 1)) {
@@ -1227,8 +1228,6 @@ static int pirq_enable_irq(struct pci_dev *dev)
1227 } 1228 }
1228 dev = temp_dev; 1229 dev = temp_dev;
1229 if (irq >= 0) { 1230 if (irq >= 0) {
1230 io_apic_set_pci_routing(&dev->dev, irq,
1231 &irq_attr);
1232 dev->irq = irq; 1231 dev->irq = irq;
1233 dev_info(&dev->dev, "PCI->APIC IRQ transform: " 1232 dev_info(&dev->dev, "PCI->APIC IRQ transform: "
1234 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq); 1233 "INT %c -> IRQ %d\n", 'A' + pin - 1, irq);
@@ -1254,3 +1253,12 @@ static int pirq_enable_irq(struct pci_dev *dev)
1254 } 1253 }
1255 return 0; 1254 return 0;
1256} 1255}
1256
1257static void pirq_disable_irq(struct pci_dev *dev)
1258{
1259 if (io_apic_assign_pci_irqs && !dev->dev.power.is_prepared &&
1260 dev->irq) {
1261 mp_unmap_irq(dev->irq);
1262 dev->irq = 0;
1263 }
1264}
diff --git a/arch/x86/pci/xen.c b/arch/x86/pci/xen.c
index 905956f16465..093f5f4272d3 100644
--- a/arch/x86/pci/xen.c
+++ b/arch/x86/pci/xen.c
@@ -23,6 +23,7 @@
23#include <xen/features.h> 23#include <xen/features.h>
24#include <xen/events.h> 24#include <xen/events.h>
25#include <asm/xen/pci.h> 25#include <asm/xen/pci.h>
26#include <asm/i8259.h>
26 27
27static int xen_pcifront_enable_irq(struct pci_dev *dev) 28static int xen_pcifront_enable_irq(struct pci_dev *dev)
28{ 29{
@@ -40,7 +41,7 @@ static int xen_pcifront_enable_irq(struct pci_dev *dev)
40 /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/ 41 /* In PV DomU the Xen PCI backend puts the PIRQ in the interrupt line.*/
41 pirq = gsi; 42 pirq = gsi;
42 43
43 if (gsi < NR_IRQS_LEGACY) 44 if (gsi < nr_legacy_irqs())
44 share = 0; 45 share = 0;
45 46
46 rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront"); 47 rc = xen_bind_pirq_gsi_to_irq(gsi, pirq, share, "pcifront");
@@ -511,7 +512,7 @@ int __init pci_xen_initial_domain(void)
511 xen_setup_acpi_sci(); 512 xen_setup_acpi_sci();
512 __acpi_register_gsi = acpi_register_gsi_xen; 513 __acpi_register_gsi = acpi_register_gsi_xen;
513 /* Pre-allocate legacy irqs */ 514 /* Pre-allocate legacy irqs */
514 for (irq = 0; irq < NR_IRQS_LEGACY; irq++) { 515 for (irq = 0; irq < nr_legacy_irqs(); irq++) {
515 int trigger, polarity; 516 int trigger, polarity;
516 517
517 if (acpi_get_override_irq(irq, &trigger, &polarity) == -1) 518 if (acpi_get_override_irq(irq, &trigger, &polarity) == -1)
@@ -522,7 +523,7 @@ int __init pci_xen_initial_domain(void)
522 true /* Map GSI to PIRQ */); 523 true /* Map GSI to PIRQ */);
523 } 524 }
524 if (0 == nr_ioapics) { 525 if (0 == nr_ioapics) {
525 for (irq = 0; irq < NR_IRQS_LEGACY; irq++) 526 for (irq = 0; irq < nr_legacy_irqs(); irq++)
526 xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic"); 527 xen_bind_pirq_gsi_to_irq(irq, irq, 0, "xt-pic");
527 } 528 }
528 return 0; 529 return 0;